1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 24 #include "SIDefines.h" 25 #include "Utils/AMDGPUBaseInfo.h" 26 27 #include "llvm/BinaryFormat/ELF.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCFixedLenDisassembler.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCSubtargetInfo.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/Endian.h" 35 #include "llvm/Support/TargetRegistry.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 42 43 44 inline static MCDisassembler::DecodeStatus 45 addOperand(MCInst &Inst, const MCOperand& Opnd) { 46 Inst.addOperand(Opnd); 47 return Opnd.isValid() ? 48 MCDisassembler::Success : 49 MCDisassembler::SoftFail; 50 } 51 52 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 53 uint16_t NameIdx) { 54 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 55 if (OpIdx != -1) { 56 auto I = MI.begin(); 57 std::advance(I, OpIdx); 58 MI.insert(I, Op); 59 } 60 return OpIdx; 61 } 62 63 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 64 uint64_t Addr, const void *Decoder) { 65 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 66 67 APInt SignedOffset(18, Imm * 4, true); 68 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 69 70 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 71 return MCDisassembler::Success; 72 return addOperand(Inst, MCOperand::createImm(Imm)); 73 } 74 75 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 76 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 77 unsigned Imm, \ 78 uint64_t /*Addr*/, \ 79 const void *Decoder) { \ 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 81 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 82 } 83 84 #define DECODE_OPERAND_REG(RegClass) \ 85 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 86 87 DECODE_OPERAND_REG(VGPR_32) 88 DECODE_OPERAND_REG(VS_32) 89 DECODE_OPERAND_REG(VS_64) 90 91 DECODE_OPERAND_REG(VReg_64) 92 DECODE_OPERAND_REG(VReg_96) 93 DECODE_OPERAND_REG(VReg_128) 94 95 DECODE_OPERAND_REG(SReg_32) 96 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 97 DECODE_OPERAND_REG(SReg_64) 98 DECODE_OPERAND_REG(SReg_64_XEXEC) 99 DECODE_OPERAND_REG(SReg_128) 100 DECODE_OPERAND_REG(SReg_256) 101 DECODE_OPERAND_REG(SReg_512) 102 103 104 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 105 unsigned Imm, 106 uint64_t Addr, 107 const void *Decoder) { 108 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 109 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 110 } 111 112 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 113 unsigned Imm, 114 uint64_t Addr, 115 const void *Decoder) { 116 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 117 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 118 } 119 120 #define DECODE_SDWA(DecName) \ 121 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 122 123 DECODE_SDWA(Src32) 124 DECODE_SDWA(Src16) 125 DECODE_SDWA(VopcDst) 126 127 #include "AMDGPUGenDisassemblerTables.inc" 128 129 //===----------------------------------------------------------------------===// 130 // 131 //===----------------------------------------------------------------------===// 132 133 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 134 assert(Bytes.size() >= sizeof(T)); 135 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 136 Bytes = Bytes.slice(sizeof(T)); 137 return Res; 138 } 139 140 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 141 MCInst &MI, 142 uint64_t Inst, 143 uint64_t Address) const { 144 assert(MI.getOpcode() == 0); 145 assert(MI.getNumOperands() == 0); 146 MCInst TmpInst; 147 HasLiteral = false; 148 const auto SavedBytes = Bytes; 149 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 150 MI = TmpInst; 151 return MCDisassembler::Success; 152 } 153 Bytes = SavedBytes; 154 return MCDisassembler::Fail; 155 } 156 157 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 158 ArrayRef<uint8_t> Bytes_, 159 uint64_t Address, 160 raw_ostream &WS, 161 raw_ostream &CS) const { 162 CommentStream = &CS; 163 bool IsSDWA = false; 164 165 // ToDo: AMDGPUDisassembler supports only VI ISA. 166 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding]) 167 report_fatal_error("Disassembly not yet supported for subtarget"); 168 169 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 170 Bytes = Bytes_.slice(0, MaxInstBytesNum); 171 172 DecodeStatus Res = MCDisassembler::Fail; 173 do { 174 // ToDo: better to switch encoding length using some bit predicate 175 // but it is unknown yet, so try all we can 176 177 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 178 // encodings 179 if (Bytes.size() >= 8) { 180 const uint64_t QW = eatBytes<uint64_t>(Bytes); 181 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 182 if (Res) break; 183 184 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 185 if (Res) { IsSDWA = true; break; } 186 187 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 188 if (Res) { IsSDWA = true; break; } 189 } 190 191 // Reinitialize Bytes as DPP64 could have eaten too much 192 Bytes = Bytes_.slice(0, MaxInstBytesNum); 193 194 // Try decode 32-bit instruction 195 if (Bytes.size() < 4) break; 196 const uint32_t DW = eatBytes<uint32_t>(Bytes); 197 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 198 if (Res) break; 199 200 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 201 if (Res) break; 202 203 if (Bytes.size() < 4) break; 204 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 205 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 206 if (Res) break; 207 208 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 209 } while (false); 210 211 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 212 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si || 213 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) { 214 // Insert dummy unused src2_modifiers. 215 insertNamedMCOperand(MI, MCOperand::createImm(0), 216 AMDGPU::OpName::src2_modifiers); 217 } 218 219 if (Res && IsSDWA) 220 Res = convertSDWAInst(MI); 221 222 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 223 return Res; 224 } 225 226 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 227 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 228 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 229 // VOPC - insert clamp 230 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 231 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 232 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 233 if (SDst != -1) { 234 // VOPC - insert VCC register as sdst 235 insertNamedMCOperand(MI, MCOperand::createReg(AMDGPU::VCC), 236 AMDGPU::OpName::sdst); 237 } else { 238 // VOP1/2 - insert omod if present in instruction 239 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 240 } 241 } 242 return MCDisassembler::Success; 243 } 244 245 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 246 return getContext().getRegisterInfo()-> 247 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 248 } 249 250 inline 251 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 252 const Twine& ErrMsg) const { 253 *CommentStream << "Error: " + ErrMsg; 254 255 // ToDo: add support for error operands to MCInst.h 256 // return MCOperand::createError(V); 257 return MCOperand(); 258 } 259 260 inline 261 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 262 return MCOperand::createReg(RegId); 263 } 264 265 inline 266 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 267 unsigned Val) const { 268 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 269 if (Val >= RegCl.getNumRegs()) 270 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 271 ": unknown register " + Twine(Val)); 272 return createRegOperand(RegCl.getRegister(Val)); 273 } 274 275 inline 276 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 277 unsigned Val) const { 278 // ToDo: SI/CI have 104 SGPRs, VI - 102 279 // Valery: here we accepting as much as we can, let assembler sort it out 280 int shift = 0; 281 switch (SRegClassID) { 282 case AMDGPU::SGPR_32RegClassID: 283 case AMDGPU::TTMP_32RegClassID: 284 break; 285 case AMDGPU::SGPR_64RegClassID: 286 case AMDGPU::TTMP_64RegClassID: 287 shift = 1; 288 break; 289 case AMDGPU::SGPR_128RegClassID: 290 case AMDGPU::TTMP_128RegClassID: 291 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 292 // this bundle? 293 case AMDGPU::SReg_256RegClassID: 294 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 295 // this bundle? 296 case AMDGPU::SReg_512RegClassID: 297 shift = 2; 298 break; 299 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 300 // this bundle? 301 default: 302 llvm_unreachable("unhandled register class"); 303 } 304 305 if (Val % (1 << shift)) { 306 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 307 << ": scalar reg isn't aligned " << Val; 308 } 309 310 return createRegOperand(SRegClassID, Val >> shift); 311 } 312 313 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 314 return decodeSrcOp(OPW32, Val); 315 } 316 317 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 318 return decodeSrcOp(OPW64, Val); 319 } 320 321 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 322 return decodeSrcOp(OPW16, Val); 323 } 324 325 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 326 return decodeSrcOp(OPWV216, Val); 327 } 328 329 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 330 // Some instructions have operand restrictions beyond what the encoding 331 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 332 // high bit. 333 Val &= 255; 334 335 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 336 } 337 338 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 339 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 340 } 341 342 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 343 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 344 } 345 346 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 347 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 348 } 349 350 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 351 // table-gen generated disassembler doesn't care about operand types 352 // leaving only registry class so SSrc_32 operand turns into SReg_32 353 // and therefore we accept immediates and literals here as well 354 return decodeSrcOp(OPW32, Val); 355 } 356 357 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 358 unsigned Val) const { 359 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 360 return decodeOperand_SReg_32(Val); 361 } 362 363 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 364 return decodeSrcOp(OPW64, Val); 365 } 366 367 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 368 return decodeSrcOp(OPW64, Val); 369 } 370 371 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 372 return decodeSrcOp(OPW128, Val); 373 } 374 375 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 376 return createSRegOperand(AMDGPU::SReg_256RegClassID, Val); 377 } 378 379 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 380 return createSRegOperand(AMDGPU::SReg_512RegClassID, Val); 381 } 382 383 384 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 385 // For now all literal constants are supposed to be unsigned integer 386 // ToDo: deal with signed/unsigned 64-bit integer constants 387 // ToDo: deal with float/double constants 388 if (!HasLiteral) { 389 if (Bytes.size() < 4) { 390 return errOperand(0, "cannot read literal, inst bytes left " + 391 Twine(Bytes.size())); 392 } 393 HasLiteral = true; 394 Literal = eatBytes<uint32_t>(Bytes); 395 } 396 return MCOperand::createImm(Literal); 397 } 398 399 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 400 using namespace AMDGPU::EncValues; 401 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 402 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 403 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 404 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 405 // Cast prevents negative overflow. 406 } 407 408 static int64_t getInlineImmVal32(unsigned Imm) { 409 switch (Imm) { 410 case 240: 411 return FloatToBits(0.5f); 412 case 241: 413 return FloatToBits(-0.5f); 414 case 242: 415 return FloatToBits(1.0f); 416 case 243: 417 return FloatToBits(-1.0f); 418 case 244: 419 return FloatToBits(2.0f); 420 case 245: 421 return FloatToBits(-2.0f); 422 case 246: 423 return FloatToBits(4.0f); 424 case 247: 425 return FloatToBits(-4.0f); 426 case 248: // 1 / (2 * PI) 427 return 0x3e22f983; 428 default: 429 llvm_unreachable("invalid fp inline imm"); 430 } 431 } 432 433 static int64_t getInlineImmVal64(unsigned Imm) { 434 switch (Imm) { 435 case 240: 436 return DoubleToBits(0.5); 437 case 241: 438 return DoubleToBits(-0.5); 439 case 242: 440 return DoubleToBits(1.0); 441 case 243: 442 return DoubleToBits(-1.0); 443 case 244: 444 return DoubleToBits(2.0); 445 case 245: 446 return DoubleToBits(-2.0); 447 case 246: 448 return DoubleToBits(4.0); 449 case 247: 450 return DoubleToBits(-4.0); 451 case 248: // 1 / (2 * PI) 452 return 0x3fc45f306dc9c882; 453 default: 454 llvm_unreachable("invalid fp inline imm"); 455 } 456 } 457 458 static int64_t getInlineImmVal16(unsigned Imm) { 459 switch (Imm) { 460 case 240: 461 return 0x3800; 462 case 241: 463 return 0xB800; 464 case 242: 465 return 0x3C00; 466 case 243: 467 return 0xBC00; 468 case 244: 469 return 0x4000; 470 case 245: 471 return 0xC000; 472 case 246: 473 return 0x4400; 474 case 247: 475 return 0xC400; 476 case 248: // 1 / (2 * PI) 477 return 0x3118; 478 default: 479 llvm_unreachable("invalid fp inline imm"); 480 } 481 } 482 483 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 484 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 485 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 486 487 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 488 switch (Width) { 489 case OPW32: 490 return MCOperand::createImm(getInlineImmVal32(Imm)); 491 case OPW64: 492 return MCOperand::createImm(getInlineImmVal64(Imm)); 493 case OPW16: 494 case OPWV216: 495 return MCOperand::createImm(getInlineImmVal16(Imm)); 496 default: 497 llvm_unreachable("implement me"); 498 } 499 } 500 501 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 502 using namespace AMDGPU; 503 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 504 switch (Width) { 505 default: // fall 506 case OPW32: 507 case OPW16: 508 case OPWV216: 509 return VGPR_32RegClassID; 510 case OPW64: return VReg_64RegClassID; 511 case OPW128: return VReg_128RegClassID; 512 } 513 } 514 515 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 516 using namespace AMDGPU; 517 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 518 switch (Width) { 519 default: // fall 520 case OPW32: 521 case OPW16: 522 case OPWV216: 523 return SGPR_32RegClassID; 524 case OPW64: return SGPR_64RegClassID; 525 case OPW128: return SGPR_128RegClassID; 526 } 527 } 528 529 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 530 using namespace AMDGPU; 531 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 532 switch (Width) { 533 default: // fall 534 case OPW32: 535 case OPW16: 536 case OPWV216: 537 return TTMP_32RegClassID; 538 case OPW64: return TTMP_64RegClassID; 539 case OPW128: return TTMP_128RegClassID; 540 } 541 } 542 543 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 544 using namespace AMDGPU::EncValues; 545 assert(Val < 512); // enum9 546 547 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 548 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); 549 } 550 if (Val <= SGPR_MAX) { 551 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 552 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 553 } 554 if (TTMP_MIN <= Val && Val <= TTMP_MAX) { 555 return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN); 556 } 557 558 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 559 return decodeIntImmed(Val); 560 561 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 562 return decodeFPImmed(Width, Val); 563 564 if (Val == LITERAL_CONST) 565 return decodeLiteralConstant(); 566 567 switch (Width) { 568 case OPW32: 569 case OPW16: 570 case OPWV216: 571 return decodeSpecialReg32(Val); 572 case OPW64: 573 return decodeSpecialReg64(Val); 574 default: 575 llvm_unreachable("unexpected immediate type"); 576 } 577 } 578 579 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 580 using namespace AMDGPU; 581 switch (Val) { 582 case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI)); 583 case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI)); 584 // ToDo: no support for xnack_mask_lo/_hi register 585 case 104: 586 case 105: break; 587 case 106: return createRegOperand(VCC_LO); 588 case 107: return createRegOperand(VCC_HI); 589 case 108: return createRegOperand(TBA_LO); 590 case 109: return createRegOperand(TBA_HI); 591 case 110: return createRegOperand(TMA_LO); 592 case 111: return createRegOperand(TMA_HI); 593 case 124: return createRegOperand(M0); 594 case 126: return createRegOperand(EXEC_LO); 595 case 127: return createRegOperand(EXEC_HI); 596 case 235: return createRegOperand(SRC_SHARED_BASE); 597 case 236: return createRegOperand(SRC_SHARED_LIMIT); 598 case 237: return createRegOperand(SRC_PRIVATE_BASE); 599 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 600 // TODO: SRC_POPS_EXITING_WAVE_ID 601 // ToDo: no support for vccz register 602 case 251: break; 603 // ToDo: no support for execz register 604 case 252: break; 605 case 253: return createRegOperand(SCC); 606 default: break; 607 } 608 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 609 } 610 611 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 612 using namespace AMDGPU; 613 switch (Val) { 614 case 102: return createRegOperand(getMCReg(FLAT_SCR, STI)); 615 case 106: return createRegOperand(VCC); 616 case 108: return createRegOperand(TBA); 617 case 110: return createRegOperand(TMA); 618 case 126: return createRegOperand(EXEC); 619 default: break; 620 } 621 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 622 } 623 624 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 625 unsigned Val) const { 626 using namespace AMDGPU::SDWA; 627 628 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 629 if (SDWA9EncValues::SRC_VGPR_MIN <= Val && 630 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 631 return createRegOperand(getVgprClassId(Width), 632 Val - SDWA9EncValues::SRC_VGPR_MIN); 633 } 634 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 635 Val <= SDWA9EncValues::SRC_SGPR_MAX) { 636 return createSRegOperand(getSgprClassId(Width), 637 Val - SDWA9EncValues::SRC_SGPR_MIN); 638 } 639 640 return decodeSpecialReg32(Val - SDWA9EncValues::SRC_SGPR_MIN); 641 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 642 return createRegOperand(getVgprClassId(Width), Val); 643 } 644 llvm_unreachable("unsupported target"); 645 } 646 647 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 648 return decodeSDWASrc(OPW16, Val); 649 } 650 651 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 652 return decodeSDWASrc(OPW32, Val); 653 } 654 655 656 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 657 using namespace AMDGPU::SDWA; 658 659 assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] && 660 "SDWAVopcDst should be present only on GFX9"); 661 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 662 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 663 if (Val > AMDGPU::EncValues::SGPR_MAX) { 664 return decodeSpecialReg64(Val); 665 } else { 666 return createSRegOperand(getSgprClassId(OPW64), Val); 667 } 668 } else { 669 return createRegOperand(AMDGPU::VCC); 670 } 671 } 672 673 //===----------------------------------------------------------------------===// 674 // AMDGPUSymbolizer 675 //===----------------------------------------------------------------------===// 676 677 // Try to find symbol name for specified label 678 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 679 raw_ostream &/*cStream*/, int64_t Value, 680 uint64_t /*Address*/, bool IsBranch, 681 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 682 typedef std::tuple<uint64_t, StringRef, uint8_t> SymbolInfoTy; 683 typedef std::vector<SymbolInfoTy> SectionSymbolsTy; 684 685 if (!IsBranch) { 686 return false; 687 } 688 689 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 690 auto Result = std::find_if(Symbols->begin(), Symbols->end(), 691 [Value](const SymbolInfoTy& Val) { 692 return std::get<0>(Val) == static_cast<uint64_t>(Value) 693 && std::get<2>(Val) == ELF::STT_NOTYPE; 694 }); 695 if (Result != Symbols->end()) { 696 auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result)); 697 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 698 Inst.addOperand(MCOperand::createExpr(Add)); 699 return true; 700 } 701 return false; 702 } 703 704 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 705 int64_t Value, 706 uint64_t Address) { 707 llvm_unreachable("unimplemented"); 708 } 709 710 //===----------------------------------------------------------------------===// 711 // Initialization 712 //===----------------------------------------------------------------------===// 713 714 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 715 LLVMOpInfoCallback /*GetOpInfo*/, 716 LLVMSymbolLookupCallback /*SymbolLookUp*/, 717 void *DisInfo, 718 MCContext *Ctx, 719 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 720 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 721 } 722 723 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 724 const MCSubtargetInfo &STI, 725 MCContext &Ctx) { 726 return new AMDGPUDisassembler(STI, Ctx); 727 } 728 729 extern "C" void LLVMInitializeAMDGPUDisassembler() { 730 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 731 createAMDGPUDisassembler); 732 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 733 createAMDGPUSymbolizer); 734 } 735