1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) { 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 95 Offset = SignExtend64<24>(Imm); 96 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 111 uint64_t Addr, 112 const MCDisassembler *Decoder) { 113 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 114 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 115 } 116 117 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 118 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 119 uint64_t /*Addr*/, \ 120 const MCDisassembler *Decoder) { \ 121 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 122 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 123 } 124 125 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 126 // number of register. Used by VGPR only and AGPR only operands. 127 #define DECODE_OPERAND_REG_8(RegClass) \ 128 static DecodeStatus Decode##RegClass##RegisterClass( \ 129 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 130 const MCDisassembler *Decoder) { \ 131 assert(Imm < (1 << 8) && "8-bit encoding"); \ 132 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 133 return addOperand( \ 134 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 135 } 136 137 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 138 ImmWidth) \ 139 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 140 const MCDisassembler *Decoder) { \ 141 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 142 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 143 return addOperand(Inst, \ 144 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 145 MandatoryLiteral, ImmWidth)); \ 146 } 147 148 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 149 // get register class. Used by SGPR only operands. 150 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 152 153 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 154 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 155 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 156 // Used by AV_ register classes (AGPR or VGPR only register operands). 157 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ 158 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ 159 Imm | AMDGPU::EncValues::IS_VGPR, false, 0) 160 161 // Decoder for Src(9-bit encoding) registers only. 162 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ 163 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 164 165 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 166 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 167 // only. 168 #define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \ 169 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) 170 171 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 172 // Imm{9} is acc, registers only. 173 #define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \ 174 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) 175 176 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 177 // register from RegClass or immediate. Registers that don't belong to RegClass 178 // will be decoded and InstPrinter will report warning. Immediate will be 179 // decoded into constant of size ImmWidth, should match width of immediate used 180 // by OperandType (important for floating point types). 181 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ 182 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ 183 false, ImmWidth) 184 185 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 186 // and decode using 'enum10' from decodeSrcOp. 187 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ 188 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ 189 Imm | 512, false, ImmWidth) 190 191 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ 192 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ 193 OpWidth, Imm, true, ImmWidth) 194 195 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 196 // when RegisterClass is used as an operand. Most often used for destination 197 // operands. 198 199 DECODE_OPERAND_REG_8(VGPR_32) 200 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 201 DECODE_OPERAND_REG_8(VReg_64) 202 DECODE_OPERAND_REG_8(VReg_96) 203 DECODE_OPERAND_REG_8(VReg_128) 204 DECODE_OPERAND_REG_8(VReg_256) 205 DECODE_OPERAND_REG_8(VReg_288) 206 DECODE_OPERAND_REG_8(VReg_352) 207 DECODE_OPERAND_REG_8(VReg_384) 208 DECODE_OPERAND_REG_8(VReg_512) 209 DECODE_OPERAND_REG_8(VReg_1024) 210 211 DECODE_OPERAND_REG_7(SReg_32, OPW32) 212 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 213 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 214 DECODE_OPERAND_REG_7(SReg_64, OPW64) 215 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 216 DECODE_OPERAND_REG_7(SReg_128, OPW128) 217 DECODE_OPERAND_REG_7(SReg_256, OPW256) 218 DECODE_OPERAND_REG_7(SReg_512, OPW512) 219 220 DECODE_OPERAND_REG_8(AGPR_32) 221 DECODE_OPERAND_REG_8(AReg_64) 222 DECODE_OPERAND_REG_8(AReg_128) 223 DECODE_OPERAND_REG_8(AReg_256) 224 DECODE_OPERAND_REG_8(AReg_512) 225 DECODE_OPERAND_REG_8(AReg_1024) 226 227 DECODE_OPERAND_REG_AV10(AVDst_128, OPW128) 228 DECODE_OPERAND_REG_AV10(AVDst_512, OPW512) 229 230 // Decoders for register only source RegisterOperands that use use 9-bit Src 231 // encoding: 'decodeOperand_<RegClass>'. 232 233 DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) 234 DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) 235 DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) 236 DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) 237 DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) 238 239 DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32) 240 241 DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32) 242 DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64) 243 DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128) 244 245 // Decoders for register or immediate RegisterOperands that use 9-bit Src 246 // encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'. 247 248 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) 249 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) 250 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 16) 251 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) 252 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) 253 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) 254 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) 255 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) 256 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32) 257 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) 258 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) 259 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) 260 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) 261 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) 262 263 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) 264 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) 265 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) 266 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) 267 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) 268 269 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) 270 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) 271 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) 272 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32) 273 274 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 275 uint64_t /*Addr*/, 276 const MCDisassembler *Decoder) { 277 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 278 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 279 280 bool IsHi = Imm & (1 << 9); 281 unsigned RegIdx = Imm & 0xff; 282 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 283 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 284 } 285 286 static DecodeStatus 287 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 288 const MCDisassembler *Decoder) { 289 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 290 291 bool IsHi = Imm & (1 << 7); 292 unsigned RegIdx = Imm & 0x7f; 293 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 294 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 295 } 296 297 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 298 uint64_t /*Addr*/, 299 const MCDisassembler *Decoder) { 300 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 301 302 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 303 bool IsVGPR = Imm & (1 << 8); 304 if (IsVGPR) { 305 bool IsHi = Imm & (1 << 7); 306 unsigned RegIdx = Imm & 0x7f; 307 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 308 } 309 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 310 Imm & 0xFF, false, 16)); 311 } 312 313 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 314 uint64_t /*Addr*/, 315 const MCDisassembler *Decoder) { 316 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 317 318 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 319 bool IsVGPR = Imm & (1 << 8); 320 if (IsVGPR) { 321 bool IsHi = Imm & (1 << 9); 322 unsigned RegIdx = Imm & 0xff; 323 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 324 } 325 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 326 Imm & 0xFF, false, 16)); 327 } 328 329 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 330 uint64_t Addr, 331 const MCDisassembler *Decoder) { 332 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 333 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 334 } 335 336 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 337 uint64_t Addr, const void *Decoder) { 338 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 339 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 340 } 341 342 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 343 const MCRegisterInfo *MRI) { 344 if (OpIdx < 0) 345 return false; 346 347 const MCOperand &Op = Inst.getOperand(OpIdx); 348 if (!Op.isReg()) 349 return false; 350 351 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 352 auto Reg = Sub ? Sub : Op.getReg(); 353 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 354 } 355 356 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 357 AMDGPUDisassembler::OpWidthTy Opw, 358 const MCDisassembler *Decoder) { 359 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 360 if (!DAsm->isGFX90A()) { 361 Imm &= 511; 362 } else { 363 // If atomic has both vdata and vdst their register classes are tied. 364 // The bit is decoded along with the vdst, first operand. We need to 365 // change register class to AGPR if vdst was AGPR. 366 // If a DS instruction has both data0 and data1 their register classes 367 // are also tied. 368 unsigned Opc = Inst.getOpcode(); 369 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 370 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 371 : AMDGPU::OpName::vdata; 372 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 373 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 374 if ((int)Inst.getNumOperands() == DataIdx) { 375 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 376 if (IsAGPROperand(Inst, DstIdx, MRI)) 377 Imm |= 512; 378 } 379 380 if (TSFlags & SIInstrFlags::DS) { 381 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 382 if ((int)Inst.getNumOperands() == Data2Idx && 383 IsAGPROperand(Inst, DataIdx, MRI)) 384 Imm |= 512; 385 } 386 } 387 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 388 } 389 390 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 391 uint64_t Addr, 392 const MCDisassembler *Decoder) { 393 assert(Imm < (1 << 9) && "9-bit encoding"); 394 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 395 return addOperand( 396 Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true)); 397 } 398 399 static DecodeStatus 400 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 401 const MCDisassembler *Decoder) { 402 return decodeOperand_AVLdSt_Any(Inst, Imm, 403 AMDGPUDisassembler::OPW32, Decoder); 404 } 405 406 static DecodeStatus 407 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 408 const MCDisassembler *Decoder) { 409 return decodeOperand_AVLdSt_Any(Inst, Imm, 410 AMDGPUDisassembler::OPW64, Decoder); 411 } 412 413 static DecodeStatus 414 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 415 const MCDisassembler *Decoder) { 416 return decodeOperand_AVLdSt_Any(Inst, Imm, 417 AMDGPUDisassembler::OPW96, Decoder); 418 } 419 420 static DecodeStatus 421 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 422 const MCDisassembler *Decoder) { 423 return decodeOperand_AVLdSt_Any(Inst, Imm, 424 AMDGPUDisassembler::OPW128, Decoder); 425 } 426 427 static DecodeStatus 428 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 429 const MCDisassembler *Decoder) { 430 return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160, 431 Decoder); 432 } 433 434 #define DECODE_SDWA(DecName) \ 435 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 436 437 DECODE_SDWA(Src32) 438 DECODE_SDWA(Src16) 439 DECODE_SDWA(VopcDst) 440 441 #include "AMDGPUGenDisassemblerTables.inc" 442 443 //===----------------------------------------------------------------------===// 444 // 445 //===----------------------------------------------------------------------===// 446 447 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 448 assert(Bytes.size() >= sizeof(T)); 449 const auto Res = 450 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 451 Bytes = Bytes.slice(sizeof(T)); 452 return Res; 453 } 454 455 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 456 assert(Bytes.size() >= 12); 457 uint64_t Lo = 458 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 459 Bytes = Bytes.slice(8); 460 uint64_t Hi = 461 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 462 Bytes = Bytes.slice(4); 463 return DecoderUInt128(Lo, Hi); 464 } 465 466 // The disassembler is greedy, so we need to check FI operand value to 467 // not parse a dpp if the correct literal is not set. For dpp16 the 468 // autogenerated decoder checks the dpp literal 469 static bool isValidDPP8(const MCInst &MI) { 470 using namespace llvm::AMDGPU::DPP; 471 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 472 assert(FiIdx != -1); 473 if ((unsigned)FiIdx >= MI.getNumOperands()) 474 return false; 475 unsigned Fi = MI.getOperand(FiIdx).getImm(); 476 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 477 } 478 479 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 480 ArrayRef<uint8_t> Bytes_, 481 uint64_t Address, 482 raw_ostream &CS) const { 483 bool IsSDWA = false; 484 485 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 486 Bytes = Bytes_.slice(0, MaxInstBytesNum); 487 488 DecodeStatus Res = MCDisassembler::Fail; 489 do { 490 // ToDo: better to switch encoding length using some bit predicate 491 // but it is unknown yet, so try all we can 492 493 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 494 // encodings 495 if (isGFX11Plus() && Bytes.size() >= 12 ) { 496 DecoderUInt128 DecW = eat12Bytes(Bytes); 497 Res = 498 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 499 MI, DecW, Address, CS); 500 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 501 break; 502 MI = MCInst(); // clear 503 Res = 504 tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696, 505 MI, DecW, Address, CS); 506 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 507 break; 508 MI = MCInst(); // clear 509 510 const auto convertVOPDPP = [&]() { 511 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) { 512 convertVOP3PDPPInst(MI); 513 } else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) { 514 convertVOPCDPPInst(MI); // Special VOP3 case 515 } else { 516 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 517 convertVOP3DPPInst(MI); // Regular VOP3 case 518 } 519 }; 520 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 521 MI, DecW, Address, CS); 522 if (Res) { 523 convertVOPDPP(); 524 break; 525 } 526 Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696, 527 MI, DecW, Address, CS); 528 if (Res) { 529 convertVOPDPP(); 530 break; 531 } 532 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 533 if (Res) 534 break; 535 536 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 537 if (Res) 538 break; 539 } 540 // Reinitialize Bytes 541 Bytes = Bytes_.slice(0, MaxInstBytesNum); 542 543 if (Bytes.size() >= 8) { 544 const uint64_t QW = eatBytes<uint64_t>(Bytes); 545 546 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 547 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 548 if (Res) { 549 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 550 == -1) 551 break; 552 if (convertDPP8Inst(MI) == MCDisassembler::Success) 553 break; 554 MI = MCInst(); // clear 555 } 556 } 557 558 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 559 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 560 break; 561 MI = MCInst(); // clear 562 563 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 564 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 565 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 566 break; 567 MI = MCInst(); // clear 568 569 Res = tryDecodeInst(DecoderTableDPP8GFX1264, 570 DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS); 571 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 572 break; 573 MI = MCInst(); // clear 574 575 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 576 if (Res) break; 577 578 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 579 MI, QW, Address, CS); 580 if (Res) { 581 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 582 convertVOPCDPPInst(MI); 583 break; 584 } 585 586 Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664, 587 MI, QW, Address, CS); 588 if (Res) { 589 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 590 convertVOPCDPPInst(MI); 591 break; 592 } 593 594 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 595 if (Res) { IsSDWA = true; break; } 596 597 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 598 if (Res) { IsSDWA = true; break; } 599 600 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 601 if (Res) { IsSDWA = true; break; } 602 603 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 604 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 605 if (Res) 606 break; 607 } 608 609 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 610 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 611 // table first so we print the correct name. 612 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 613 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 614 if (Res) 615 break; 616 } 617 } 618 619 // Reinitialize Bytes as DPP64 could have eaten too much 620 Bytes = Bytes_.slice(0, MaxInstBytesNum); 621 622 // Try decode 32-bit instruction 623 if (Bytes.size() < 4) break; 624 const uint32_t DW = eatBytes<uint32_t>(Bytes); 625 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 626 if (Res) break; 627 628 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 629 if (Res) break; 630 631 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 632 if (Res) break; 633 634 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 635 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 636 if (Res) 637 break; 638 } 639 640 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 641 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 642 if (Res) break; 643 } 644 645 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 646 if (Res) break; 647 648 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 649 Address, CS); 650 if (Res) break; 651 652 Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 653 Address, CS); 654 if (Res) 655 break; 656 657 if (Bytes.size() < 4) break; 658 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 659 660 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 661 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 662 if (Res) 663 break; 664 } 665 666 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 667 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 668 if (Res) 669 break; 670 } 671 672 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 673 if (Res) break; 674 675 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS); 676 if (Res) break; 677 678 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 679 if (Res) break; 680 681 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 682 if (Res) break; 683 684 Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW, 685 Address, CS); 686 if (Res) 687 break; 688 689 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 690 Address, CS); 691 if (Res) 692 break; 693 694 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS); 695 } while (false); 696 697 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 698 // Insert dummy unused src2_modifiers. 699 insertNamedMCOperand(MI, MCOperand::createImm(0), 700 AMDGPU::OpName::src2_modifiers); 701 } 702 703 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 704 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 705 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 706 AMDGPU::OpName::cpol); 707 if (CPolPos != -1) { 708 unsigned CPol = 709 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 710 AMDGPU::CPol::GLC : 0; 711 if (MI.getNumOperands() <= (unsigned)CPolPos) { 712 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 713 AMDGPU::OpName::cpol); 714 } else if (CPol) { 715 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 716 } 717 } 718 } 719 720 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 721 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 722 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 723 // GFX90A lost TFE, its place is occupied by ACC. 724 int TFEOpIdx = 725 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 726 if (TFEOpIdx != -1) { 727 auto TFEIter = MI.begin(); 728 std::advance(TFEIter, TFEOpIdx); 729 MI.insert(TFEIter, MCOperand::createImm(0)); 730 } 731 } 732 733 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 734 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 735 int SWZOpIdx = 736 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 737 if (SWZOpIdx != -1) { 738 auto SWZIter = MI.begin(); 739 std::advance(SWZIter, SWZOpIdx); 740 MI.insert(SWZIter, MCOperand::createImm(0)); 741 } 742 } 743 744 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 745 int VAddr0Idx = 746 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 747 int RsrcIdx = 748 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 749 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 750 if (VAddr0Idx >= 0 && NSAArgs > 0) { 751 unsigned NSAWords = (NSAArgs + 3) / 4; 752 if (Bytes.size() < 4 * NSAWords) { 753 Res = MCDisassembler::Fail; 754 } else { 755 for (unsigned i = 0; i < NSAArgs; ++i) { 756 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 757 auto VAddrRCID = 758 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 759 MI.insert(MI.begin() + VAddrIdx, 760 createRegOperand(VAddrRCID, Bytes[i])); 761 } 762 Bytes = Bytes.slice(4 * NSAWords); 763 } 764 } 765 766 if (Res) 767 Res = convertMIMGInst(MI); 768 } 769 770 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 771 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 772 Res = convertMIMGInst(MI); 773 774 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 775 Res = convertEXPInst(MI); 776 777 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 778 Res = convertVINTERPInst(MI); 779 780 if (Res && IsSDWA) 781 Res = convertSDWAInst(MI); 782 783 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 784 AMDGPU::OpName::vdst_in); 785 if (VDstIn_Idx != -1) { 786 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 787 MCOI::OperandConstraint::TIED_TO); 788 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 789 !MI.getOperand(VDstIn_Idx).isReg() || 790 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 791 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 792 MI.erase(&MI.getOperand(VDstIn_Idx)); 793 insertNamedMCOperand(MI, 794 MCOperand::createReg(MI.getOperand(Tied).getReg()), 795 AMDGPU::OpName::vdst_in); 796 } 797 } 798 799 int ImmLitIdx = 800 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 801 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 802 if (Res && ImmLitIdx != -1 && !IsSOPK) 803 Res = convertFMAanyK(MI, ImmLitIdx); 804 805 // if the opcode was not recognized we'll assume a Size of 4 bytes 806 // (unless there are fewer bytes left) 807 Size = Res ? (MaxInstBytesNum - Bytes.size()) 808 : std::min((size_t)4, Bytes_.size()); 809 return Res; 810 } 811 812 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 813 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 814 // The MCInst still has these fields even though they are no longer encoded 815 // in the GFX11 instruction. 816 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 817 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 818 } 819 return MCDisassembler::Success; 820 } 821 822 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 823 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 824 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 825 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 826 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 827 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 828 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 829 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 830 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 831 // The MCInst has this field that is not directly encoded in the 832 // instruction. 833 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 834 } 835 return MCDisassembler::Success; 836 } 837 838 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 839 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 840 STI.hasFeature(AMDGPU::FeatureGFX10)) { 841 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 842 // VOPC - insert clamp 843 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 844 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 845 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 846 if (SDst != -1) { 847 // VOPC - insert VCC register as sdst 848 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 849 AMDGPU::OpName::sdst); 850 } else { 851 // VOP1/2 - insert omod if present in instruction 852 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 853 } 854 } 855 return MCDisassembler::Success; 856 } 857 858 struct VOPModifiers { 859 unsigned OpSel = 0; 860 unsigned OpSelHi = 0; 861 unsigned NegLo = 0; 862 unsigned NegHi = 0; 863 }; 864 865 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 866 // Note that these values do not affect disassembler output, 867 // so this is only necessary for consistency with src_modifiers. 868 static VOPModifiers collectVOPModifiers(const MCInst &MI, 869 bool IsVOP3P = false) { 870 VOPModifiers Modifiers; 871 unsigned Opc = MI.getOpcode(); 872 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 873 AMDGPU::OpName::src1_modifiers, 874 AMDGPU::OpName::src2_modifiers}; 875 for (int J = 0; J < 3; ++J) { 876 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 877 if (OpIdx == -1) 878 continue; 879 880 unsigned Val = MI.getOperand(OpIdx).getImm(); 881 882 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 883 if (IsVOP3P) { 884 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 885 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 886 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 887 } else if (J == 0) { 888 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 889 } 890 } 891 892 return Modifiers; 893 } 894 895 // MAC opcodes have special old and src2 operands. 896 // src2 is tied to dst, while old is not tied (but assumed to be). 897 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 898 constexpr int DST_IDX = 0; 899 auto Opcode = MI.getOpcode(); 900 const auto &Desc = MCII->get(Opcode); 901 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 902 903 if (OldIdx != -1 && Desc.getOperandConstraint( 904 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 905 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 906 assert(Desc.getOperandConstraint( 907 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 908 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 909 (void)DST_IDX; 910 return true; 911 } 912 913 return false; 914 } 915 916 // Create dummy old operand and insert dummy unused src2_modifiers 917 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 918 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 919 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 920 insertNamedMCOperand(MI, MCOperand::createImm(0), 921 AMDGPU::OpName::src2_modifiers); 922 } 923 924 // We must check FI == literal to reject not genuine dpp8 insts, and we must 925 // first add optional MI operands to check FI 926 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 927 unsigned Opc = MI.getOpcode(); 928 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 929 convertVOP3PDPPInst(MI); 930 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 931 AMDGPU::isVOPC64DPP(Opc)) { 932 convertVOPCDPPInst(MI); 933 } else { 934 if (isMacDPP(MI)) 935 convertMacDPPInst(MI); 936 937 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 938 if (MI.getNumOperands() < DescNumOps && 939 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 940 auto Mods = collectVOPModifiers(MI); 941 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 942 AMDGPU::OpName::op_sel); 943 } else { 944 // Insert dummy unused src modifiers. 945 if (MI.getNumOperands() < DescNumOps && 946 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 947 insertNamedMCOperand(MI, MCOperand::createImm(0), 948 AMDGPU::OpName::src0_modifiers); 949 950 if (MI.getNumOperands() < DescNumOps && 951 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 952 insertNamedMCOperand(MI, MCOperand::createImm(0), 953 AMDGPU::OpName::src1_modifiers); 954 } 955 } 956 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 957 } 958 959 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 960 if (isMacDPP(MI)) 961 convertMacDPPInst(MI); 962 963 unsigned Opc = MI.getOpcode(); 964 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 965 if (MI.getNumOperands() < DescNumOps && 966 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 967 auto Mods = collectVOPModifiers(MI); 968 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 969 AMDGPU::OpName::op_sel); 970 } 971 return MCDisassembler::Success; 972 } 973 974 // Note that before gfx10, the MIMG encoding provided no information about 975 // VADDR size. Consequently, decoded instructions always show address as if it 976 // has 1 dword, which could be not really so. 977 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 978 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 979 980 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 981 AMDGPU::OpName::vdst); 982 983 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 984 AMDGPU::OpName::vdata); 985 int VAddr0Idx = 986 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 987 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 988 : AMDGPU::OpName::rsrc; 989 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 990 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 991 AMDGPU::OpName::dmask); 992 993 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 994 AMDGPU::OpName::tfe); 995 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 996 AMDGPU::OpName::d16); 997 998 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 999 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 1000 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 1001 1002 assert(VDataIdx != -1); 1003 if (BaseOpcode->BVH) { 1004 // Add A16 operand for intersect_ray instructions 1005 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 1006 return MCDisassembler::Success; 1007 } 1008 1009 bool IsAtomic = (VDstIdx != -1); 1010 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 1011 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 1012 bool IsNSA = false; 1013 bool IsPartialNSA = false; 1014 unsigned AddrSize = Info->VAddrDwords; 1015 1016 if (isGFX10Plus()) { 1017 unsigned DimIdx = 1018 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 1019 int A16Idx = 1020 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 1021 const AMDGPU::MIMGDimInfo *Dim = 1022 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 1023 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 1024 1025 AddrSize = 1026 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1027 1028 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1029 // VIMAGE insts other than BVH never use vaddr4. 1030 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1031 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1032 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1033 if (!IsNSA) { 1034 if (!IsVSample && AddrSize > 12) 1035 AddrSize = 16; 1036 } else { 1037 if (AddrSize > Info->VAddrDwords) { 1038 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1039 // The NSA encoding does not contain enough operands for the 1040 // combination of base opcode / dimension. Should this be an error? 1041 return MCDisassembler::Success; 1042 } 1043 IsPartialNSA = true; 1044 } 1045 } 1046 } 1047 1048 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1049 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1050 1051 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1052 if (D16 && AMDGPU::hasPackedD16(STI)) { 1053 DstSize = (DstSize + 1) / 2; 1054 } 1055 1056 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1057 DstSize += 1; 1058 1059 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1060 return MCDisassembler::Success; 1061 1062 int NewOpcode = 1063 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1064 if (NewOpcode == -1) 1065 return MCDisassembler::Success; 1066 1067 // Widen the register to the correct number of enabled channels. 1068 unsigned NewVdata = AMDGPU::NoRegister; 1069 if (DstSize != Info->VDataDwords) { 1070 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1071 1072 // Get first subregister of VData 1073 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1074 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1075 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1076 1077 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1078 &MRI.getRegClass(DataRCID)); 1079 if (NewVdata == AMDGPU::NoRegister) { 1080 // It's possible to encode this such that the low register + enabled 1081 // components exceeds the register count. 1082 return MCDisassembler::Success; 1083 } 1084 } 1085 1086 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1087 // If using partial NSA on GFX11+ widen last address register. 1088 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1089 unsigned NewVAddrSA = AMDGPU::NoRegister; 1090 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1091 AddrSize != Info->VAddrDwords) { 1092 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1093 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1094 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1095 1096 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1097 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1098 &MRI.getRegClass(AddrRCID)); 1099 if (!NewVAddrSA) 1100 return MCDisassembler::Success; 1101 } 1102 1103 MI.setOpcode(NewOpcode); 1104 1105 if (NewVdata != AMDGPU::NoRegister) { 1106 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1107 1108 if (IsAtomic) { 1109 // Atomic operations have an additional operand (a copy of data) 1110 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1111 } 1112 } 1113 1114 if (NewVAddrSA) { 1115 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1116 } else if (IsNSA) { 1117 assert(AddrSize <= Info->VAddrDwords); 1118 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1119 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1120 } 1121 1122 return MCDisassembler::Success; 1123 } 1124 1125 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1126 // decoder only adds to src_modifiers, so manually add the bits to the other 1127 // operands. 1128 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1129 unsigned Opc = MI.getOpcode(); 1130 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1131 auto Mods = collectVOPModifiers(MI, true); 1132 1133 if (MI.getNumOperands() < DescNumOps && 1134 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1135 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1136 1137 if (MI.getNumOperands() < DescNumOps && 1138 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1139 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1140 AMDGPU::OpName::op_sel); 1141 if (MI.getNumOperands() < DescNumOps && 1142 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1143 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1144 AMDGPU::OpName::op_sel_hi); 1145 if (MI.getNumOperands() < DescNumOps && 1146 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1147 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1148 AMDGPU::OpName::neg_lo); 1149 if (MI.getNumOperands() < DescNumOps && 1150 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1151 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1152 AMDGPU::OpName::neg_hi); 1153 1154 return MCDisassembler::Success; 1155 } 1156 1157 // Create dummy old operand and insert optional operands 1158 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1159 unsigned Opc = MI.getOpcode(); 1160 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1161 1162 if (MI.getNumOperands() < DescNumOps && 1163 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1164 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1165 1166 if (MI.getNumOperands() < DescNumOps && 1167 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1168 insertNamedMCOperand(MI, MCOperand::createImm(0), 1169 AMDGPU::OpName::src0_modifiers); 1170 1171 if (MI.getNumOperands() < DescNumOps && 1172 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1173 insertNamedMCOperand(MI, MCOperand::createImm(0), 1174 AMDGPU::OpName::src1_modifiers); 1175 return MCDisassembler::Success; 1176 } 1177 1178 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1179 int ImmLitIdx) const { 1180 assert(HasLiteral && "Should have decoded a literal"); 1181 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1182 unsigned DescNumOps = Desc.getNumOperands(); 1183 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1184 AMDGPU::OpName::immDeferred); 1185 assert(DescNumOps == MI.getNumOperands()); 1186 for (unsigned I = 0; I < DescNumOps; ++I) { 1187 auto &Op = MI.getOperand(I); 1188 auto OpType = Desc.operands()[I].OperandType; 1189 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1190 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1191 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1192 IsDeferredOp) 1193 Op.setImm(Literal); 1194 } 1195 return MCDisassembler::Success; 1196 } 1197 1198 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1199 return getContext().getRegisterInfo()-> 1200 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1201 } 1202 1203 inline 1204 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1205 const Twine& ErrMsg) const { 1206 *CommentStream << "Error: " + ErrMsg; 1207 1208 // ToDo: add support for error operands to MCInst.h 1209 // return MCOperand::createError(V); 1210 return MCOperand(); 1211 } 1212 1213 inline 1214 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1215 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1216 } 1217 1218 inline 1219 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1220 unsigned Val) const { 1221 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1222 if (Val >= RegCl.getNumRegs()) 1223 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1224 ": unknown register " + Twine(Val)); 1225 return createRegOperand(RegCl.getRegister(Val)); 1226 } 1227 1228 inline 1229 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1230 unsigned Val) const { 1231 // ToDo: SI/CI have 104 SGPRs, VI - 102 1232 // Valery: here we accepting as much as we can, let assembler sort it out 1233 int shift = 0; 1234 switch (SRegClassID) { 1235 case AMDGPU::SGPR_32RegClassID: 1236 case AMDGPU::TTMP_32RegClassID: 1237 break; 1238 case AMDGPU::SGPR_64RegClassID: 1239 case AMDGPU::TTMP_64RegClassID: 1240 shift = 1; 1241 break; 1242 case AMDGPU::SGPR_128RegClassID: 1243 case AMDGPU::TTMP_128RegClassID: 1244 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1245 // this bundle? 1246 case AMDGPU::SGPR_256RegClassID: 1247 case AMDGPU::TTMP_256RegClassID: 1248 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1249 // this bundle? 1250 case AMDGPU::SGPR_288RegClassID: 1251 case AMDGPU::TTMP_288RegClassID: 1252 case AMDGPU::SGPR_320RegClassID: 1253 case AMDGPU::TTMP_320RegClassID: 1254 case AMDGPU::SGPR_352RegClassID: 1255 case AMDGPU::TTMP_352RegClassID: 1256 case AMDGPU::SGPR_384RegClassID: 1257 case AMDGPU::TTMP_384RegClassID: 1258 case AMDGPU::SGPR_512RegClassID: 1259 case AMDGPU::TTMP_512RegClassID: 1260 shift = 2; 1261 break; 1262 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1263 // this bundle? 1264 default: 1265 llvm_unreachable("unhandled register class"); 1266 } 1267 1268 if (Val % (1 << shift)) { 1269 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1270 << ": scalar reg isn't aligned " << Val; 1271 } 1272 1273 return createRegOperand(SRegClassID, Val >> shift); 1274 } 1275 1276 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1277 bool IsHi) const { 1278 unsigned RCID = 1279 IsHi ? AMDGPU::VGPR_HI16RegClassID : AMDGPU::VGPR_LO16RegClassID; 1280 return createRegOperand(RCID, RegIdx); 1281 } 1282 1283 // Decode Literals for insts which always have a literal in the encoding 1284 MCOperand 1285 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1286 if (HasLiteral) { 1287 assert( 1288 AMDGPU::hasVOPD(STI) && 1289 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1290 if (Literal != Val) 1291 return errOperand(Val, "More than one unique literal is illegal"); 1292 } 1293 HasLiteral = true; 1294 Literal = Val; 1295 return MCOperand::createImm(Literal); 1296 } 1297 1298 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1299 // For now all literal constants are supposed to be unsigned integer 1300 // ToDo: deal with signed/unsigned 64-bit integer constants 1301 // ToDo: deal with float/double constants 1302 if (!HasLiteral) { 1303 if (Bytes.size() < 4) { 1304 return errOperand(0, "cannot read literal, inst bytes left " + 1305 Twine(Bytes.size())); 1306 } 1307 HasLiteral = true; 1308 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1309 if (ExtendFP64) 1310 Literal64 <<= 32; 1311 } 1312 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1313 } 1314 1315 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1316 using namespace AMDGPU::EncValues; 1317 1318 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1319 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1320 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1321 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1322 // Cast prevents negative overflow. 1323 } 1324 1325 static int64_t getInlineImmVal32(unsigned Imm) { 1326 switch (Imm) { 1327 case 240: 1328 return llvm::bit_cast<uint32_t>(0.5f); 1329 case 241: 1330 return llvm::bit_cast<uint32_t>(-0.5f); 1331 case 242: 1332 return llvm::bit_cast<uint32_t>(1.0f); 1333 case 243: 1334 return llvm::bit_cast<uint32_t>(-1.0f); 1335 case 244: 1336 return llvm::bit_cast<uint32_t>(2.0f); 1337 case 245: 1338 return llvm::bit_cast<uint32_t>(-2.0f); 1339 case 246: 1340 return llvm::bit_cast<uint32_t>(4.0f); 1341 case 247: 1342 return llvm::bit_cast<uint32_t>(-4.0f); 1343 case 248: // 1 / (2 * PI) 1344 return 0x3e22f983; 1345 default: 1346 llvm_unreachable("invalid fp inline imm"); 1347 } 1348 } 1349 1350 static int64_t getInlineImmVal64(unsigned Imm) { 1351 switch (Imm) { 1352 case 240: 1353 return llvm::bit_cast<uint64_t>(0.5); 1354 case 241: 1355 return llvm::bit_cast<uint64_t>(-0.5); 1356 case 242: 1357 return llvm::bit_cast<uint64_t>(1.0); 1358 case 243: 1359 return llvm::bit_cast<uint64_t>(-1.0); 1360 case 244: 1361 return llvm::bit_cast<uint64_t>(2.0); 1362 case 245: 1363 return llvm::bit_cast<uint64_t>(-2.0); 1364 case 246: 1365 return llvm::bit_cast<uint64_t>(4.0); 1366 case 247: 1367 return llvm::bit_cast<uint64_t>(-4.0); 1368 case 248: // 1 / (2 * PI) 1369 return 0x3fc45f306dc9c882; 1370 default: 1371 llvm_unreachable("invalid fp inline imm"); 1372 } 1373 } 1374 1375 static int64_t getInlineImmVal16(unsigned Imm) { 1376 switch (Imm) { 1377 case 240: 1378 return 0x3800; 1379 case 241: 1380 return 0xB800; 1381 case 242: 1382 return 0x3C00; 1383 case 243: 1384 return 0xBC00; 1385 case 244: 1386 return 0x4000; 1387 case 245: 1388 return 0xC000; 1389 case 246: 1390 return 0x4400; 1391 case 247: 1392 return 0xC400; 1393 case 248: // 1 / (2 * PI) 1394 return 0x3118; 1395 default: 1396 llvm_unreachable("invalid fp inline imm"); 1397 } 1398 } 1399 1400 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1401 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1402 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1403 1404 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1405 // ImmWidth 0 is a default case where operand should not allow immediates. 1406 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1407 // use it to print verbose error message. 1408 switch (ImmWidth) { 1409 case 0: 1410 case 32: 1411 return MCOperand::createImm(getInlineImmVal32(Imm)); 1412 case 64: 1413 return MCOperand::createImm(getInlineImmVal64(Imm)); 1414 case 16: 1415 return MCOperand::createImm(getInlineImmVal16(Imm)); 1416 default: 1417 llvm_unreachable("implement me"); 1418 } 1419 } 1420 1421 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1422 using namespace AMDGPU; 1423 1424 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1425 switch (Width) { 1426 default: // fall 1427 case OPW32: 1428 case OPW16: 1429 case OPWV216: 1430 return VGPR_32RegClassID; 1431 case OPW64: 1432 case OPWV232: return VReg_64RegClassID; 1433 case OPW96: return VReg_96RegClassID; 1434 case OPW128: return VReg_128RegClassID; 1435 case OPW160: return VReg_160RegClassID; 1436 case OPW256: return VReg_256RegClassID; 1437 case OPW288: return VReg_288RegClassID; 1438 case OPW320: return VReg_320RegClassID; 1439 case OPW352: return VReg_352RegClassID; 1440 case OPW384: return VReg_384RegClassID; 1441 case OPW512: return VReg_512RegClassID; 1442 case OPW1024: return VReg_1024RegClassID; 1443 } 1444 } 1445 1446 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1447 using namespace AMDGPU; 1448 1449 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1450 switch (Width) { 1451 default: // fall 1452 case OPW32: 1453 case OPW16: 1454 case OPWV216: 1455 return AGPR_32RegClassID; 1456 case OPW64: 1457 case OPWV232: return AReg_64RegClassID; 1458 case OPW96: return AReg_96RegClassID; 1459 case OPW128: return AReg_128RegClassID; 1460 case OPW160: return AReg_160RegClassID; 1461 case OPW256: return AReg_256RegClassID; 1462 case OPW288: return AReg_288RegClassID; 1463 case OPW320: return AReg_320RegClassID; 1464 case OPW352: return AReg_352RegClassID; 1465 case OPW384: return AReg_384RegClassID; 1466 case OPW512: return AReg_512RegClassID; 1467 case OPW1024: return AReg_1024RegClassID; 1468 } 1469 } 1470 1471 1472 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1473 using namespace AMDGPU; 1474 1475 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1476 switch (Width) { 1477 default: // fall 1478 case OPW32: 1479 case OPW16: 1480 case OPWV216: 1481 return SGPR_32RegClassID; 1482 case OPW64: 1483 case OPWV232: return SGPR_64RegClassID; 1484 case OPW96: return SGPR_96RegClassID; 1485 case OPW128: return SGPR_128RegClassID; 1486 case OPW160: return SGPR_160RegClassID; 1487 case OPW256: return SGPR_256RegClassID; 1488 case OPW288: return SGPR_288RegClassID; 1489 case OPW320: return SGPR_320RegClassID; 1490 case OPW352: return SGPR_352RegClassID; 1491 case OPW384: return SGPR_384RegClassID; 1492 case OPW512: return SGPR_512RegClassID; 1493 } 1494 } 1495 1496 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1497 using namespace AMDGPU; 1498 1499 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1500 switch (Width) { 1501 default: // fall 1502 case OPW32: 1503 case OPW16: 1504 case OPWV216: 1505 return TTMP_32RegClassID; 1506 case OPW64: 1507 case OPWV232: return TTMP_64RegClassID; 1508 case OPW128: return TTMP_128RegClassID; 1509 case OPW256: return TTMP_256RegClassID; 1510 case OPW288: return TTMP_288RegClassID; 1511 case OPW320: return TTMP_320RegClassID; 1512 case OPW352: return TTMP_352RegClassID; 1513 case OPW384: return TTMP_384RegClassID; 1514 case OPW512: return TTMP_512RegClassID; 1515 } 1516 } 1517 1518 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1519 using namespace AMDGPU::EncValues; 1520 1521 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1522 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1523 1524 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1525 } 1526 1527 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1528 bool MandatoryLiteral, 1529 unsigned ImmWidth, bool IsFP) const { 1530 using namespace AMDGPU::EncValues; 1531 1532 assert(Val < 1024); // enum10 1533 1534 bool IsAGPR = Val & 512; 1535 Val &= 511; 1536 1537 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1538 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1539 : getVgprClassId(Width), Val - VGPR_MIN); 1540 } 1541 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1542 IsFP); 1543 } 1544 1545 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, 1546 unsigned Val, 1547 bool MandatoryLiteral, 1548 unsigned ImmWidth, 1549 bool IsFP) const { 1550 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1551 // decoded earlier. 1552 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1553 using namespace AMDGPU::EncValues; 1554 1555 if (Val <= SGPR_MAX) { 1556 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1557 static_assert(SGPR_MIN == 0); 1558 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1559 } 1560 1561 int TTmpIdx = getTTmpIdx(Val); 1562 if (TTmpIdx >= 0) { 1563 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1564 } 1565 1566 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1567 return decodeIntImmed(Val); 1568 1569 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1570 return decodeFPImmed(ImmWidth, Val); 1571 1572 if (Val == LITERAL_CONST) { 1573 if (MandatoryLiteral) 1574 // Keep a sentinel value for deferred setting 1575 return MCOperand::createImm(LITERAL_CONST); 1576 else 1577 return decodeLiteralConstant(IsFP && ImmWidth == 64); 1578 } 1579 1580 switch (Width) { 1581 case OPW32: 1582 case OPW16: 1583 case OPWV216: 1584 return decodeSpecialReg32(Val); 1585 case OPW64: 1586 case OPWV232: 1587 return decodeSpecialReg64(Val); 1588 default: 1589 llvm_unreachable("unexpected immediate type"); 1590 } 1591 } 1592 1593 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1594 // opposite of bit 0 of DstX. 1595 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1596 unsigned Val) const { 1597 int VDstXInd = 1598 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1599 assert(VDstXInd != -1); 1600 assert(Inst.getOperand(VDstXInd).isReg()); 1601 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1602 Val |= ~XDstReg & 1; 1603 auto Width = llvm::AMDGPUDisassembler::OPW32; 1604 return createRegOperand(getVgprClassId(Width), Val); 1605 } 1606 1607 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1608 using namespace AMDGPU; 1609 1610 switch (Val) { 1611 // clang-format off 1612 case 102: return createRegOperand(FLAT_SCR_LO); 1613 case 103: return createRegOperand(FLAT_SCR_HI); 1614 case 104: return createRegOperand(XNACK_MASK_LO); 1615 case 105: return createRegOperand(XNACK_MASK_HI); 1616 case 106: return createRegOperand(VCC_LO); 1617 case 107: return createRegOperand(VCC_HI); 1618 case 108: return createRegOperand(TBA_LO); 1619 case 109: return createRegOperand(TBA_HI); 1620 case 110: return createRegOperand(TMA_LO); 1621 case 111: return createRegOperand(TMA_HI); 1622 case 124: 1623 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1624 case 125: 1625 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1626 case 126: return createRegOperand(EXEC_LO); 1627 case 127: return createRegOperand(EXEC_HI); 1628 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1629 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1630 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1631 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1632 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1633 case 251: return createRegOperand(SRC_VCCZ); 1634 case 252: return createRegOperand(SRC_EXECZ); 1635 case 253: return createRegOperand(SRC_SCC); 1636 case 254: return createRegOperand(LDS_DIRECT); 1637 default: break; 1638 // clang-format on 1639 } 1640 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1641 } 1642 1643 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1644 using namespace AMDGPU; 1645 1646 switch (Val) { 1647 case 102: return createRegOperand(FLAT_SCR); 1648 case 104: return createRegOperand(XNACK_MASK); 1649 case 106: return createRegOperand(VCC); 1650 case 108: return createRegOperand(TBA); 1651 case 110: return createRegOperand(TMA); 1652 case 124: 1653 if (isGFX11Plus()) 1654 return createRegOperand(SGPR_NULL); 1655 break; 1656 case 125: 1657 if (!isGFX11Plus()) 1658 return createRegOperand(SGPR_NULL); 1659 break; 1660 case 126: return createRegOperand(EXEC); 1661 case 235: return createRegOperand(SRC_SHARED_BASE); 1662 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1663 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1664 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1665 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1666 case 251: return createRegOperand(SRC_VCCZ); 1667 case 252: return createRegOperand(SRC_EXECZ); 1668 case 253: return createRegOperand(SRC_SCC); 1669 default: break; 1670 } 1671 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1672 } 1673 1674 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1675 const unsigned Val, 1676 unsigned ImmWidth) const { 1677 using namespace AMDGPU::SDWA; 1678 using namespace AMDGPU::EncValues; 1679 1680 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1681 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1682 // XXX: cast to int is needed to avoid stupid warning: 1683 // compare with unsigned is always true 1684 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1685 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1686 return createRegOperand(getVgprClassId(Width), 1687 Val - SDWA9EncValues::SRC_VGPR_MIN); 1688 } 1689 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1690 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1691 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1692 return createSRegOperand(getSgprClassId(Width), 1693 Val - SDWA9EncValues::SRC_SGPR_MIN); 1694 } 1695 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1696 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1697 return createSRegOperand(getTtmpClassId(Width), 1698 Val - SDWA9EncValues::SRC_TTMP_MIN); 1699 } 1700 1701 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1702 1703 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1704 return decodeIntImmed(SVal); 1705 1706 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1707 return decodeFPImmed(ImmWidth, SVal); 1708 1709 return decodeSpecialReg32(SVal); 1710 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1711 return createRegOperand(getVgprClassId(Width), Val); 1712 } 1713 llvm_unreachable("unsupported target"); 1714 } 1715 1716 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1717 return decodeSDWASrc(OPW16, Val, 16); 1718 } 1719 1720 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1721 return decodeSDWASrc(OPW32, Val, 32); 1722 } 1723 1724 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1725 using namespace AMDGPU::SDWA; 1726 1727 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1728 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1729 "SDWAVopcDst should be present only on GFX9+"); 1730 1731 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1732 1733 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1734 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1735 1736 int TTmpIdx = getTTmpIdx(Val); 1737 if (TTmpIdx >= 0) { 1738 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1739 return createSRegOperand(TTmpClsId, TTmpIdx); 1740 } else if (Val > SGPR_MAX) { 1741 return IsWave64 ? decodeSpecialReg64(Val) 1742 : decodeSpecialReg32(Val); 1743 } else { 1744 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1745 } 1746 } else { 1747 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1748 } 1749 } 1750 1751 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1752 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1753 ? decodeSrcOp(OPW64, Val) 1754 : decodeSrcOp(OPW32, Val); 1755 } 1756 1757 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1758 return decodeSrcOp(OPW32, Val); 1759 } 1760 1761 bool AMDGPUDisassembler::isVI() const { 1762 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1763 } 1764 1765 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1766 1767 bool AMDGPUDisassembler::isGFX90A() const { 1768 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1769 } 1770 1771 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1772 1773 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1774 1775 bool AMDGPUDisassembler::isGFX10Plus() const { 1776 return AMDGPU::isGFX10Plus(STI); 1777 } 1778 1779 bool AMDGPUDisassembler::isGFX11() const { 1780 return STI.hasFeature(AMDGPU::FeatureGFX11); 1781 } 1782 1783 bool AMDGPUDisassembler::isGFX11Plus() const { 1784 return AMDGPU::isGFX11Plus(STI); 1785 } 1786 1787 bool AMDGPUDisassembler::isGFX12Plus() const { 1788 return AMDGPU::isGFX12Plus(STI); 1789 } 1790 1791 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1792 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1793 } 1794 1795 bool AMDGPUDisassembler::hasKernargPreload() const { 1796 return AMDGPU::hasKernargPreload(STI); 1797 } 1798 1799 //===----------------------------------------------------------------------===// 1800 // AMDGPU specific symbol handling 1801 //===----------------------------------------------------------------------===// 1802 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1803 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1804 do { \ 1805 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1806 } while (0) 1807 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1808 do { \ 1809 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1810 << GET_FIELD(MASK) << '\n'; \ 1811 } while (0) 1812 1813 // NOLINTNEXTLINE(readability-identifier-naming) 1814 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1815 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1816 using namespace amdhsa; 1817 StringRef Indent = "\t"; 1818 1819 // We cannot accurately backward compute #VGPRs used from 1820 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1821 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1822 // simply calculate the inverse of what the assembler does. 1823 1824 uint32_t GranulatedWorkitemVGPRCount = 1825 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1826 1827 uint32_t NextFreeVGPR = 1828 (GranulatedWorkitemVGPRCount + 1) * 1829 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1830 1831 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1832 1833 // We cannot backward compute values used to calculate 1834 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1835 // directives can't be computed: 1836 // .amdhsa_reserve_vcc 1837 // .amdhsa_reserve_flat_scratch 1838 // .amdhsa_reserve_xnack_mask 1839 // They take their respective default values if not specified in the assembly. 1840 // 1841 // GRANULATED_WAVEFRONT_SGPR_COUNT 1842 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1843 // 1844 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1845 // are set to 0. So while disassembling we consider that: 1846 // 1847 // GRANULATED_WAVEFRONT_SGPR_COUNT 1848 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1849 // 1850 // The disassembler cannot recover the original values of those 3 directives. 1851 1852 uint32_t GranulatedWavefrontSGPRCount = 1853 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1854 1855 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1856 return MCDisassembler::Fail; 1857 1858 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1859 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1860 1861 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1862 if (!hasArchitectedFlatScratch()) 1863 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1864 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1865 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1866 1867 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1868 return MCDisassembler::Fail; 1869 1870 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1871 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1872 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1873 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1874 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1875 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1876 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1877 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1878 1879 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1880 return MCDisassembler::Fail; 1881 1882 if (!isGFX12Plus()) 1883 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1884 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1885 1886 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1887 return MCDisassembler::Fail; 1888 1889 if (!isGFX12Plus()) 1890 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1891 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1892 1893 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1894 return MCDisassembler::Fail; 1895 1896 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1897 return MCDisassembler::Fail; 1898 1899 if (isGFX9Plus()) 1900 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1901 1902 if (!isGFX9Plus()) 1903 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1904 return MCDisassembler::Fail; 1905 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1906 return MCDisassembler::Fail; 1907 if (!isGFX10Plus()) 1908 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1909 return MCDisassembler::Fail; 1910 1911 if (isGFX10Plus()) { 1912 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1913 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1914 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1915 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1916 } 1917 1918 if (isGFX12Plus()) 1919 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 1920 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 1921 1922 return MCDisassembler::Success; 1923 } 1924 1925 // NOLINTNEXTLINE(readability-identifier-naming) 1926 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1927 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1928 using namespace amdhsa; 1929 StringRef Indent = "\t"; 1930 if (hasArchitectedFlatScratch()) 1931 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1932 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1933 else 1934 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1935 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1936 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1937 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1938 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1939 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1940 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1941 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1942 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1943 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1944 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1945 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1946 1947 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1948 return MCDisassembler::Fail; 1949 1950 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1951 return MCDisassembler::Fail; 1952 1953 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1954 return MCDisassembler::Fail; 1955 1956 PRINT_DIRECTIVE( 1957 ".amdhsa_exception_fp_ieee_invalid_op", 1958 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1959 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1960 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1961 PRINT_DIRECTIVE( 1962 ".amdhsa_exception_fp_ieee_div_zero", 1963 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1964 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1965 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1966 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1967 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1968 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1969 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1970 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1971 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1972 1973 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1974 return MCDisassembler::Fail; 1975 1976 return MCDisassembler::Success; 1977 } 1978 1979 // NOLINTNEXTLINE(readability-identifier-naming) 1980 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 1981 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1982 using namespace amdhsa; 1983 StringRef Indent = "\t"; 1984 if (isGFX90A()) { 1985 KdStream << Indent << ".amdhsa_accum_offset " 1986 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 1987 << '\n'; 1988 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 1989 return MCDisassembler::Fail; 1990 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 1991 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 1992 return MCDisassembler::Fail; 1993 } else if (isGFX10Plus()) { 1994 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 1995 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 1996 COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1997 } else { 1998 PRINT_PSEUDO_DIRECTIVE_COMMENT( 1999 "SHARED_VGPR_COUNT", COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 2000 } 2001 2002 if (isGFX11Plus()) { 2003 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 2004 COMPUTE_PGM_RSRC3_GFX11_PLUS_INST_PREF_SIZE); 2005 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 2006 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 2007 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 2008 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_END); 2009 } else { 2010 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED0) 2011 return MCDisassembler::Fail; 2012 } 2013 2014 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED1) 2015 return MCDisassembler::Fail; 2016 2017 if (isGFX11Plus()) { 2018 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2019 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 2020 } else { 2021 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED2) 2022 return MCDisassembler::Fail; 2023 } 2024 } else if (FourByteBuffer) { 2025 return MCDisassembler::Fail; 2026 } 2027 return MCDisassembler::Success; 2028 } 2029 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2030 #undef PRINT_DIRECTIVE 2031 #undef GET_FIELD 2032 2033 MCDisassembler::DecodeStatus 2034 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2035 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2036 raw_string_ostream &KdStream) const { 2037 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2038 do { \ 2039 KdStream << Indent << DIRECTIVE " " \ 2040 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2041 } while (0) 2042 2043 uint16_t TwoByteBuffer = 0; 2044 uint32_t FourByteBuffer = 0; 2045 2046 StringRef ReservedBytes; 2047 StringRef Indent = "\t"; 2048 2049 assert(Bytes.size() == 64); 2050 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2051 2052 switch (Cursor.tell()) { 2053 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2054 FourByteBuffer = DE.getU32(Cursor); 2055 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2056 << '\n'; 2057 return MCDisassembler::Success; 2058 2059 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2060 FourByteBuffer = DE.getU32(Cursor); 2061 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2062 << FourByteBuffer << '\n'; 2063 return MCDisassembler::Success; 2064 2065 case amdhsa::KERNARG_SIZE_OFFSET: 2066 FourByteBuffer = DE.getU32(Cursor); 2067 KdStream << Indent << ".amdhsa_kernarg_size " 2068 << FourByteBuffer << '\n'; 2069 return MCDisassembler::Success; 2070 2071 case amdhsa::RESERVED0_OFFSET: 2072 // 4 reserved bytes, must be 0. 2073 ReservedBytes = DE.getBytes(Cursor, 4); 2074 for (int I = 0; I < 4; ++I) { 2075 if (ReservedBytes[I] != 0) { 2076 return MCDisassembler::Fail; 2077 } 2078 } 2079 return MCDisassembler::Success; 2080 2081 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2082 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2083 // So far no directive controls this for Code Object V3, so simply skip for 2084 // disassembly. 2085 DE.skip(Cursor, 8); 2086 return MCDisassembler::Success; 2087 2088 case amdhsa::RESERVED1_OFFSET: 2089 // 20 reserved bytes, must be 0. 2090 ReservedBytes = DE.getBytes(Cursor, 20); 2091 for (int I = 0; I < 20; ++I) { 2092 if (ReservedBytes[I] != 0) { 2093 return MCDisassembler::Fail; 2094 } 2095 } 2096 return MCDisassembler::Success; 2097 2098 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2099 FourByteBuffer = DE.getU32(Cursor); 2100 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2101 2102 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2103 FourByteBuffer = DE.getU32(Cursor); 2104 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2105 2106 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2107 FourByteBuffer = DE.getU32(Cursor); 2108 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2109 2110 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2111 using namespace amdhsa; 2112 TwoByteBuffer = DE.getU16(Cursor); 2113 2114 if (!hasArchitectedFlatScratch()) 2115 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2116 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2117 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2118 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2119 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2120 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2121 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2122 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2123 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2124 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2125 if (!hasArchitectedFlatScratch()) 2126 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2127 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2128 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2129 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2130 2131 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2132 return MCDisassembler::Fail; 2133 2134 // Reserved for GFX9 2135 if (isGFX9() && 2136 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2137 return MCDisassembler::Fail; 2138 } else if (isGFX10Plus()) { 2139 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2140 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2141 } 2142 2143 if (AMDGPU::getAmdhsaCodeObjectVersion() >= AMDGPU::AMDHSA_COV5) 2144 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2145 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2146 2147 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2148 return MCDisassembler::Fail; 2149 2150 return MCDisassembler::Success; 2151 2152 case amdhsa::KERNARG_PRELOAD_OFFSET: 2153 using namespace amdhsa; 2154 TwoByteBuffer = DE.getU16(Cursor); 2155 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2156 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2157 KERNARG_PRELOAD_SPEC_LENGTH); 2158 } 2159 2160 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2161 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2162 KERNARG_PRELOAD_SPEC_OFFSET); 2163 } 2164 return MCDisassembler::Success; 2165 2166 case amdhsa::RESERVED3_OFFSET: 2167 // 4 bytes from here are reserved, must be 0. 2168 ReservedBytes = DE.getBytes(Cursor, 4); 2169 for (int I = 0; I < 4; ++I) { 2170 if (ReservedBytes[I] != 0) 2171 return MCDisassembler::Fail; 2172 } 2173 return MCDisassembler::Success; 2174 2175 default: 2176 llvm_unreachable("Unhandled index. Case statements cover everything."); 2177 return MCDisassembler::Fail; 2178 } 2179 #undef PRINT_DIRECTIVE 2180 } 2181 2182 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2183 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2184 // CP microcode requires the kernel descriptor to be 64 aligned. 2185 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2186 return MCDisassembler::Fail; 2187 2188 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2189 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2190 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2191 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2192 // when required. 2193 if (isGFX10Plus()) { 2194 uint16_t KernelCodeProperties = 2195 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2196 llvm::endianness::little); 2197 EnableWavefrontSize32 = 2198 AMDHSA_BITS_GET(KernelCodeProperties, 2199 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2200 } 2201 2202 std::string Kd; 2203 raw_string_ostream KdStream(Kd); 2204 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2205 2206 DataExtractor::Cursor C(0); 2207 while (C && C.tell() < Bytes.size()) { 2208 MCDisassembler::DecodeStatus Status = 2209 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2210 2211 cantFail(C.takeError()); 2212 2213 if (Status == MCDisassembler::Fail) 2214 return MCDisassembler::Fail; 2215 } 2216 KdStream << ".end_amdhsa_kernel\n"; 2217 outs() << KdStream.str(); 2218 return MCDisassembler::Success; 2219 } 2220 2221 std::optional<MCDisassembler::DecodeStatus> 2222 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2223 ArrayRef<uint8_t> Bytes, uint64_t Address, 2224 raw_ostream &CStream) const { 2225 // Right now only kernel descriptor needs to be handled. 2226 // We ignore all other symbols for target specific handling. 2227 // TODO: 2228 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2229 // Object V2 and V3 when symbols are marked protected. 2230 2231 // amd_kernel_code_t for Code Object V2. 2232 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2233 Size = 256; 2234 return MCDisassembler::Fail; 2235 } 2236 2237 // Code Object V3 kernel descriptors. 2238 StringRef Name = Symbol.Name; 2239 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2240 Size = 64; // Size = 64 regardless of success or failure. 2241 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2242 } 2243 return std::nullopt; 2244 } 2245 2246 //===----------------------------------------------------------------------===// 2247 // AMDGPUSymbolizer 2248 //===----------------------------------------------------------------------===// 2249 2250 // Try to find symbol name for specified label 2251 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2252 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2253 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2254 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2255 2256 if (!IsBranch) { 2257 return false; 2258 } 2259 2260 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2261 if (!Symbols) 2262 return false; 2263 2264 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2265 return Val.Addr == static_cast<uint64_t>(Value) && 2266 Val.Type == ELF::STT_NOTYPE; 2267 }); 2268 if (Result != Symbols->end()) { 2269 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2270 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2271 Inst.addOperand(MCOperand::createExpr(Add)); 2272 return true; 2273 } 2274 // Add to list of referenced addresses, so caller can synthesize a label. 2275 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2276 return false; 2277 } 2278 2279 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2280 int64_t Value, 2281 uint64_t Address) { 2282 llvm_unreachable("unimplemented"); 2283 } 2284 2285 //===----------------------------------------------------------------------===// 2286 // Initialization 2287 //===----------------------------------------------------------------------===// 2288 2289 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2290 LLVMOpInfoCallback /*GetOpInfo*/, 2291 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2292 void *DisInfo, 2293 MCContext *Ctx, 2294 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2295 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2296 } 2297 2298 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2299 const MCSubtargetInfo &STI, 2300 MCContext &Ctx) { 2301 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2302 } 2303 2304 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2305 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2306 createAMDGPUDisassembler); 2307 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2308 createAMDGPUSymbolizer); 2309 } 2310