xref: /llvm-project/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (revision 7847986ceb95eb844369c743685aea6e433fd27e) 
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
19 #include "Disassembler/AMDGPUDisassembler.h"
20 #include "AMDGPU.h"
21 #include "AMDGPURegisterInfo.h"
22 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
23 #include "SIDefines.h"
24 #include "TargetInfo/AMDGPUTargetInfo.h"
25 #include "Utils/AMDGPUBaseInfo.h"
26 #include "llvm-c/Disassembler.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/Twine.h"
30 #include "llvm/BinaryFormat/ELF.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCFixedLenDisassembler.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/Support/Endian.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include <algorithm>
44 #include <cassert>
45 #include <cstddef>
46 #include <cstdint>
47 #include <iterator>
48 #include <tuple>
49 #include <vector>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "amdgpu-disassembler"
54 
55 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
56                             : AMDGPU::EncValues::SGPR_MAX_SI)
57 
58 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
59 
60 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
61                                        MCContext &Ctx,
62                                        MCInstrInfo const *MCII) :
63   MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
64   TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
65 
66   // ToDo: AMDGPUDisassembler supports only VI ISA.
67   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
68     report_fatal_error("Disassembly not yet supported for subtarget");
69 }
70 
71 inline static MCDisassembler::DecodeStatus
72 addOperand(MCInst &Inst, const MCOperand& Opnd) {
73   Inst.addOperand(Opnd);
74   return Opnd.isValid() ?
75     MCDisassembler::Success :
76     MCDisassembler::Fail;
77 }
78 
79 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
80                                 uint16_t NameIdx) {
81   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
82   if (OpIdx != -1) {
83     auto I = MI.begin();
84     std::advance(I, OpIdx);
85     MI.insert(I, Op);
86   }
87   return OpIdx;
88 }
89 
90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
91                                        uint64_t Addr, const void *Decoder) {
92   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
93 
94   // Our branches take a simm16, but we need two extra bits to account for the
95   // factor of 4.
96   APInt SignedOffset(18, Imm * 4, true);
97   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
98 
99   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
100     return MCDisassembler::Success;
101   return addOperand(Inst, MCOperand::createImm(Imm));
102 }
103 
104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
105                                   uint64_t Addr, const void *Decoder) {
106   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
107   return addOperand(Inst, DAsm->decodeBoolReg(Val));
108 }
109 
110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
111 static DecodeStatus StaticDecoderName(MCInst &Inst, \
112                                        unsigned Imm, \
113                                        uint64_t /*Addr*/, \
114                                        const void *Decoder) { \
115   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
116   return addOperand(Inst, DAsm->DecoderName(Imm)); \
117 }
118 
119 #define DECODE_OPERAND_REG(RegClass) \
120 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
121 
122 DECODE_OPERAND_REG(VGPR_32)
123 DECODE_OPERAND_REG(VRegOrLds_32)
124 DECODE_OPERAND_REG(VS_32)
125 DECODE_OPERAND_REG(VS_64)
126 DECODE_OPERAND_REG(VS_128)
127 
128 DECODE_OPERAND_REG(VReg_64)
129 DECODE_OPERAND_REG(VReg_96)
130 DECODE_OPERAND_REG(VReg_128)
131 
132 DECODE_OPERAND_REG(SReg_32)
133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
135 DECODE_OPERAND_REG(SRegOrLds_32)
136 DECODE_OPERAND_REG(SReg_64)
137 DECODE_OPERAND_REG(SReg_64_XEXEC)
138 DECODE_OPERAND_REG(SReg_128)
139 DECODE_OPERAND_REG(SReg_256)
140 DECODE_OPERAND_REG(SReg_512)
141 
142 DECODE_OPERAND_REG(AGPR_32)
143 DECODE_OPERAND_REG(AReg_128)
144 DECODE_OPERAND_REG(AReg_512)
145 DECODE_OPERAND_REG(AReg_1024)
146 DECODE_OPERAND_REG(AV_32)
147 DECODE_OPERAND_REG(AV_64)
148 
149 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
150                                          unsigned Imm,
151                                          uint64_t Addr,
152                                          const void *Decoder) {
153   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
154   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
155 }
156 
157 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
158                                          unsigned Imm,
159                                          uint64_t Addr,
160                                          const void *Decoder) {
161   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
162   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
163 }
164 
165 static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
166                                         unsigned Imm,
167                                         uint64_t Addr,
168                                         const void *Decoder) {
169   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
170   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
171 }
172 
173 static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
174                                         unsigned Imm,
175                                         uint64_t Addr,
176                                         const void *Decoder) {
177   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
178   return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
179 }
180 
181 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
182                                            unsigned Imm,
183                                            uint64_t Addr,
184                                            const void *Decoder) {
185   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
186   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
187 }
188 
189 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
190                                            unsigned Imm,
191                                            uint64_t Addr,
192                                            const void *Decoder) {
193   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
194   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
195 }
196 
197 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
198                                             unsigned Imm,
199                                             uint64_t Addr,
200                                             const void *Decoder) {
201   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
202   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
203 }
204 
205 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
206                                           unsigned Imm,
207                                           uint64_t Addr,
208                                           const void *Decoder) {
209   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
210   return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
211 }
212 
213 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst,
214                                          unsigned Imm,
215                                          uint64_t Addr,
216                                          const void *Decoder) {
217   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
218   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
219 }
220 
221 #define DECODE_SDWA(DecName) \
222 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
223 
224 DECODE_SDWA(Src32)
225 DECODE_SDWA(Src16)
226 DECODE_SDWA(VopcDst)
227 
228 #include "AMDGPUGenDisassemblerTables.inc"
229 
230 //===----------------------------------------------------------------------===//
231 //
232 //===----------------------------------------------------------------------===//
233 
234 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
235   assert(Bytes.size() >= sizeof(T));
236   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
237   Bytes = Bytes.slice(sizeof(T));
238   return Res;
239 }
240 
241 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
242                                                MCInst &MI,
243                                                uint64_t Inst,
244                                                uint64_t Address) const {
245   assert(MI.getOpcode() == 0);
246   assert(MI.getNumOperands() == 0);
247   MCInst TmpInst;
248   HasLiteral = false;
249   const auto SavedBytes = Bytes;
250   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
251     MI = TmpInst;
252     return MCDisassembler::Success;
253   }
254   Bytes = SavedBytes;
255   return MCDisassembler::Fail;
256 }
257 
258 static bool isValidDPP8(const MCInst &MI) {
259   using namespace llvm::AMDGPU::DPP;
260   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
261   assert(FiIdx != -1);
262   if ((unsigned)FiIdx >= MI.getNumOperands())
263     return false;
264   unsigned Fi = MI.getOperand(FiIdx).getImm();
265   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
266 }
267 
268 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
269                                                 ArrayRef<uint8_t> Bytes_,
270                                                 uint64_t Address,
271                                                 raw_ostream &WS,
272                                                 raw_ostream &CS) const {
273   CommentStream = &CS;
274   bool IsSDWA = false;
275 
276   unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
277   Bytes = Bytes_.slice(0, MaxInstBytesNum);
278 
279   DecodeStatus Res = MCDisassembler::Fail;
280   do {
281     // ToDo: better to switch encoding length using some bit predicate
282     // but it is unknown yet, so try all we can
283 
284     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
285     // encodings
286     if (Bytes.size() >= 8) {
287       const uint64_t QW = eatBytes<uint64_t>(Bytes);
288 
289       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
290       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
291         break;
292 
293       MI = MCInst(); // clear
294 
295       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
296       if (Res) break;
297 
298       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
299       if (Res) { IsSDWA = true;  break; }
300 
301       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
302       if (Res) { IsSDWA = true;  break; }
303 
304       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
305       if (Res) { IsSDWA = true;  break; }
306 
307       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
308         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
309         if (Res)
310           break;
311       }
312 
313       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
314       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
315       // table first so we print the correct name.
316       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
317         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
318         if (Res)
319           break;
320       }
321     }
322 
323     // Reinitialize Bytes as DPP64 could have eaten too much
324     Bytes = Bytes_.slice(0, MaxInstBytesNum);
325 
326     // Try decode 32-bit instruction
327     if (Bytes.size() < 4) break;
328     const uint32_t DW = eatBytes<uint32_t>(Bytes);
329     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
330     if (Res) break;
331 
332     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
333     if (Res) break;
334 
335     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
336     if (Res) break;
337 
338     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
339     if (Res) break;
340 
341     if (Bytes.size() < 4) break;
342     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
343     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
344     if (Res) break;
345 
346     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
347     if (Res) break;
348 
349     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
350     if (Res) break;
351 
352     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
353   } while (false);
354 
355   if (Res && (MaxInstBytesNum - Bytes.size()) == 12 && (!HasLiteral ||
356         !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
357     MaxInstBytesNum = 8;
358     Bytes = Bytes_.slice(0, MaxInstBytesNum);
359     eatBytes<uint64_t>(Bytes);
360   }
361 
362   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
363               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
364               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
365               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
366               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
367               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
368               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
369     // Insert dummy unused src2_modifiers.
370     insertNamedMCOperand(MI, MCOperand::createImm(0),
371                          AMDGPU::OpName::src2_modifiers);
372   }
373 
374   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
375     int VAddr0Idx =
376         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
377     int RsrcIdx =
378         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
379     unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
380     if (VAddr0Idx >= 0 && NSAArgs > 0) {
381       unsigned NSAWords = (NSAArgs + 3) / 4;
382       if (Bytes.size() < 4 * NSAWords) {
383         Res = MCDisassembler::Fail;
384       } else {
385         for (unsigned i = 0; i < NSAArgs; ++i) {
386           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
387                     decodeOperand_VGPR_32(Bytes[i]));
388         }
389         Bytes = Bytes.slice(4 * NSAWords);
390       }
391     }
392 
393     if (Res)
394       Res = convertMIMGInst(MI);
395   }
396 
397   if (Res && IsSDWA)
398     Res = convertSDWAInst(MI);
399 
400   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
401                                               AMDGPU::OpName::vdst_in);
402   if (VDstIn_Idx != -1) {
403     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
404                            MCOI::OperandConstraint::TIED_TO);
405     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
406          !MI.getOperand(VDstIn_Idx).isReg() ||
407          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
408       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
409         MI.erase(&MI.getOperand(VDstIn_Idx));
410       insertNamedMCOperand(MI,
411         MCOperand::createReg(MI.getOperand(Tied).getReg()),
412         AMDGPU::OpName::vdst_in);
413     }
414   }
415 
416   // if the opcode was not recognized we'll assume a Size of 4 bytes
417   // (unless there are fewer bytes left)
418   Size = Res ? (MaxInstBytesNum - Bytes.size())
419              : std::min((size_t)4, Bytes_.size());
420   return Res;
421 }
422 
423 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
424   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
425       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
426     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
427       // VOPC - insert clamp
428       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
429   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
430     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
431     if (SDst != -1) {
432       // VOPC - insert VCC register as sdst
433       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
434                            AMDGPU::OpName::sdst);
435     } else {
436       // VOP1/2 - insert omod if present in instruction
437       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
438     }
439   }
440   return MCDisassembler::Success;
441 }
442 
443 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
444   unsigned Opc = MI.getOpcode();
445   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
446 
447   // Insert dummy unused src modifiers.
448   if (MI.getNumOperands() < DescNumOps &&
449       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
450     insertNamedMCOperand(MI, MCOperand::createImm(0),
451                          AMDGPU::OpName::src0_modifiers);
452 
453   if (MI.getNumOperands() < DescNumOps &&
454       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
455     insertNamedMCOperand(MI, MCOperand::createImm(0),
456                          AMDGPU::OpName::src1_modifiers);
457 
458   return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail;
459 }
460 
461 // Note that before gfx10, the MIMG encoding provided no information about
462 // VADDR size. Consequently, decoded instructions always show address as if it
463 // has 1 dword, which could be not really so.
464 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
465 
466   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
467                                            AMDGPU::OpName::vdst);
468 
469   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
470                                             AMDGPU::OpName::vdata);
471   int VAddr0Idx =
472       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
473   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
474                                             AMDGPU::OpName::dmask);
475 
476   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
477                                             AMDGPU::OpName::tfe);
478   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
479                                             AMDGPU::OpName::d16);
480 
481   assert(VDataIdx != -1);
482   assert(DMaskIdx != -1);
483   assert(TFEIdx != -1);
484 
485   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
486   bool IsAtomic = (VDstIdx != -1);
487   bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
488 
489   bool IsNSA = false;
490   unsigned AddrSize = Info->VAddrDwords;
491 
492   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
493     unsigned DimIdx =
494         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
495     const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
496         AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
497     const AMDGPU::MIMGDimInfo *Dim =
498         AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
499 
500     AddrSize = BaseOpcode->NumExtraArgs +
501                (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
502                (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
503                (BaseOpcode->LodOrClampOrMip ? 1 : 0);
504     IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
505     if (!IsNSA) {
506       if (AddrSize > 8)
507         AddrSize = 16;
508       else if (AddrSize > 4)
509         AddrSize = 8;
510     } else {
511       if (AddrSize > Info->VAddrDwords) {
512         // The NSA encoding does not contain enough operands for the combination
513         // of base opcode / dimension. Should this be an error?
514         return MCDisassembler::Success;
515       }
516     }
517   }
518 
519   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
520   unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
521 
522   bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
523   if (D16 && AMDGPU::hasPackedD16(STI)) {
524     DstSize = (DstSize + 1) / 2;
525   }
526 
527   // FIXME: Add tfe support
528   if (MI.getOperand(TFEIdx).getImm())
529     return MCDisassembler::Success;
530 
531   if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
532     return MCDisassembler::Success;
533 
534   int NewOpcode =
535       AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
536   if (NewOpcode == -1)
537     return MCDisassembler::Success;
538 
539   // Widen the register to the correct number of enabled channels.
540   unsigned NewVdata = AMDGPU::NoRegister;
541   if (DstSize != Info->VDataDwords) {
542     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
543 
544     // Get first subregister of VData
545     unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
546     unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
547     Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
548 
549     NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
550                                        &MRI.getRegClass(DataRCID));
551     if (NewVdata == AMDGPU::NoRegister) {
552       // It's possible to encode this such that the low register + enabled
553       // components exceeds the register count.
554       return MCDisassembler::Success;
555     }
556   }
557 
558   unsigned NewVAddr0 = AMDGPU::NoRegister;
559   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
560       AddrSize != Info->VAddrDwords) {
561     unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
562     unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
563     VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
564 
565     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
566     NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
567                                         &MRI.getRegClass(AddrRCID));
568     if (NewVAddr0 == AMDGPU::NoRegister)
569       return MCDisassembler::Success;
570   }
571 
572   MI.setOpcode(NewOpcode);
573 
574   if (NewVdata != AMDGPU::NoRegister) {
575     MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
576 
577     if (IsAtomic) {
578       // Atomic operations have an additional operand (a copy of data)
579       MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
580     }
581   }
582 
583   if (NewVAddr0 != AMDGPU::NoRegister) {
584     MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
585   } else if (IsNSA) {
586     assert(AddrSize <= Info->VAddrDwords);
587     MI.erase(MI.begin() + VAddr0Idx + AddrSize,
588              MI.begin() + VAddr0Idx + Info->VAddrDwords);
589   }
590 
591   return MCDisassembler::Success;
592 }
593 
594 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
595   return getContext().getRegisterInfo()->
596     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
597 }
598 
599 inline
600 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
601                                          const Twine& ErrMsg) const {
602   *CommentStream << "Error: " + ErrMsg;
603 
604   // ToDo: add support for error operands to MCInst.h
605   // return MCOperand::createError(V);
606   return MCOperand();
607 }
608 
609 inline
610 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
611   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
612 }
613 
614 inline
615 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
616                                                unsigned Val) const {
617   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
618   if (Val >= RegCl.getNumRegs())
619     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
620                            ": unknown register " + Twine(Val));
621   return createRegOperand(RegCl.getRegister(Val));
622 }
623 
624 inline
625 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
626                                                 unsigned Val) const {
627   // ToDo: SI/CI have 104 SGPRs, VI - 102
628   // Valery: here we accepting as much as we can, let assembler sort it out
629   int shift = 0;
630   switch (SRegClassID) {
631   case AMDGPU::SGPR_32RegClassID:
632   case AMDGPU::TTMP_32RegClassID:
633     break;
634   case AMDGPU::SGPR_64RegClassID:
635   case AMDGPU::TTMP_64RegClassID:
636     shift = 1;
637     break;
638   case AMDGPU::SGPR_128RegClassID:
639   case AMDGPU::TTMP_128RegClassID:
640   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
641   // this bundle?
642   case AMDGPU::SGPR_256RegClassID:
643   case AMDGPU::TTMP_256RegClassID:
644     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
645   // this bundle?
646   case AMDGPU::SGPR_512RegClassID:
647   case AMDGPU::TTMP_512RegClassID:
648     shift = 2;
649     break;
650   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
651   // this bundle?
652   default:
653     llvm_unreachable("unhandled register class");
654   }
655 
656   if (Val % (1 << shift)) {
657     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
658                    << ": scalar reg isn't aligned " << Val;
659   }
660 
661   return createRegOperand(SRegClassID, Val >> shift);
662 }
663 
664 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
665   return decodeSrcOp(OPW32, Val);
666 }
667 
668 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
669   return decodeSrcOp(OPW64, Val);
670 }
671 
672 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
673   return decodeSrcOp(OPW128, Val);
674 }
675 
676 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
677   return decodeSrcOp(OPW16, Val);
678 }
679 
680 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
681   return decodeSrcOp(OPWV216, Val);
682 }
683 
684 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
685   // Some instructions have operand restrictions beyond what the encoding
686   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
687   // high bit.
688   Val &= 255;
689 
690   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
691 }
692 
693 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
694   return decodeSrcOp(OPW32, Val);
695 }
696 
697 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
698   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
699 }
700 
701 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
702   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
703 }
704 
705 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
706   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
707 }
708 
709 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
710   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
711 }
712 
713 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
714   return decodeSrcOp(OPW32, Val);
715 }
716 
717 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
718   return decodeSrcOp(OPW64, Val);
719 }
720 
721 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
722   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
723 }
724 
725 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
726   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
727 }
728 
729 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
730   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
731 }
732 
733 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
734   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
735 }
736 
737 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
738   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
739 }
740 
741 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
742   // table-gen generated disassembler doesn't care about operand types
743   // leaving only registry class so SSrc_32 operand turns into SReg_32
744   // and therefore we accept immediates and literals here as well
745   return decodeSrcOp(OPW32, Val);
746 }
747 
748 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
749   unsigned Val) const {
750   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
751   return decodeOperand_SReg_32(Val);
752 }
753 
754 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
755   unsigned Val) const {
756   // SReg_32_XM0 is SReg_32 without EXEC_HI
757   return decodeOperand_SReg_32(Val);
758 }
759 
760 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
761   // table-gen generated disassembler doesn't care about operand types
762   // leaving only registry class so SSrc_32 operand turns into SReg_32
763   // and therefore we accept immediates and literals here as well
764   return decodeSrcOp(OPW32, Val);
765 }
766 
767 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
768   return decodeSrcOp(OPW64, Val);
769 }
770 
771 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
772   return decodeSrcOp(OPW64, Val);
773 }
774 
775 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
776   return decodeSrcOp(OPW128, Val);
777 }
778 
779 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
780   return decodeDstOp(OPW256, Val);
781 }
782 
783 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
784   return decodeDstOp(OPW512, Val);
785 }
786 
787 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
788   // For now all literal constants are supposed to be unsigned integer
789   // ToDo: deal with signed/unsigned 64-bit integer constants
790   // ToDo: deal with float/double constants
791   if (!HasLiteral) {
792     if (Bytes.size() < 4) {
793       return errOperand(0, "cannot read literal, inst bytes left " +
794                         Twine(Bytes.size()));
795     }
796     HasLiteral = true;
797     Literal = eatBytes<uint32_t>(Bytes);
798   }
799   return MCOperand::createImm(Literal);
800 }
801 
802 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
803   using namespace AMDGPU::EncValues;
804 
805   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
806   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
807     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
808     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
809       // Cast prevents negative overflow.
810 }
811 
812 static int64_t getInlineImmVal32(unsigned Imm) {
813   switch (Imm) {
814   case 240:
815     return FloatToBits(0.5f);
816   case 241:
817     return FloatToBits(-0.5f);
818   case 242:
819     return FloatToBits(1.0f);
820   case 243:
821     return FloatToBits(-1.0f);
822   case 244:
823     return FloatToBits(2.0f);
824   case 245:
825     return FloatToBits(-2.0f);
826   case 246:
827     return FloatToBits(4.0f);
828   case 247:
829     return FloatToBits(-4.0f);
830   case 248: // 1 / (2 * PI)
831     return 0x3e22f983;
832   default:
833     llvm_unreachable("invalid fp inline imm");
834   }
835 }
836 
837 static int64_t getInlineImmVal64(unsigned Imm) {
838   switch (Imm) {
839   case 240:
840     return DoubleToBits(0.5);
841   case 241:
842     return DoubleToBits(-0.5);
843   case 242:
844     return DoubleToBits(1.0);
845   case 243:
846     return DoubleToBits(-1.0);
847   case 244:
848     return DoubleToBits(2.0);
849   case 245:
850     return DoubleToBits(-2.0);
851   case 246:
852     return DoubleToBits(4.0);
853   case 247:
854     return DoubleToBits(-4.0);
855   case 248: // 1 / (2 * PI)
856     return 0x3fc45f306dc9c882;
857   default:
858     llvm_unreachable("invalid fp inline imm");
859   }
860 }
861 
862 static int64_t getInlineImmVal16(unsigned Imm) {
863   switch (Imm) {
864   case 240:
865     return 0x3800;
866   case 241:
867     return 0xB800;
868   case 242:
869     return 0x3C00;
870   case 243:
871     return 0xBC00;
872   case 244:
873     return 0x4000;
874   case 245:
875     return 0xC000;
876   case 246:
877     return 0x4400;
878   case 247:
879     return 0xC400;
880   case 248: // 1 / (2 * PI)
881     return 0x3118;
882   default:
883     llvm_unreachable("invalid fp inline imm");
884   }
885 }
886 
887 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
888   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
889       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
890 
891   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
892   switch (Width) {
893   case OPW32:
894   case OPW128: // splat constants
895   case OPW512:
896   case OPW1024:
897     return MCOperand::createImm(getInlineImmVal32(Imm));
898   case OPW64:
899     return MCOperand::createImm(getInlineImmVal64(Imm));
900   case OPW16:
901   case OPWV216:
902     return MCOperand::createImm(getInlineImmVal16(Imm));
903   default:
904     llvm_unreachable("implement me");
905   }
906 }
907 
908 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
909   using namespace AMDGPU;
910 
911   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
912   switch (Width) {
913   default: // fall
914   case OPW32:
915   case OPW16:
916   case OPWV216:
917     return VGPR_32RegClassID;
918   case OPW64: return VReg_64RegClassID;
919   case OPW128: return VReg_128RegClassID;
920   }
921 }
922 
923 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
924   using namespace AMDGPU;
925 
926   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
927   switch (Width) {
928   default: // fall
929   case OPW32:
930   case OPW16:
931   case OPWV216:
932     return AGPR_32RegClassID;
933   case OPW64: return AReg_64RegClassID;
934   case OPW128: return AReg_128RegClassID;
935   case OPW512: return AReg_512RegClassID;
936   case OPW1024: return AReg_1024RegClassID;
937   }
938 }
939 
940 
941 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
942   using namespace AMDGPU;
943 
944   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
945   switch (Width) {
946   default: // fall
947   case OPW32:
948   case OPW16:
949   case OPWV216:
950     return SGPR_32RegClassID;
951   case OPW64: return SGPR_64RegClassID;
952   case OPW128: return SGPR_128RegClassID;
953   case OPW256: return SGPR_256RegClassID;
954   case OPW512: return SGPR_512RegClassID;
955   }
956 }
957 
958 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
959   using namespace AMDGPU;
960 
961   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
962   switch (Width) {
963   default: // fall
964   case OPW32:
965   case OPW16:
966   case OPWV216:
967     return TTMP_32RegClassID;
968   case OPW64: return TTMP_64RegClassID;
969   case OPW128: return TTMP_128RegClassID;
970   case OPW256: return TTMP_256RegClassID;
971   case OPW512: return TTMP_512RegClassID;
972   }
973 }
974 
975 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
976   using namespace AMDGPU::EncValues;
977 
978   unsigned TTmpMin =
979       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
980   unsigned TTmpMax =
981       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
982 
983   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
984 }
985 
986 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
987   using namespace AMDGPU::EncValues;
988 
989   assert(Val < 1024); // enum10
990 
991   bool IsAGPR = Val & 512;
992   Val &= 511;
993 
994   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
995     return createRegOperand(IsAGPR ? getAgprClassId(Width)
996                                    : getVgprClassId(Width), Val - VGPR_MIN);
997   }
998   if (Val <= SGPR_MAX) {
999     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1000     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1001   }
1002 
1003   int TTmpIdx = getTTmpIdx(Val);
1004   if (TTmpIdx >= 0) {
1005     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1006   }
1007 
1008   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1009     return decodeIntImmed(Val);
1010 
1011   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1012     return decodeFPImmed(Width, Val);
1013 
1014   if (Val == LITERAL_CONST)
1015     return decodeLiteralConstant();
1016 
1017   switch (Width) {
1018   case OPW32:
1019   case OPW16:
1020   case OPWV216:
1021     return decodeSpecialReg32(Val);
1022   case OPW64:
1023     return decodeSpecialReg64(Val);
1024   default:
1025     llvm_unreachable("unexpected immediate type");
1026   }
1027 }
1028 
1029 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1030   using namespace AMDGPU::EncValues;
1031 
1032   assert(Val < 128);
1033   assert(Width == OPW256 || Width == OPW512);
1034 
1035   if (Val <= SGPR_MAX) {
1036     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1037     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1038   }
1039 
1040   int TTmpIdx = getTTmpIdx(Val);
1041   if (TTmpIdx >= 0) {
1042     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1043   }
1044 
1045   llvm_unreachable("unknown dst register");
1046 }
1047 
1048 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1049   using namespace AMDGPU;
1050 
1051   switch (Val) {
1052   case 102: return createRegOperand(FLAT_SCR_LO);
1053   case 103: return createRegOperand(FLAT_SCR_HI);
1054   case 104: return createRegOperand(XNACK_MASK_LO);
1055   case 105: return createRegOperand(XNACK_MASK_HI);
1056   case 106: return createRegOperand(VCC_LO);
1057   case 107: return createRegOperand(VCC_HI);
1058   case 108: return createRegOperand(TBA_LO);
1059   case 109: return createRegOperand(TBA_HI);
1060   case 110: return createRegOperand(TMA_LO);
1061   case 111: return createRegOperand(TMA_HI);
1062   case 124: return createRegOperand(M0);
1063   case 125: return createRegOperand(SGPR_NULL);
1064   case 126: return createRegOperand(EXEC_LO);
1065   case 127: return createRegOperand(EXEC_HI);
1066   case 235: return createRegOperand(SRC_SHARED_BASE);
1067   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1068   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1069   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1070   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1071   case 251: return createRegOperand(SRC_VCCZ);
1072   case 252: return createRegOperand(SRC_EXECZ);
1073   case 253: return createRegOperand(SRC_SCC);
1074   case 254: return createRegOperand(LDS_DIRECT);
1075   default: break;
1076   }
1077   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1078 }
1079 
1080 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1081   using namespace AMDGPU;
1082 
1083   switch (Val) {
1084   case 102: return createRegOperand(FLAT_SCR);
1085   case 104: return createRegOperand(XNACK_MASK);
1086   case 106: return createRegOperand(VCC);
1087   case 108: return createRegOperand(TBA);
1088   case 110: return createRegOperand(TMA);
1089   case 125: return createRegOperand(SGPR_NULL);
1090   case 126: return createRegOperand(EXEC);
1091   case 235: return createRegOperand(SRC_SHARED_BASE);
1092   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1093   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1094   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1095   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1096   case 251: return createRegOperand(SRC_VCCZ);
1097   case 252: return createRegOperand(SRC_EXECZ);
1098   case 253: return createRegOperand(SRC_SCC);
1099   default: break;
1100   }
1101   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1102 }
1103 
1104 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1105                                             const unsigned Val) const {
1106   using namespace AMDGPU::SDWA;
1107   using namespace AMDGPU::EncValues;
1108 
1109   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1110       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1111     // XXX: cast to int is needed to avoid stupid warning:
1112     // compare with unsigned is always true
1113     if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1114         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1115       return createRegOperand(getVgprClassId(Width),
1116                               Val - SDWA9EncValues::SRC_VGPR_MIN);
1117     }
1118     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1119         Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1120                           : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1121       return createSRegOperand(getSgprClassId(Width),
1122                                Val - SDWA9EncValues::SRC_SGPR_MIN);
1123     }
1124     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1125         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1126       return createSRegOperand(getTtmpClassId(Width),
1127                                Val - SDWA9EncValues::SRC_TTMP_MIN);
1128     }
1129 
1130     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1131 
1132     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1133       return decodeIntImmed(SVal);
1134 
1135     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1136       return decodeFPImmed(Width, SVal);
1137 
1138     return decodeSpecialReg32(SVal);
1139   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1140     return createRegOperand(getVgprClassId(Width), Val);
1141   }
1142   llvm_unreachable("unsupported target");
1143 }
1144 
1145 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1146   return decodeSDWASrc(OPW16, Val);
1147 }
1148 
1149 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1150   return decodeSDWASrc(OPW32, Val);
1151 }
1152 
1153 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1154   using namespace AMDGPU::SDWA;
1155 
1156   assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1157           STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1158          "SDWAVopcDst should be present only on GFX9+");
1159 
1160   bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1161 
1162   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1163     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1164 
1165     int TTmpIdx = getTTmpIdx(Val);
1166     if (TTmpIdx >= 0) {
1167       auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1168       return createSRegOperand(TTmpClsId, TTmpIdx);
1169     } else if (Val > SGPR_MAX) {
1170       return IsWave64 ? decodeSpecialReg64(Val)
1171                       : decodeSpecialReg32(Val);
1172     } else {
1173       return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1174     }
1175   } else {
1176     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1177   }
1178 }
1179 
1180 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1181   return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1182     decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
1183 }
1184 
1185 bool AMDGPUDisassembler::isVI() const {
1186   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1187 }
1188 
1189 bool AMDGPUDisassembler::isGFX9() const {
1190   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1191 }
1192 
1193 bool AMDGPUDisassembler::isGFX10() const {
1194   return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1195 }
1196 
1197 //===----------------------------------------------------------------------===//
1198 // AMDGPUSymbolizer
1199 //===----------------------------------------------------------------------===//
1200 
1201 // Try to find symbol name for specified label
1202 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
1203                                 raw_ostream &/*cStream*/, int64_t Value,
1204                                 uint64_t /*Address*/, bool IsBranch,
1205                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1206   using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>;
1207   using SectionSymbolsTy = std::vector<SymbolInfoTy>;
1208 
1209   if (!IsBranch) {
1210     return false;
1211   }
1212 
1213   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1214   if (!Symbols)
1215     return false;
1216 
1217   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1218                              [Value](const SymbolInfoTy& Val) {
1219                                 return std::get<0>(Val) == static_cast<uint64_t>(Value)
1220                                     && std::get<2>(Val) == ELF::STT_NOTYPE;
1221                              });
1222   if (Result != Symbols->end()) {
1223     auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
1224     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1225     Inst.addOperand(MCOperand::createExpr(Add));
1226     return true;
1227   }
1228   return false;
1229 }
1230 
1231 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
1232                                                        int64_t Value,
1233                                                        uint64_t Address) {
1234   llvm_unreachable("unimplemented");
1235 }
1236 
1237 //===----------------------------------------------------------------------===//
1238 // Initialization
1239 //===----------------------------------------------------------------------===//
1240 
1241 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
1242                               LLVMOpInfoCallback /*GetOpInfo*/,
1243                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
1244                               void *DisInfo,
1245                               MCContext *Ctx,
1246                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1247   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1248 }
1249 
1250 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
1251                                                 const MCSubtargetInfo &STI,
1252                                                 MCContext &Ctx) {
1253   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1254 }
1255 
1256 extern "C" void LLVMInitializeAMDGPUDisassembler() {
1257   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
1258                                          createAMDGPUDisassembler);
1259   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
1260                                        createAMDGPUSymbolizer);
1261 }
1262