1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VGPR_32_Lo128) 123 DECODE_OPERAND_REG(VRegOrLds_32) 124 DECODE_OPERAND_REG(VS_32) 125 DECODE_OPERAND_REG(VS_64) 126 DECODE_OPERAND_REG(VS_128) 127 128 DECODE_OPERAND_REG(VReg_64) 129 DECODE_OPERAND_REG(VReg_96) 130 DECODE_OPERAND_REG(VReg_128) 131 DECODE_OPERAND_REG(VReg_256) 132 DECODE_OPERAND_REG(VReg_512) 133 DECODE_OPERAND_REG(VReg_1024) 134 135 DECODE_OPERAND_REG(SReg_32) 136 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 137 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 138 DECODE_OPERAND_REG(SRegOrLds_32) 139 DECODE_OPERAND_REG(SReg_64) 140 DECODE_OPERAND_REG(SReg_64_XEXEC) 141 DECODE_OPERAND_REG(SReg_128) 142 DECODE_OPERAND_REG(SReg_256) 143 DECODE_OPERAND_REG(SReg_512) 144 145 DECODE_OPERAND_REG(AGPR_32) 146 DECODE_OPERAND_REG(AReg_64) 147 DECODE_OPERAND_REG(AReg_128) 148 DECODE_OPERAND_REG(AReg_256) 149 DECODE_OPERAND_REG(AReg_512) 150 DECODE_OPERAND_REG(AReg_1024) 151 DECODE_OPERAND_REG(AV_32) 152 DECODE_OPERAND_REG(AV_64) 153 DECODE_OPERAND_REG(AV_128) 154 DECODE_OPERAND_REG(AVDst_128) 155 DECODE_OPERAND_REG(AVDst_512) 156 157 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 158 uint64_t Addr, 159 const MCDisassembler *Decoder) { 160 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 161 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 162 } 163 164 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 165 uint64_t Addr, 166 const MCDisassembler *Decoder) { 167 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 168 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 169 } 170 171 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 172 uint64_t Addr, 173 const MCDisassembler *Decoder) { 174 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 175 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 176 } 177 178 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 179 uint64_t Addr, 180 const MCDisassembler *Decoder) { 181 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 182 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 183 } 184 185 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 186 uint64_t Addr, 187 const MCDisassembler *Decoder) { 188 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 189 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 190 } 191 192 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 193 uint64_t Addr, 194 const MCDisassembler *Decoder) { 195 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 196 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 197 } 198 199 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 200 uint64_t Addr, 201 const MCDisassembler *Decoder) { 202 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 203 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 204 } 205 206 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 207 uint64_t Addr, 208 const MCDisassembler *Decoder) { 209 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 210 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 211 } 212 213 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 214 uint64_t Addr, 215 const MCDisassembler *Decoder) { 216 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 217 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 218 } 219 220 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 221 uint64_t Addr, 222 const MCDisassembler *Decoder) { 223 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 224 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 225 } 226 227 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 228 uint64_t Addr, 229 const MCDisassembler *Decoder) { 230 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 231 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 232 } 233 234 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 235 uint64_t Addr, 236 const MCDisassembler *Decoder) { 237 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 238 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 239 } 240 241 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 242 uint64_t Addr, 243 const MCDisassembler *Decoder) { 244 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 245 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 246 } 247 248 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 249 uint64_t Addr, 250 const MCDisassembler *Decoder) { 251 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 252 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 253 } 254 255 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 256 uint64_t Addr, 257 const MCDisassembler *Decoder) { 258 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 259 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 260 } 261 262 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 263 uint64_t Addr, 264 const MCDisassembler *Decoder) { 265 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 266 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 267 } 268 269 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 270 uint64_t Addr, 271 const MCDisassembler *Decoder) { 272 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 273 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 274 } 275 276 static DecodeStatus 277 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 278 const MCDisassembler *Decoder) { 279 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 280 return addOperand( 281 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 282 } 283 284 static DecodeStatus 285 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 286 const MCDisassembler *Decoder) { 287 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 288 return addOperand( 289 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 290 } 291 292 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 293 uint64_t Addr, const void *Decoder) { 294 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 295 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 296 } 297 298 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 299 const MCRegisterInfo *MRI) { 300 if (OpIdx < 0) 301 return false; 302 303 const MCOperand &Op = Inst.getOperand(OpIdx); 304 if (!Op.isReg()) 305 return false; 306 307 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 308 auto Reg = Sub ? Sub : Op.getReg(); 309 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 310 } 311 312 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 313 AMDGPUDisassembler::OpWidthTy Opw, 314 const MCDisassembler *Decoder) { 315 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 316 if (!DAsm->isGFX90A()) { 317 Imm &= 511; 318 } else { 319 // If atomic has both vdata and vdst their register classes are tied. 320 // The bit is decoded along with the vdst, first operand. We need to 321 // change register class to AGPR if vdst was AGPR. 322 // If a DS instruction has both data0 and data1 their register classes 323 // are also tied. 324 unsigned Opc = Inst.getOpcode(); 325 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 326 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 327 : AMDGPU::OpName::vdata; 328 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 329 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 330 if ((int)Inst.getNumOperands() == DataIdx) { 331 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 332 if (IsAGPROperand(Inst, DstIdx, MRI)) 333 Imm |= 512; 334 } 335 336 if (TSFlags & SIInstrFlags::DS) { 337 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 338 if ((int)Inst.getNumOperands() == Data2Idx && 339 IsAGPROperand(Inst, DataIdx, MRI)) 340 Imm |= 512; 341 } 342 } 343 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 344 } 345 346 static DecodeStatus 347 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 348 const MCDisassembler *Decoder) { 349 return decodeOperand_AVLdSt_Any(Inst, Imm, 350 AMDGPUDisassembler::OPW32, Decoder); 351 } 352 353 static DecodeStatus 354 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 355 const MCDisassembler *Decoder) { 356 return decodeOperand_AVLdSt_Any(Inst, Imm, 357 AMDGPUDisassembler::OPW64, Decoder); 358 } 359 360 static DecodeStatus 361 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 362 const MCDisassembler *Decoder) { 363 return decodeOperand_AVLdSt_Any(Inst, Imm, 364 AMDGPUDisassembler::OPW96, Decoder); 365 } 366 367 static DecodeStatus 368 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 369 const MCDisassembler *Decoder) { 370 return decodeOperand_AVLdSt_Any(Inst, Imm, 371 AMDGPUDisassembler::OPW128, Decoder); 372 } 373 374 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 375 uint64_t Addr, 376 const MCDisassembler *Decoder) { 377 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 378 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 379 } 380 381 #define DECODE_SDWA(DecName) \ 382 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 383 384 DECODE_SDWA(Src32) 385 DECODE_SDWA(Src16) 386 DECODE_SDWA(VopcDst) 387 388 #include "AMDGPUGenDisassemblerTables.inc" 389 390 //===----------------------------------------------------------------------===// 391 // 392 //===----------------------------------------------------------------------===// 393 394 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 395 assert(Bytes.size() >= sizeof(T)); 396 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 397 Bytes = Bytes.slice(sizeof(T)); 398 return Res; 399 } 400 401 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 402 assert(Bytes.size() >= 12); 403 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 404 Bytes.data()); 405 Bytes = Bytes.slice(8); 406 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 407 Bytes.data()); 408 Bytes = Bytes.slice(4); 409 return DecoderUInt128(Lo, Hi); 410 } 411 412 // The disassembler is greedy, so we need to check FI operand value to 413 // not parse a dpp if the correct literal is not set. For dpp16 the 414 // autogenerated decoder checks the dpp literal 415 static bool isValidDPP8(const MCInst &MI) { 416 using namespace llvm::AMDGPU::DPP; 417 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 418 assert(FiIdx != -1); 419 if ((unsigned)FiIdx >= MI.getNumOperands()) 420 return false; 421 unsigned Fi = MI.getOperand(FiIdx).getImm(); 422 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 423 } 424 425 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 426 ArrayRef<uint8_t> Bytes_, 427 uint64_t Address, 428 raw_ostream &CS) const { 429 CommentStream = &CS; 430 bool IsSDWA = false; 431 432 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 433 Bytes = Bytes_.slice(0, MaxInstBytesNum); 434 435 DecodeStatus Res = MCDisassembler::Fail; 436 do { 437 // ToDo: better to switch encoding length using some bit predicate 438 // but it is unknown yet, so try all we can 439 440 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 441 // encodings 442 if (isGFX11Plus() && Bytes.size() >= 12 ) { 443 DecoderUInt128 DecW = eat12Bytes(Bytes); 444 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 445 Address); 446 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 447 break; 448 MI = MCInst(); // clear 449 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 450 Address); 451 if (Res) { 452 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 453 convertVOP3PDPPInst(MI); 454 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 455 convertVOPCDPPInst(MI); // Special VOP3 case 456 else { 457 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 458 convertVOP3DPPInst(MI); // Regular VOP3 case 459 } 460 break; 461 } 462 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address); 463 if (Res) 464 break; 465 } 466 // Reinitialize Bytes 467 Bytes = Bytes_.slice(0, MaxInstBytesNum); 468 469 if (Bytes.size() >= 8) { 470 const uint64_t QW = eatBytes<uint64_t>(Bytes); 471 472 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 473 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 474 if (Res) { 475 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 476 == -1) 477 break; 478 if (convertDPP8Inst(MI) == MCDisassembler::Success) 479 break; 480 MI = MCInst(); // clear 481 } 482 } 483 484 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 485 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 486 break; 487 MI = MCInst(); // clear 488 489 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 490 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 491 break; 492 MI = MCInst(); // clear 493 494 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 495 if (Res) break; 496 497 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 498 if (Res) { 499 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 500 convertVOPCDPPInst(MI); 501 break; 502 } 503 504 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 505 if (Res) { IsSDWA = true; break; } 506 507 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 508 if (Res) { IsSDWA = true; break; } 509 510 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 511 if (Res) { IsSDWA = true; break; } 512 513 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 514 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 515 if (Res) 516 break; 517 } 518 519 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 520 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 521 // table first so we print the correct name. 522 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 523 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 524 if (Res) 525 break; 526 } 527 } 528 529 // Reinitialize Bytes as DPP64 could have eaten too much 530 Bytes = Bytes_.slice(0, MaxInstBytesNum); 531 532 // Try decode 32-bit instruction 533 if (Bytes.size() < 4) break; 534 const uint32_t DW = eatBytes<uint32_t>(Bytes); 535 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 536 if (Res) break; 537 538 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 539 if (Res) break; 540 541 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 542 if (Res) break; 543 544 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 545 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 546 if (Res) 547 break; 548 } 549 550 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 551 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 552 if (Res) break; 553 } 554 555 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 556 if (Res) break; 557 558 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 559 if (Res) break; 560 561 if (Bytes.size() < 4) break; 562 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 563 564 if (STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts]) { 565 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address); 566 if (Res) 567 break; 568 } 569 570 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 571 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 572 if (Res) 573 break; 574 } 575 576 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 577 if (Res) break; 578 579 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 580 if (Res) break; 581 582 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 583 if (Res) break; 584 585 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 586 if (Res) break; 587 588 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 589 if (Res) 590 break; 591 592 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address); 593 } while (false); 594 595 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 596 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 597 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 598 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 599 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 600 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 601 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 602 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 603 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 604 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 || 605 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 606 MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || 607 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 || 608 MI.getOpcode() == AMDGPU::V_FMAC_F16_t16_e64_gfx11)) { 609 // Insert dummy unused src2_modifiers. 610 insertNamedMCOperand(MI, MCOperand::createImm(0), 611 AMDGPU::OpName::src2_modifiers); 612 } 613 614 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 615 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 616 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 617 AMDGPU::OpName::cpol); 618 if (CPolPos != -1) { 619 unsigned CPol = 620 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 621 AMDGPU::CPol::GLC : 0; 622 if (MI.getNumOperands() <= (unsigned)CPolPos) { 623 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 624 AMDGPU::OpName::cpol); 625 } else if (CPol) { 626 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 627 } 628 } 629 } 630 631 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 632 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 633 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 634 // GFX90A lost TFE, its place is occupied by ACC. 635 int TFEOpIdx = 636 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 637 if (TFEOpIdx != -1) { 638 auto TFEIter = MI.begin(); 639 std::advance(TFEIter, TFEOpIdx); 640 MI.insert(TFEIter, MCOperand::createImm(0)); 641 } 642 } 643 644 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 645 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 646 int SWZOpIdx = 647 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 648 if (SWZOpIdx != -1) { 649 auto SWZIter = MI.begin(); 650 std::advance(SWZIter, SWZOpIdx); 651 MI.insert(SWZIter, MCOperand::createImm(0)); 652 } 653 } 654 655 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 656 int VAddr0Idx = 657 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 658 int RsrcIdx = 659 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 660 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 661 if (VAddr0Idx >= 0 && NSAArgs > 0) { 662 unsigned NSAWords = (NSAArgs + 3) / 4; 663 if (Bytes.size() < 4 * NSAWords) { 664 Res = MCDisassembler::Fail; 665 } else { 666 for (unsigned i = 0; i < NSAArgs; ++i) { 667 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 668 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 669 MI.insert(MI.begin() + VAddrIdx, 670 createRegOperand(VAddrRCID, Bytes[i])); 671 } 672 Bytes = Bytes.slice(4 * NSAWords); 673 } 674 } 675 676 if (Res) 677 Res = convertMIMGInst(MI); 678 } 679 680 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 681 Res = convertEXPInst(MI); 682 683 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 684 Res = convertVINTERPInst(MI); 685 686 if (Res && IsSDWA) 687 Res = convertSDWAInst(MI); 688 689 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 690 AMDGPU::OpName::vdst_in); 691 if (VDstIn_Idx != -1) { 692 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 693 MCOI::OperandConstraint::TIED_TO); 694 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 695 !MI.getOperand(VDstIn_Idx).isReg() || 696 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 697 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 698 MI.erase(&MI.getOperand(VDstIn_Idx)); 699 insertNamedMCOperand(MI, 700 MCOperand::createReg(MI.getOperand(Tied).getReg()), 701 AMDGPU::OpName::vdst_in); 702 } 703 } 704 705 int ImmLitIdx = 706 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 707 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 708 if (Res && ImmLitIdx != -1 && !IsSOPK) 709 Res = convertFMAanyK(MI, ImmLitIdx); 710 711 // if the opcode was not recognized we'll assume a Size of 4 bytes 712 // (unless there are fewer bytes left) 713 Size = Res ? (MaxInstBytesNum - Bytes.size()) 714 : std::min((size_t)4, Bytes_.size()); 715 return Res; 716 } 717 718 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 719 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 720 // The MCInst still has these fields even though they are no longer encoded 721 // in the GFX11 instruction. 722 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 723 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 724 } 725 return MCDisassembler::Success; 726 } 727 728 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 729 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 730 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 731 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 732 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 733 // The MCInst has this field that is not directly encoded in the 734 // instruction. 735 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 736 } 737 return MCDisassembler::Success; 738 } 739 740 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 741 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 742 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 743 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 744 // VOPC - insert clamp 745 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 746 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 747 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 748 if (SDst != -1) { 749 // VOPC - insert VCC register as sdst 750 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 751 AMDGPU::OpName::sdst); 752 } else { 753 // VOP1/2 - insert omod if present in instruction 754 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 755 } 756 } 757 return MCDisassembler::Success; 758 } 759 760 struct VOPModifiers { 761 unsigned OpSel = 0; 762 unsigned OpSelHi = 0; 763 unsigned NegLo = 0; 764 unsigned NegHi = 0; 765 }; 766 767 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 768 // Note that these values do not affect disassembler output, 769 // so this is only necessary for consistency with src_modifiers. 770 static VOPModifiers collectVOPModifiers(const MCInst &MI, 771 bool IsVOP3P = false) { 772 VOPModifiers Modifiers; 773 unsigned Opc = MI.getOpcode(); 774 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 775 AMDGPU::OpName::src1_modifiers, 776 AMDGPU::OpName::src2_modifiers}; 777 for (int J = 0; J < 3; ++J) { 778 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 779 if (OpIdx == -1) 780 continue; 781 782 unsigned Val = MI.getOperand(OpIdx).getImm(); 783 784 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 785 if (IsVOP3P) { 786 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 787 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 788 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 789 } else if (J == 0) { 790 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 791 } 792 } 793 794 return Modifiers; 795 } 796 797 // MAC opcodes have special old and src2 operands. 798 // src2 is tied to dst, while old is not tied (but assumed to be). 799 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 800 constexpr int DST_IDX = 0; 801 auto Opcode = MI.getOpcode(); 802 const auto &Desc = MCII->get(Opcode); 803 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 804 805 if (OldIdx != -1 && Desc.getOperandConstraint( 806 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 807 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 808 assert(Desc.getOperandConstraint( 809 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 810 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 811 (void)DST_IDX; 812 return true; 813 } 814 815 return false; 816 } 817 818 // Create dummy old operand and insert dummy unused src2_modifiers 819 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 820 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 821 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 822 insertNamedMCOperand(MI, MCOperand::createImm(0), 823 AMDGPU::OpName::src2_modifiers); 824 } 825 826 // We must check FI == literal to reject not genuine dpp8 insts, and we must 827 // first add optional MI operands to check FI 828 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 829 unsigned Opc = MI.getOpcode(); 830 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 831 convertVOP3PDPPInst(MI); 832 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 833 AMDGPU::isVOPC64DPP(Opc)) { 834 convertVOPCDPPInst(MI); 835 } else { 836 if (isMacDPP(MI)) 837 convertMacDPPInst(MI); 838 839 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 840 if (MI.getNumOperands() < DescNumOps && 841 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 842 auto Mods = collectVOPModifiers(MI); 843 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 844 AMDGPU::OpName::op_sel); 845 } else { 846 // Insert dummy unused src modifiers. 847 if (MI.getNumOperands() < DescNumOps && 848 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 849 insertNamedMCOperand(MI, MCOperand::createImm(0), 850 AMDGPU::OpName::src0_modifiers); 851 852 if (MI.getNumOperands() < DescNumOps && 853 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 854 insertNamedMCOperand(MI, MCOperand::createImm(0), 855 AMDGPU::OpName::src1_modifiers); 856 } 857 } 858 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 859 } 860 861 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 862 if (isMacDPP(MI)) 863 convertMacDPPInst(MI); 864 865 unsigned Opc = MI.getOpcode(); 866 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 867 if (MI.getNumOperands() < DescNumOps && 868 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 869 auto Mods = collectVOPModifiers(MI); 870 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 871 AMDGPU::OpName::op_sel); 872 } 873 return MCDisassembler::Success; 874 } 875 876 // Note that before gfx10, the MIMG encoding provided no information about 877 // VADDR size. Consequently, decoded instructions always show address as if it 878 // has 1 dword, which could be not really so. 879 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 880 881 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 882 AMDGPU::OpName::vdst); 883 884 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 885 AMDGPU::OpName::vdata); 886 int VAddr0Idx = 887 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 888 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 889 AMDGPU::OpName::dmask); 890 891 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 892 AMDGPU::OpName::tfe); 893 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 894 AMDGPU::OpName::d16); 895 896 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 897 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 898 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 899 900 assert(VDataIdx != -1); 901 if (BaseOpcode->BVH) { 902 // Add A16 operand for intersect_ray instructions 903 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::a16)) 904 addOperand(MI, MCOperand::createImm(1)); 905 return MCDisassembler::Success; 906 } 907 908 bool IsAtomic = (VDstIdx != -1); 909 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 910 bool IsNSA = false; 911 unsigned AddrSize = Info->VAddrDwords; 912 913 if (isGFX10Plus()) { 914 unsigned DimIdx = 915 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 916 int A16Idx = 917 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 918 const AMDGPU::MIMGDimInfo *Dim = 919 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 920 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 921 922 AddrSize = 923 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 924 925 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 926 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 927 if (!IsNSA) { 928 if (AddrSize > 8) 929 AddrSize = 16; 930 } else { 931 if (AddrSize > Info->VAddrDwords) { 932 // The NSA encoding does not contain enough operands for the combination 933 // of base opcode / dimension. Should this be an error? 934 return MCDisassembler::Success; 935 } 936 } 937 } 938 939 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 940 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 941 942 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 943 if (D16 && AMDGPU::hasPackedD16(STI)) { 944 DstSize = (DstSize + 1) / 2; 945 } 946 947 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 948 DstSize += 1; 949 950 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 951 return MCDisassembler::Success; 952 953 int NewOpcode = 954 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 955 if (NewOpcode == -1) 956 return MCDisassembler::Success; 957 958 // Widen the register to the correct number of enabled channels. 959 unsigned NewVdata = AMDGPU::NoRegister; 960 if (DstSize != Info->VDataDwords) { 961 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 962 963 // Get first subregister of VData 964 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 965 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 966 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 967 968 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 969 &MRI.getRegClass(DataRCID)); 970 if (NewVdata == AMDGPU::NoRegister) { 971 // It's possible to encode this such that the low register + enabled 972 // components exceeds the register count. 973 return MCDisassembler::Success; 974 } 975 } 976 977 // If not using NSA on GFX10+, widen address register to correct size. 978 unsigned NewVAddr0 = AMDGPU::NoRegister; 979 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 980 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 981 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 982 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 983 984 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 985 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 986 &MRI.getRegClass(AddrRCID)); 987 if (NewVAddr0 == AMDGPU::NoRegister) 988 return MCDisassembler::Success; 989 } 990 991 MI.setOpcode(NewOpcode); 992 993 if (NewVdata != AMDGPU::NoRegister) { 994 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 995 996 if (IsAtomic) { 997 // Atomic operations have an additional operand (a copy of data) 998 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 999 } 1000 } 1001 1002 if (NewVAddr0 != AMDGPU::NoRegister) { 1003 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 1004 } else if (IsNSA) { 1005 assert(AddrSize <= Info->VAddrDwords); 1006 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1007 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1008 } 1009 1010 return MCDisassembler::Success; 1011 } 1012 1013 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1014 // decoder only adds to src_modifiers, so manually add the bits to the other 1015 // operands. 1016 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1017 unsigned Opc = MI.getOpcode(); 1018 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1019 auto Mods = collectVOPModifiers(MI, true); 1020 1021 if (MI.getNumOperands() < DescNumOps && 1022 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1023 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1024 1025 if (MI.getNumOperands() < DescNumOps && 1026 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1027 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1028 AMDGPU::OpName::op_sel); 1029 if (MI.getNumOperands() < DescNumOps && 1030 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1031 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1032 AMDGPU::OpName::op_sel_hi); 1033 if (MI.getNumOperands() < DescNumOps && 1034 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1035 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1036 AMDGPU::OpName::neg_lo); 1037 if (MI.getNumOperands() < DescNumOps && 1038 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1039 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1040 AMDGPU::OpName::neg_hi); 1041 1042 return MCDisassembler::Success; 1043 } 1044 1045 // Create dummy old operand and insert optional operands 1046 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1047 unsigned Opc = MI.getOpcode(); 1048 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1049 1050 if (MI.getNumOperands() < DescNumOps && 1051 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1052 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1053 1054 if (MI.getNumOperands() < DescNumOps && 1055 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1056 insertNamedMCOperand(MI, MCOperand::createImm(0), 1057 AMDGPU::OpName::src0_modifiers); 1058 1059 if (MI.getNumOperands() < DescNumOps && 1060 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1061 insertNamedMCOperand(MI, MCOperand::createImm(0), 1062 AMDGPU::OpName::src1_modifiers); 1063 return MCDisassembler::Success; 1064 } 1065 1066 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1067 int ImmLitIdx) const { 1068 assert(HasLiteral && "Should have decoded a literal"); 1069 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1070 unsigned DescNumOps = Desc.getNumOperands(); 1071 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1072 AMDGPU::OpName::immDeferred); 1073 assert(DescNumOps == MI.getNumOperands()); 1074 for (unsigned I = 0; I < DescNumOps; ++I) { 1075 auto &Op = MI.getOperand(I); 1076 auto OpType = Desc.OpInfo[I].OperandType; 1077 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1078 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1079 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1080 IsDeferredOp) 1081 Op.setImm(Literal); 1082 } 1083 return MCDisassembler::Success; 1084 } 1085 1086 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1087 return getContext().getRegisterInfo()-> 1088 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1089 } 1090 1091 inline 1092 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1093 const Twine& ErrMsg) const { 1094 *CommentStream << "Error: " + ErrMsg; 1095 1096 // ToDo: add support for error operands to MCInst.h 1097 // return MCOperand::createError(V); 1098 return MCOperand(); 1099 } 1100 1101 inline 1102 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1103 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1104 } 1105 1106 inline 1107 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1108 unsigned Val) const { 1109 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1110 if (Val >= RegCl.getNumRegs()) 1111 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1112 ": unknown register " + Twine(Val)); 1113 return createRegOperand(RegCl.getRegister(Val)); 1114 } 1115 1116 inline 1117 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1118 unsigned Val) const { 1119 // ToDo: SI/CI have 104 SGPRs, VI - 102 1120 // Valery: here we accepting as much as we can, let assembler sort it out 1121 int shift = 0; 1122 switch (SRegClassID) { 1123 case AMDGPU::SGPR_32RegClassID: 1124 case AMDGPU::TTMP_32RegClassID: 1125 break; 1126 case AMDGPU::SGPR_64RegClassID: 1127 case AMDGPU::TTMP_64RegClassID: 1128 shift = 1; 1129 break; 1130 case AMDGPU::SGPR_128RegClassID: 1131 case AMDGPU::TTMP_128RegClassID: 1132 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1133 // this bundle? 1134 case AMDGPU::SGPR_256RegClassID: 1135 case AMDGPU::TTMP_256RegClassID: 1136 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1137 // this bundle? 1138 case AMDGPU::SGPR_512RegClassID: 1139 case AMDGPU::TTMP_512RegClassID: 1140 shift = 2; 1141 break; 1142 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1143 // this bundle? 1144 default: 1145 llvm_unreachable("unhandled register class"); 1146 } 1147 1148 if (Val % (1 << shift)) { 1149 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1150 << ": scalar reg isn't aligned " << Val; 1151 } 1152 1153 return createRegOperand(SRegClassID, Val >> shift); 1154 } 1155 1156 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 1157 return decodeSrcOp(OPW32, Val); 1158 } 1159 1160 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 1161 return decodeSrcOp(OPW64, Val); 1162 } 1163 1164 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 1165 return decodeSrcOp(OPW128, Val); 1166 } 1167 1168 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 1169 return decodeSrcOp(OPW16, Val); 1170 } 1171 1172 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 1173 return decodeSrcOp(OPWV216, Val); 1174 } 1175 1176 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 1177 return decodeSrcOp(OPWV232, Val); 1178 } 1179 1180 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32_Lo128(unsigned Val) const { 1181 return createRegOperand(AMDGPU::VGPR_32_Lo128RegClassID, Val); 1182 } 1183 1184 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 1185 // Some instructions have operand restrictions beyond what the encoding 1186 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1187 // high bit. 1188 Val &= 255; 1189 1190 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1191 } 1192 1193 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1194 return decodeSrcOp(OPW32, Val); 1195 } 1196 1197 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1198 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1199 } 1200 1201 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1202 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1203 } 1204 1205 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1206 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1207 } 1208 1209 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1210 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1211 } 1212 1213 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1214 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1215 } 1216 1217 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1218 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1219 } 1220 1221 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1222 return decodeSrcOp(OPW32, Val); 1223 } 1224 1225 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1226 return decodeSrcOp(OPW64, Val); 1227 } 1228 1229 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1230 return decodeSrcOp(OPW128, Val); 1231 } 1232 1233 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1234 using namespace AMDGPU::EncValues; 1235 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1236 return decodeSrcOp(OPW128, Val | IS_VGPR); 1237 } 1238 1239 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1240 using namespace AMDGPU::EncValues; 1241 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1242 return decodeSrcOp(OPW512, Val | IS_VGPR); 1243 } 1244 1245 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1246 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1247 } 1248 1249 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1250 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1251 } 1252 1253 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1254 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1255 } 1256 1257 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1258 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1259 } 1260 1261 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1262 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1263 } 1264 1265 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1266 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1267 } 1268 1269 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1270 // table-gen generated disassembler doesn't care about operand types 1271 // leaving only registry class so SSrc_32 operand turns into SReg_32 1272 // and therefore we accept immediates and literals here as well 1273 return decodeSrcOp(OPW32, Val); 1274 } 1275 1276 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1277 unsigned Val) const { 1278 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1279 return decodeOperand_SReg_32(Val); 1280 } 1281 1282 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1283 unsigned Val) const { 1284 // SReg_32_XM0 is SReg_32 without EXEC_HI 1285 return decodeOperand_SReg_32(Val); 1286 } 1287 1288 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1289 // table-gen generated disassembler doesn't care about operand types 1290 // leaving only registry class so SSrc_32 operand turns into SReg_32 1291 // and therefore we accept immediates and literals here as well 1292 return decodeSrcOp(OPW32, Val); 1293 } 1294 1295 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1296 return decodeSrcOp(OPW64, Val); 1297 } 1298 1299 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1300 return decodeSrcOp(OPW64, Val); 1301 } 1302 1303 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1304 return decodeSrcOp(OPW128, Val); 1305 } 1306 1307 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1308 return decodeDstOp(OPW256, Val); 1309 } 1310 1311 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1312 return decodeDstOp(OPW512, Val); 1313 } 1314 1315 // Decode Literals for insts which always have a literal in the encoding 1316 MCOperand 1317 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1318 if (HasLiteral) { 1319 assert( 1320 AMDGPU::hasVOPD(STI) && 1321 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1322 if (Literal != Val) 1323 return errOperand(Val, "More than one unique literal is illegal"); 1324 } 1325 HasLiteral = true; 1326 Literal = Val; 1327 return MCOperand::createImm(Literal); 1328 } 1329 1330 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1331 // For now all literal constants are supposed to be unsigned integer 1332 // ToDo: deal with signed/unsigned 64-bit integer constants 1333 // ToDo: deal with float/double constants 1334 if (!HasLiteral) { 1335 if (Bytes.size() < 4) { 1336 return errOperand(0, "cannot read literal, inst bytes left " + 1337 Twine(Bytes.size())); 1338 } 1339 HasLiteral = true; 1340 Literal = eatBytes<uint32_t>(Bytes); 1341 } 1342 return MCOperand::createImm(Literal); 1343 } 1344 1345 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1346 using namespace AMDGPU::EncValues; 1347 1348 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1349 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1350 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1351 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1352 // Cast prevents negative overflow. 1353 } 1354 1355 static int64_t getInlineImmVal32(unsigned Imm) { 1356 switch (Imm) { 1357 case 240: 1358 return FloatToBits(0.5f); 1359 case 241: 1360 return FloatToBits(-0.5f); 1361 case 242: 1362 return FloatToBits(1.0f); 1363 case 243: 1364 return FloatToBits(-1.0f); 1365 case 244: 1366 return FloatToBits(2.0f); 1367 case 245: 1368 return FloatToBits(-2.0f); 1369 case 246: 1370 return FloatToBits(4.0f); 1371 case 247: 1372 return FloatToBits(-4.0f); 1373 case 248: // 1 / (2 * PI) 1374 return 0x3e22f983; 1375 default: 1376 llvm_unreachable("invalid fp inline imm"); 1377 } 1378 } 1379 1380 static int64_t getInlineImmVal64(unsigned Imm) { 1381 switch (Imm) { 1382 case 240: 1383 return DoubleToBits(0.5); 1384 case 241: 1385 return DoubleToBits(-0.5); 1386 case 242: 1387 return DoubleToBits(1.0); 1388 case 243: 1389 return DoubleToBits(-1.0); 1390 case 244: 1391 return DoubleToBits(2.0); 1392 case 245: 1393 return DoubleToBits(-2.0); 1394 case 246: 1395 return DoubleToBits(4.0); 1396 case 247: 1397 return DoubleToBits(-4.0); 1398 case 248: // 1 / (2 * PI) 1399 return 0x3fc45f306dc9c882; 1400 default: 1401 llvm_unreachable("invalid fp inline imm"); 1402 } 1403 } 1404 1405 static int64_t getInlineImmVal16(unsigned Imm) { 1406 switch (Imm) { 1407 case 240: 1408 return 0x3800; 1409 case 241: 1410 return 0xB800; 1411 case 242: 1412 return 0x3C00; 1413 case 243: 1414 return 0xBC00; 1415 case 244: 1416 return 0x4000; 1417 case 245: 1418 return 0xC000; 1419 case 246: 1420 return 0x4400; 1421 case 247: 1422 return 0xC400; 1423 case 248: // 1 / (2 * PI) 1424 return 0x3118; 1425 default: 1426 llvm_unreachable("invalid fp inline imm"); 1427 } 1428 } 1429 1430 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1431 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1432 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1433 1434 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1435 switch (Width) { 1436 case OPW32: 1437 case OPW128: // splat constants 1438 case OPW512: 1439 case OPW1024: 1440 case OPWV232: 1441 return MCOperand::createImm(getInlineImmVal32(Imm)); 1442 case OPW64: 1443 case OPW256: 1444 return MCOperand::createImm(getInlineImmVal64(Imm)); 1445 case OPW16: 1446 case OPWV216: 1447 return MCOperand::createImm(getInlineImmVal16(Imm)); 1448 default: 1449 llvm_unreachable("implement me"); 1450 } 1451 } 1452 1453 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1454 using namespace AMDGPU; 1455 1456 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1457 switch (Width) { 1458 default: // fall 1459 case OPW32: 1460 case OPW16: 1461 case OPWV216: 1462 return VGPR_32RegClassID; 1463 case OPW64: 1464 case OPWV232: return VReg_64RegClassID; 1465 case OPW96: return VReg_96RegClassID; 1466 case OPW128: return VReg_128RegClassID; 1467 case OPW160: return VReg_160RegClassID; 1468 case OPW256: return VReg_256RegClassID; 1469 case OPW512: return VReg_512RegClassID; 1470 case OPW1024: return VReg_1024RegClassID; 1471 } 1472 } 1473 1474 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1475 using namespace AMDGPU; 1476 1477 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1478 switch (Width) { 1479 default: // fall 1480 case OPW32: 1481 case OPW16: 1482 case OPWV216: 1483 return AGPR_32RegClassID; 1484 case OPW64: 1485 case OPWV232: return AReg_64RegClassID; 1486 case OPW96: return AReg_96RegClassID; 1487 case OPW128: return AReg_128RegClassID; 1488 case OPW160: return AReg_160RegClassID; 1489 case OPW256: return AReg_256RegClassID; 1490 case OPW512: return AReg_512RegClassID; 1491 case OPW1024: return AReg_1024RegClassID; 1492 } 1493 } 1494 1495 1496 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1497 using namespace AMDGPU; 1498 1499 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1500 switch (Width) { 1501 default: // fall 1502 case OPW32: 1503 case OPW16: 1504 case OPWV216: 1505 return SGPR_32RegClassID; 1506 case OPW64: 1507 case OPWV232: return SGPR_64RegClassID; 1508 case OPW96: return SGPR_96RegClassID; 1509 case OPW128: return SGPR_128RegClassID; 1510 case OPW160: return SGPR_160RegClassID; 1511 case OPW256: return SGPR_256RegClassID; 1512 case OPW512: return SGPR_512RegClassID; 1513 } 1514 } 1515 1516 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1517 using namespace AMDGPU; 1518 1519 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1520 switch (Width) { 1521 default: // fall 1522 case OPW32: 1523 case OPW16: 1524 case OPWV216: 1525 return TTMP_32RegClassID; 1526 case OPW64: 1527 case OPWV232: return TTMP_64RegClassID; 1528 case OPW128: return TTMP_128RegClassID; 1529 case OPW256: return TTMP_256RegClassID; 1530 case OPW512: return TTMP_512RegClassID; 1531 } 1532 } 1533 1534 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1535 using namespace AMDGPU::EncValues; 1536 1537 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1538 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1539 1540 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1541 } 1542 1543 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1544 bool MandatoryLiteral) const { 1545 using namespace AMDGPU::EncValues; 1546 1547 assert(Val < 1024); // enum10 1548 1549 bool IsAGPR = Val & 512; 1550 Val &= 511; 1551 1552 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1553 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1554 : getVgprClassId(Width), Val - VGPR_MIN); 1555 } 1556 if (Val <= SGPR_MAX) { 1557 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1558 static_assert(SGPR_MIN == 0); 1559 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1560 } 1561 1562 int TTmpIdx = getTTmpIdx(Val); 1563 if (TTmpIdx >= 0) { 1564 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1565 } 1566 1567 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1568 return decodeIntImmed(Val); 1569 1570 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1571 return decodeFPImmed(Width, Val); 1572 1573 if (Val == LITERAL_CONST) { 1574 if (MandatoryLiteral) 1575 // Keep a sentinel value for deferred setting 1576 return MCOperand::createImm(LITERAL_CONST); 1577 else 1578 return decodeLiteralConstant(); 1579 } 1580 1581 switch (Width) { 1582 case OPW32: 1583 case OPW16: 1584 case OPWV216: 1585 return decodeSpecialReg32(Val); 1586 case OPW64: 1587 case OPWV232: 1588 return decodeSpecialReg64(Val); 1589 default: 1590 llvm_unreachable("unexpected immediate type"); 1591 } 1592 } 1593 1594 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1595 using namespace AMDGPU::EncValues; 1596 1597 assert(Val < 128); 1598 assert(Width == OPW256 || Width == OPW512); 1599 1600 if (Val <= SGPR_MAX) { 1601 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1602 static_assert(SGPR_MIN == 0); 1603 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1604 } 1605 1606 int TTmpIdx = getTTmpIdx(Val); 1607 if (TTmpIdx >= 0) { 1608 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1609 } 1610 1611 llvm_unreachable("unknown dst register"); 1612 } 1613 1614 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1615 // opposite of bit 0 of DstX. 1616 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1617 unsigned Val) const { 1618 int VDstXInd = 1619 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1620 assert(VDstXInd != -1); 1621 assert(Inst.getOperand(VDstXInd).isReg()); 1622 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1623 Val |= ~XDstReg & 1; 1624 auto Width = llvm::AMDGPUDisassembler::OPW32; 1625 return createRegOperand(getVgprClassId(Width), Val); 1626 } 1627 1628 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1629 using namespace AMDGPU; 1630 1631 switch (Val) { 1632 case 102: return createRegOperand(FLAT_SCR_LO); 1633 case 103: return createRegOperand(FLAT_SCR_HI); 1634 case 104: return createRegOperand(XNACK_MASK_LO); 1635 case 105: return createRegOperand(XNACK_MASK_HI); 1636 case 106: return createRegOperand(VCC_LO); 1637 case 107: return createRegOperand(VCC_HI); 1638 case 108: return createRegOperand(TBA_LO); 1639 case 109: return createRegOperand(TBA_HI); 1640 case 110: return createRegOperand(TMA_LO); 1641 case 111: return createRegOperand(TMA_HI); 1642 case 124: 1643 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1644 case 125: 1645 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1646 case 126: return createRegOperand(EXEC_LO); 1647 case 127: return createRegOperand(EXEC_HI); 1648 case 235: return createRegOperand(SRC_SHARED_BASE); 1649 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1650 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1651 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1652 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1653 case 251: return createRegOperand(SRC_VCCZ); 1654 case 252: return createRegOperand(SRC_EXECZ); 1655 case 253: return createRegOperand(SRC_SCC); 1656 case 254: return createRegOperand(LDS_DIRECT); 1657 default: break; 1658 } 1659 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1660 } 1661 1662 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1663 using namespace AMDGPU; 1664 1665 switch (Val) { 1666 case 102: return createRegOperand(FLAT_SCR); 1667 case 104: return createRegOperand(XNACK_MASK); 1668 case 106: return createRegOperand(VCC); 1669 case 108: return createRegOperand(TBA); 1670 case 110: return createRegOperand(TMA); 1671 case 124: 1672 if (isGFX11Plus()) 1673 return createRegOperand(SGPR_NULL); 1674 break; 1675 case 125: 1676 if (!isGFX11Plus()) 1677 return createRegOperand(SGPR_NULL); 1678 break; 1679 case 126: return createRegOperand(EXEC); 1680 case 235: return createRegOperand(SRC_SHARED_BASE); 1681 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1682 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1683 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1684 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1685 case 251: return createRegOperand(SRC_VCCZ); 1686 case 252: return createRegOperand(SRC_EXECZ); 1687 case 253: return createRegOperand(SRC_SCC); 1688 default: break; 1689 } 1690 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1691 } 1692 1693 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1694 const unsigned Val) const { 1695 using namespace AMDGPU::SDWA; 1696 using namespace AMDGPU::EncValues; 1697 1698 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1699 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1700 // XXX: cast to int is needed to avoid stupid warning: 1701 // compare with unsigned is always true 1702 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1703 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1704 return createRegOperand(getVgprClassId(Width), 1705 Val - SDWA9EncValues::SRC_VGPR_MIN); 1706 } 1707 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1708 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1709 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1710 return createSRegOperand(getSgprClassId(Width), 1711 Val - SDWA9EncValues::SRC_SGPR_MIN); 1712 } 1713 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1714 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1715 return createSRegOperand(getTtmpClassId(Width), 1716 Val - SDWA9EncValues::SRC_TTMP_MIN); 1717 } 1718 1719 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1720 1721 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1722 return decodeIntImmed(SVal); 1723 1724 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1725 return decodeFPImmed(Width, SVal); 1726 1727 return decodeSpecialReg32(SVal); 1728 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1729 return createRegOperand(getVgprClassId(Width), Val); 1730 } 1731 llvm_unreachable("unsupported target"); 1732 } 1733 1734 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1735 return decodeSDWASrc(OPW16, Val); 1736 } 1737 1738 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1739 return decodeSDWASrc(OPW32, Val); 1740 } 1741 1742 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1743 using namespace AMDGPU::SDWA; 1744 1745 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1746 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1747 "SDWAVopcDst should be present only on GFX9+"); 1748 1749 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1750 1751 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1752 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1753 1754 int TTmpIdx = getTTmpIdx(Val); 1755 if (TTmpIdx >= 0) { 1756 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1757 return createSRegOperand(TTmpClsId, TTmpIdx); 1758 } else if (Val > SGPR_MAX) { 1759 return IsWave64 ? decodeSpecialReg64(Val) 1760 : decodeSpecialReg32(Val); 1761 } else { 1762 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1763 } 1764 } else { 1765 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1766 } 1767 } 1768 1769 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1770 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1771 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1772 } 1773 1774 bool AMDGPUDisassembler::isVI() const { 1775 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1776 } 1777 1778 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1779 1780 bool AMDGPUDisassembler::isGFX90A() const { 1781 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1782 } 1783 1784 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1785 1786 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1787 1788 bool AMDGPUDisassembler::isGFX10Plus() const { 1789 return AMDGPU::isGFX10Plus(STI); 1790 } 1791 1792 bool AMDGPUDisassembler::isGFX11() const { 1793 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1794 } 1795 1796 bool AMDGPUDisassembler::isGFX11Plus() const { 1797 return AMDGPU::isGFX11Plus(STI); 1798 } 1799 1800 1801 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1802 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1803 } 1804 1805 //===----------------------------------------------------------------------===// 1806 // AMDGPU specific symbol handling 1807 //===----------------------------------------------------------------------===// 1808 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1809 do { \ 1810 KdStream << Indent << DIRECTIVE " " \ 1811 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1812 } while (0) 1813 1814 // NOLINTNEXTLINE(readability-identifier-naming) 1815 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1816 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1817 using namespace amdhsa; 1818 StringRef Indent = "\t"; 1819 1820 // We cannot accurately backward compute #VGPRs used from 1821 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1822 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1823 // simply calculate the inverse of what the assembler does. 1824 1825 uint32_t GranulatedWorkitemVGPRCount = 1826 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1827 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1828 1829 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1830 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1831 1832 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1833 1834 // We cannot backward compute values used to calculate 1835 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1836 // directives can't be computed: 1837 // .amdhsa_reserve_vcc 1838 // .amdhsa_reserve_flat_scratch 1839 // .amdhsa_reserve_xnack_mask 1840 // They take their respective default values if not specified in the assembly. 1841 // 1842 // GRANULATED_WAVEFRONT_SGPR_COUNT 1843 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1844 // 1845 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1846 // are set to 0. So while disassembling we consider that: 1847 // 1848 // GRANULATED_WAVEFRONT_SGPR_COUNT 1849 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1850 // 1851 // The disassembler cannot recover the original values of those 3 directives. 1852 1853 uint32_t GranulatedWavefrontSGPRCount = 1854 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1855 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1856 1857 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1858 return MCDisassembler::Fail; 1859 1860 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1861 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1862 1863 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1864 if (!hasArchitectedFlatScratch()) 1865 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1866 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1867 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1868 1869 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1870 return MCDisassembler::Fail; 1871 1872 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1873 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1874 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1875 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1876 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1877 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1878 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1879 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1880 1881 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1882 return MCDisassembler::Fail; 1883 1884 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1885 1886 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1887 return MCDisassembler::Fail; 1888 1889 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1890 1891 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1892 return MCDisassembler::Fail; 1893 1894 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1895 return MCDisassembler::Fail; 1896 1897 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1898 1899 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1900 return MCDisassembler::Fail; 1901 1902 if (isGFX10Plus()) { 1903 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1904 COMPUTE_PGM_RSRC1_WGP_MODE); 1905 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1906 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1907 } 1908 return MCDisassembler::Success; 1909 } 1910 1911 // NOLINTNEXTLINE(readability-identifier-naming) 1912 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1913 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1914 using namespace amdhsa; 1915 StringRef Indent = "\t"; 1916 if (hasArchitectedFlatScratch()) 1917 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1918 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1919 else 1920 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1921 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1922 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1923 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1924 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1925 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1926 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1927 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1928 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1929 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1930 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1931 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1932 1933 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1934 return MCDisassembler::Fail; 1935 1936 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1937 return MCDisassembler::Fail; 1938 1939 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1940 return MCDisassembler::Fail; 1941 1942 PRINT_DIRECTIVE( 1943 ".amdhsa_exception_fp_ieee_invalid_op", 1944 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1945 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1946 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1947 PRINT_DIRECTIVE( 1948 ".amdhsa_exception_fp_ieee_div_zero", 1949 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1950 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1951 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1952 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1953 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1954 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1955 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1956 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1957 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1958 1959 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1960 return MCDisassembler::Fail; 1961 1962 return MCDisassembler::Success; 1963 } 1964 1965 #undef PRINT_DIRECTIVE 1966 1967 MCDisassembler::DecodeStatus 1968 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1969 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1970 raw_string_ostream &KdStream) const { 1971 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1972 do { \ 1973 KdStream << Indent << DIRECTIVE " " \ 1974 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1975 } while (0) 1976 1977 uint16_t TwoByteBuffer = 0; 1978 uint32_t FourByteBuffer = 0; 1979 1980 StringRef ReservedBytes; 1981 StringRef Indent = "\t"; 1982 1983 assert(Bytes.size() == 64); 1984 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1985 1986 switch (Cursor.tell()) { 1987 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1988 FourByteBuffer = DE.getU32(Cursor); 1989 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1990 << '\n'; 1991 return MCDisassembler::Success; 1992 1993 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1994 FourByteBuffer = DE.getU32(Cursor); 1995 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1996 << FourByteBuffer << '\n'; 1997 return MCDisassembler::Success; 1998 1999 case amdhsa::KERNARG_SIZE_OFFSET: 2000 FourByteBuffer = DE.getU32(Cursor); 2001 KdStream << Indent << ".amdhsa_kernarg_size " 2002 << FourByteBuffer << '\n'; 2003 return MCDisassembler::Success; 2004 2005 case amdhsa::RESERVED0_OFFSET: 2006 // 4 reserved bytes, must be 0. 2007 ReservedBytes = DE.getBytes(Cursor, 4); 2008 for (int I = 0; I < 4; ++I) { 2009 if (ReservedBytes[I] != 0) { 2010 return MCDisassembler::Fail; 2011 } 2012 } 2013 return MCDisassembler::Success; 2014 2015 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2016 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2017 // So far no directive controls this for Code Object V3, so simply skip for 2018 // disassembly. 2019 DE.skip(Cursor, 8); 2020 return MCDisassembler::Success; 2021 2022 case amdhsa::RESERVED1_OFFSET: 2023 // 20 reserved bytes, must be 0. 2024 ReservedBytes = DE.getBytes(Cursor, 20); 2025 for (int I = 0; I < 20; ++I) { 2026 if (ReservedBytes[I] != 0) { 2027 return MCDisassembler::Fail; 2028 } 2029 } 2030 return MCDisassembler::Success; 2031 2032 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2033 // COMPUTE_PGM_RSRC3 2034 // - Only set for GFX10, GFX6-9 have this to be 0. 2035 // - Currently no directives directly control this. 2036 FourByteBuffer = DE.getU32(Cursor); 2037 if (!isGFX10Plus() && FourByteBuffer) { 2038 return MCDisassembler::Fail; 2039 } 2040 return MCDisassembler::Success; 2041 2042 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2043 FourByteBuffer = DE.getU32(Cursor); 2044 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 2045 MCDisassembler::Fail) { 2046 return MCDisassembler::Fail; 2047 } 2048 return MCDisassembler::Success; 2049 2050 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2051 FourByteBuffer = DE.getU32(Cursor); 2052 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 2053 MCDisassembler::Fail) { 2054 return MCDisassembler::Fail; 2055 } 2056 return MCDisassembler::Success; 2057 2058 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2059 using namespace amdhsa; 2060 TwoByteBuffer = DE.getU16(Cursor); 2061 2062 if (!hasArchitectedFlatScratch()) 2063 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2064 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2065 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2066 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2067 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2068 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2069 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2070 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2071 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2072 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2073 if (!hasArchitectedFlatScratch()) 2074 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2075 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2076 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2077 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2078 2079 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2080 return MCDisassembler::Fail; 2081 2082 // Reserved for GFX9 2083 if (isGFX9() && 2084 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2085 return MCDisassembler::Fail; 2086 } else if (isGFX10Plus()) { 2087 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2088 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2089 } 2090 2091 if (AMDGPU::getAmdhsaCodeObjectVersion() >= 5) 2092 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2093 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2094 2095 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2096 return MCDisassembler::Fail; 2097 2098 return MCDisassembler::Success; 2099 2100 case amdhsa::RESERVED2_OFFSET: 2101 // 6 bytes from here are reserved, must be 0. 2102 ReservedBytes = DE.getBytes(Cursor, 6); 2103 for (int I = 0; I < 6; ++I) { 2104 if (ReservedBytes[I] != 0) 2105 return MCDisassembler::Fail; 2106 } 2107 return MCDisassembler::Success; 2108 2109 default: 2110 llvm_unreachable("Unhandled index. Case statements cover everything."); 2111 return MCDisassembler::Fail; 2112 } 2113 #undef PRINT_DIRECTIVE 2114 } 2115 2116 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2117 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2118 // CP microcode requires the kernel descriptor to be 64 aligned. 2119 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2120 return MCDisassembler::Fail; 2121 2122 std::string Kd; 2123 raw_string_ostream KdStream(Kd); 2124 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2125 2126 DataExtractor::Cursor C(0); 2127 while (C && C.tell() < Bytes.size()) { 2128 MCDisassembler::DecodeStatus Status = 2129 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2130 2131 cantFail(C.takeError()); 2132 2133 if (Status == MCDisassembler::Fail) 2134 return MCDisassembler::Fail; 2135 } 2136 KdStream << ".end_amdhsa_kernel\n"; 2137 outs() << KdStream.str(); 2138 return MCDisassembler::Success; 2139 } 2140 2141 Optional<MCDisassembler::DecodeStatus> 2142 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2143 ArrayRef<uint8_t> Bytes, uint64_t Address, 2144 raw_ostream &CStream) const { 2145 // Right now only kernel descriptor needs to be handled. 2146 // We ignore all other symbols for target specific handling. 2147 // TODO: 2148 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2149 // Object V2 and V3 when symbols are marked protected. 2150 2151 // amd_kernel_code_t for Code Object V2. 2152 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2153 Size = 256; 2154 return MCDisassembler::Fail; 2155 } 2156 2157 // Code Object V3 kernel descriptors. 2158 StringRef Name = Symbol.Name; 2159 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2160 Size = 64; // Size = 64 regardless of success or failure. 2161 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2162 } 2163 return None; 2164 } 2165 2166 //===----------------------------------------------------------------------===// 2167 // AMDGPUSymbolizer 2168 //===----------------------------------------------------------------------===// 2169 2170 // Try to find symbol name for specified label 2171 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2172 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2173 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2174 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2175 2176 if (!IsBranch) { 2177 return false; 2178 } 2179 2180 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2181 if (!Symbols) 2182 return false; 2183 2184 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2185 return Val.Addr == static_cast<uint64_t>(Value) && 2186 Val.Type == ELF::STT_NOTYPE; 2187 }); 2188 if (Result != Symbols->end()) { 2189 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2190 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2191 Inst.addOperand(MCOperand::createExpr(Add)); 2192 return true; 2193 } 2194 // Add to list of referenced addresses, so caller can synthesize a label. 2195 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2196 return false; 2197 } 2198 2199 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2200 int64_t Value, 2201 uint64_t Address) { 2202 llvm_unreachable("unimplemented"); 2203 } 2204 2205 //===----------------------------------------------------------------------===// 2206 // Initialization 2207 //===----------------------------------------------------------------------===// 2208 2209 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2210 LLVMOpInfoCallback /*GetOpInfo*/, 2211 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2212 void *DisInfo, 2213 MCContext *Ctx, 2214 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2215 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2216 } 2217 2218 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2219 const MCSubtargetInfo &STI, 2220 MCContext &Ctx) { 2221 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2222 } 2223 2224 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2225 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2226 createAMDGPUDisassembler); 2227 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2228 createAMDGPUSymbolizer); 2229 } 2230