1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "Disassembler/AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "SIDefines.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/Disassembler.h" 26 #include "llvm/ADT/APInt.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/Twine.h" 29 #include "llvm/BinaryFormat/ELF.h" 30 #include "llvm/MC/MCContext.h" 31 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 32 #include "llvm/MC/MCExpr.h" 33 #include "llvm/MC/MCFixedLenDisassembler.h" 34 #include "llvm/MC/MCInst.h" 35 #include "llvm/MC/MCSubtargetInfo.h" 36 #include "llvm/Support/Endian.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/TargetRegistry.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include <algorithm> 42 #include <cassert> 43 #include <cstddef> 44 #include <cstdint> 45 #include <iterator> 46 #include <tuple> 47 #include <vector> 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "amdgpu-disassembler" 52 53 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 54 55 inline static MCDisassembler::DecodeStatus 56 addOperand(MCInst &Inst, const MCOperand& Opnd) { 57 Inst.addOperand(Opnd); 58 return Opnd.isValid() ? 59 MCDisassembler::Success : 60 MCDisassembler::SoftFail; 61 } 62 63 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 64 uint16_t NameIdx) { 65 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 66 if (OpIdx != -1) { 67 auto I = MI.begin(); 68 std::advance(I, OpIdx); 69 MI.insert(I, Op); 70 } 71 return OpIdx; 72 } 73 74 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 75 uint64_t Addr, const void *Decoder) { 76 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 77 78 APInt SignedOffset(18, Imm * 4, true); 79 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 80 81 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 82 return MCDisassembler::Success; 83 return addOperand(Inst, MCOperand::createImm(Imm)); 84 } 85 86 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 87 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 88 unsigned Imm, \ 89 uint64_t /*Addr*/, \ 90 const void *Decoder) { \ 91 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 92 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 93 } 94 95 #define DECODE_OPERAND_REG(RegClass) \ 96 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 97 98 DECODE_OPERAND_REG(VGPR_32) 99 DECODE_OPERAND_REG(VS_32) 100 DECODE_OPERAND_REG(VS_64) 101 DECODE_OPERAND_REG(VS_128) 102 103 DECODE_OPERAND_REG(VReg_64) 104 DECODE_OPERAND_REG(VReg_96) 105 DECODE_OPERAND_REG(VReg_128) 106 107 DECODE_OPERAND_REG(SReg_32) 108 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 109 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 110 DECODE_OPERAND_REG(SReg_64) 111 DECODE_OPERAND_REG(SReg_64_XEXEC) 112 DECODE_OPERAND_REG(SReg_128) 113 DECODE_OPERAND_REG(SReg_256) 114 DECODE_OPERAND_REG(SReg_512) 115 116 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 117 unsigned Imm, 118 uint64_t Addr, 119 const void *Decoder) { 120 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 121 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 122 } 123 124 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 125 unsigned Imm, 126 uint64_t Addr, 127 const void *Decoder) { 128 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 129 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 130 } 131 132 #define DECODE_SDWA(DecName) \ 133 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 134 135 DECODE_SDWA(Src32) 136 DECODE_SDWA(Src16) 137 DECODE_SDWA(VopcDst) 138 139 #include "AMDGPUGenDisassemblerTables.inc" 140 141 //===----------------------------------------------------------------------===// 142 // 143 //===----------------------------------------------------------------------===// 144 145 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 146 assert(Bytes.size() >= sizeof(T)); 147 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 148 Bytes = Bytes.slice(sizeof(T)); 149 return Res; 150 } 151 152 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 153 MCInst &MI, 154 uint64_t Inst, 155 uint64_t Address) const { 156 assert(MI.getOpcode() == 0); 157 assert(MI.getNumOperands() == 0); 158 MCInst TmpInst; 159 HasLiteral = false; 160 const auto SavedBytes = Bytes; 161 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 162 MI = TmpInst; 163 return MCDisassembler::Success; 164 } 165 Bytes = SavedBytes; 166 return MCDisassembler::Fail; 167 } 168 169 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 170 ArrayRef<uint8_t> Bytes_, 171 uint64_t Address, 172 raw_ostream &WS, 173 raw_ostream &CS) const { 174 CommentStream = &CS; 175 bool IsSDWA = false; 176 177 // ToDo: AMDGPUDisassembler supports only VI ISA. 178 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding]) 179 report_fatal_error("Disassembly not yet supported for subtarget"); 180 181 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 182 Bytes = Bytes_.slice(0, MaxInstBytesNum); 183 184 DecodeStatus Res = MCDisassembler::Fail; 185 do { 186 // ToDo: better to switch encoding length using some bit predicate 187 // but it is unknown yet, so try all we can 188 189 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 190 // encodings 191 if (Bytes.size() >= 8) { 192 const uint64_t QW = eatBytes<uint64_t>(Bytes); 193 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 194 if (Res) break; 195 196 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 197 if (Res) { IsSDWA = true; break; } 198 199 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 200 if (Res) { IsSDWA = true; break; } 201 202 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 203 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 204 if (Res) break; 205 } 206 } 207 208 // Reinitialize Bytes as DPP64 could have eaten too much 209 Bytes = Bytes_.slice(0, MaxInstBytesNum); 210 211 // Try decode 32-bit instruction 212 if (Bytes.size() < 4) break; 213 const uint32_t DW = eatBytes<uint32_t>(Bytes); 214 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 215 if (Res) break; 216 217 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 218 if (Res) break; 219 220 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 221 if (Res) break; 222 223 if (Bytes.size() < 4) break; 224 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 225 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 226 if (Res) break; 227 228 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 229 if (Res) break; 230 231 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 232 } while (false); 233 234 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 235 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si || 236 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) { 237 // Insert dummy unused src2_modifiers. 238 insertNamedMCOperand(MI, MCOperand::createImm(0), 239 AMDGPU::OpName::src2_modifiers); 240 } 241 242 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 243 Res = convertMIMGInst(MI); 244 } 245 246 if (Res && IsSDWA) 247 Res = convertSDWAInst(MI); 248 249 // if the opcode was not recognized we'll assume a Size of 4 bytes 250 // (unless there are fewer bytes left) 251 Size = Res ? (MaxInstBytesNum - Bytes.size()) 252 : std::min((size_t)4, Bytes_.size()); 253 return Res; 254 } 255 256 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 257 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 258 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 259 // VOPC - insert clamp 260 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 261 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 262 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 263 if (SDst != -1) { 264 // VOPC - insert VCC register as sdst 265 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 266 AMDGPU::OpName::sdst); 267 } else { 268 // VOP1/2 - insert omod if present in instruction 269 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 270 } 271 } 272 return MCDisassembler::Success; 273 } 274 275 // Note that MIMG format provides no information about VADDR size. 276 // Consequently, decoded instructions always show address 277 // as if it has 1 dword, which could be not really so. 278 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 279 280 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4) { 281 return MCDisassembler::Success; 282 } 283 284 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 285 AMDGPU::OpName::vdst); 286 287 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 288 AMDGPU::OpName::vdata); 289 290 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 291 AMDGPU::OpName::dmask); 292 293 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 294 AMDGPU::OpName::tfe); 295 296 assert(VDataIdx != -1); 297 assert(DMaskIdx != -1); 298 assert(TFEIdx != -1); 299 300 bool IsAtomic = (VDstIdx != -1); 301 302 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 303 if (DMask == 0) 304 return MCDisassembler::Success; 305 306 unsigned DstSize = countPopulation(DMask); 307 if (DstSize == 1) 308 return MCDisassembler::Success; 309 310 bool D16 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::D16; 311 if (D16 && AMDGPU::hasPackedD16(STI)) { 312 DstSize = (DstSize + 1) / 2; 313 } 314 315 // FIXME: Add tfe support 316 if (MI.getOperand(TFEIdx).getImm()) 317 return MCDisassembler::Success; 318 319 int NewOpcode = -1; 320 321 if (IsAtomic) { 322 if (DMask == 0x1 || DMask == 0x3 || DMask == 0xF) { 323 NewOpcode = AMDGPU::getMaskedMIMGAtomicOp(*MCII, MI.getOpcode(), DstSize); 324 } 325 if (NewOpcode == -1) return MCDisassembler::Success; 326 } else { 327 NewOpcode = AMDGPU::getMaskedMIMGOp(*MCII, MI.getOpcode(), DstSize); 328 assert(NewOpcode != -1 && "could not find matching mimg channel instruction"); 329 } 330 331 auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 332 333 // Get first subregister of VData 334 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 335 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 336 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 337 338 // Widen the register to the correct number of enabled channels. 339 auto NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 340 &MRI.getRegClass(RCID)); 341 if (NewVdata == AMDGPU::NoRegister) { 342 // It's possible to encode this such that the low register + enabled 343 // components exceeds the register count. 344 return MCDisassembler::Success; 345 } 346 347 MI.setOpcode(NewOpcode); 348 // vaddr will be always appear as a single VGPR. This will look different than 349 // how it is usually emitted because the number of register components is not 350 // in the instruction encoding. 351 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 352 353 if (IsAtomic) { 354 // Atomic operations have an additional operand (a copy of data) 355 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 356 } 357 358 return MCDisassembler::Success; 359 } 360 361 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 362 return getContext().getRegisterInfo()-> 363 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 364 } 365 366 inline 367 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 368 const Twine& ErrMsg) const { 369 *CommentStream << "Error: " + ErrMsg; 370 371 // ToDo: add support for error operands to MCInst.h 372 // return MCOperand::createError(V); 373 return MCOperand(); 374 } 375 376 inline 377 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 378 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 379 } 380 381 inline 382 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 383 unsigned Val) const { 384 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 385 if (Val >= RegCl.getNumRegs()) 386 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 387 ": unknown register " + Twine(Val)); 388 return createRegOperand(RegCl.getRegister(Val)); 389 } 390 391 inline 392 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 393 unsigned Val) const { 394 // ToDo: SI/CI have 104 SGPRs, VI - 102 395 // Valery: here we accepting as much as we can, let assembler sort it out 396 int shift = 0; 397 switch (SRegClassID) { 398 case AMDGPU::SGPR_32RegClassID: 399 case AMDGPU::TTMP_32RegClassID: 400 break; 401 case AMDGPU::SGPR_64RegClassID: 402 case AMDGPU::TTMP_64RegClassID: 403 shift = 1; 404 break; 405 case AMDGPU::SGPR_128RegClassID: 406 case AMDGPU::TTMP_128RegClassID: 407 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 408 // this bundle? 409 case AMDGPU::SGPR_256RegClassID: 410 case AMDGPU::TTMP_256RegClassID: 411 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 412 // this bundle? 413 case AMDGPU::SGPR_512RegClassID: 414 case AMDGPU::TTMP_512RegClassID: 415 shift = 2; 416 break; 417 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 418 // this bundle? 419 default: 420 llvm_unreachable("unhandled register class"); 421 } 422 423 if (Val % (1 << shift)) { 424 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 425 << ": scalar reg isn't aligned " << Val; 426 } 427 428 return createRegOperand(SRegClassID, Val >> shift); 429 } 430 431 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 432 return decodeSrcOp(OPW32, Val); 433 } 434 435 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 436 return decodeSrcOp(OPW64, Val); 437 } 438 439 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 440 return decodeSrcOp(OPW128, Val); 441 } 442 443 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 444 return decodeSrcOp(OPW16, Val); 445 } 446 447 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 448 return decodeSrcOp(OPWV216, Val); 449 } 450 451 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 452 // Some instructions have operand restrictions beyond what the encoding 453 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 454 // high bit. 455 Val &= 255; 456 457 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 458 } 459 460 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 461 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 462 } 463 464 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 465 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 466 } 467 468 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 469 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 470 } 471 472 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 473 // table-gen generated disassembler doesn't care about operand types 474 // leaving only registry class so SSrc_32 operand turns into SReg_32 475 // and therefore we accept immediates and literals here as well 476 return decodeSrcOp(OPW32, Val); 477 } 478 479 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 480 unsigned Val) const { 481 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 482 return decodeOperand_SReg_32(Val); 483 } 484 485 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 486 unsigned Val) const { 487 // SReg_32_XM0 is SReg_32 without EXEC_HI 488 return decodeOperand_SReg_32(Val); 489 } 490 491 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 492 return decodeSrcOp(OPW64, Val); 493 } 494 495 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 496 return decodeSrcOp(OPW64, Val); 497 } 498 499 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 500 return decodeSrcOp(OPW128, Val); 501 } 502 503 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 504 return decodeDstOp(OPW256, Val); 505 } 506 507 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 508 return decodeDstOp(OPW512, Val); 509 } 510 511 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 512 // For now all literal constants are supposed to be unsigned integer 513 // ToDo: deal with signed/unsigned 64-bit integer constants 514 // ToDo: deal with float/double constants 515 if (!HasLiteral) { 516 if (Bytes.size() < 4) { 517 return errOperand(0, "cannot read literal, inst bytes left " + 518 Twine(Bytes.size())); 519 } 520 HasLiteral = true; 521 Literal = eatBytes<uint32_t>(Bytes); 522 } 523 return MCOperand::createImm(Literal); 524 } 525 526 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 527 using namespace AMDGPU::EncValues; 528 529 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 530 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 531 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 532 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 533 // Cast prevents negative overflow. 534 } 535 536 static int64_t getInlineImmVal32(unsigned Imm) { 537 switch (Imm) { 538 case 240: 539 return FloatToBits(0.5f); 540 case 241: 541 return FloatToBits(-0.5f); 542 case 242: 543 return FloatToBits(1.0f); 544 case 243: 545 return FloatToBits(-1.0f); 546 case 244: 547 return FloatToBits(2.0f); 548 case 245: 549 return FloatToBits(-2.0f); 550 case 246: 551 return FloatToBits(4.0f); 552 case 247: 553 return FloatToBits(-4.0f); 554 case 248: // 1 / (2 * PI) 555 return 0x3e22f983; 556 default: 557 llvm_unreachable("invalid fp inline imm"); 558 } 559 } 560 561 static int64_t getInlineImmVal64(unsigned Imm) { 562 switch (Imm) { 563 case 240: 564 return DoubleToBits(0.5); 565 case 241: 566 return DoubleToBits(-0.5); 567 case 242: 568 return DoubleToBits(1.0); 569 case 243: 570 return DoubleToBits(-1.0); 571 case 244: 572 return DoubleToBits(2.0); 573 case 245: 574 return DoubleToBits(-2.0); 575 case 246: 576 return DoubleToBits(4.0); 577 case 247: 578 return DoubleToBits(-4.0); 579 case 248: // 1 / (2 * PI) 580 return 0x3fc45f306dc9c882; 581 default: 582 llvm_unreachable("invalid fp inline imm"); 583 } 584 } 585 586 static int64_t getInlineImmVal16(unsigned Imm) { 587 switch (Imm) { 588 case 240: 589 return 0x3800; 590 case 241: 591 return 0xB800; 592 case 242: 593 return 0x3C00; 594 case 243: 595 return 0xBC00; 596 case 244: 597 return 0x4000; 598 case 245: 599 return 0xC000; 600 case 246: 601 return 0x4400; 602 case 247: 603 return 0xC400; 604 case 248: // 1 / (2 * PI) 605 return 0x3118; 606 default: 607 llvm_unreachable("invalid fp inline imm"); 608 } 609 } 610 611 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 612 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 613 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 614 615 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 616 switch (Width) { 617 case OPW32: 618 return MCOperand::createImm(getInlineImmVal32(Imm)); 619 case OPW64: 620 return MCOperand::createImm(getInlineImmVal64(Imm)); 621 case OPW16: 622 case OPWV216: 623 return MCOperand::createImm(getInlineImmVal16(Imm)); 624 default: 625 llvm_unreachable("implement me"); 626 } 627 } 628 629 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 630 using namespace AMDGPU; 631 632 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 633 switch (Width) { 634 default: // fall 635 case OPW32: 636 case OPW16: 637 case OPWV216: 638 return VGPR_32RegClassID; 639 case OPW64: return VReg_64RegClassID; 640 case OPW128: return VReg_128RegClassID; 641 } 642 } 643 644 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 645 using namespace AMDGPU; 646 647 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 648 switch (Width) { 649 default: // fall 650 case OPW32: 651 case OPW16: 652 case OPWV216: 653 return SGPR_32RegClassID; 654 case OPW64: return SGPR_64RegClassID; 655 case OPW128: return SGPR_128RegClassID; 656 case OPW256: return SGPR_256RegClassID; 657 case OPW512: return SGPR_512RegClassID; 658 } 659 } 660 661 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 662 using namespace AMDGPU; 663 664 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 665 switch (Width) { 666 default: // fall 667 case OPW32: 668 case OPW16: 669 case OPWV216: 670 return TTMP_32RegClassID; 671 case OPW64: return TTMP_64RegClassID; 672 case OPW128: return TTMP_128RegClassID; 673 case OPW256: return TTMP_256RegClassID; 674 case OPW512: return TTMP_512RegClassID; 675 } 676 } 677 678 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 679 using namespace AMDGPU::EncValues; 680 681 unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN; 682 unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX; 683 684 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 685 } 686 687 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 688 using namespace AMDGPU::EncValues; 689 690 assert(Val < 512); // enum9 691 692 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 693 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); 694 } 695 if (Val <= SGPR_MAX) { 696 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 697 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 698 } 699 700 int TTmpIdx = getTTmpIdx(Val); 701 if (TTmpIdx >= 0) { 702 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 703 } 704 705 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 706 return decodeIntImmed(Val); 707 708 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 709 return decodeFPImmed(Width, Val); 710 711 if (Val == LITERAL_CONST) 712 return decodeLiteralConstant(); 713 714 switch (Width) { 715 case OPW32: 716 case OPW16: 717 case OPWV216: 718 return decodeSpecialReg32(Val); 719 case OPW64: 720 return decodeSpecialReg64(Val); 721 default: 722 llvm_unreachable("unexpected immediate type"); 723 } 724 } 725 726 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 727 using namespace AMDGPU::EncValues; 728 729 assert(Val < 128); 730 assert(Width == OPW256 || Width == OPW512); 731 732 if (Val <= SGPR_MAX) { 733 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 734 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 735 } 736 737 int TTmpIdx = getTTmpIdx(Val); 738 if (TTmpIdx >= 0) { 739 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 740 } 741 742 llvm_unreachable("unknown dst register"); 743 } 744 745 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 746 using namespace AMDGPU; 747 748 switch (Val) { 749 case 102: return createRegOperand(FLAT_SCR_LO); 750 case 103: return createRegOperand(FLAT_SCR_HI); 751 case 104: return createRegOperand(XNACK_MASK_LO); 752 case 105: return createRegOperand(XNACK_MASK_HI); 753 case 106: return createRegOperand(VCC_LO); 754 case 107: return createRegOperand(VCC_HI); 755 case 108: assert(!isGFX9()); return createRegOperand(TBA_LO); 756 case 109: assert(!isGFX9()); return createRegOperand(TBA_HI); 757 case 110: assert(!isGFX9()); return createRegOperand(TMA_LO); 758 case 111: assert(!isGFX9()); return createRegOperand(TMA_HI); 759 case 124: return createRegOperand(M0); 760 case 126: return createRegOperand(EXEC_LO); 761 case 127: return createRegOperand(EXEC_HI); 762 case 235: return createRegOperand(SRC_SHARED_BASE); 763 case 236: return createRegOperand(SRC_SHARED_LIMIT); 764 case 237: return createRegOperand(SRC_PRIVATE_BASE); 765 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 766 // TODO: SRC_POPS_EXITING_WAVE_ID 767 // ToDo: no support for vccz register 768 case 251: break; 769 // ToDo: no support for execz register 770 case 252: break; 771 case 253: return createRegOperand(SCC); 772 default: break; 773 } 774 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 775 } 776 777 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 778 using namespace AMDGPU; 779 780 switch (Val) { 781 case 102: return createRegOperand(FLAT_SCR); 782 case 104: return createRegOperand(XNACK_MASK); 783 case 106: return createRegOperand(VCC); 784 case 108: assert(!isGFX9()); return createRegOperand(TBA); 785 case 110: assert(!isGFX9()); return createRegOperand(TMA); 786 case 126: return createRegOperand(EXEC); 787 default: break; 788 } 789 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 790 } 791 792 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 793 const unsigned Val) const { 794 using namespace AMDGPU::SDWA; 795 using namespace AMDGPU::EncValues; 796 797 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 798 // XXX: static_cast<int> is needed to avoid stupid warning: 799 // compare with unsigned is always true 800 if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) && 801 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 802 return createRegOperand(getVgprClassId(Width), 803 Val - SDWA9EncValues::SRC_VGPR_MIN); 804 } 805 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 806 Val <= SDWA9EncValues::SRC_SGPR_MAX) { 807 return createSRegOperand(getSgprClassId(Width), 808 Val - SDWA9EncValues::SRC_SGPR_MIN); 809 } 810 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 811 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 812 return createSRegOperand(getTtmpClassId(Width), 813 Val - SDWA9EncValues::SRC_TTMP_MIN); 814 } 815 816 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 817 818 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 819 return decodeIntImmed(SVal); 820 821 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 822 return decodeFPImmed(Width, SVal); 823 824 return decodeSpecialReg32(SVal); 825 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 826 return createRegOperand(getVgprClassId(Width), Val); 827 } 828 llvm_unreachable("unsupported target"); 829 } 830 831 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 832 return decodeSDWASrc(OPW16, Val); 833 } 834 835 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 836 return decodeSDWASrc(OPW32, Val); 837 } 838 839 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 840 using namespace AMDGPU::SDWA; 841 842 assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] && 843 "SDWAVopcDst should be present only on GFX9"); 844 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 845 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 846 847 int TTmpIdx = getTTmpIdx(Val); 848 if (TTmpIdx >= 0) { 849 return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx); 850 } else if (Val > AMDGPU::EncValues::SGPR_MAX) { 851 return decodeSpecialReg64(Val); 852 } else { 853 return createSRegOperand(getSgprClassId(OPW64), Val); 854 } 855 } else { 856 return createRegOperand(AMDGPU::VCC); 857 } 858 } 859 860 bool AMDGPUDisassembler::isVI() const { 861 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 862 } 863 864 bool AMDGPUDisassembler::isGFX9() const { 865 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; 866 } 867 868 //===----------------------------------------------------------------------===// 869 // AMDGPUSymbolizer 870 //===----------------------------------------------------------------------===// 871 872 // Try to find symbol name for specified label 873 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 874 raw_ostream &/*cStream*/, int64_t Value, 875 uint64_t /*Address*/, bool IsBranch, 876 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 877 using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>; 878 using SectionSymbolsTy = std::vector<SymbolInfoTy>; 879 880 if (!IsBranch) { 881 return false; 882 } 883 884 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 885 auto Result = std::find_if(Symbols->begin(), Symbols->end(), 886 [Value](const SymbolInfoTy& Val) { 887 return std::get<0>(Val) == static_cast<uint64_t>(Value) 888 && std::get<2>(Val) == ELF::STT_NOTYPE; 889 }); 890 if (Result != Symbols->end()) { 891 auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result)); 892 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 893 Inst.addOperand(MCOperand::createExpr(Add)); 894 return true; 895 } 896 return false; 897 } 898 899 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 900 int64_t Value, 901 uint64_t Address) { 902 llvm_unreachable("unimplemented"); 903 } 904 905 //===----------------------------------------------------------------------===// 906 // Initialization 907 //===----------------------------------------------------------------------===// 908 909 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 910 LLVMOpInfoCallback /*GetOpInfo*/, 911 LLVMSymbolLookupCallback /*SymbolLookUp*/, 912 void *DisInfo, 913 MCContext *Ctx, 914 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 915 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 916 } 917 918 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 919 const MCSubtargetInfo &STI, 920 MCContext &Ctx) { 921 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 922 } 923 924 extern "C" void LLVMInitializeAMDGPUDisassembler() { 925 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 926 createAMDGPUDisassembler); 927 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 928 createAMDGPUSymbolizer); 929 } 930