1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) { 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 95 Offset = SignExtend64<24>(Imm); 96 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 111 uint64_t Addr, 112 const MCDisassembler *Decoder) { 113 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 114 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 115 } 116 117 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 118 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 119 uint64_t /*Addr*/, \ 120 const MCDisassembler *Decoder) { \ 121 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 122 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 123 } 124 125 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 126 // number of register. Used by VGPR only and AGPR only operands. 127 #define DECODE_OPERAND_REG_8(RegClass) \ 128 static DecodeStatus Decode##RegClass##RegisterClass( \ 129 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 130 const MCDisassembler *Decoder) { \ 131 assert(Imm < (1 << 8) && "8-bit encoding"); \ 132 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 133 return addOperand( \ 134 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 135 } 136 137 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 138 ImmWidth) \ 139 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 140 const MCDisassembler *Decoder) { \ 141 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 142 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 143 return addOperand(Inst, \ 144 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 145 MandatoryLiteral, ImmWidth)); \ 146 } 147 148 static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize, 149 AMDGPUDisassembler::OpWidthTy OpWidth, 150 unsigned Imm, unsigned EncImm, 151 bool MandatoryLiteral, unsigned ImmWidth, 152 const MCDisassembler *Decoder) { 153 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!"); 154 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 155 return addOperand( 156 Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral, ImmWidth)); 157 } 158 159 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 160 // get register class. Used by SGPR only operands. 161 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 162 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 163 164 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 165 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 166 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 167 // Used by AV_ register classes (AGPR or VGPR only register operands). 168 template <AMDGPUDisassembler::OpWidthTy OpWidth> 169 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 170 const MCDisassembler *Decoder) { 171 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR, 172 false, 0, Decoder); 173 } 174 175 // Decoder for Src(9-bit encoding) registers only. 176 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ 177 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 178 179 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 180 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 181 // only. 182 template <AMDGPUDisassembler::OpWidthTy OpWidth> 183 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 184 const MCDisassembler *Decoder) { 185 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0, Decoder); 186 } 187 188 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 189 // Imm{9} is acc, registers only. 190 template <AMDGPUDisassembler::OpWidthTy OpWidth> 191 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm, 192 uint64_t /* Addr */, 193 const MCDisassembler *Decoder) { 194 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0, Decoder); 195 } 196 197 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 198 // register from RegClass or immediate. Registers that don't belong to RegClass 199 // will be decoded and InstPrinter will report warning. Immediate will be 200 // decoded into constant of size ImmWidth, should match width of immediate used 201 // by OperandType (important for floating point types). 202 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ 203 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ 204 false, ImmWidth) 205 206 #define DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(Name, OpWidth, ImmWidth) \ 207 DECODE_SrcOp(decodeOperand_##Name, 9, OpWidth, Imm, false, ImmWidth) 208 209 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 210 // and decode using 'enum10' from decodeSrcOp. 211 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ 212 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ 213 Imm | 512, false, ImmWidth) 214 215 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ 216 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ 217 OpWidth, Imm, true, ImmWidth) 218 219 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 220 // when RegisterClass is used as an operand. Most often used for destination 221 // operands. 222 223 DECODE_OPERAND_REG_8(VGPR_32) 224 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 225 DECODE_OPERAND_REG_8(VReg_64) 226 DECODE_OPERAND_REG_8(VReg_96) 227 DECODE_OPERAND_REG_8(VReg_128) 228 DECODE_OPERAND_REG_8(VReg_256) 229 DECODE_OPERAND_REG_8(VReg_288) 230 DECODE_OPERAND_REG_8(VReg_352) 231 DECODE_OPERAND_REG_8(VReg_384) 232 DECODE_OPERAND_REG_8(VReg_512) 233 DECODE_OPERAND_REG_8(VReg_1024) 234 235 DECODE_OPERAND_REG_7(SReg_32, OPW32) 236 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) 237 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 238 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 239 DECODE_OPERAND_REG_7(SReg_64, OPW64) 240 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 241 DECODE_OPERAND_REG_7(SReg_96, OPW96) 242 DECODE_OPERAND_REG_7(SReg_128, OPW128) 243 DECODE_OPERAND_REG_7(SReg_256, OPW256) 244 DECODE_OPERAND_REG_7(SReg_512, OPW512) 245 246 DECODE_OPERAND_REG_8(AGPR_32) 247 DECODE_OPERAND_REG_8(AReg_64) 248 DECODE_OPERAND_REG_8(AReg_128) 249 DECODE_OPERAND_REG_8(AReg_256) 250 DECODE_OPERAND_REG_8(AReg_512) 251 DECODE_OPERAND_REG_8(AReg_1024) 252 253 // Decoders for register only source RegisterOperands that use use 9-bit Src 254 // encoding: 'decodeOperand_<RegClass>'. 255 256 DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) 257 DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) 258 DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) 259 DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) 260 DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) 261 262 // Decoders for register or immediate RegisterOperands that use 9-bit Src 263 // encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'. 264 265 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) 266 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) 267 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 16) 268 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) 269 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) 270 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) 271 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) 272 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) 273 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32) 274 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) 275 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 32) 276 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 16) 277 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) 278 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 16) 279 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) 280 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 32) 281 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) 282 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) 283 284 DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(VS_32_ImmV2I16, OPW32, 32) 285 DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(VS_32_ImmV2F16, OPW32, 16) 286 287 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) 288 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) 289 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) 290 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) 291 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) 292 293 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) 294 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) 295 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) 296 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32) 297 298 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 299 uint64_t /*Addr*/, 300 const MCDisassembler *Decoder) { 301 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 302 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 303 304 bool IsHi = Imm & (1 << 9); 305 unsigned RegIdx = Imm & 0xff; 306 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 307 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 308 } 309 310 static DecodeStatus 311 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 312 const MCDisassembler *Decoder) { 313 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 314 315 bool IsHi = Imm & (1 << 7); 316 unsigned RegIdx = Imm & 0x7f; 317 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 318 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 319 } 320 321 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 322 uint64_t /*Addr*/, 323 const MCDisassembler *Decoder) { 324 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 325 326 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 327 bool IsVGPR = Imm & (1 << 8); 328 if (IsVGPR) { 329 bool IsHi = Imm & (1 << 7); 330 unsigned RegIdx = Imm & 0x7f; 331 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 332 } 333 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 334 Imm & 0xFF, false, 16)); 335 } 336 337 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 338 uint64_t /*Addr*/, 339 const MCDisassembler *Decoder) { 340 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 341 342 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 343 bool IsVGPR = Imm & (1 << 8); 344 if (IsVGPR) { 345 bool IsHi = Imm & (1 << 9); 346 unsigned RegIdx = Imm & 0xff; 347 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 348 } 349 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 350 Imm & 0xFF, false, 16)); 351 } 352 353 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 354 uint64_t Addr, 355 const MCDisassembler *Decoder) { 356 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 357 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 358 } 359 360 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 361 uint64_t Addr, const void *Decoder) { 362 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 363 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 364 } 365 366 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 367 const MCRegisterInfo *MRI) { 368 if (OpIdx < 0) 369 return false; 370 371 const MCOperand &Op = Inst.getOperand(OpIdx); 372 if (!Op.isReg()) 373 return false; 374 375 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 376 auto Reg = Sub ? Sub : Op.getReg(); 377 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 378 } 379 380 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 381 AMDGPUDisassembler::OpWidthTy Opw, 382 const MCDisassembler *Decoder) { 383 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 384 if (!DAsm->isGFX90A()) { 385 Imm &= 511; 386 } else { 387 // If atomic has both vdata and vdst their register classes are tied. 388 // The bit is decoded along with the vdst, first operand. We need to 389 // change register class to AGPR if vdst was AGPR. 390 // If a DS instruction has both data0 and data1 their register classes 391 // are also tied. 392 unsigned Opc = Inst.getOpcode(); 393 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 394 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 395 : AMDGPU::OpName::vdata; 396 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 397 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 398 if ((int)Inst.getNumOperands() == DataIdx) { 399 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 400 if (IsAGPROperand(Inst, DstIdx, MRI)) 401 Imm |= 512; 402 } 403 404 if (TSFlags & SIInstrFlags::DS) { 405 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 406 if ((int)Inst.getNumOperands() == Data2Idx && 407 IsAGPROperand(Inst, DataIdx, MRI)) 408 Imm |= 512; 409 } 410 } 411 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 412 } 413 414 template <AMDGPUDisassembler::OpWidthTy Opw> 415 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 416 uint64_t /* Addr */, 417 const MCDisassembler *Decoder) { 418 return decodeAVLdSt(Inst, Imm, Opw, Decoder); 419 } 420 421 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 422 uint64_t Addr, 423 const MCDisassembler *Decoder) { 424 assert(Imm < (1 << 9) && "9-bit encoding"); 425 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 426 return addOperand( 427 Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true)); 428 } 429 430 #define DECODE_SDWA(DecName) \ 431 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 432 433 DECODE_SDWA(Src32) 434 DECODE_SDWA(Src16) 435 DECODE_SDWA(VopcDst) 436 437 #include "AMDGPUGenDisassemblerTables.inc" 438 439 //===----------------------------------------------------------------------===// 440 // 441 //===----------------------------------------------------------------------===// 442 443 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 444 assert(Bytes.size() >= sizeof(T)); 445 const auto Res = 446 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 447 Bytes = Bytes.slice(sizeof(T)); 448 return Res; 449 } 450 451 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 452 assert(Bytes.size() >= 12); 453 uint64_t Lo = 454 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 455 Bytes = Bytes.slice(8); 456 uint64_t Hi = 457 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 458 Bytes = Bytes.slice(4); 459 return DecoderUInt128(Lo, Hi); 460 } 461 462 // The disassembler is greedy, so we need to check FI operand value to 463 // not parse a dpp if the correct literal is not set. For dpp16 the 464 // autogenerated decoder checks the dpp literal 465 static bool isValidDPP8(const MCInst &MI) { 466 using namespace llvm::AMDGPU::DPP; 467 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 468 assert(FiIdx != -1); 469 if ((unsigned)FiIdx >= MI.getNumOperands()) 470 return false; 471 unsigned Fi = MI.getOperand(FiIdx).getImm(); 472 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 473 } 474 475 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 476 ArrayRef<uint8_t> Bytes_, 477 uint64_t Address, 478 raw_ostream &CS) const { 479 bool IsSDWA = false; 480 481 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 482 Bytes = Bytes_.slice(0, MaxInstBytesNum); 483 484 DecodeStatus Res = MCDisassembler::Fail; 485 do { 486 // ToDo: better to switch encoding length using some bit predicate 487 // but it is unknown yet, so try all we can 488 489 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 490 // encodings 491 if (isGFX11Plus() && Bytes.size() >= 12 ) { 492 DecoderUInt128 DecW = eat12Bytes(Bytes); 493 Res = 494 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 495 MI, DecW, Address, CS); 496 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 497 break; 498 MI = MCInst(); // clear 499 Res = 500 tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696, 501 MI, DecW, Address, CS); 502 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 503 break; 504 MI = MCInst(); // clear 505 506 const auto convertVOPDPP = [&]() { 507 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) { 508 convertVOP3PDPPInst(MI); 509 } else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) { 510 convertVOPCDPPInst(MI); // Special VOP3 case 511 } else { 512 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 513 convertVOP3DPPInst(MI); // Regular VOP3 case 514 } 515 }; 516 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 517 MI, DecW, Address, CS); 518 if (Res) { 519 convertVOPDPP(); 520 break; 521 } 522 Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696, 523 MI, DecW, Address, CS); 524 if (Res) { 525 convertVOPDPP(); 526 break; 527 } 528 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 529 if (Res) 530 break; 531 532 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 533 if (Res) 534 break; 535 536 Res = tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS); 537 if (Res) 538 break; 539 } 540 // Reinitialize Bytes 541 Bytes = Bytes_.slice(0, MaxInstBytesNum); 542 543 if (Bytes.size() >= 8) { 544 const uint64_t QW = eatBytes<uint64_t>(Bytes); 545 546 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 547 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 548 if (Res) { 549 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 550 == -1) 551 break; 552 if (convertDPP8Inst(MI) == MCDisassembler::Success) 553 break; 554 MI = MCInst(); // clear 555 } 556 } 557 558 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 559 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 560 break; 561 MI = MCInst(); // clear 562 563 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 564 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 565 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 566 break; 567 MI = MCInst(); // clear 568 569 Res = tryDecodeInst(DecoderTableDPP8GFX1264, 570 DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS); 571 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 572 break; 573 MI = MCInst(); // clear 574 575 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 576 if (Res) break; 577 578 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 579 MI, QW, Address, CS); 580 if (Res) { 581 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 582 convertVOPCDPPInst(MI); 583 break; 584 } 585 586 Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664, 587 MI, QW, Address, CS); 588 if (Res) { 589 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 590 convertVOPCDPPInst(MI); 591 break; 592 } 593 594 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 595 if (Res) { IsSDWA = true; break; } 596 597 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 598 if (Res) { IsSDWA = true; break; } 599 600 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 601 if (Res) { IsSDWA = true; break; } 602 603 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 604 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 605 if (Res) 606 break; 607 } 608 609 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 610 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 611 // table first so we print the correct name. 612 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 613 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 614 if (Res) 615 break; 616 } 617 } 618 619 // Reinitialize Bytes as DPP64 could have eaten too much 620 Bytes = Bytes_.slice(0, MaxInstBytesNum); 621 622 // Try decode 32-bit instruction 623 if (Bytes.size() < 4) break; 624 const uint32_t DW = eatBytes<uint32_t>(Bytes); 625 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 626 if (Res) break; 627 628 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 629 if (Res) break; 630 631 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 632 if (Res) break; 633 634 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 635 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 636 if (Res) 637 break; 638 } 639 640 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 641 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 642 if (Res) break; 643 } 644 645 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 646 if (Res) break; 647 648 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 649 Address, CS); 650 if (Res) break; 651 652 Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 653 Address, CS); 654 if (Res) 655 break; 656 657 if (Bytes.size() < 4) break; 658 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 659 660 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 661 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 662 if (Res) 663 break; 664 } 665 666 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 667 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 668 if (Res) 669 break; 670 } 671 672 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 673 if (Res) break; 674 675 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS); 676 if (Res) break; 677 678 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 679 if (Res) break; 680 681 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 682 if (Res) break; 683 684 Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW, 685 Address, CS); 686 if (Res) 687 break; 688 689 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 690 Address, CS); 691 if (Res) 692 break; 693 694 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS); 695 if (Res) 696 break; 697 698 Res = tryDecodeInst(DecoderTableWMMAGFX1264, MI, QW, Address, CS); 699 } while (false); 700 701 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 702 // Insert dummy unused src2_modifiers. 703 insertNamedMCOperand(MI, MCOperand::createImm(0), 704 AMDGPU::OpName::src2_modifiers); 705 } 706 707 if (Res && (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp || 708 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp)) { 709 // Insert dummy unused src2_modifiers. 710 insertNamedMCOperand(MI, MCOperand::createImm(0), 711 AMDGPU::OpName::src2_modifiers); 712 } 713 714 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && 715 !AMDGPU::hasGDS(STI)) { 716 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); 717 } 718 719 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 720 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 721 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 722 AMDGPU::OpName::cpol); 723 if (CPolPos != -1) { 724 unsigned CPol = 725 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 726 AMDGPU::CPol::GLC : 0; 727 if (MI.getNumOperands() <= (unsigned)CPolPos) { 728 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 729 AMDGPU::OpName::cpol); 730 } else if (CPol) { 731 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 732 } 733 } 734 } 735 736 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 737 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 738 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 739 // GFX90A lost TFE, its place is occupied by ACC. 740 int TFEOpIdx = 741 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 742 if (TFEOpIdx != -1) { 743 auto TFEIter = MI.begin(); 744 std::advance(TFEIter, TFEOpIdx); 745 MI.insert(TFEIter, MCOperand::createImm(0)); 746 } 747 } 748 749 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 750 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 751 int SWZOpIdx = 752 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 753 if (SWZOpIdx != -1) { 754 auto SWZIter = MI.begin(); 755 std::advance(SWZIter, SWZOpIdx); 756 MI.insert(SWZIter, MCOperand::createImm(0)); 757 } 758 } 759 760 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 761 int VAddr0Idx = 762 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 763 int RsrcIdx = 764 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 765 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 766 if (VAddr0Idx >= 0 && NSAArgs > 0) { 767 unsigned NSAWords = (NSAArgs + 3) / 4; 768 if (Bytes.size() < 4 * NSAWords) { 769 Res = MCDisassembler::Fail; 770 } else { 771 for (unsigned i = 0; i < NSAArgs; ++i) { 772 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 773 auto VAddrRCID = 774 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 775 MI.insert(MI.begin() + VAddrIdx, 776 createRegOperand(VAddrRCID, Bytes[i])); 777 } 778 Bytes = Bytes.slice(4 * NSAWords); 779 } 780 } 781 782 if (Res) 783 Res = convertMIMGInst(MI); 784 } 785 786 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 787 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 788 Res = convertMIMGInst(MI); 789 790 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 791 Res = convertEXPInst(MI); 792 793 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 794 Res = convertVINTERPInst(MI); 795 796 if (Res && IsSDWA) 797 Res = convertSDWAInst(MI); 798 799 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 800 AMDGPU::OpName::vdst_in); 801 if (VDstIn_Idx != -1) { 802 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 803 MCOI::OperandConstraint::TIED_TO); 804 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 805 !MI.getOperand(VDstIn_Idx).isReg() || 806 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 807 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 808 MI.erase(&MI.getOperand(VDstIn_Idx)); 809 insertNamedMCOperand(MI, 810 MCOperand::createReg(MI.getOperand(Tied).getReg()), 811 AMDGPU::OpName::vdst_in); 812 } 813 } 814 815 int ImmLitIdx = 816 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 817 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 818 if (Res && ImmLitIdx != -1 && !IsSOPK) 819 Res = convertFMAanyK(MI, ImmLitIdx); 820 821 // if the opcode was not recognized we'll assume a Size of 4 bytes 822 // (unless there are fewer bytes left) 823 Size = Res ? (MaxInstBytesNum - Bytes.size()) 824 : std::min((size_t)4, Bytes_.size()); 825 return Res; 826 } 827 828 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 829 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 830 // The MCInst still has these fields even though they are no longer encoded 831 // in the GFX11 instruction. 832 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 833 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 834 } 835 return MCDisassembler::Success; 836 } 837 838 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 839 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 840 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 841 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 842 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 843 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 844 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 845 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 846 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 847 // The MCInst has this field that is not directly encoded in the 848 // instruction. 849 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 850 } 851 return MCDisassembler::Success; 852 } 853 854 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 855 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 856 STI.hasFeature(AMDGPU::FeatureGFX10)) { 857 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 858 // VOPC - insert clamp 859 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 860 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 861 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 862 if (SDst != -1) { 863 // VOPC - insert VCC register as sdst 864 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 865 AMDGPU::OpName::sdst); 866 } else { 867 // VOP1/2 - insert omod if present in instruction 868 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 869 } 870 } 871 return MCDisassembler::Success; 872 } 873 874 struct VOPModifiers { 875 unsigned OpSel = 0; 876 unsigned OpSelHi = 0; 877 unsigned NegLo = 0; 878 unsigned NegHi = 0; 879 }; 880 881 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 882 // Note that these values do not affect disassembler output, 883 // so this is only necessary for consistency with src_modifiers. 884 static VOPModifiers collectVOPModifiers(const MCInst &MI, 885 bool IsVOP3P = false) { 886 VOPModifiers Modifiers; 887 unsigned Opc = MI.getOpcode(); 888 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 889 AMDGPU::OpName::src1_modifiers, 890 AMDGPU::OpName::src2_modifiers}; 891 for (int J = 0; J < 3; ++J) { 892 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 893 if (OpIdx == -1) 894 continue; 895 896 unsigned Val = MI.getOperand(OpIdx).getImm(); 897 898 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 899 if (IsVOP3P) { 900 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 901 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 902 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 903 } else if (J == 0) { 904 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 905 } 906 } 907 908 return Modifiers; 909 } 910 911 // MAC opcodes have special old and src2 operands. 912 // src2 is tied to dst, while old is not tied (but assumed to be). 913 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 914 constexpr int DST_IDX = 0; 915 auto Opcode = MI.getOpcode(); 916 const auto &Desc = MCII->get(Opcode); 917 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 918 919 if (OldIdx != -1 && Desc.getOperandConstraint( 920 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 921 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 922 assert(Desc.getOperandConstraint( 923 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 924 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 925 (void)DST_IDX; 926 return true; 927 } 928 929 return false; 930 } 931 932 // Create dummy old operand and insert dummy unused src2_modifiers 933 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 934 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 935 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 936 insertNamedMCOperand(MI, MCOperand::createImm(0), 937 AMDGPU::OpName::src2_modifiers); 938 } 939 940 // We must check FI == literal to reject not genuine dpp8 insts, and we must 941 // first add optional MI operands to check FI 942 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 943 unsigned Opc = MI.getOpcode(); 944 945 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 946 convertVOP3PDPPInst(MI); 947 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 948 AMDGPU::isVOPC64DPP(Opc)) { 949 convertVOPCDPPInst(MI); 950 } else { 951 if (isMacDPP(MI)) 952 convertMacDPPInst(MI); 953 954 int VDstInIdx = 955 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 956 if (VDstInIdx != -1) 957 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 958 959 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 || 960 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12) 961 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 962 963 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 964 if (MI.getNumOperands() < DescNumOps && 965 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 966 auto Mods = collectVOPModifiers(MI); 967 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 968 AMDGPU::OpName::op_sel); 969 } else { 970 // Insert dummy unused src modifiers. 971 if (MI.getNumOperands() < DescNumOps && 972 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 973 insertNamedMCOperand(MI, MCOperand::createImm(0), 974 AMDGPU::OpName::src0_modifiers); 975 976 if (MI.getNumOperands() < DescNumOps && 977 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 978 insertNamedMCOperand(MI, MCOperand::createImm(0), 979 AMDGPU::OpName::src1_modifiers); 980 } 981 } 982 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 983 } 984 985 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 986 if (isMacDPP(MI)) 987 convertMacDPPInst(MI); 988 989 int VDstInIdx = 990 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 991 if (VDstInIdx != -1) 992 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 993 994 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 || 995 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12) 996 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 997 998 unsigned Opc = MI.getOpcode(); 999 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1000 if (MI.getNumOperands() < DescNumOps && 1001 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 1002 auto Mods = collectVOPModifiers(MI); 1003 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1004 AMDGPU::OpName::op_sel); 1005 } 1006 return MCDisassembler::Success; 1007 } 1008 1009 // Note that before gfx10, the MIMG encoding provided no information about 1010 // VADDR size. Consequently, decoded instructions always show address as if it 1011 // has 1 dword, which could be not really so. 1012 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 1013 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 1014 1015 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1016 AMDGPU::OpName::vdst); 1017 1018 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1019 AMDGPU::OpName::vdata); 1020 int VAddr0Idx = 1021 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 1022 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 1023 : AMDGPU::OpName::rsrc; 1024 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 1025 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1026 AMDGPU::OpName::dmask); 1027 1028 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1029 AMDGPU::OpName::tfe); 1030 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1031 AMDGPU::OpName::d16); 1032 1033 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 1034 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 1035 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 1036 1037 assert(VDataIdx != -1); 1038 if (BaseOpcode->BVH) { 1039 // Add A16 operand for intersect_ray instructions 1040 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 1041 return MCDisassembler::Success; 1042 } 1043 1044 bool IsAtomic = (VDstIdx != -1); 1045 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 1046 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 1047 bool IsNSA = false; 1048 bool IsPartialNSA = false; 1049 unsigned AddrSize = Info->VAddrDwords; 1050 1051 if (isGFX10Plus()) { 1052 unsigned DimIdx = 1053 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 1054 int A16Idx = 1055 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 1056 const AMDGPU::MIMGDimInfo *Dim = 1057 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 1058 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 1059 1060 AddrSize = 1061 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1062 1063 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1064 // VIMAGE insts other than BVH never use vaddr4. 1065 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1066 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1067 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1068 if (!IsNSA) { 1069 if (!IsVSample && AddrSize > 12) 1070 AddrSize = 16; 1071 } else { 1072 if (AddrSize > Info->VAddrDwords) { 1073 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1074 // The NSA encoding does not contain enough operands for the 1075 // combination of base opcode / dimension. Should this be an error? 1076 return MCDisassembler::Success; 1077 } 1078 IsPartialNSA = true; 1079 } 1080 } 1081 } 1082 1083 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1084 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1085 1086 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1087 if (D16 && AMDGPU::hasPackedD16(STI)) { 1088 DstSize = (DstSize + 1) / 2; 1089 } 1090 1091 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1092 DstSize += 1; 1093 1094 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1095 return MCDisassembler::Success; 1096 1097 int NewOpcode = 1098 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1099 if (NewOpcode == -1) 1100 return MCDisassembler::Success; 1101 1102 // Widen the register to the correct number of enabled channels. 1103 unsigned NewVdata = AMDGPU::NoRegister; 1104 if (DstSize != Info->VDataDwords) { 1105 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1106 1107 // Get first subregister of VData 1108 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1109 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1110 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1111 1112 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1113 &MRI.getRegClass(DataRCID)); 1114 if (NewVdata == AMDGPU::NoRegister) { 1115 // It's possible to encode this such that the low register + enabled 1116 // components exceeds the register count. 1117 return MCDisassembler::Success; 1118 } 1119 } 1120 1121 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1122 // If using partial NSA on GFX11+ widen last address register. 1123 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1124 unsigned NewVAddrSA = AMDGPU::NoRegister; 1125 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1126 AddrSize != Info->VAddrDwords) { 1127 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1128 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1129 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1130 1131 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1132 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1133 &MRI.getRegClass(AddrRCID)); 1134 if (!NewVAddrSA) 1135 return MCDisassembler::Success; 1136 } 1137 1138 MI.setOpcode(NewOpcode); 1139 1140 if (NewVdata != AMDGPU::NoRegister) { 1141 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1142 1143 if (IsAtomic) { 1144 // Atomic operations have an additional operand (a copy of data) 1145 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1146 } 1147 } 1148 1149 if (NewVAddrSA) { 1150 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1151 } else if (IsNSA) { 1152 assert(AddrSize <= Info->VAddrDwords); 1153 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1154 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1155 } 1156 1157 return MCDisassembler::Success; 1158 } 1159 1160 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1161 // decoder only adds to src_modifiers, so manually add the bits to the other 1162 // operands. 1163 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1164 unsigned Opc = MI.getOpcode(); 1165 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1166 auto Mods = collectVOPModifiers(MI, true); 1167 1168 if (MI.getNumOperands() < DescNumOps && 1169 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1170 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1171 1172 if (MI.getNumOperands() < DescNumOps && 1173 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1174 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1175 AMDGPU::OpName::op_sel); 1176 if (MI.getNumOperands() < DescNumOps && 1177 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1178 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1179 AMDGPU::OpName::op_sel_hi); 1180 if (MI.getNumOperands() < DescNumOps && 1181 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1182 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1183 AMDGPU::OpName::neg_lo); 1184 if (MI.getNumOperands() < DescNumOps && 1185 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1186 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1187 AMDGPU::OpName::neg_hi); 1188 1189 return MCDisassembler::Success; 1190 } 1191 1192 // Create dummy old operand and insert optional operands 1193 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1194 unsigned Opc = MI.getOpcode(); 1195 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1196 1197 if (MI.getNumOperands() < DescNumOps && 1198 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1199 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1200 1201 if (MI.getNumOperands() < DescNumOps && 1202 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1203 insertNamedMCOperand(MI, MCOperand::createImm(0), 1204 AMDGPU::OpName::src0_modifiers); 1205 1206 if (MI.getNumOperands() < DescNumOps && 1207 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1208 insertNamedMCOperand(MI, MCOperand::createImm(0), 1209 AMDGPU::OpName::src1_modifiers); 1210 return MCDisassembler::Success; 1211 } 1212 1213 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1214 int ImmLitIdx) const { 1215 assert(HasLiteral && "Should have decoded a literal"); 1216 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1217 unsigned DescNumOps = Desc.getNumOperands(); 1218 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1219 AMDGPU::OpName::immDeferred); 1220 assert(DescNumOps == MI.getNumOperands()); 1221 for (unsigned I = 0; I < DescNumOps; ++I) { 1222 auto &Op = MI.getOperand(I); 1223 auto OpType = Desc.operands()[I].OperandType; 1224 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1225 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1226 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1227 IsDeferredOp) 1228 Op.setImm(Literal); 1229 } 1230 return MCDisassembler::Success; 1231 } 1232 1233 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1234 return getContext().getRegisterInfo()-> 1235 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1236 } 1237 1238 inline 1239 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1240 const Twine& ErrMsg) const { 1241 *CommentStream << "Error: " + ErrMsg; 1242 1243 // ToDo: add support for error operands to MCInst.h 1244 // return MCOperand::createError(V); 1245 return MCOperand(); 1246 } 1247 1248 inline 1249 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1250 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1251 } 1252 1253 inline 1254 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1255 unsigned Val) const { 1256 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1257 if (Val >= RegCl.getNumRegs()) 1258 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1259 ": unknown register " + Twine(Val)); 1260 return createRegOperand(RegCl.getRegister(Val)); 1261 } 1262 1263 inline 1264 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1265 unsigned Val) const { 1266 // ToDo: SI/CI have 104 SGPRs, VI - 102 1267 // Valery: here we accepting as much as we can, let assembler sort it out 1268 int shift = 0; 1269 switch (SRegClassID) { 1270 case AMDGPU::SGPR_32RegClassID: 1271 case AMDGPU::TTMP_32RegClassID: 1272 break; 1273 case AMDGPU::SGPR_64RegClassID: 1274 case AMDGPU::TTMP_64RegClassID: 1275 shift = 1; 1276 break; 1277 case AMDGPU::SGPR_96RegClassID: 1278 case AMDGPU::TTMP_96RegClassID: 1279 case AMDGPU::SGPR_128RegClassID: 1280 case AMDGPU::TTMP_128RegClassID: 1281 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1282 // this bundle? 1283 case AMDGPU::SGPR_256RegClassID: 1284 case AMDGPU::TTMP_256RegClassID: 1285 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1286 // this bundle? 1287 case AMDGPU::SGPR_288RegClassID: 1288 case AMDGPU::TTMP_288RegClassID: 1289 case AMDGPU::SGPR_320RegClassID: 1290 case AMDGPU::TTMP_320RegClassID: 1291 case AMDGPU::SGPR_352RegClassID: 1292 case AMDGPU::TTMP_352RegClassID: 1293 case AMDGPU::SGPR_384RegClassID: 1294 case AMDGPU::TTMP_384RegClassID: 1295 case AMDGPU::SGPR_512RegClassID: 1296 case AMDGPU::TTMP_512RegClassID: 1297 shift = 2; 1298 break; 1299 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1300 // this bundle? 1301 default: 1302 llvm_unreachable("unhandled register class"); 1303 } 1304 1305 if (Val % (1 << shift)) { 1306 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1307 << ": scalar reg isn't aligned " << Val; 1308 } 1309 1310 return createRegOperand(SRegClassID, Val >> shift); 1311 } 1312 1313 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1314 bool IsHi) const { 1315 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); 1316 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); 1317 } 1318 1319 // Decode Literals for insts which always have a literal in the encoding 1320 MCOperand 1321 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1322 if (HasLiteral) { 1323 assert( 1324 AMDGPU::hasVOPD(STI) && 1325 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1326 if (Literal != Val) 1327 return errOperand(Val, "More than one unique literal is illegal"); 1328 } 1329 HasLiteral = true; 1330 Literal = Val; 1331 return MCOperand::createImm(Literal); 1332 } 1333 1334 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1335 // For now all literal constants are supposed to be unsigned integer 1336 // ToDo: deal with signed/unsigned 64-bit integer constants 1337 // ToDo: deal with float/double constants 1338 if (!HasLiteral) { 1339 if (Bytes.size() < 4) { 1340 return errOperand(0, "cannot read literal, inst bytes left " + 1341 Twine(Bytes.size())); 1342 } 1343 HasLiteral = true; 1344 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1345 if (ExtendFP64) 1346 Literal64 <<= 32; 1347 } 1348 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1349 } 1350 1351 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1352 using namespace AMDGPU::EncValues; 1353 1354 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1355 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1356 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1357 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1358 // Cast prevents negative overflow. 1359 } 1360 1361 static int64_t getInlineImmVal32(unsigned Imm) { 1362 switch (Imm) { 1363 case 240: 1364 return llvm::bit_cast<uint32_t>(0.5f); 1365 case 241: 1366 return llvm::bit_cast<uint32_t>(-0.5f); 1367 case 242: 1368 return llvm::bit_cast<uint32_t>(1.0f); 1369 case 243: 1370 return llvm::bit_cast<uint32_t>(-1.0f); 1371 case 244: 1372 return llvm::bit_cast<uint32_t>(2.0f); 1373 case 245: 1374 return llvm::bit_cast<uint32_t>(-2.0f); 1375 case 246: 1376 return llvm::bit_cast<uint32_t>(4.0f); 1377 case 247: 1378 return llvm::bit_cast<uint32_t>(-4.0f); 1379 case 248: // 1 / (2 * PI) 1380 return 0x3e22f983; 1381 default: 1382 llvm_unreachable("invalid fp inline imm"); 1383 } 1384 } 1385 1386 static int64_t getInlineImmVal64(unsigned Imm) { 1387 switch (Imm) { 1388 case 240: 1389 return llvm::bit_cast<uint64_t>(0.5); 1390 case 241: 1391 return llvm::bit_cast<uint64_t>(-0.5); 1392 case 242: 1393 return llvm::bit_cast<uint64_t>(1.0); 1394 case 243: 1395 return llvm::bit_cast<uint64_t>(-1.0); 1396 case 244: 1397 return llvm::bit_cast<uint64_t>(2.0); 1398 case 245: 1399 return llvm::bit_cast<uint64_t>(-2.0); 1400 case 246: 1401 return llvm::bit_cast<uint64_t>(4.0); 1402 case 247: 1403 return llvm::bit_cast<uint64_t>(-4.0); 1404 case 248: // 1 / (2 * PI) 1405 return 0x3fc45f306dc9c882; 1406 default: 1407 llvm_unreachable("invalid fp inline imm"); 1408 } 1409 } 1410 1411 static int64_t getInlineImmVal16(unsigned Imm) { 1412 switch (Imm) { 1413 case 240: 1414 return 0x3800; 1415 case 241: 1416 return 0xB800; 1417 case 242: 1418 return 0x3C00; 1419 case 243: 1420 return 0xBC00; 1421 case 244: 1422 return 0x4000; 1423 case 245: 1424 return 0xC000; 1425 case 246: 1426 return 0x4400; 1427 case 247: 1428 return 0xC400; 1429 case 248: // 1 / (2 * PI) 1430 return 0x3118; 1431 default: 1432 llvm_unreachable("invalid fp inline imm"); 1433 } 1434 } 1435 1436 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1437 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1438 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1439 1440 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1441 // ImmWidth 0 is a default case where operand should not allow immediates. 1442 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1443 // use it to print verbose error message. 1444 switch (ImmWidth) { 1445 case 0: 1446 case 32: 1447 return MCOperand::createImm(getInlineImmVal32(Imm)); 1448 case 64: 1449 return MCOperand::createImm(getInlineImmVal64(Imm)); 1450 case 16: 1451 return MCOperand::createImm(getInlineImmVal16(Imm)); 1452 default: 1453 llvm_unreachable("implement me"); 1454 } 1455 } 1456 1457 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1458 using namespace AMDGPU; 1459 1460 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1461 switch (Width) { 1462 default: // fall 1463 case OPW32: 1464 case OPW16: 1465 case OPWV216: 1466 return VGPR_32RegClassID; 1467 case OPW64: 1468 case OPWV232: return VReg_64RegClassID; 1469 case OPW96: return VReg_96RegClassID; 1470 case OPW128: return VReg_128RegClassID; 1471 case OPW160: return VReg_160RegClassID; 1472 case OPW256: return VReg_256RegClassID; 1473 case OPW288: return VReg_288RegClassID; 1474 case OPW320: return VReg_320RegClassID; 1475 case OPW352: return VReg_352RegClassID; 1476 case OPW384: return VReg_384RegClassID; 1477 case OPW512: return VReg_512RegClassID; 1478 case OPW1024: return VReg_1024RegClassID; 1479 } 1480 } 1481 1482 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1483 using namespace AMDGPU; 1484 1485 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1486 switch (Width) { 1487 default: // fall 1488 case OPW32: 1489 case OPW16: 1490 case OPWV216: 1491 return AGPR_32RegClassID; 1492 case OPW64: 1493 case OPWV232: return AReg_64RegClassID; 1494 case OPW96: return AReg_96RegClassID; 1495 case OPW128: return AReg_128RegClassID; 1496 case OPW160: return AReg_160RegClassID; 1497 case OPW256: return AReg_256RegClassID; 1498 case OPW288: return AReg_288RegClassID; 1499 case OPW320: return AReg_320RegClassID; 1500 case OPW352: return AReg_352RegClassID; 1501 case OPW384: return AReg_384RegClassID; 1502 case OPW512: return AReg_512RegClassID; 1503 case OPW1024: return AReg_1024RegClassID; 1504 } 1505 } 1506 1507 1508 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1509 using namespace AMDGPU; 1510 1511 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1512 switch (Width) { 1513 default: // fall 1514 case OPW32: 1515 case OPW16: 1516 case OPWV216: 1517 return SGPR_32RegClassID; 1518 case OPW64: 1519 case OPWV232: return SGPR_64RegClassID; 1520 case OPW96: return SGPR_96RegClassID; 1521 case OPW128: return SGPR_128RegClassID; 1522 case OPW160: return SGPR_160RegClassID; 1523 case OPW256: return SGPR_256RegClassID; 1524 case OPW288: return SGPR_288RegClassID; 1525 case OPW320: return SGPR_320RegClassID; 1526 case OPW352: return SGPR_352RegClassID; 1527 case OPW384: return SGPR_384RegClassID; 1528 case OPW512: return SGPR_512RegClassID; 1529 } 1530 } 1531 1532 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1533 using namespace AMDGPU; 1534 1535 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1536 switch (Width) { 1537 default: // fall 1538 case OPW32: 1539 case OPW16: 1540 case OPWV216: 1541 return TTMP_32RegClassID; 1542 case OPW64: 1543 case OPWV232: return TTMP_64RegClassID; 1544 case OPW128: return TTMP_128RegClassID; 1545 case OPW256: return TTMP_256RegClassID; 1546 case OPW288: return TTMP_288RegClassID; 1547 case OPW320: return TTMP_320RegClassID; 1548 case OPW352: return TTMP_352RegClassID; 1549 case OPW384: return TTMP_384RegClassID; 1550 case OPW512: return TTMP_512RegClassID; 1551 } 1552 } 1553 1554 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1555 using namespace AMDGPU::EncValues; 1556 1557 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1558 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1559 1560 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1561 } 1562 1563 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1564 bool MandatoryLiteral, 1565 unsigned ImmWidth, bool IsFP) const { 1566 using namespace AMDGPU::EncValues; 1567 1568 assert(Val < 1024); // enum10 1569 1570 bool IsAGPR = Val & 512; 1571 Val &= 511; 1572 1573 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1574 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1575 : getVgprClassId(Width), Val - VGPR_MIN); 1576 } 1577 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1578 IsFP); 1579 } 1580 1581 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, 1582 unsigned Val, 1583 bool MandatoryLiteral, 1584 unsigned ImmWidth, 1585 bool IsFP) const { 1586 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1587 // decoded earlier. 1588 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1589 using namespace AMDGPU::EncValues; 1590 1591 if (Val <= SGPR_MAX) { 1592 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1593 static_assert(SGPR_MIN == 0); 1594 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1595 } 1596 1597 int TTmpIdx = getTTmpIdx(Val); 1598 if (TTmpIdx >= 0) { 1599 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1600 } 1601 1602 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1603 return decodeIntImmed(Val); 1604 1605 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1606 return decodeFPImmed(ImmWidth, Val); 1607 1608 if (Val == LITERAL_CONST) { 1609 if (MandatoryLiteral) 1610 // Keep a sentinel value for deferred setting 1611 return MCOperand::createImm(LITERAL_CONST); 1612 else 1613 return decodeLiteralConstant(IsFP && ImmWidth == 64); 1614 } 1615 1616 switch (Width) { 1617 case OPW32: 1618 case OPW16: 1619 case OPWV216: 1620 return decodeSpecialReg32(Val); 1621 case OPW64: 1622 case OPWV232: 1623 return decodeSpecialReg64(Val); 1624 default: 1625 llvm_unreachable("unexpected immediate type"); 1626 } 1627 } 1628 1629 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1630 // opposite of bit 0 of DstX. 1631 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1632 unsigned Val) const { 1633 int VDstXInd = 1634 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1635 assert(VDstXInd != -1); 1636 assert(Inst.getOperand(VDstXInd).isReg()); 1637 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1638 Val |= ~XDstReg & 1; 1639 auto Width = llvm::AMDGPUDisassembler::OPW32; 1640 return createRegOperand(getVgprClassId(Width), Val); 1641 } 1642 1643 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1644 using namespace AMDGPU; 1645 1646 switch (Val) { 1647 // clang-format off 1648 case 102: return createRegOperand(FLAT_SCR_LO); 1649 case 103: return createRegOperand(FLAT_SCR_HI); 1650 case 104: return createRegOperand(XNACK_MASK_LO); 1651 case 105: return createRegOperand(XNACK_MASK_HI); 1652 case 106: return createRegOperand(VCC_LO); 1653 case 107: return createRegOperand(VCC_HI); 1654 case 108: return createRegOperand(TBA_LO); 1655 case 109: return createRegOperand(TBA_HI); 1656 case 110: return createRegOperand(TMA_LO); 1657 case 111: return createRegOperand(TMA_HI); 1658 case 124: 1659 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1660 case 125: 1661 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1662 case 126: return createRegOperand(EXEC_LO); 1663 case 127: return createRegOperand(EXEC_HI); 1664 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1665 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1666 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1667 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1668 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1669 case 251: return createRegOperand(SRC_VCCZ); 1670 case 252: return createRegOperand(SRC_EXECZ); 1671 case 253: return createRegOperand(SRC_SCC); 1672 case 254: return createRegOperand(LDS_DIRECT); 1673 default: break; 1674 // clang-format on 1675 } 1676 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1677 } 1678 1679 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1680 using namespace AMDGPU; 1681 1682 switch (Val) { 1683 case 102: return createRegOperand(FLAT_SCR); 1684 case 104: return createRegOperand(XNACK_MASK); 1685 case 106: return createRegOperand(VCC); 1686 case 108: return createRegOperand(TBA); 1687 case 110: return createRegOperand(TMA); 1688 case 124: 1689 if (isGFX11Plus()) 1690 return createRegOperand(SGPR_NULL); 1691 break; 1692 case 125: 1693 if (!isGFX11Plus()) 1694 return createRegOperand(SGPR_NULL); 1695 break; 1696 case 126: return createRegOperand(EXEC); 1697 case 235: return createRegOperand(SRC_SHARED_BASE); 1698 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1699 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1700 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1701 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1702 case 251: return createRegOperand(SRC_VCCZ); 1703 case 252: return createRegOperand(SRC_EXECZ); 1704 case 253: return createRegOperand(SRC_SCC); 1705 default: break; 1706 } 1707 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1708 } 1709 1710 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1711 const unsigned Val, 1712 unsigned ImmWidth) const { 1713 using namespace AMDGPU::SDWA; 1714 using namespace AMDGPU::EncValues; 1715 1716 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1717 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1718 // XXX: cast to int is needed to avoid stupid warning: 1719 // compare with unsigned is always true 1720 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1721 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1722 return createRegOperand(getVgprClassId(Width), 1723 Val - SDWA9EncValues::SRC_VGPR_MIN); 1724 } 1725 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1726 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1727 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1728 return createSRegOperand(getSgprClassId(Width), 1729 Val - SDWA9EncValues::SRC_SGPR_MIN); 1730 } 1731 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1732 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1733 return createSRegOperand(getTtmpClassId(Width), 1734 Val - SDWA9EncValues::SRC_TTMP_MIN); 1735 } 1736 1737 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1738 1739 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1740 return decodeIntImmed(SVal); 1741 1742 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1743 return decodeFPImmed(ImmWidth, SVal); 1744 1745 return decodeSpecialReg32(SVal); 1746 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1747 return createRegOperand(getVgprClassId(Width), Val); 1748 } 1749 llvm_unreachable("unsupported target"); 1750 } 1751 1752 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1753 return decodeSDWASrc(OPW16, Val, 16); 1754 } 1755 1756 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1757 return decodeSDWASrc(OPW32, Val, 32); 1758 } 1759 1760 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1761 using namespace AMDGPU::SDWA; 1762 1763 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1764 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1765 "SDWAVopcDst should be present only on GFX9+"); 1766 1767 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1768 1769 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1770 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1771 1772 int TTmpIdx = getTTmpIdx(Val); 1773 if (TTmpIdx >= 0) { 1774 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1775 return createSRegOperand(TTmpClsId, TTmpIdx); 1776 } else if (Val > SGPR_MAX) { 1777 return IsWave64 ? decodeSpecialReg64(Val) 1778 : decodeSpecialReg32(Val); 1779 } else { 1780 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1781 } 1782 } else { 1783 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1784 } 1785 } 1786 1787 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1788 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1789 ? decodeSrcOp(OPW64, Val) 1790 : decodeSrcOp(OPW32, Val); 1791 } 1792 1793 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1794 return decodeSrcOp(OPW32, Val); 1795 } 1796 1797 bool AMDGPUDisassembler::isVI() const { 1798 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1799 } 1800 1801 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1802 1803 bool AMDGPUDisassembler::isGFX90A() const { 1804 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1805 } 1806 1807 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1808 1809 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1810 1811 bool AMDGPUDisassembler::isGFX10Plus() const { 1812 return AMDGPU::isGFX10Plus(STI); 1813 } 1814 1815 bool AMDGPUDisassembler::isGFX11() const { 1816 return STI.hasFeature(AMDGPU::FeatureGFX11); 1817 } 1818 1819 bool AMDGPUDisassembler::isGFX11Plus() const { 1820 return AMDGPU::isGFX11Plus(STI); 1821 } 1822 1823 bool AMDGPUDisassembler::isGFX12Plus() const { 1824 return AMDGPU::isGFX12Plus(STI); 1825 } 1826 1827 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1828 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1829 } 1830 1831 bool AMDGPUDisassembler::hasKernargPreload() const { 1832 return AMDGPU::hasKernargPreload(STI); 1833 } 1834 1835 //===----------------------------------------------------------------------===// 1836 // AMDGPU specific symbol handling 1837 //===----------------------------------------------------------------------===// 1838 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1839 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1840 do { \ 1841 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1842 } while (0) 1843 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1844 do { \ 1845 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1846 << GET_FIELD(MASK) << '\n'; \ 1847 } while (0) 1848 1849 // NOLINTNEXTLINE(readability-identifier-naming) 1850 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1851 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1852 using namespace amdhsa; 1853 StringRef Indent = "\t"; 1854 1855 // We cannot accurately backward compute #VGPRs used from 1856 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1857 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1858 // simply calculate the inverse of what the assembler does. 1859 1860 uint32_t GranulatedWorkitemVGPRCount = 1861 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1862 1863 uint32_t NextFreeVGPR = 1864 (GranulatedWorkitemVGPRCount + 1) * 1865 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1866 1867 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1868 1869 // We cannot backward compute values used to calculate 1870 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1871 // directives can't be computed: 1872 // .amdhsa_reserve_vcc 1873 // .amdhsa_reserve_flat_scratch 1874 // .amdhsa_reserve_xnack_mask 1875 // They take their respective default values if not specified in the assembly. 1876 // 1877 // GRANULATED_WAVEFRONT_SGPR_COUNT 1878 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1879 // 1880 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1881 // are set to 0. So while disassembling we consider that: 1882 // 1883 // GRANULATED_WAVEFRONT_SGPR_COUNT 1884 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1885 // 1886 // The disassembler cannot recover the original values of those 3 directives. 1887 1888 uint32_t GranulatedWavefrontSGPRCount = 1889 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1890 1891 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1892 return MCDisassembler::Fail; 1893 1894 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1895 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1896 1897 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1898 if (!hasArchitectedFlatScratch()) 1899 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1900 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1901 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1902 1903 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1904 return MCDisassembler::Fail; 1905 1906 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1907 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1908 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1909 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1910 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1911 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1912 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1913 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1914 1915 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1916 return MCDisassembler::Fail; 1917 1918 if (!isGFX12Plus()) 1919 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1920 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1921 1922 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1923 return MCDisassembler::Fail; 1924 1925 if (!isGFX12Plus()) 1926 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1927 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1928 1929 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1930 return MCDisassembler::Fail; 1931 1932 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1933 return MCDisassembler::Fail; 1934 1935 if (isGFX9Plus()) 1936 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1937 1938 if (!isGFX9Plus()) 1939 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1940 return MCDisassembler::Fail; 1941 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1942 return MCDisassembler::Fail; 1943 if (!isGFX10Plus()) 1944 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1945 return MCDisassembler::Fail; 1946 1947 if (isGFX10Plus()) { 1948 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1949 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1950 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1951 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1952 } 1953 1954 if (isGFX12Plus()) 1955 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 1956 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 1957 1958 return MCDisassembler::Success; 1959 } 1960 1961 // NOLINTNEXTLINE(readability-identifier-naming) 1962 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1963 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1964 using namespace amdhsa; 1965 StringRef Indent = "\t"; 1966 if (hasArchitectedFlatScratch()) 1967 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1968 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1969 else 1970 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1971 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1972 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1973 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1974 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1975 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1976 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1977 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1978 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1979 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1980 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1981 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1982 1983 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1984 return MCDisassembler::Fail; 1985 1986 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1987 return MCDisassembler::Fail; 1988 1989 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1990 return MCDisassembler::Fail; 1991 1992 PRINT_DIRECTIVE( 1993 ".amdhsa_exception_fp_ieee_invalid_op", 1994 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1995 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1996 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1997 PRINT_DIRECTIVE( 1998 ".amdhsa_exception_fp_ieee_div_zero", 1999 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 2000 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 2001 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 2002 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 2003 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 2004 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 2005 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 2006 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 2007 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 2008 2009 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 2010 return MCDisassembler::Fail; 2011 2012 return MCDisassembler::Success; 2013 } 2014 2015 // NOLINTNEXTLINE(readability-identifier-naming) 2016 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 2017 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 2018 using namespace amdhsa; 2019 StringRef Indent = "\t"; 2020 if (isGFX90A()) { 2021 KdStream << Indent << ".amdhsa_accum_offset " 2022 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 2023 << '\n'; 2024 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 2025 return MCDisassembler::Fail; 2026 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 2027 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 2028 return MCDisassembler::Fail; 2029 } else if (isGFX10Plus()) { 2030 // Bits [0-3]. 2031 if (!isGFX12Plus()) { 2032 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 2033 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 2034 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2035 } else { 2036 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2037 "SHARED_VGPR_COUNT", 2038 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2039 } 2040 } else { 2041 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX12_PLUS_RESERVED0) 2042 return MCDisassembler::Fail; 2043 } 2044 2045 // Bits [4-11]. 2046 if (isGFX11()) { 2047 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 2048 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE); 2049 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 2050 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START); 2051 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 2052 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END); 2053 } else if (isGFX12Plus()) { 2054 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2055 "INST_PREF_SIZE", COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE); 2056 } else { 2057 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED1) 2058 return MCDisassembler::Fail; 2059 } 2060 2061 // Bits [12]. 2062 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED2) 2063 return MCDisassembler::Fail; 2064 2065 // Bits [13]. 2066 if (isGFX12Plus()) { 2067 PRINT_PSEUDO_DIRECTIVE_COMMENT("GLG_EN", 2068 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN); 2069 } else { 2070 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_GFX11_RESERVED3) 2071 return MCDisassembler::Fail; 2072 } 2073 2074 // Bits [14-30]. 2075 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED4) 2076 return MCDisassembler::Fail; 2077 2078 // Bits [31]. 2079 if (isGFX11Plus()) { 2080 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2081 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP); 2082 } else { 2083 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED5) 2084 return MCDisassembler::Fail; 2085 } 2086 } else if (FourByteBuffer) { 2087 return MCDisassembler::Fail; 2088 } 2089 return MCDisassembler::Success; 2090 } 2091 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2092 #undef PRINT_DIRECTIVE 2093 #undef GET_FIELD 2094 2095 MCDisassembler::DecodeStatus 2096 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2097 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2098 raw_string_ostream &KdStream) const { 2099 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2100 do { \ 2101 KdStream << Indent << DIRECTIVE " " \ 2102 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2103 } while (0) 2104 2105 uint16_t TwoByteBuffer = 0; 2106 uint32_t FourByteBuffer = 0; 2107 2108 StringRef ReservedBytes; 2109 StringRef Indent = "\t"; 2110 2111 assert(Bytes.size() == 64); 2112 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2113 2114 switch (Cursor.tell()) { 2115 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2116 FourByteBuffer = DE.getU32(Cursor); 2117 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2118 << '\n'; 2119 return MCDisassembler::Success; 2120 2121 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2122 FourByteBuffer = DE.getU32(Cursor); 2123 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2124 << FourByteBuffer << '\n'; 2125 return MCDisassembler::Success; 2126 2127 case amdhsa::KERNARG_SIZE_OFFSET: 2128 FourByteBuffer = DE.getU32(Cursor); 2129 KdStream << Indent << ".amdhsa_kernarg_size " 2130 << FourByteBuffer << '\n'; 2131 return MCDisassembler::Success; 2132 2133 case amdhsa::RESERVED0_OFFSET: 2134 // 4 reserved bytes, must be 0. 2135 ReservedBytes = DE.getBytes(Cursor, 4); 2136 for (int I = 0; I < 4; ++I) { 2137 if (ReservedBytes[I] != 0) { 2138 return MCDisassembler::Fail; 2139 } 2140 } 2141 return MCDisassembler::Success; 2142 2143 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2144 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2145 // So far no directive controls this for Code Object V3, so simply skip for 2146 // disassembly. 2147 DE.skip(Cursor, 8); 2148 return MCDisassembler::Success; 2149 2150 case amdhsa::RESERVED1_OFFSET: 2151 // 20 reserved bytes, must be 0. 2152 ReservedBytes = DE.getBytes(Cursor, 20); 2153 for (int I = 0; I < 20; ++I) { 2154 if (ReservedBytes[I] != 0) { 2155 return MCDisassembler::Fail; 2156 } 2157 } 2158 return MCDisassembler::Success; 2159 2160 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2161 FourByteBuffer = DE.getU32(Cursor); 2162 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2163 2164 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2165 FourByteBuffer = DE.getU32(Cursor); 2166 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2167 2168 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2169 FourByteBuffer = DE.getU32(Cursor); 2170 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2171 2172 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2173 using namespace amdhsa; 2174 TwoByteBuffer = DE.getU16(Cursor); 2175 2176 if (!hasArchitectedFlatScratch()) 2177 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2178 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2179 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2180 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2181 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2182 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2183 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2184 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2185 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2186 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2187 if (!hasArchitectedFlatScratch()) 2188 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2189 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2190 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2191 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2192 2193 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2194 return MCDisassembler::Fail; 2195 2196 // Reserved for GFX9 2197 if (isGFX9() && 2198 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2199 return MCDisassembler::Fail; 2200 } else if (isGFX10Plus()) { 2201 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2202 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2203 } 2204 2205 // FIXME: We should be looking at the ELF header ABI version for this. 2206 if (AMDGPU::getDefaultAMDHSACodeObjectVersion() >= AMDGPU::AMDHSA_COV5) 2207 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2208 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2209 2210 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2211 return MCDisassembler::Fail; 2212 2213 return MCDisassembler::Success; 2214 2215 case amdhsa::KERNARG_PRELOAD_OFFSET: 2216 using namespace amdhsa; 2217 TwoByteBuffer = DE.getU16(Cursor); 2218 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2219 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2220 KERNARG_PRELOAD_SPEC_LENGTH); 2221 } 2222 2223 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2224 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2225 KERNARG_PRELOAD_SPEC_OFFSET); 2226 } 2227 return MCDisassembler::Success; 2228 2229 case amdhsa::RESERVED3_OFFSET: 2230 // 4 bytes from here are reserved, must be 0. 2231 ReservedBytes = DE.getBytes(Cursor, 4); 2232 for (int I = 0; I < 4; ++I) { 2233 if (ReservedBytes[I] != 0) 2234 return MCDisassembler::Fail; 2235 } 2236 return MCDisassembler::Success; 2237 2238 default: 2239 llvm_unreachable("Unhandled index. Case statements cover everything."); 2240 return MCDisassembler::Fail; 2241 } 2242 #undef PRINT_DIRECTIVE 2243 } 2244 2245 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2246 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2247 // CP microcode requires the kernel descriptor to be 64 aligned. 2248 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2249 return MCDisassembler::Fail; 2250 2251 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2252 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2253 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2254 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2255 // when required. 2256 if (isGFX10Plus()) { 2257 uint16_t KernelCodeProperties = 2258 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2259 llvm::endianness::little); 2260 EnableWavefrontSize32 = 2261 AMDHSA_BITS_GET(KernelCodeProperties, 2262 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2263 } 2264 2265 std::string Kd; 2266 raw_string_ostream KdStream(Kd); 2267 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2268 2269 DataExtractor::Cursor C(0); 2270 while (C && C.tell() < Bytes.size()) { 2271 MCDisassembler::DecodeStatus Status = 2272 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2273 2274 cantFail(C.takeError()); 2275 2276 if (Status == MCDisassembler::Fail) 2277 return MCDisassembler::Fail; 2278 } 2279 KdStream << ".end_amdhsa_kernel\n"; 2280 outs() << KdStream.str(); 2281 return MCDisassembler::Success; 2282 } 2283 2284 std::optional<MCDisassembler::DecodeStatus> 2285 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2286 ArrayRef<uint8_t> Bytes, uint64_t Address, 2287 raw_ostream &CStream) const { 2288 // Right now only kernel descriptor needs to be handled. 2289 // We ignore all other symbols for target specific handling. 2290 // TODO: 2291 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2292 // Object V2 and V3 when symbols are marked protected. 2293 2294 // amd_kernel_code_t for Code Object V2. 2295 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2296 Size = 256; 2297 return MCDisassembler::Fail; 2298 } 2299 2300 // Code Object V3 kernel descriptors. 2301 StringRef Name = Symbol.Name; 2302 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2303 Size = 64; // Size = 64 regardless of success or failure. 2304 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2305 } 2306 return std::nullopt; 2307 } 2308 2309 //===----------------------------------------------------------------------===// 2310 // AMDGPUSymbolizer 2311 //===----------------------------------------------------------------------===// 2312 2313 // Try to find symbol name for specified label 2314 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2315 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2316 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2317 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2318 2319 if (!IsBranch) { 2320 return false; 2321 } 2322 2323 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2324 if (!Symbols) 2325 return false; 2326 2327 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2328 return Val.Addr == static_cast<uint64_t>(Value) && 2329 Val.Type == ELF::STT_NOTYPE; 2330 }); 2331 if (Result != Symbols->end()) { 2332 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2333 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2334 Inst.addOperand(MCOperand::createExpr(Add)); 2335 return true; 2336 } 2337 // Add to list of referenced addresses, so caller can synthesize a label. 2338 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2339 return false; 2340 } 2341 2342 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2343 int64_t Value, 2344 uint64_t Address) { 2345 llvm_unreachable("unimplemented"); 2346 } 2347 2348 //===----------------------------------------------------------------------===// 2349 // Initialization 2350 //===----------------------------------------------------------------------===// 2351 2352 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2353 LLVMOpInfoCallback /*GetOpInfo*/, 2354 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2355 void *DisInfo, 2356 MCContext *Ctx, 2357 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2358 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2359 } 2360 2361 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2362 const MCSubtargetInfo &STI, 2363 MCContext &Ctx) { 2364 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2365 } 2366 2367 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2368 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2369 createAMDGPUDisassembler); 2370 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2371 createAMDGPUSymbolizer); 2372 } 2373