1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/BinaryFormat/ELF.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCExpr.h" 28 #include "llvm/MC/MCFixedLenDisassembler.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/AMDHSAKernelDescriptor.h" 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 #define SGPR_MAX \ 40 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 41 : AMDGPU::EncValues::SGPR_MAX_SI) 42 43 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 44 45 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 46 MCContext &Ctx, 47 MCInstrInfo const *MCII) : 48 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 49 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 50 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, const void *Decoder) { 77 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 78 79 // Our branches take a simm16, but we need two extra bits to account for the 80 // factor of 4. 81 APInt SignedOffset(18, Imm * 4, true); 82 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 83 84 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 85 return MCDisassembler::Success; 86 return addOperand(Inst, MCOperand::createImm(Imm)); 87 } 88 89 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, 90 uint64_t Addr, const void *Decoder) { 91 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 92 int64_t Offset; 93 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 94 Offset = Imm & 0xFFFFF; 95 } else { // GFX9+ supports 21-bit signed offsets. 96 Offset = SignExtend64<21>(Imm); 97 } 98 return addOperand(Inst, MCOperand::createImm(Offset)); 99 } 100 101 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, 102 uint64_t Addr, const void *Decoder) { 103 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 104 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 105 } 106 107 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 108 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 109 unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const void *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 #define DECODE_OPERAND_REG(RegClass) \ 117 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 118 119 DECODE_OPERAND_REG(VGPR_32) 120 DECODE_OPERAND_REG(VRegOrLds_32) 121 DECODE_OPERAND_REG(VS_32) 122 DECODE_OPERAND_REG(VS_64) 123 DECODE_OPERAND_REG(VS_128) 124 125 DECODE_OPERAND_REG(VReg_64) 126 DECODE_OPERAND_REG(VReg_96) 127 DECODE_OPERAND_REG(VReg_128) 128 DECODE_OPERAND_REG(VReg_256) 129 DECODE_OPERAND_REG(VReg_512) 130 DECODE_OPERAND_REG(VReg_1024) 131 132 DECODE_OPERAND_REG(SReg_32) 133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 135 DECODE_OPERAND_REG(SRegOrLds_32) 136 DECODE_OPERAND_REG(SReg_64) 137 DECODE_OPERAND_REG(SReg_64_XEXEC) 138 DECODE_OPERAND_REG(SReg_128) 139 DECODE_OPERAND_REG(SReg_256) 140 DECODE_OPERAND_REG(SReg_512) 141 142 DECODE_OPERAND_REG(AGPR_32) 143 DECODE_OPERAND_REG(AReg_64) 144 DECODE_OPERAND_REG(AReg_128) 145 DECODE_OPERAND_REG(AReg_256) 146 DECODE_OPERAND_REG(AReg_512) 147 DECODE_OPERAND_REG(AReg_1024) 148 DECODE_OPERAND_REG(AV_32) 149 DECODE_OPERAND_REG(AV_64) 150 DECODE_OPERAND_REG(AV_128) 151 DECODE_OPERAND_REG(AV_512) 152 153 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 154 unsigned Imm, 155 uint64_t Addr, 156 const void *Decoder) { 157 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 158 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 159 } 160 161 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 162 unsigned Imm, 163 uint64_t Addr, 164 const void *Decoder) { 165 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 166 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 167 } 168 169 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, 170 unsigned Imm, 171 uint64_t Addr, 172 const void *Decoder) { 173 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 174 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 175 } 176 177 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, 178 unsigned Imm, 179 uint64_t Addr, 180 const void *Decoder) { 181 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 182 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 183 } 184 185 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, 186 unsigned Imm, 187 uint64_t Addr, 188 const void *Decoder) { 189 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 190 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 191 } 192 193 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, 194 unsigned Imm, 195 uint64_t Addr, 196 const void *Decoder) { 197 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 198 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 199 } 200 201 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, 202 unsigned Imm, 203 uint64_t Addr, 204 const void *Decoder) { 205 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 206 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 207 } 208 209 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, 210 unsigned Imm, 211 uint64_t Addr, 212 const void *Decoder) { 213 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 214 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 215 } 216 217 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, 218 unsigned Imm, 219 uint64_t Addr, 220 const void *Decoder) { 221 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 222 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 223 } 224 225 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, 226 unsigned Imm, 227 uint64_t Addr, 228 const void *Decoder) { 229 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 230 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 231 } 232 233 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, 234 unsigned Imm, 235 uint64_t Addr, 236 const void *Decoder) { 237 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 238 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 239 } 240 241 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, 242 unsigned Imm, 243 uint64_t Addr, 244 const void *Decoder) { 245 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 246 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 247 } 248 249 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, 250 unsigned Imm, 251 uint64_t Addr, 252 const void *Decoder) { 253 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 254 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 255 } 256 257 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, 258 unsigned Imm, 259 uint64_t Addr, 260 const void *Decoder) { 261 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 262 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 263 } 264 265 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, 266 unsigned Imm, 267 uint64_t Addr, 268 const void *Decoder) { 269 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 270 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 271 } 272 273 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 274 uint64_t Addr, const void *Decoder) { 275 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 276 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 277 } 278 279 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 280 uint64_t Addr, const void *Decoder) { 281 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 282 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 283 } 284 285 static DecodeStatus decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, 286 uint64_t Addr, 287 const void *Decoder) { 288 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 289 return addOperand( 290 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 291 } 292 293 static DecodeStatus decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, 294 uint64_t Addr, 295 const void *Decoder) { 296 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 297 return addOperand( 298 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 299 } 300 301 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 302 const MCRegisterInfo *MRI) { 303 if (OpIdx < 0) 304 return false; 305 306 const MCOperand &Op = Inst.getOperand(OpIdx); 307 if (!Op.isReg()) 308 return false; 309 310 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 311 auto Reg = Sub ? Sub : Op.getReg(); 312 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 313 } 314 315 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, 316 unsigned Imm, 317 AMDGPUDisassembler::OpWidthTy Opw, 318 const void *Decoder) { 319 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 320 if (!DAsm->isGFX90A()) { 321 Imm &= 511; 322 } else { 323 // If atomic has both vdata and vdst their register classes are tied. 324 // The bit is decoded along with the vdst, first operand. We need to 325 // change register class to AGPR if vdst was AGPR. 326 // If a DS instruction has both data0 and data1 their register classes 327 // are also tied. 328 unsigned Opc = Inst.getOpcode(); 329 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 330 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 331 : AMDGPU::OpName::vdata; 332 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 333 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 334 if ((int)Inst.getNumOperands() == DataIdx) { 335 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 336 if (IsAGPROperand(Inst, DstIdx, MRI)) 337 Imm |= 512; 338 } 339 340 if (TSFlags & SIInstrFlags::DS) { 341 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 342 if ((int)Inst.getNumOperands() == Data2Idx && 343 IsAGPROperand(Inst, DataIdx, MRI)) 344 Imm |= 512; 345 } 346 } 347 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 348 } 349 350 static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, 351 unsigned Imm, 352 uint64_t Addr, 353 const void *Decoder) { 354 return decodeOperand_AVLdSt_Any(Inst, Imm, 355 AMDGPUDisassembler::OPW32, Decoder); 356 } 357 358 static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, 359 unsigned Imm, 360 uint64_t Addr, 361 const void *Decoder) { 362 return decodeOperand_AVLdSt_Any(Inst, Imm, 363 AMDGPUDisassembler::OPW64, Decoder); 364 } 365 366 static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, 367 unsigned Imm, 368 uint64_t Addr, 369 const void *Decoder) { 370 return decodeOperand_AVLdSt_Any(Inst, Imm, 371 AMDGPUDisassembler::OPW96, Decoder); 372 } 373 374 static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, 375 unsigned Imm, 376 uint64_t Addr, 377 const void *Decoder) { 378 return decodeOperand_AVLdSt_Any(Inst, Imm, 379 AMDGPUDisassembler::OPW128, Decoder); 380 } 381 382 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, 383 unsigned Imm, 384 uint64_t Addr, 385 const void *Decoder) { 386 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 387 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 388 } 389 390 #define DECODE_SDWA(DecName) \ 391 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 392 393 DECODE_SDWA(Src32) 394 DECODE_SDWA(Src16) 395 DECODE_SDWA(VopcDst) 396 397 #include "AMDGPUGenDisassemblerTables.inc" 398 399 //===----------------------------------------------------------------------===// 400 // 401 //===----------------------------------------------------------------------===// 402 403 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 404 assert(Bytes.size() >= sizeof(T)); 405 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 406 Bytes = Bytes.slice(sizeof(T)); 407 return Res; 408 } 409 410 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 411 MCInst &MI, 412 uint64_t Inst, 413 uint64_t Address) const { 414 assert(MI.getOpcode() == 0); 415 assert(MI.getNumOperands() == 0); 416 MCInst TmpInst; 417 HasLiteral = false; 418 const auto SavedBytes = Bytes; 419 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 420 MI = TmpInst; 421 return MCDisassembler::Success; 422 } 423 Bytes = SavedBytes; 424 return MCDisassembler::Fail; 425 } 426 427 // The disassembler is greedy, so we need to check FI operand value to 428 // not parse a dpp if the correct literal is not set. For dpp16 the 429 // autogenerated decoder checks the dpp literal 430 static bool isValidDPP8(const MCInst &MI) { 431 using namespace llvm::AMDGPU::DPP; 432 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 433 assert(FiIdx != -1); 434 if ((unsigned)FiIdx >= MI.getNumOperands()) 435 return false; 436 unsigned Fi = MI.getOperand(FiIdx).getImm(); 437 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 438 } 439 440 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 441 ArrayRef<uint8_t> Bytes_, 442 uint64_t Address, 443 raw_ostream &CS) const { 444 CommentStream = &CS; 445 bool IsSDWA = false; 446 447 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 448 Bytes = Bytes_.slice(0, MaxInstBytesNum); 449 450 DecodeStatus Res = MCDisassembler::Fail; 451 do { 452 // ToDo: better to switch encoding length using some bit predicate 453 // but it is unknown yet, so try all we can 454 455 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 456 // encodings 457 if (Bytes.size() >= 8) { 458 const uint64_t QW = eatBytes<uint64_t>(Bytes); 459 460 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 461 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 462 if (Res) { 463 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 464 == -1) 465 break; 466 if (convertDPP8Inst(MI) == MCDisassembler::Success) 467 break; 468 MI = MCInst(); // clear 469 } 470 } 471 472 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 473 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 474 break; 475 476 MI = MCInst(); // clear 477 478 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 479 if (Res) break; 480 481 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 482 if (Res) { IsSDWA = true; break; } 483 484 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 485 if (Res) { IsSDWA = true; break; } 486 487 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 488 if (Res) { IsSDWA = true; break; } 489 490 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 491 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 492 if (Res) 493 break; 494 } 495 496 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 497 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 498 // table first so we print the correct name. 499 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 500 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 501 if (Res) 502 break; 503 } 504 } 505 506 // Reinitialize Bytes as DPP64 could have eaten too much 507 Bytes = Bytes_.slice(0, MaxInstBytesNum); 508 509 // Try decode 32-bit instruction 510 if (Bytes.size() < 4) break; 511 const uint32_t DW = eatBytes<uint32_t>(Bytes); 512 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 513 if (Res) break; 514 515 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 516 if (Res) break; 517 518 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 519 if (Res) break; 520 521 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 522 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 523 if (Res) 524 break; 525 } 526 527 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 528 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 529 if (Res) break; 530 } 531 532 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 533 if (Res) break; 534 535 if (Bytes.size() < 4) break; 536 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 537 538 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 539 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 540 if (Res) 541 break; 542 } 543 544 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 545 if (Res) break; 546 547 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 548 if (Res) break; 549 550 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 551 if (Res) break; 552 553 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 554 } while (false); 555 556 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 557 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 558 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 559 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 560 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 561 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 562 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 563 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 564 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 565 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 566 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 567 // Insert dummy unused src2_modifiers. 568 insertNamedMCOperand(MI, MCOperand::createImm(0), 569 AMDGPU::OpName::src2_modifiers); 570 } 571 572 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 573 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 574 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 575 AMDGPU::OpName::cpol); 576 if (CPolPos != -1) { 577 unsigned CPol = 578 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 579 AMDGPU::CPol::GLC : 0; 580 if (MI.getNumOperands() <= (unsigned)CPolPos) { 581 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 582 AMDGPU::OpName::cpol); 583 } else if (CPol) { 584 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 585 } 586 } 587 } 588 589 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 590 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 591 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 592 // GFX90A lost TFE, its place is occupied by ACC. 593 int TFEOpIdx = 594 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 595 if (TFEOpIdx != -1) { 596 auto TFEIter = MI.begin(); 597 std::advance(TFEIter, TFEOpIdx); 598 MI.insert(TFEIter, MCOperand::createImm(0)); 599 } 600 } 601 602 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 603 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 604 int SWZOpIdx = 605 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 606 if (SWZOpIdx != -1) { 607 auto SWZIter = MI.begin(); 608 std::advance(SWZIter, SWZOpIdx); 609 MI.insert(SWZIter, MCOperand::createImm(0)); 610 } 611 } 612 613 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 614 int VAddr0Idx = 615 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 616 int RsrcIdx = 617 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 618 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 619 if (VAddr0Idx >= 0 && NSAArgs > 0) { 620 unsigned NSAWords = (NSAArgs + 3) / 4; 621 if (Bytes.size() < 4 * NSAWords) { 622 Res = MCDisassembler::Fail; 623 } else { 624 for (unsigned i = 0; i < NSAArgs; ++i) { 625 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 626 decodeOperand_VGPR_32(Bytes[i])); 627 } 628 Bytes = Bytes.slice(4 * NSAWords); 629 } 630 } 631 632 if (Res) 633 Res = convertMIMGInst(MI); 634 } 635 636 if (Res && IsSDWA) 637 Res = convertSDWAInst(MI); 638 639 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 640 AMDGPU::OpName::vdst_in); 641 if (VDstIn_Idx != -1) { 642 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 643 MCOI::OperandConstraint::TIED_TO); 644 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 645 !MI.getOperand(VDstIn_Idx).isReg() || 646 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 647 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 648 MI.erase(&MI.getOperand(VDstIn_Idx)); 649 insertNamedMCOperand(MI, 650 MCOperand::createReg(MI.getOperand(Tied).getReg()), 651 AMDGPU::OpName::vdst_in); 652 } 653 } 654 655 int ImmLitIdx = 656 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 657 if (Res && ImmLitIdx != -1) 658 Res = convertFMAanyK(MI, ImmLitIdx); 659 660 // if the opcode was not recognized we'll assume a Size of 4 bytes 661 // (unless there are fewer bytes left) 662 Size = Res ? (MaxInstBytesNum - Bytes.size()) 663 : std::min((size_t)4, Bytes_.size()); 664 return Res; 665 } 666 667 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 668 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 669 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 670 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 671 // VOPC - insert clamp 672 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 673 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 674 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 675 if (SDst != -1) { 676 // VOPC - insert VCC register as sdst 677 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 678 AMDGPU::OpName::sdst); 679 } else { 680 // VOP1/2 - insert omod if present in instruction 681 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 682 } 683 } 684 return MCDisassembler::Success; 685 } 686 687 // We must check FI == literal to reject not genuine dpp8 insts, and we must 688 // first add optional MI operands to check FI 689 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 690 unsigned Opc = MI.getOpcode(); 691 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 692 693 // Insert dummy unused src modifiers. 694 if (MI.getNumOperands() < DescNumOps && 695 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 696 insertNamedMCOperand(MI, MCOperand::createImm(0), 697 AMDGPU::OpName::src0_modifiers); 698 699 if (MI.getNumOperands() < DescNumOps && 700 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 701 insertNamedMCOperand(MI, MCOperand::createImm(0), 702 AMDGPU::OpName::src1_modifiers); 703 704 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 705 } 706 707 // Note that before gfx10, the MIMG encoding provided no information about 708 // VADDR size. Consequently, decoded instructions always show address as if it 709 // has 1 dword, which could be not really so. 710 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 711 712 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 713 AMDGPU::OpName::vdst); 714 715 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 716 AMDGPU::OpName::vdata); 717 int VAddr0Idx = 718 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 719 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 720 AMDGPU::OpName::dmask); 721 722 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 723 AMDGPU::OpName::tfe); 724 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 725 AMDGPU::OpName::d16); 726 727 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 728 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 729 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 730 731 assert(VDataIdx != -1); 732 if (BaseOpcode->BVH) { 733 // Add A16 operand for intersect_ray instructions 734 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 735 addOperand(MI, MCOperand::createImm(1)); 736 } 737 return MCDisassembler::Success; 738 } 739 740 bool IsAtomic = (VDstIdx != -1); 741 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 742 bool IsNSA = false; 743 unsigned AddrSize = Info->VAddrDwords; 744 745 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 746 unsigned DimIdx = 747 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 748 int A16Idx = 749 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 750 const AMDGPU::MIMGDimInfo *Dim = 751 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 752 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 753 754 AddrSize = 755 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 756 757 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 758 if (!IsNSA) { 759 if (AddrSize > 8) 760 AddrSize = 16; 761 } else { 762 if (AddrSize > Info->VAddrDwords) { 763 // The NSA encoding does not contain enough operands for the combination 764 // of base opcode / dimension. Should this be an error? 765 return MCDisassembler::Success; 766 } 767 } 768 } 769 770 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 771 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 772 773 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 774 if (D16 && AMDGPU::hasPackedD16(STI)) { 775 DstSize = (DstSize + 1) / 2; 776 } 777 778 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 779 DstSize += 1; 780 781 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 782 return MCDisassembler::Success; 783 784 int NewOpcode = 785 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 786 if (NewOpcode == -1) 787 return MCDisassembler::Success; 788 789 // Widen the register to the correct number of enabled channels. 790 unsigned NewVdata = AMDGPU::NoRegister; 791 if (DstSize != Info->VDataDwords) { 792 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 793 794 // Get first subregister of VData 795 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 796 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 797 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 798 799 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 800 &MRI.getRegClass(DataRCID)); 801 if (NewVdata == AMDGPU::NoRegister) { 802 // It's possible to encode this such that the low register + enabled 803 // components exceeds the register count. 804 return MCDisassembler::Success; 805 } 806 } 807 808 unsigned NewVAddr0 = AMDGPU::NoRegister; 809 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 810 AddrSize != Info->VAddrDwords) { 811 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 812 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 813 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 814 815 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 816 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 817 &MRI.getRegClass(AddrRCID)); 818 if (NewVAddr0 == AMDGPU::NoRegister) 819 return MCDisassembler::Success; 820 } 821 822 MI.setOpcode(NewOpcode); 823 824 if (NewVdata != AMDGPU::NoRegister) { 825 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 826 827 if (IsAtomic) { 828 // Atomic operations have an additional operand (a copy of data) 829 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 830 } 831 } 832 833 if (NewVAddr0 != AMDGPU::NoRegister) { 834 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 835 } else if (IsNSA) { 836 assert(AddrSize <= Info->VAddrDwords); 837 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 838 MI.begin() + VAddr0Idx + Info->VAddrDwords); 839 } 840 841 return MCDisassembler::Success; 842 } 843 844 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 845 int ImmLitIdx) const { 846 assert(HasLiteral && "Should have decoded a literal"); 847 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 848 unsigned DescNumOps = Desc.getNumOperands(); 849 assert(DescNumOps == MI.getNumOperands()); 850 for (unsigned I = 0; I < DescNumOps; ++I) { 851 auto &Op = MI.getOperand(I); 852 auto OpType = Desc.OpInfo[I].OperandType; 853 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 854 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 855 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 856 IsDeferredOp) 857 Op.setImm(Literal); 858 } 859 return MCDisassembler::Success; 860 } 861 862 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 863 return getContext().getRegisterInfo()-> 864 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 865 } 866 867 inline 868 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 869 const Twine& ErrMsg) const { 870 *CommentStream << "Error: " + ErrMsg; 871 872 // ToDo: add support for error operands to MCInst.h 873 // return MCOperand::createError(V); 874 return MCOperand(); 875 } 876 877 inline 878 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 879 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 880 } 881 882 inline 883 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 884 unsigned Val) const { 885 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 886 if (Val >= RegCl.getNumRegs()) 887 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 888 ": unknown register " + Twine(Val)); 889 return createRegOperand(RegCl.getRegister(Val)); 890 } 891 892 inline 893 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 894 unsigned Val) const { 895 // ToDo: SI/CI have 104 SGPRs, VI - 102 896 // Valery: here we accepting as much as we can, let assembler sort it out 897 int shift = 0; 898 switch (SRegClassID) { 899 case AMDGPU::SGPR_32RegClassID: 900 case AMDGPU::TTMP_32RegClassID: 901 break; 902 case AMDGPU::SGPR_64RegClassID: 903 case AMDGPU::TTMP_64RegClassID: 904 shift = 1; 905 break; 906 case AMDGPU::SGPR_128RegClassID: 907 case AMDGPU::TTMP_128RegClassID: 908 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 909 // this bundle? 910 case AMDGPU::SGPR_256RegClassID: 911 case AMDGPU::TTMP_256RegClassID: 912 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 913 // this bundle? 914 case AMDGPU::SGPR_512RegClassID: 915 case AMDGPU::TTMP_512RegClassID: 916 shift = 2; 917 break; 918 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 919 // this bundle? 920 default: 921 llvm_unreachable("unhandled register class"); 922 } 923 924 if (Val % (1 << shift)) { 925 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 926 << ": scalar reg isn't aligned " << Val; 927 } 928 929 return createRegOperand(SRegClassID, Val >> shift); 930 } 931 932 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 933 return decodeSrcOp(OPW32, Val); 934 } 935 936 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 937 return decodeSrcOp(OPW64, Val); 938 } 939 940 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 941 return decodeSrcOp(OPW128, Val); 942 } 943 944 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 945 return decodeSrcOp(OPW16, Val); 946 } 947 948 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 949 return decodeSrcOp(OPWV216, Val); 950 } 951 952 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 953 return decodeSrcOp(OPWV232, Val); 954 } 955 956 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 957 // Some instructions have operand restrictions beyond what the encoding 958 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 959 // high bit. 960 Val &= 255; 961 962 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 963 } 964 965 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 966 return decodeSrcOp(OPW32, Val); 967 } 968 969 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 970 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 971 } 972 973 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 974 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 975 } 976 977 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 978 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 979 } 980 981 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 982 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 983 } 984 985 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 986 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 987 } 988 989 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 990 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 991 } 992 993 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 994 return decodeSrcOp(OPW32, Val); 995 } 996 997 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 998 return decodeSrcOp(OPW64, Val); 999 } 1000 1001 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1002 return decodeSrcOp(OPW128, Val); 1003 } 1004 1005 MCOperand AMDGPUDisassembler::decodeOperand_AV_512(unsigned Val) const { 1006 return decodeSrcOp(OPW512, Val); 1007 } 1008 1009 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1010 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1011 } 1012 1013 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1014 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1015 } 1016 1017 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1018 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1019 } 1020 1021 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1022 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1023 } 1024 1025 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1026 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1027 } 1028 1029 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1030 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1031 } 1032 1033 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1034 // table-gen generated disassembler doesn't care about operand types 1035 // leaving only registry class so SSrc_32 operand turns into SReg_32 1036 // and therefore we accept immediates and literals here as well 1037 return decodeSrcOp(OPW32, Val); 1038 } 1039 1040 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1041 unsigned Val) const { 1042 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1043 return decodeOperand_SReg_32(Val); 1044 } 1045 1046 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1047 unsigned Val) const { 1048 // SReg_32_XM0 is SReg_32 without EXEC_HI 1049 return decodeOperand_SReg_32(Val); 1050 } 1051 1052 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1053 // table-gen generated disassembler doesn't care about operand types 1054 // leaving only registry class so SSrc_32 operand turns into SReg_32 1055 // and therefore we accept immediates and literals here as well 1056 return decodeSrcOp(OPW32, Val); 1057 } 1058 1059 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1060 return decodeSrcOp(OPW64, Val); 1061 } 1062 1063 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1064 return decodeSrcOp(OPW64, Val); 1065 } 1066 1067 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1068 return decodeSrcOp(OPW128, Val); 1069 } 1070 1071 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1072 return decodeDstOp(OPW256, Val); 1073 } 1074 1075 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1076 return decodeDstOp(OPW512, Val); 1077 } 1078 1079 // Decode Literals for insts which always have a literal in the encoding 1080 MCOperand 1081 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1082 if (HasLiteral) { 1083 if (Literal != Val) 1084 return errOperand(Val, "More than one unique literal is illegal"); 1085 } 1086 HasLiteral = true; 1087 Literal = Val; 1088 return MCOperand::createImm(Literal); 1089 } 1090 1091 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1092 // For now all literal constants are supposed to be unsigned integer 1093 // ToDo: deal with signed/unsigned 64-bit integer constants 1094 // ToDo: deal with float/double constants 1095 if (!HasLiteral) { 1096 if (Bytes.size() < 4) { 1097 return errOperand(0, "cannot read literal, inst bytes left " + 1098 Twine(Bytes.size())); 1099 } 1100 HasLiteral = true; 1101 Literal = eatBytes<uint32_t>(Bytes); 1102 } 1103 return MCOperand::createImm(Literal); 1104 } 1105 1106 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1107 using namespace AMDGPU::EncValues; 1108 1109 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1110 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1111 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1112 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1113 // Cast prevents negative overflow. 1114 } 1115 1116 static int64_t getInlineImmVal32(unsigned Imm) { 1117 switch (Imm) { 1118 case 240: 1119 return FloatToBits(0.5f); 1120 case 241: 1121 return FloatToBits(-0.5f); 1122 case 242: 1123 return FloatToBits(1.0f); 1124 case 243: 1125 return FloatToBits(-1.0f); 1126 case 244: 1127 return FloatToBits(2.0f); 1128 case 245: 1129 return FloatToBits(-2.0f); 1130 case 246: 1131 return FloatToBits(4.0f); 1132 case 247: 1133 return FloatToBits(-4.0f); 1134 case 248: // 1 / (2 * PI) 1135 return 0x3e22f983; 1136 default: 1137 llvm_unreachable("invalid fp inline imm"); 1138 } 1139 } 1140 1141 static int64_t getInlineImmVal64(unsigned Imm) { 1142 switch (Imm) { 1143 case 240: 1144 return DoubleToBits(0.5); 1145 case 241: 1146 return DoubleToBits(-0.5); 1147 case 242: 1148 return DoubleToBits(1.0); 1149 case 243: 1150 return DoubleToBits(-1.0); 1151 case 244: 1152 return DoubleToBits(2.0); 1153 case 245: 1154 return DoubleToBits(-2.0); 1155 case 246: 1156 return DoubleToBits(4.0); 1157 case 247: 1158 return DoubleToBits(-4.0); 1159 case 248: // 1 / (2 * PI) 1160 return 0x3fc45f306dc9c882; 1161 default: 1162 llvm_unreachable("invalid fp inline imm"); 1163 } 1164 } 1165 1166 static int64_t getInlineImmVal16(unsigned Imm) { 1167 switch (Imm) { 1168 case 240: 1169 return 0x3800; 1170 case 241: 1171 return 0xB800; 1172 case 242: 1173 return 0x3C00; 1174 case 243: 1175 return 0xBC00; 1176 case 244: 1177 return 0x4000; 1178 case 245: 1179 return 0xC000; 1180 case 246: 1181 return 0x4400; 1182 case 247: 1183 return 0xC400; 1184 case 248: // 1 / (2 * PI) 1185 return 0x3118; 1186 default: 1187 llvm_unreachable("invalid fp inline imm"); 1188 } 1189 } 1190 1191 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1192 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1193 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1194 1195 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1196 switch (Width) { 1197 case OPW32: 1198 case OPW128: // splat constants 1199 case OPW512: 1200 case OPW1024: 1201 case OPWV232: 1202 return MCOperand::createImm(getInlineImmVal32(Imm)); 1203 case OPW64: 1204 case OPW256: 1205 return MCOperand::createImm(getInlineImmVal64(Imm)); 1206 case OPW16: 1207 case OPWV216: 1208 return MCOperand::createImm(getInlineImmVal16(Imm)); 1209 default: 1210 llvm_unreachable("implement me"); 1211 } 1212 } 1213 1214 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1215 using namespace AMDGPU; 1216 1217 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1218 switch (Width) { 1219 default: // fall 1220 case OPW32: 1221 case OPW16: 1222 case OPWV216: 1223 return VGPR_32RegClassID; 1224 case OPW64: 1225 case OPWV232: return VReg_64RegClassID; 1226 case OPW96: return VReg_96RegClassID; 1227 case OPW128: return VReg_128RegClassID; 1228 case OPW160: return VReg_160RegClassID; 1229 case OPW256: return VReg_256RegClassID; 1230 case OPW512: return VReg_512RegClassID; 1231 case OPW1024: return VReg_1024RegClassID; 1232 } 1233 } 1234 1235 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1236 using namespace AMDGPU; 1237 1238 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1239 switch (Width) { 1240 default: // fall 1241 case OPW32: 1242 case OPW16: 1243 case OPWV216: 1244 return AGPR_32RegClassID; 1245 case OPW64: 1246 case OPWV232: return AReg_64RegClassID; 1247 case OPW96: return AReg_96RegClassID; 1248 case OPW128: return AReg_128RegClassID; 1249 case OPW160: return AReg_160RegClassID; 1250 case OPW256: return AReg_256RegClassID; 1251 case OPW512: return AReg_512RegClassID; 1252 case OPW1024: return AReg_1024RegClassID; 1253 } 1254 } 1255 1256 1257 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1258 using namespace AMDGPU; 1259 1260 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1261 switch (Width) { 1262 default: // fall 1263 case OPW32: 1264 case OPW16: 1265 case OPWV216: 1266 return SGPR_32RegClassID; 1267 case OPW64: 1268 case OPWV232: return SGPR_64RegClassID; 1269 case OPW96: return SGPR_96RegClassID; 1270 case OPW128: return SGPR_128RegClassID; 1271 case OPW160: return SGPR_160RegClassID; 1272 case OPW256: return SGPR_256RegClassID; 1273 case OPW512: return SGPR_512RegClassID; 1274 } 1275 } 1276 1277 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1278 using namespace AMDGPU; 1279 1280 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1281 switch (Width) { 1282 default: // fall 1283 case OPW32: 1284 case OPW16: 1285 case OPWV216: 1286 return TTMP_32RegClassID; 1287 case OPW64: 1288 case OPWV232: return TTMP_64RegClassID; 1289 case OPW128: return TTMP_128RegClassID; 1290 case OPW256: return TTMP_256RegClassID; 1291 case OPW512: return TTMP_512RegClassID; 1292 } 1293 } 1294 1295 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1296 using namespace AMDGPU::EncValues; 1297 1298 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1299 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1300 1301 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1302 } 1303 1304 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1305 bool MandatoryLiteral) const { 1306 using namespace AMDGPU::EncValues; 1307 1308 assert(Val < 1024); // enum10 1309 1310 bool IsAGPR = Val & 512; 1311 Val &= 511; 1312 1313 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1314 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1315 : getVgprClassId(Width), Val - VGPR_MIN); 1316 } 1317 if (Val <= SGPR_MAX) { 1318 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1319 static_assert(SGPR_MIN == 0, ""); 1320 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1321 } 1322 1323 int TTmpIdx = getTTmpIdx(Val); 1324 if (TTmpIdx >= 0) { 1325 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1326 } 1327 1328 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1329 return decodeIntImmed(Val); 1330 1331 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1332 return decodeFPImmed(Width, Val); 1333 1334 if (Val == LITERAL_CONST) { 1335 if (MandatoryLiteral) 1336 // Keep a sentinel value for deferred setting 1337 return MCOperand::createImm(LITERAL_CONST); 1338 else 1339 return decodeLiteralConstant(); 1340 } 1341 1342 switch (Width) { 1343 case OPW32: 1344 case OPW16: 1345 case OPWV216: 1346 return decodeSpecialReg32(Val); 1347 case OPW64: 1348 case OPWV232: 1349 return decodeSpecialReg64(Val); 1350 default: 1351 llvm_unreachable("unexpected immediate type"); 1352 } 1353 } 1354 1355 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1356 using namespace AMDGPU::EncValues; 1357 1358 assert(Val < 128); 1359 assert(Width == OPW256 || Width == OPW512); 1360 1361 if (Val <= SGPR_MAX) { 1362 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1363 static_assert(SGPR_MIN == 0, ""); 1364 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1365 } 1366 1367 int TTmpIdx = getTTmpIdx(Val); 1368 if (TTmpIdx >= 0) { 1369 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1370 } 1371 1372 llvm_unreachable("unknown dst register"); 1373 } 1374 1375 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1376 using namespace AMDGPU; 1377 1378 switch (Val) { 1379 case 102: return createRegOperand(FLAT_SCR_LO); 1380 case 103: return createRegOperand(FLAT_SCR_HI); 1381 case 104: return createRegOperand(XNACK_MASK_LO); 1382 case 105: return createRegOperand(XNACK_MASK_HI); 1383 case 106: return createRegOperand(VCC_LO); 1384 case 107: return createRegOperand(VCC_HI); 1385 case 108: return createRegOperand(TBA_LO); 1386 case 109: return createRegOperand(TBA_HI); 1387 case 110: return createRegOperand(TMA_LO); 1388 case 111: return createRegOperand(TMA_HI); 1389 case 124: return createRegOperand(M0); 1390 case 125: return createRegOperand(SGPR_NULL); 1391 case 126: return createRegOperand(EXEC_LO); 1392 case 127: return createRegOperand(EXEC_HI); 1393 case 235: return createRegOperand(SRC_SHARED_BASE); 1394 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1395 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1396 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1397 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1398 case 251: return createRegOperand(SRC_VCCZ); 1399 case 252: return createRegOperand(SRC_EXECZ); 1400 case 253: return createRegOperand(SRC_SCC); 1401 case 254: return createRegOperand(LDS_DIRECT); 1402 default: break; 1403 } 1404 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1405 } 1406 1407 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1408 using namespace AMDGPU; 1409 1410 switch (Val) { 1411 case 102: return createRegOperand(FLAT_SCR); 1412 case 104: return createRegOperand(XNACK_MASK); 1413 case 106: return createRegOperand(VCC); 1414 case 108: return createRegOperand(TBA); 1415 case 110: return createRegOperand(TMA); 1416 case 125: return createRegOperand(SGPR_NULL); 1417 case 126: return createRegOperand(EXEC); 1418 case 235: return createRegOperand(SRC_SHARED_BASE); 1419 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1420 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1421 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1422 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1423 case 251: return createRegOperand(SRC_VCCZ); 1424 case 252: return createRegOperand(SRC_EXECZ); 1425 case 253: return createRegOperand(SRC_SCC); 1426 default: break; 1427 } 1428 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1429 } 1430 1431 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1432 const unsigned Val) const { 1433 using namespace AMDGPU::SDWA; 1434 using namespace AMDGPU::EncValues; 1435 1436 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1437 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1438 // XXX: cast to int is needed to avoid stupid warning: 1439 // compare with unsigned is always true 1440 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1441 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1442 return createRegOperand(getVgprClassId(Width), 1443 Val - SDWA9EncValues::SRC_VGPR_MIN); 1444 } 1445 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1446 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1447 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1448 return createSRegOperand(getSgprClassId(Width), 1449 Val - SDWA9EncValues::SRC_SGPR_MIN); 1450 } 1451 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1452 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1453 return createSRegOperand(getTtmpClassId(Width), 1454 Val - SDWA9EncValues::SRC_TTMP_MIN); 1455 } 1456 1457 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1458 1459 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1460 return decodeIntImmed(SVal); 1461 1462 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1463 return decodeFPImmed(Width, SVal); 1464 1465 return decodeSpecialReg32(SVal); 1466 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1467 return createRegOperand(getVgprClassId(Width), Val); 1468 } 1469 llvm_unreachable("unsupported target"); 1470 } 1471 1472 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1473 return decodeSDWASrc(OPW16, Val); 1474 } 1475 1476 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1477 return decodeSDWASrc(OPW32, Val); 1478 } 1479 1480 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1481 using namespace AMDGPU::SDWA; 1482 1483 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1484 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1485 "SDWAVopcDst should be present only on GFX9+"); 1486 1487 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1488 1489 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1490 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1491 1492 int TTmpIdx = getTTmpIdx(Val); 1493 if (TTmpIdx >= 0) { 1494 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1495 return createSRegOperand(TTmpClsId, TTmpIdx); 1496 } else if (Val > SGPR_MAX) { 1497 return IsWave64 ? decodeSpecialReg64(Val) 1498 : decodeSpecialReg32(Val); 1499 } else { 1500 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1501 } 1502 } else { 1503 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1504 } 1505 } 1506 1507 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1508 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1509 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1510 } 1511 1512 bool AMDGPUDisassembler::isVI() const { 1513 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1514 } 1515 1516 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1517 1518 bool AMDGPUDisassembler::isGFX90A() const { 1519 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1520 } 1521 1522 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1523 1524 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1525 1526 bool AMDGPUDisassembler::isGFX10Plus() const { 1527 return AMDGPU::isGFX10Plus(STI); 1528 } 1529 1530 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1531 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1532 } 1533 1534 //===----------------------------------------------------------------------===// 1535 // AMDGPU specific symbol handling 1536 //===----------------------------------------------------------------------===// 1537 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1538 do { \ 1539 KdStream << Indent << DIRECTIVE " " \ 1540 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1541 } while (0) 1542 1543 // NOLINTNEXTLINE(readability-identifier-naming) 1544 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1545 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1546 using namespace amdhsa; 1547 StringRef Indent = "\t"; 1548 1549 // We cannot accurately backward compute #VGPRs used from 1550 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1551 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1552 // simply calculate the inverse of what the assembler does. 1553 1554 uint32_t GranulatedWorkitemVGPRCount = 1555 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1556 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1557 1558 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1559 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1560 1561 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1562 1563 // We cannot backward compute values used to calculate 1564 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1565 // directives can't be computed: 1566 // .amdhsa_reserve_vcc 1567 // .amdhsa_reserve_flat_scratch 1568 // .amdhsa_reserve_xnack_mask 1569 // They take their respective default values if not specified in the assembly. 1570 // 1571 // GRANULATED_WAVEFRONT_SGPR_COUNT 1572 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1573 // 1574 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1575 // are set to 0. So while disassembling we consider that: 1576 // 1577 // GRANULATED_WAVEFRONT_SGPR_COUNT 1578 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1579 // 1580 // The disassembler cannot recover the original values of those 3 directives. 1581 1582 uint32_t GranulatedWavefrontSGPRCount = 1583 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1584 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1585 1586 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1587 return MCDisassembler::Fail; 1588 1589 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1590 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1591 1592 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1593 if (!hasArchitectedFlatScratch()) 1594 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1595 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1596 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1597 1598 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1599 return MCDisassembler::Fail; 1600 1601 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1602 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1603 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1604 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1605 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1606 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1607 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1608 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1609 1610 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1611 return MCDisassembler::Fail; 1612 1613 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1614 1615 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1616 return MCDisassembler::Fail; 1617 1618 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1619 1620 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1621 return MCDisassembler::Fail; 1622 1623 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1624 return MCDisassembler::Fail; 1625 1626 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1627 1628 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1629 return MCDisassembler::Fail; 1630 1631 if (isGFX10Plus()) { 1632 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1633 COMPUTE_PGM_RSRC1_WGP_MODE); 1634 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1635 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1636 } 1637 return MCDisassembler::Success; 1638 } 1639 1640 // NOLINTNEXTLINE(readability-identifier-naming) 1641 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1642 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1643 using namespace amdhsa; 1644 StringRef Indent = "\t"; 1645 if (hasArchitectedFlatScratch()) 1646 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1647 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1648 else 1649 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1650 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1651 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1652 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1653 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1654 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1655 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1656 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1657 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1658 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1659 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1660 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1661 1662 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1663 return MCDisassembler::Fail; 1664 1665 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1666 return MCDisassembler::Fail; 1667 1668 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1669 return MCDisassembler::Fail; 1670 1671 PRINT_DIRECTIVE( 1672 ".amdhsa_exception_fp_ieee_invalid_op", 1673 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1674 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1675 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1676 PRINT_DIRECTIVE( 1677 ".amdhsa_exception_fp_ieee_div_zero", 1678 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1679 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1680 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1681 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1682 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1683 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1684 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1685 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1686 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1687 1688 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1689 return MCDisassembler::Fail; 1690 1691 return MCDisassembler::Success; 1692 } 1693 1694 #undef PRINT_DIRECTIVE 1695 1696 MCDisassembler::DecodeStatus 1697 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1698 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1699 raw_string_ostream &KdStream) const { 1700 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1701 do { \ 1702 KdStream << Indent << DIRECTIVE " " \ 1703 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1704 } while (0) 1705 1706 uint16_t TwoByteBuffer = 0; 1707 uint32_t FourByteBuffer = 0; 1708 1709 StringRef ReservedBytes; 1710 StringRef Indent = "\t"; 1711 1712 assert(Bytes.size() == 64); 1713 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1714 1715 switch (Cursor.tell()) { 1716 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1717 FourByteBuffer = DE.getU32(Cursor); 1718 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1719 << '\n'; 1720 return MCDisassembler::Success; 1721 1722 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1723 FourByteBuffer = DE.getU32(Cursor); 1724 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1725 << FourByteBuffer << '\n'; 1726 return MCDisassembler::Success; 1727 1728 case amdhsa::KERNARG_SIZE_OFFSET: 1729 FourByteBuffer = DE.getU32(Cursor); 1730 KdStream << Indent << ".amdhsa_kernarg_size " 1731 << FourByteBuffer << '\n'; 1732 return MCDisassembler::Success; 1733 1734 case amdhsa::RESERVED0_OFFSET: 1735 // 4 reserved bytes, must be 0. 1736 ReservedBytes = DE.getBytes(Cursor, 4); 1737 for (int I = 0; I < 4; ++I) { 1738 if (ReservedBytes[I] != 0) { 1739 return MCDisassembler::Fail; 1740 } 1741 } 1742 return MCDisassembler::Success; 1743 1744 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1745 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1746 // So far no directive controls this for Code Object V3, so simply skip for 1747 // disassembly. 1748 DE.skip(Cursor, 8); 1749 return MCDisassembler::Success; 1750 1751 case amdhsa::RESERVED1_OFFSET: 1752 // 20 reserved bytes, must be 0. 1753 ReservedBytes = DE.getBytes(Cursor, 20); 1754 for (int I = 0; I < 20; ++I) { 1755 if (ReservedBytes[I] != 0) { 1756 return MCDisassembler::Fail; 1757 } 1758 } 1759 return MCDisassembler::Success; 1760 1761 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1762 // COMPUTE_PGM_RSRC3 1763 // - Only set for GFX10, GFX6-9 have this to be 0. 1764 // - Currently no directives directly control this. 1765 FourByteBuffer = DE.getU32(Cursor); 1766 if (!isGFX10Plus() && FourByteBuffer) { 1767 return MCDisassembler::Fail; 1768 } 1769 return MCDisassembler::Success; 1770 1771 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1772 FourByteBuffer = DE.getU32(Cursor); 1773 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1774 MCDisassembler::Fail) { 1775 return MCDisassembler::Fail; 1776 } 1777 return MCDisassembler::Success; 1778 1779 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1780 FourByteBuffer = DE.getU32(Cursor); 1781 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1782 MCDisassembler::Fail) { 1783 return MCDisassembler::Fail; 1784 } 1785 return MCDisassembler::Success; 1786 1787 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1788 using namespace amdhsa; 1789 TwoByteBuffer = DE.getU16(Cursor); 1790 1791 if (!hasArchitectedFlatScratch()) 1792 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1793 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1794 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1795 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1796 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1797 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1798 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1799 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1800 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1801 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1802 if (!hasArchitectedFlatScratch()) 1803 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1804 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1805 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1806 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1807 1808 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1809 return MCDisassembler::Fail; 1810 1811 // Reserved for GFX9 1812 if (isGFX9() && 1813 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1814 return MCDisassembler::Fail; 1815 } else if (isGFX10Plus()) { 1816 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1817 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1818 } 1819 1820 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1821 return MCDisassembler::Fail; 1822 1823 return MCDisassembler::Success; 1824 1825 case amdhsa::RESERVED2_OFFSET: 1826 // 6 bytes from here are reserved, must be 0. 1827 ReservedBytes = DE.getBytes(Cursor, 6); 1828 for (int I = 0; I < 6; ++I) { 1829 if (ReservedBytes[I] != 0) 1830 return MCDisassembler::Fail; 1831 } 1832 return MCDisassembler::Success; 1833 1834 default: 1835 llvm_unreachable("Unhandled index. Case statements cover everything."); 1836 return MCDisassembler::Fail; 1837 } 1838 #undef PRINT_DIRECTIVE 1839 } 1840 1841 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1842 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1843 // CP microcode requires the kernel descriptor to be 64 aligned. 1844 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1845 return MCDisassembler::Fail; 1846 1847 std::string Kd; 1848 raw_string_ostream KdStream(Kd); 1849 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1850 1851 DataExtractor::Cursor C(0); 1852 while (C && C.tell() < Bytes.size()) { 1853 MCDisassembler::DecodeStatus Status = 1854 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1855 1856 cantFail(C.takeError()); 1857 1858 if (Status == MCDisassembler::Fail) 1859 return MCDisassembler::Fail; 1860 } 1861 KdStream << ".end_amdhsa_kernel\n"; 1862 outs() << KdStream.str(); 1863 return MCDisassembler::Success; 1864 } 1865 1866 Optional<MCDisassembler::DecodeStatus> 1867 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1868 ArrayRef<uint8_t> Bytes, uint64_t Address, 1869 raw_ostream &CStream) const { 1870 // Right now only kernel descriptor needs to be handled. 1871 // We ignore all other symbols for target specific handling. 1872 // TODO: 1873 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1874 // Object V2 and V3 when symbols are marked protected. 1875 1876 // amd_kernel_code_t for Code Object V2. 1877 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1878 Size = 256; 1879 return MCDisassembler::Fail; 1880 } 1881 1882 // Code Object V3 kernel descriptors. 1883 StringRef Name = Symbol.Name; 1884 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1885 Size = 64; // Size = 64 regardless of success or failure. 1886 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1887 } 1888 return None; 1889 } 1890 1891 //===----------------------------------------------------------------------===// 1892 // AMDGPUSymbolizer 1893 //===----------------------------------------------------------------------===// 1894 1895 // Try to find symbol name for specified label 1896 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1897 raw_ostream &/*cStream*/, int64_t Value, 1898 uint64_t /*Address*/, bool IsBranch, 1899 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1900 1901 if (!IsBranch) { 1902 return false; 1903 } 1904 1905 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1906 if (!Symbols) 1907 return false; 1908 1909 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1910 return Val.Addr == static_cast<uint64_t>(Value) && 1911 Val.Type == ELF::STT_NOTYPE; 1912 }); 1913 if (Result != Symbols->end()) { 1914 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1915 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1916 Inst.addOperand(MCOperand::createExpr(Add)); 1917 return true; 1918 } 1919 // Add to list of referenced addresses, so caller can synthesize a label. 1920 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1921 return false; 1922 } 1923 1924 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1925 int64_t Value, 1926 uint64_t Address) { 1927 llvm_unreachable("unimplemented"); 1928 } 1929 1930 //===----------------------------------------------------------------------===// 1931 // Initialization 1932 //===----------------------------------------------------------------------===// 1933 1934 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1935 LLVMOpInfoCallback /*GetOpInfo*/, 1936 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1937 void *DisInfo, 1938 MCContext *Ctx, 1939 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1940 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1941 } 1942 1943 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1944 const MCSubtargetInfo &STI, 1945 MCContext &Ctx) { 1946 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1947 } 1948 1949 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1950 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1951 createAMDGPUDisassembler); 1952 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1953 createAMDGPUSymbolizer); 1954 } 1955