1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) { 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 95 Offset = Imm & 0xFFFFF; 96 } else { // GFX9+ supports 21-bit signed offsets. 97 Offset = SignExtend64<21>(Imm); 98 } 99 return addOperand(Inst, MCOperand::createImm(Offset)); 100 } 101 102 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 103 const MCDisassembler *Decoder) { 104 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 105 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 106 } 107 108 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 109 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const MCDisassembler *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 117 // number of register. Used by VGPR only and AGPR only operands. 118 #define DECODE_OPERAND_REG_8(RegClass) \ 119 static DecodeStatus Decode##RegClass##RegisterClass( \ 120 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 121 const MCDisassembler *Decoder) { \ 122 assert(Imm < (1 << 8) && "8-bit encoding"); \ 123 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 124 return addOperand( \ 125 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 126 } 127 128 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 129 ImmWidth) \ 130 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 131 const MCDisassembler *Decoder) { \ 132 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 133 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 134 return addOperand(Inst, \ 135 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 136 MandatoryLiteral, ImmWidth)); \ 137 } 138 139 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 140 // get register class. Used by SGPR only operands. 141 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 142 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 143 144 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 145 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 146 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 147 // Used by AV_ register classes (AGPR or VGPR only register operands). 148 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ 149 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ 150 Imm | AMDGPU::EncValues::IS_VGPR, false, 0) 151 152 // Decoder for Src(9-bit encoding) registers only. 153 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ 154 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 155 156 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 157 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 158 // only. 159 #define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \ 160 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) 161 162 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 163 // Imm{9} is acc, registers only. 164 #define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \ 165 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) 166 167 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 168 // register from RegClass or immediate. Registers that don't belong to RegClass 169 // will be decoded and InstPrinter will report warning. Immediate will be 170 // decoded into constant of size ImmWidth, should match width of immediate used 171 // by OperandType (important for floating point types). 172 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ 173 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ 174 false, ImmWidth) 175 176 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 177 // and decode using 'enum10' from decodeSrcOp. 178 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ 179 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ 180 Imm | 512, false, ImmWidth) 181 182 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ 183 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ 184 OpWidth, Imm, true, ImmWidth) 185 186 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 187 // when RegisterClass is used as an operand. Most often used for destination 188 // operands. 189 190 DECODE_OPERAND_REG_8(VGPR_32) 191 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 192 DECODE_OPERAND_REG_8(VReg_64) 193 DECODE_OPERAND_REG_8(VReg_96) 194 DECODE_OPERAND_REG_8(VReg_128) 195 DECODE_OPERAND_REG_8(VReg_256) 196 DECODE_OPERAND_REG_8(VReg_288) 197 DECODE_OPERAND_REG_8(VReg_352) 198 DECODE_OPERAND_REG_8(VReg_384) 199 DECODE_OPERAND_REG_8(VReg_512) 200 DECODE_OPERAND_REG_8(VReg_1024) 201 202 DECODE_OPERAND_REG_7(SReg_32, OPW32) 203 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 204 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 205 DECODE_OPERAND_REG_7(SReg_64, OPW64) 206 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 207 DECODE_OPERAND_REG_7(SReg_128, OPW128) 208 DECODE_OPERAND_REG_7(SReg_256, OPW256) 209 DECODE_OPERAND_REG_7(SReg_512, OPW512) 210 211 DECODE_OPERAND_REG_8(AGPR_32) 212 DECODE_OPERAND_REG_8(AReg_64) 213 DECODE_OPERAND_REG_8(AReg_128) 214 DECODE_OPERAND_REG_8(AReg_256) 215 DECODE_OPERAND_REG_8(AReg_512) 216 DECODE_OPERAND_REG_8(AReg_1024) 217 218 DECODE_OPERAND_REG_AV10(AVDst_128, OPW128) 219 DECODE_OPERAND_REG_AV10(AVDst_512, OPW512) 220 221 // Decoders for register only source RegisterOperands that use use 9-bit Src 222 // encoding: 'decodeOperand_<RegClass>'. 223 224 DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) 225 DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) 226 DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) 227 DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) 228 DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) 229 230 DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32) 231 232 DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32) 233 DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64) 234 DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128) 235 236 // Decoders for register or immediate RegisterOperands that use 9-bit Src 237 // encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'. 238 239 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) 240 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) 241 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 16) 242 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) 243 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) 244 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) 245 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) 246 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) 247 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32) 248 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) 249 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) 250 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) 251 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) 252 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) 253 254 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) 255 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) 256 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) 257 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) 258 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) 259 260 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) 261 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) 262 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) 263 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32) 264 265 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 266 uint64_t /*Addr*/, 267 const MCDisassembler *Decoder) { 268 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 269 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 270 271 bool IsHi = Imm & (1 << 9); 272 unsigned RegIdx = Imm & 0xff; 273 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 274 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 275 } 276 277 static DecodeStatus 278 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 279 const MCDisassembler *Decoder) { 280 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 281 282 bool IsHi = Imm & (1 << 7); 283 unsigned RegIdx = Imm & 0x7f; 284 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 285 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 286 } 287 288 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 289 uint64_t /*Addr*/, 290 const MCDisassembler *Decoder) { 291 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 292 293 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 294 bool IsVGPR = Imm & (1 << 8); 295 if (IsVGPR) { 296 bool IsHi = Imm & (1 << 7); 297 unsigned RegIdx = Imm & 0x7f; 298 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 299 } 300 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 301 Imm & 0xFF, false, 16)); 302 } 303 304 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 305 uint64_t /*Addr*/, 306 const MCDisassembler *Decoder) { 307 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 308 309 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 310 bool IsVGPR = Imm & (1 << 8); 311 if (IsVGPR) { 312 bool IsHi = Imm & (1 << 9); 313 unsigned RegIdx = Imm & 0xff; 314 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 315 } 316 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 317 Imm & 0xFF, false, 16)); 318 } 319 320 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 321 uint64_t Addr, 322 const MCDisassembler *Decoder) { 323 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 324 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 325 } 326 327 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 328 uint64_t Addr, const void *Decoder) { 329 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 330 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 331 } 332 333 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 334 const MCRegisterInfo *MRI) { 335 if (OpIdx < 0) 336 return false; 337 338 const MCOperand &Op = Inst.getOperand(OpIdx); 339 if (!Op.isReg()) 340 return false; 341 342 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 343 auto Reg = Sub ? Sub : Op.getReg(); 344 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 345 } 346 347 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 348 AMDGPUDisassembler::OpWidthTy Opw, 349 const MCDisassembler *Decoder) { 350 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 351 if (!DAsm->isGFX90A()) { 352 Imm &= 511; 353 } else { 354 // If atomic has both vdata and vdst their register classes are tied. 355 // The bit is decoded along with the vdst, first operand. We need to 356 // change register class to AGPR if vdst was AGPR. 357 // If a DS instruction has both data0 and data1 their register classes 358 // are also tied. 359 unsigned Opc = Inst.getOpcode(); 360 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 361 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 362 : AMDGPU::OpName::vdata; 363 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 364 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 365 if ((int)Inst.getNumOperands() == DataIdx) { 366 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 367 if (IsAGPROperand(Inst, DstIdx, MRI)) 368 Imm |= 512; 369 } 370 371 if (TSFlags & SIInstrFlags::DS) { 372 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 373 if ((int)Inst.getNumOperands() == Data2Idx && 374 IsAGPROperand(Inst, DataIdx, MRI)) 375 Imm |= 512; 376 } 377 } 378 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 379 } 380 381 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 382 uint64_t Addr, 383 const MCDisassembler *Decoder) { 384 assert(Imm < (1 << 9) && "9-bit encoding"); 385 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 386 return addOperand( 387 Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true)); 388 } 389 390 static DecodeStatus 391 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 392 const MCDisassembler *Decoder) { 393 return decodeOperand_AVLdSt_Any(Inst, Imm, 394 AMDGPUDisassembler::OPW32, Decoder); 395 } 396 397 static DecodeStatus 398 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 399 const MCDisassembler *Decoder) { 400 return decodeOperand_AVLdSt_Any(Inst, Imm, 401 AMDGPUDisassembler::OPW64, Decoder); 402 } 403 404 static DecodeStatus 405 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 406 const MCDisassembler *Decoder) { 407 return decodeOperand_AVLdSt_Any(Inst, Imm, 408 AMDGPUDisassembler::OPW96, Decoder); 409 } 410 411 static DecodeStatus 412 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 413 const MCDisassembler *Decoder) { 414 return decodeOperand_AVLdSt_Any(Inst, Imm, 415 AMDGPUDisassembler::OPW128, Decoder); 416 } 417 418 static DecodeStatus 419 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 420 const MCDisassembler *Decoder) { 421 return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160, 422 Decoder); 423 } 424 425 #define DECODE_SDWA(DecName) \ 426 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 427 428 DECODE_SDWA(Src32) 429 DECODE_SDWA(Src16) 430 DECODE_SDWA(VopcDst) 431 432 #include "AMDGPUGenDisassemblerTables.inc" 433 434 //===----------------------------------------------------------------------===// 435 // 436 //===----------------------------------------------------------------------===// 437 438 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 439 assert(Bytes.size() >= sizeof(T)); 440 const auto Res = 441 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 442 Bytes = Bytes.slice(sizeof(T)); 443 return Res; 444 } 445 446 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 447 assert(Bytes.size() >= 12); 448 uint64_t Lo = 449 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 450 Bytes = Bytes.slice(8); 451 uint64_t Hi = 452 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 453 Bytes = Bytes.slice(4); 454 return DecoderUInt128(Lo, Hi); 455 } 456 457 // The disassembler is greedy, so we need to check FI operand value to 458 // not parse a dpp if the correct literal is not set. For dpp16 the 459 // autogenerated decoder checks the dpp literal 460 static bool isValidDPP8(const MCInst &MI) { 461 using namespace llvm::AMDGPU::DPP; 462 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 463 assert(FiIdx != -1); 464 if ((unsigned)FiIdx >= MI.getNumOperands()) 465 return false; 466 unsigned Fi = MI.getOperand(FiIdx).getImm(); 467 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 468 } 469 470 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 471 ArrayRef<uint8_t> Bytes_, 472 uint64_t Address, 473 raw_ostream &CS) const { 474 bool IsSDWA = false; 475 476 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 477 Bytes = Bytes_.slice(0, MaxInstBytesNum); 478 479 DecodeStatus Res = MCDisassembler::Fail; 480 do { 481 // ToDo: better to switch encoding length using some bit predicate 482 // but it is unknown yet, so try all we can 483 484 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 485 // encodings 486 if (isGFX11Plus() && Bytes.size() >= 12 ) { 487 DecoderUInt128 DecW = eat12Bytes(Bytes); 488 Res = 489 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 490 MI, DecW, Address, CS); 491 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 492 break; 493 MI = MCInst(); // clear 494 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 495 MI, DecW, Address, CS); 496 if (Res) { 497 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 498 convertVOP3PDPPInst(MI); 499 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 500 convertVOPCDPPInst(MI); // Special VOP3 case 501 else { 502 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 503 convertVOP3DPPInst(MI); // Regular VOP3 case 504 } 505 break; 506 } 507 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 508 if (Res) 509 break; 510 } 511 // Reinitialize Bytes 512 Bytes = Bytes_.slice(0, MaxInstBytesNum); 513 514 if (Bytes.size() >= 8) { 515 const uint64_t QW = eatBytes<uint64_t>(Bytes); 516 517 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 518 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 519 if (Res) { 520 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 521 == -1) 522 break; 523 if (convertDPP8Inst(MI) == MCDisassembler::Success) 524 break; 525 MI = MCInst(); // clear 526 } 527 } 528 529 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 530 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 531 break; 532 MI = MCInst(); // clear 533 534 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 535 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 536 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 537 break; 538 MI = MCInst(); // clear 539 540 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 541 if (Res) break; 542 543 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 544 MI, QW, Address, CS); 545 if (Res) { 546 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 547 convertVOPCDPPInst(MI); 548 break; 549 } 550 551 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 552 if (Res) { IsSDWA = true; break; } 553 554 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 555 if (Res) { IsSDWA = true; break; } 556 557 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 558 if (Res) { IsSDWA = true; break; } 559 560 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 561 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 562 if (Res) 563 break; 564 } 565 566 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 567 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 568 // table first so we print the correct name. 569 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 570 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 571 if (Res) 572 break; 573 } 574 } 575 576 // Reinitialize Bytes as DPP64 could have eaten too much 577 Bytes = Bytes_.slice(0, MaxInstBytesNum); 578 579 // Try decode 32-bit instruction 580 if (Bytes.size() < 4) break; 581 const uint32_t DW = eatBytes<uint32_t>(Bytes); 582 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 583 if (Res) break; 584 585 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 586 if (Res) break; 587 588 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 589 if (Res) break; 590 591 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 592 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 593 if (Res) 594 break; 595 } 596 597 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 598 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 599 if (Res) break; 600 } 601 602 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 603 if (Res) break; 604 605 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 606 Address, CS); 607 if (Res) break; 608 609 if (Bytes.size() < 4) break; 610 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 611 612 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 613 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 614 if (Res) 615 break; 616 } 617 618 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 619 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 620 if (Res) 621 break; 622 } 623 624 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 625 if (Res) break; 626 627 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS); 628 if (Res) break; 629 630 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 631 if (Res) break; 632 633 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 634 if (Res) break; 635 636 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 637 Address, CS); 638 if (Res) 639 break; 640 641 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS); 642 } while (false); 643 644 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 645 // Insert dummy unused src2_modifiers. 646 insertNamedMCOperand(MI, MCOperand::createImm(0), 647 AMDGPU::OpName::src2_modifiers); 648 } 649 650 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 651 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 652 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 653 AMDGPU::OpName::cpol); 654 if (CPolPos != -1) { 655 unsigned CPol = 656 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 657 AMDGPU::CPol::GLC : 0; 658 if (MI.getNumOperands() <= (unsigned)CPolPos) { 659 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 660 AMDGPU::OpName::cpol); 661 } else if (CPol) { 662 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 663 } 664 } 665 } 666 667 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 668 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 669 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 670 // GFX90A lost TFE, its place is occupied by ACC. 671 int TFEOpIdx = 672 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 673 if (TFEOpIdx != -1) { 674 auto TFEIter = MI.begin(); 675 std::advance(TFEIter, TFEOpIdx); 676 MI.insert(TFEIter, MCOperand::createImm(0)); 677 } 678 } 679 680 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 681 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 682 int SWZOpIdx = 683 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 684 if (SWZOpIdx != -1) { 685 auto SWZIter = MI.begin(); 686 std::advance(SWZIter, SWZOpIdx); 687 MI.insert(SWZIter, MCOperand::createImm(0)); 688 } 689 } 690 691 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 692 int VAddr0Idx = 693 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 694 int RsrcIdx = 695 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 696 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 697 if (VAddr0Idx >= 0 && NSAArgs > 0) { 698 unsigned NSAWords = (NSAArgs + 3) / 4; 699 if (Bytes.size() < 4 * NSAWords) { 700 Res = MCDisassembler::Fail; 701 } else { 702 for (unsigned i = 0; i < NSAArgs; ++i) { 703 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 704 auto VAddrRCID = 705 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 706 MI.insert(MI.begin() + VAddrIdx, 707 createRegOperand(VAddrRCID, Bytes[i])); 708 } 709 Bytes = Bytes.slice(4 * NSAWords); 710 } 711 } 712 713 if (Res) 714 Res = convertMIMGInst(MI); 715 } 716 717 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 718 Res = convertEXPInst(MI); 719 720 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 721 Res = convertVINTERPInst(MI); 722 723 if (Res && IsSDWA) 724 Res = convertSDWAInst(MI); 725 726 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 727 AMDGPU::OpName::vdst_in); 728 if (VDstIn_Idx != -1) { 729 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 730 MCOI::OperandConstraint::TIED_TO); 731 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 732 !MI.getOperand(VDstIn_Idx).isReg() || 733 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 734 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 735 MI.erase(&MI.getOperand(VDstIn_Idx)); 736 insertNamedMCOperand(MI, 737 MCOperand::createReg(MI.getOperand(Tied).getReg()), 738 AMDGPU::OpName::vdst_in); 739 } 740 } 741 742 int ImmLitIdx = 743 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 744 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 745 if (Res && ImmLitIdx != -1 && !IsSOPK) 746 Res = convertFMAanyK(MI, ImmLitIdx); 747 748 // if the opcode was not recognized we'll assume a Size of 4 bytes 749 // (unless there are fewer bytes left) 750 Size = Res ? (MaxInstBytesNum - Bytes.size()) 751 : std::min((size_t)4, Bytes_.size()); 752 return Res; 753 } 754 755 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 756 if (STI.hasFeature(AMDGPU::FeatureGFX11)) { 757 // The MCInst still has these fields even though they are no longer encoded 758 // in the GFX11 instruction. 759 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 760 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 761 } 762 return MCDisassembler::Success; 763 } 764 765 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 766 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 767 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 768 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 769 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 770 // The MCInst has this field that is not directly encoded in the 771 // instruction. 772 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 773 } 774 return MCDisassembler::Success; 775 } 776 777 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 778 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 779 STI.hasFeature(AMDGPU::FeatureGFX10)) { 780 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 781 // VOPC - insert clamp 782 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 783 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 784 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 785 if (SDst != -1) { 786 // VOPC - insert VCC register as sdst 787 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 788 AMDGPU::OpName::sdst); 789 } else { 790 // VOP1/2 - insert omod if present in instruction 791 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 792 } 793 } 794 return MCDisassembler::Success; 795 } 796 797 struct VOPModifiers { 798 unsigned OpSel = 0; 799 unsigned OpSelHi = 0; 800 unsigned NegLo = 0; 801 unsigned NegHi = 0; 802 }; 803 804 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 805 // Note that these values do not affect disassembler output, 806 // so this is only necessary for consistency with src_modifiers. 807 static VOPModifiers collectVOPModifiers(const MCInst &MI, 808 bool IsVOP3P = false) { 809 VOPModifiers Modifiers; 810 unsigned Opc = MI.getOpcode(); 811 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 812 AMDGPU::OpName::src1_modifiers, 813 AMDGPU::OpName::src2_modifiers}; 814 for (int J = 0; J < 3; ++J) { 815 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 816 if (OpIdx == -1) 817 continue; 818 819 unsigned Val = MI.getOperand(OpIdx).getImm(); 820 821 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 822 if (IsVOP3P) { 823 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 824 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 825 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 826 } else if (J == 0) { 827 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 828 } 829 } 830 831 return Modifiers; 832 } 833 834 // MAC opcodes have special old and src2 operands. 835 // src2 is tied to dst, while old is not tied (but assumed to be). 836 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 837 constexpr int DST_IDX = 0; 838 auto Opcode = MI.getOpcode(); 839 const auto &Desc = MCII->get(Opcode); 840 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 841 842 if (OldIdx != -1 && Desc.getOperandConstraint( 843 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 844 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 845 assert(Desc.getOperandConstraint( 846 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 847 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 848 (void)DST_IDX; 849 return true; 850 } 851 852 return false; 853 } 854 855 // Create dummy old operand and insert dummy unused src2_modifiers 856 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 857 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 858 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 859 insertNamedMCOperand(MI, MCOperand::createImm(0), 860 AMDGPU::OpName::src2_modifiers); 861 } 862 863 // We must check FI == literal to reject not genuine dpp8 insts, and we must 864 // first add optional MI operands to check FI 865 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 866 unsigned Opc = MI.getOpcode(); 867 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 868 convertVOP3PDPPInst(MI); 869 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 870 AMDGPU::isVOPC64DPP(Opc)) { 871 convertVOPCDPPInst(MI); 872 } else { 873 if (isMacDPP(MI)) 874 convertMacDPPInst(MI); 875 876 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 877 if (MI.getNumOperands() < DescNumOps && 878 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 879 auto Mods = collectVOPModifiers(MI); 880 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 881 AMDGPU::OpName::op_sel); 882 } else { 883 // Insert dummy unused src modifiers. 884 if (MI.getNumOperands() < DescNumOps && 885 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 886 insertNamedMCOperand(MI, MCOperand::createImm(0), 887 AMDGPU::OpName::src0_modifiers); 888 889 if (MI.getNumOperands() < DescNumOps && 890 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 891 insertNamedMCOperand(MI, MCOperand::createImm(0), 892 AMDGPU::OpName::src1_modifiers); 893 } 894 } 895 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 896 } 897 898 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 899 if (isMacDPP(MI)) 900 convertMacDPPInst(MI); 901 902 unsigned Opc = MI.getOpcode(); 903 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 904 if (MI.getNumOperands() < DescNumOps && 905 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 906 auto Mods = collectVOPModifiers(MI); 907 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 908 AMDGPU::OpName::op_sel); 909 } 910 return MCDisassembler::Success; 911 } 912 913 // Note that before gfx10, the MIMG encoding provided no information about 914 // VADDR size. Consequently, decoded instructions always show address as if it 915 // has 1 dword, which could be not really so. 916 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 917 918 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 919 AMDGPU::OpName::vdst); 920 921 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 922 AMDGPU::OpName::vdata); 923 int VAddr0Idx = 924 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 925 int RsrcIdx = 926 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 927 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 928 AMDGPU::OpName::dmask); 929 930 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 931 AMDGPU::OpName::tfe); 932 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 933 AMDGPU::OpName::d16); 934 935 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 936 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 937 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 938 939 assert(VDataIdx != -1); 940 if (BaseOpcode->BVH) { 941 // Add A16 operand for intersect_ray instructions 942 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 943 return MCDisassembler::Success; 944 } 945 946 bool IsAtomic = (VDstIdx != -1); 947 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 948 bool IsNSA = false; 949 bool IsPartialNSA = false; 950 unsigned AddrSize = Info->VAddrDwords; 951 952 if (isGFX10Plus()) { 953 unsigned DimIdx = 954 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 955 int A16Idx = 956 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 957 const AMDGPU::MIMGDimInfo *Dim = 958 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 959 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 960 961 AddrSize = 962 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 963 964 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 965 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 966 if (!IsNSA) { 967 if (AddrSize > 12) 968 AddrSize = 16; 969 } else { 970 if (AddrSize > Info->VAddrDwords) { 971 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 972 // The NSA encoding does not contain enough operands for the 973 // combination of base opcode / dimension. Should this be an error? 974 return MCDisassembler::Success; 975 } 976 IsPartialNSA = true; 977 } 978 } 979 } 980 981 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 982 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 983 984 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 985 if (D16 && AMDGPU::hasPackedD16(STI)) { 986 DstSize = (DstSize + 1) / 2; 987 } 988 989 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 990 DstSize += 1; 991 992 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 993 return MCDisassembler::Success; 994 995 int NewOpcode = 996 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 997 if (NewOpcode == -1) 998 return MCDisassembler::Success; 999 1000 // Widen the register to the correct number of enabled channels. 1001 unsigned NewVdata = AMDGPU::NoRegister; 1002 if (DstSize != Info->VDataDwords) { 1003 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1004 1005 // Get first subregister of VData 1006 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1007 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1008 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1009 1010 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1011 &MRI.getRegClass(DataRCID)); 1012 if (NewVdata == AMDGPU::NoRegister) { 1013 // It's possible to encode this such that the low register + enabled 1014 // components exceeds the register count. 1015 return MCDisassembler::Success; 1016 } 1017 } 1018 1019 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1020 // If using partial NSA on GFX11+ widen last address register. 1021 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1022 unsigned NewVAddrSA = AMDGPU::NoRegister; 1023 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1024 AddrSize != Info->VAddrDwords) { 1025 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1026 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1027 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1028 1029 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1030 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1031 &MRI.getRegClass(AddrRCID)); 1032 if (!NewVAddrSA) 1033 return MCDisassembler::Success; 1034 } 1035 1036 MI.setOpcode(NewOpcode); 1037 1038 if (NewVdata != AMDGPU::NoRegister) { 1039 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1040 1041 if (IsAtomic) { 1042 // Atomic operations have an additional operand (a copy of data) 1043 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1044 } 1045 } 1046 1047 if (NewVAddrSA) { 1048 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1049 } else if (IsNSA) { 1050 assert(AddrSize <= Info->VAddrDwords); 1051 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1052 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1053 } 1054 1055 return MCDisassembler::Success; 1056 } 1057 1058 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1059 // decoder only adds to src_modifiers, so manually add the bits to the other 1060 // operands. 1061 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1062 unsigned Opc = MI.getOpcode(); 1063 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1064 auto Mods = collectVOPModifiers(MI, true); 1065 1066 if (MI.getNumOperands() < DescNumOps && 1067 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1068 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1069 1070 if (MI.getNumOperands() < DescNumOps && 1071 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1072 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1073 AMDGPU::OpName::op_sel); 1074 if (MI.getNumOperands() < DescNumOps && 1075 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1076 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1077 AMDGPU::OpName::op_sel_hi); 1078 if (MI.getNumOperands() < DescNumOps && 1079 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1080 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1081 AMDGPU::OpName::neg_lo); 1082 if (MI.getNumOperands() < DescNumOps && 1083 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1084 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1085 AMDGPU::OpName::neg_hi); 1086 1087 return MCDisassembler::Success; 1088 } 1089 1090 // Create dummy old operand and insert optional operands 1091 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1092 unsigned Opc = MI.getOpcode(); 1093 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1094 1095 if (MI.getNumOperands() < DescNumOps && 1096 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1097 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1098 1099 if (MI.getNumOperands() < DescNumOps && 1100 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1101 insertNamedMCOperand(MI, MCOperand::createImm(0), 1102 AMDGPU::OpName::src0_modifiers); 1103 1104 if (MI.getNumOperands() < DescNumOps && 1105 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1106 insertNamedMCOperand(MI, MCOperand::createImm(0), 1107 AMDGPU::OpName::src1_modifiers); 1108 return MCDisassembler::Success; 1109 } 1110 1111 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1112 int ImmLitIdx) const { 1113 assert(HasLiteral && "Should have decoded a literal"); 1114 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1115 unsigned DescNumOps = Desc.getNumOperands(); 1116 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1117 AMDGPU::OpName::immDeferred); 1118 assert(DescNumOps == MI.getNumOperands()); 1119 for (unsigned I = 0; I < DescNumOps; ++I) { 1120 auto &Op = MI.getOperand(I); 1121 auto OpType = Desc.operands()[I].OperandType; 1122 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1123 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1124 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1125 IsDeferredOp) 1126 Op.setImm(Literal); 1127 } 1128 return MCDisassembler::Success; 1129 } 1130 1131 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1132 return getContext().getRegisterInfo()-> 1133 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1134 } 1135 1136 inline 1137 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1138 const Twine& ErrMsg) const { 1139 *CommentStream << "Error: " + ErrMsg; 1140 1141 // ToDo: add support for error operands to MCInst.h 1142 // return MCOperand::createError(V); 1143 return MCOperand(); 1144 } 1145 1146 inline 1147 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1148 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1149 } 1150 1151 inline 1152 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1153 unsigned Val) const { 1154 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1155 if (Val >= RegCl.getNumRegs()) 1156 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1157 ": unknown register " + Twine(Val)); 1158 return createRegOperand(RegCl.getRegister(Val)); 1159 } 1160 1161 inline 1162 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1163 unsigned Val) const { 1164 // ToDo: SI/CI have 104 SGPRs, VI - 102 1165 // Valery: here we accepting as much as we can, let assembler sort it out 1166 int shift = 0; 1167 switch (SRegClassID) { 1168 case AMDGPU::SGPR_32RegClassID: 1169 case AMDGPU::TTMP_32RegClassID: 1170 break; 1171 case AMDGPU::SGPR_64RegClassID: 1172 case AMDGPU::TTMP_64RegClassID: 1173 shift = 1; 1174 break; 1175 case AMDGPU::SGPR_128RegClassID: 1176 case AMDGPU::TTMP_128RegClassID: 1177 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1178 // this bundle? 1179 case AMDGPU::SGPR_256RegClassID: 1180 case AMDGPU::TTMP_256RegClassID: 1181 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1182 // this bundle? 1183 case AMDGPU::SGPR_288RegClassID: 1184 case AMDGPU::TTMP_288RegClassID: 1185 case AMDGPU::SGPR_320RegClassID: 1186 case AMDGPU::TTMP_320RegClassID: 1187 case AMDGPU::SGPR_352RegClassID: 1188 case AMDGPU::TTMP_352RegClassID: 1189 case AMDGPU::SGPR_384RegClassID: 1190 case AMDGPU::TTMP_384RegClassID: 1191 case AMDGPU::SGPR_512RegClassID: 1192 case AMDGPU::TTMP_512RegClassID: 1193 shift = 2; 1194 break; 1195 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1196 // this bundle? 1197 default: 1198 llvm_unreachable("unhandled register class"); 1199 } 1200 1201 if (Val % (1 << shift)) { 1202 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1203 << ": scalar reg isn't aligned " << Val; 1204 } 1205 1206 return createRegOperand(SRegClassID, Val >> shift); 1207 } 1208 1209 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1210 bool IsHi) const { 1211 unsigned RCID = 1212 IsHi ? AMDGPU::VGPR_HI16RegClassID : AMDGPU::VGPR_LO16RegClassID; 1213 return createRegOperand(RCID, RegIdx); 1214 } 1215 1216 // Decode Literals for insts which always have a literal in the encoding 1217 MCOperand 1218 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1219 if (HasLiteral) { 1220 assert( 1221 AMDGPU::hasVOPD(STI) && 1222 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1223 if (Literal != Val) 1224 return errOperand(Val, "More than one unique literal is illegal"); 1225 } 1226 HasLiteral = true; 1227 Literal = Val; 1228 return MCOperand::createImm(Literal); 1229 } 1230 1231 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1232 // For now all literal constants are supposed to be unsigned integer 1233 // ToDo: deal with signed/unsigned 64-bit integer constants 1234 // ToDo: deal with float/double constants 1235 if (!HasLiteral) { 1236 if (Bytes.size() < 4) { 1237 return errOperand(0, "cannot read literal, inst bytes left " + 1238 Twine(Bytes.size())); 1239 } 1240 HasLiteral = true; 1241 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1242 if (ExtendFP64) 1243 Literal64 <<= 32; 1244 } 1245 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1246 } 1247 1248 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1249 using namespace AMDGPU::EncValues; 1250 1251 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1252 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1253 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1254 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1255 // Cast prevents negative overflow. 1256 } 1257 1258 static int64_t getInlineImmVal32(unsigned Imm) { 1259 switch (Imm) { 1260 case 240: 1261 return llvm::bit_cast<uint32_t>(0.5f); 1262 case 241: 1263 return llvm::bit_cast<uint32_t>(-0.5f); 1264 case 242: 1265 return llvm::bit_cast<uint32_t>(1.0f); 1266 case 243: 1267 return llvm::bit_cast<uint32_t>(-1.0f); 1268 case 244: 1269 return llvm::bit_cast<uint32_t>(2.0f); 1270 case 245: 1271 return llvm::bit_cast<uint32_t>(-2.0f); 1272 case 246: 1273 return llvm::bit_cast<uint32_t>(4.0f); 1274 case 247: 1275 return llvm::bit_cast<uint32_t>(-4.0f); 1276 case 248: // 1 / (2 * PI) 1277 return 0x3e22f983; 1278 default: 1279 llvm_unreachable("invalid fp inline imm"); 1280 } 1281 } 1282 1283 static int64_t getInlineImmVal64(unsigned Imm) { 1284 switch (Imm) { 1285 case 240: 1286 return llvm::bit_cast<uint64_t>(0.5); 1287 case 241: 1288 return llvm::bit_cast<uint64_t>(-0.5); 1289 case 242: 1290 return llvm::bit_cast<uint64_t>(1.0); 1291 case 243: 1292 return llvm::bit_cast<uint64_t>(-1.0); 1293 case 244: 1294 return llvm::bit_cast<uint64_t>(2.0); 1295 case 245: 1296 return llvm::bit_cast<uint64_t>(-2.0); 1297 case 246: 1298 return llvm::bit_cast<uint64_t>(4.0); 1299 case 247: 1300 return llvm::bit_cast<uint64_t>(-4.0); 1301 case 248: // 1 / (2 * PI) 1302 return 0x3fc45f306dc9c882; 1303 default: 1304 llvm_unreachable("invalid fp inline imm"); 1305 } 1306 } 1307 1308 static int64_t getInlineImmVal16(unsigned Imm) { 1309 switch (Imm) { 1310 case 240: 1311 return 0x3800; 1312 case 241: 1313 return 0xB800; 1314 case 242: 1315 return 0x3C00; 1316 case 243: 1317 return 0xBC00; 1318 case 244: 1319 return 0x4000; 1320 case 245: 1321 return 0xC000; 1322 case 246: 1323 return 0x4400; 1324 case 247: 1325 return 0xC400; 1326 case 248: // 1 / (2 * PI) 1327 return 0x3118; 1328 default: 1329 llvm_unreachable("invalid fp inline imm"); 1330 } 1331 } 1332 1333 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1334 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1335 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1336 1337 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1338 // ImmWidth 0 is a default case where operand should not allow immediates. 1339 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1340 // use it to print verbose error message. 1341 switch (ImmWidth) { 1342 case 0: 1343 case 32: 1344 return MCOperand::createImm(getInlineImmVal32(Imm)); 1345 case 64: 1346 return MCOperand::createImm(getInlineImmVal64(Imm)); 1347 case 16: 1348 return MCOperand::createImm(getInlineImmVal16(Imm)); 1349 default: 1350 llvm_unreachable("implement me"); 1351 } 1352 } 1353 1354 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1355 using namespace AMDGPU; 1356 1357 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1358 switch (Width) { 1359 default: // fall 1360 case OPW32: 1361 case OPW16: 1362 case OPWV216: 1363 return VGPR_32RegClassID; 1364 case OPW64: 1365 case OPWV232: return VReg_64RegClassID; 1366 case OPW96: return VReg_96RegClassID; 1367 case OPW128: return VReg_128RegClassID; 1368 case OPW160: return VReg_160RegClassID; 1369 case OPW256: return VReg_256RegClassID; 1370 case OPW288: return VReg_288RegClassID; 1371 case OPW320: return VReg_320RegClassID; 1372 case OPW352: return VReg_352RegClassID; 1373 case OPW384: return VReg_384RegClassID; 1374 case OPW512: return VReg_512RegClassID; 1375 case OPW1024: return VReg_1024RegClassID; 1376 } 1377 } 1378 1379 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1380 using namespace AMDGPU; 1381 1382 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1383 switch (Width) { 1384 default: // fall 1385 case OPW32: 1386 case OPW16: 1387 case OPWV216: 1388 return AGPR_32RegClassID; 1389 case OPW64: 1390 case OPWV232: return AReg_64RegClassID; 1391 case OPW96: return AReg_96RegClassID; 1392 case OPW128: return AReg_128RegClassID; 1393 case OPW160: return AReg_160RegClassID; 1394 case OPW256: return AReg_256RegClassID; 1395 case OPW288: return AReg_288RegClassID; 1396 case OPW320: return AReg_320RegClassID; 1397 case OPW352: return AReg_352RegClassID; 1398 case OPW384: return AReg_384RegClassID; 1399 case OPW512: return AReg_512RegClassID; 1400 case OPW1024: return AReg_1024RegClassID; 1401 } 1402 } 1403 1404 1405 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1406 using namespace AMDGPU; 1407 1408 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1409 switch (Width) { 1410 default: // fall 1411 case OPW32: 1412 case OPW16: 1413 case OPWV216: 1414 return SGPR_32RegClassID; 1415 case OPW64: 1416 case OPWV232: return SGPR_64RegClassID; 1417 case OPW96: return SGPR_96RegClassID; 1418 case OPW128: return SGPR_128RegClassID; 1419 case OPW160: return SGPR_160RegClassID; 1420 case OPW256: return SGPR_256RegClassID; 1421 case OPW288: return SGPR_288RegClassID; 1422 case OPW320: return SGPR_320RegClassID; 1423 case OPW352: return SGPR_352RegClassID; 1424 case OPW384: return SGPR_384RegClassID; 1425 case OPW512: return SGPR_512RegClassID; 1426 } 1427 } 1428 1429 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1430 using namespace AMDGPU; 1431 1432 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1433 switch (Width) { 1434 default: // fall 1435 case OPW32: 1436 case OPW16: 1437 case OPWV216: 1438 return TTMP_32RegClassID; 1439 case OPW64: 1440 case OPWV232: return TTMP_64RegClassID; 1441 case OPW128: return TTMP_128RegClassID; 1442 case OPW256: return TTMP_256RegClassID; 1443 case OPW288: return TTMP_288RegClassID; 1444 case OPW320: return TTMP_320RegClassID; 1445 case OPW352: return TTMP_352RegClassID; 1446 case OPW384: return TTMP_384RegClassID; 1447 case OPW512: return TTMP_512RegClassID; 1448 } 1449 } 1450 1451 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1452 using namespace AMDGPU::EncValues; 1453 1454 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1455 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1456 1457 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1458 } 1459 1460 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1461 bool MandatoryLiteral, 1462 unsigned ImmWidth, bool IsFP) const { 1463 using namespace AMDGPU::EncValues; 1464 1465 assert(Val < 1024); // enum10 1466 1467 bool IsAGPR = Val & 512; 1468 Val &= 511; 1469 1470 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1471 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1472 : getVgprClassId(Width), Val - VGPR_MIN); 1473 } 1474 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1475 IsFP); 1476 } 1477 1478 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, 1479 unsigned Val, 1480 bool MandatoryLiteral, 1481 unsigned ImmWidth, 1482 bool IsFP) const { 1483 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1484 // decoded earlier. 1485 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1486 using namespace AMDGPU::EncValues; 1487 1488 if (Val <= SGPR_MAX) { 1489 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1490 static_assert(SGPR_MIN == 0); 1491 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1492 } 1493 1494 int TTmpIdx = getTTmpIdx(Val); 1495 if (TTmpIdx >= 0) { 1496 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1497 } 1498 1499 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1500 return decodeIntImmed(Val); 1501 1502 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1503 return decodeFPImmed(ImmWidth, Val); 1504 1505 if (Val == LITERAL_CONST) { 1506 if (MandatoryLiteral) 1507 // Keep a sentinel value for deferred setting 1508 return MCOperand::createImm(LITERAL_CONST); 1509 else 1510 return decodeLiteralConstant(IsFP && ImmWidth == 64); 1511 } 1512 1513 switch (Width) { 1514 case OPW32: 1515 case OPW16: 1516 case OPWV216: 1517 return decodeSpecialReg32(Val); 1518 case OPW64: 1519 case OPWV232: 1520 return decodeSpecialReg64(Val); 1521 default: 1522 llvm_unreachable("unexpected immediate type"); 1523 } 1524 } 1525 1526 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1527 // opposite of bit 0 of DstX. 1528 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1529 unsigned Val) const { 1530 int VDstXInd = 1531 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1532 assert(VDstXInd != -1); 1533 assert(Inst.getOperand(VDstXInd).isReg()); 1534 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1535 Val |= ~XDstReg & 1; 1536 auto Width = llvm::AMDGPUDisassembler::OPW32; 1537 return createRegOperand(getVgprClassId(Width), Val); 1538 } 1539 1540 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1541 using namespace AMDGPU; 1542 1543 switch (Val) { 1544 // clang-format off 1545 case 102: return createRegOperand(FLAT_SCR_LO); 1546 case 103: return createRegOperand(FLAT_SCR_HI); 1547 case 104: return createRegOperand(XNACK_MASK_LO); 1548 case 105: return createRegOperand(XNACK_MASK_HI); 1549 case 106: return createRegOperand(VCC_LO); 1550 case 107: return createRegOperand(VCC_HI); 1551 case 108: return createRegOperand(TBA_LO); 1552 case 109: return createRegOperand(TBA_HI); 1553 case 110: return createRegOperand(TMA_LO); 1554 case 111: return createRegOperand(TMA_HI); 1555 case 124: 1556 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1557 case 125: 1558 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1559 case 126: return createRegOperand(EXEC_LO); 1560 case 127: return createRegOperand(EXEC_HI); 1561 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1562 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1563 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1564 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1565 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1566 case 251: return createRegOperand(SRC_VCCZ); 1567 case 252: return createRegOperand(SRC_EXECZ); 1568 case 253: return createRegOperand(SRC_SCC); 1569 case 254: return createRegOperand(LDS_DIRECT); 1570 default: break; 1571 // clang-format on 1572 } 1573 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1574 } 1575 1576 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1577 using namespace AMDGPU; 1578 1579 switch (Val) { 1580 case 102: return createRegOperand(FLAT_SCR); 1581 case 104: return createRegOperand(XNACK_MASK); 1582 case 106: return createRegOperand(VCC); 1583 case 108: return createRegOperand(TBA); 1584 case 110: return createRegOperand(TMA); 1585 case 124: 1586 if (isGFX11Plus()) 1587 return createRegOperand(SGPR_NULL); 1588 break; 1589 case 125: 1590 if (!isGFX11Plus()) 1591 return createRegOperand(SGPR_NULL); 1592 break; 1593 case 126: return createRegOperand(EXEC); 1594 case 235: return createRegOperand(SRC_SHARED_BASE); 1595 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1596 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1597 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1598 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1599 case 251: return createRegOperand(SRC_VCCZ); 1600 case 252: return createRegOperand(SRC_EXECZ); 1601 case 253: return createRegOperand(SRC_SCC); 1602 default: break; 1603 } 1604 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1605 } 1606 1607 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1608 const unsigned Val, 1609 unsigned ImmWidth) const { 1610 using namespace AMDGPU::SDWA; 1611 using namespace AMDGPU::EncValues; 1612 1613 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1614 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1615 // XXX: cast to int is needed to avoid stupid warning: 1616 // compare with unsigned is always true 1617 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1618 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1619 return createRegOperand(getVgprClassId(Width), 1620 Val - SDWA9EncValues::SRC_VGPR_MIN); 1621 } 1622 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1623 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1624 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1625 return createSRegOperand(getSgprClassId(Width), 1626 Val - SDWA9EncValues::SRC_SGPR_MIN); 1627 } 1628 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1629 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1630 return createSRegOperand(getTtmpClassId(Width), 1631 Val - SDWA9EncValues::SRC_TTMP_MIN); 1632 } 1633 1634 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1635 1636 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1637 return decodeIntImmed(SVal); 1638 1639 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1640 return decodeFPImmed(ImmWidth, SVal); 1641 1642 return decodeSpecialReg32(SVal); 1643 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1644 return createRegOperand(getVgprClassId(Width), Val); 1645 } 1646 llvm_unreachable("unsupported target"); 1647 } 1648 1649 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1650 return decodeSDWASrc(OPW16, Val, 16); 1651 } 1652 1653 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1654 return decodeSDWASrc(OPW32, Val, 32); 1655 } 1656 1657 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1658 using namespace AMDGPU::SDWA; 1659 1660 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1661 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1662 "SDWAVopcDst should be present only on GFX9+"); 1663 1664 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1665 1666 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1667 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1668 1669 int TTmpIdx = getTTmpIdx(Val); 1670 if (TTmpIdx >= 0) { 1671 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1672 return createSRegOperand(TTmpClsId, TTmpIdx); 1673 } else if (Val > SGPR_MAX) { 1674 return IsWave64 ? decodeSpecialReg64(Val) 1675 : decodeSpecialReg32(Val); 1676 } else { 1677 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1678 } 1679 } else { 1680 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1681 } 1682 } 1683 1684 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1685 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1686 ? decodeSrcOp(OPW64, Val) 1687 : decodeSrcOp(OPW32, Val); 1688 } 1689 1690 bool AMDGPUDisassembler::isVI() const { 1691 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1692 } 1693 1694 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1695 1696 bool AMDGPUDisassembler::isGFX90A() const { 1697 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1698 } 1699 1700 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1701 1702 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1703 1704 bool AMDGPUDisassembler::isGFX10Plus() const { 1705 return AMDGPU::isGFX10Plus(STI); 1706 } 1707 1708 bool AMDGPUDisassembler::isGFX11() const { 1709 return STI.hasFeature(AMDGPU::FeatureGFX11); 1710 } 1711 1712 bool AMDGPUDisassembler::isGFX11Plus() const { 1713 return AMDGPU::isGFX11Plus(STI); 1714 } 1715 1716 1717 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1718 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1719 } 1720 1721 bool AMDGPUDisassembler::hasKernargPreload() const { 1722 return AMDGPU::hasKernargPreload(STI); 1723 } 1724 1725 //===----------------------------------------------------------------------===// 1726 // AMDGPU specific symbol handling 1727 //===----------------------------------------------------------------------===// 1728 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1729 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1730 do { \ 1731 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1732 } while (0) 1733 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1734 do { \ 1735 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1736 << GET_FIELD(MASK) << '\n'; \ 1737 } while (0) 1738 1739 // NOLINTNEXTLINE(readability-identifier-naming) 1740 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1741 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1742 using namespace amdhsa; 1743 StringRef Indent = "\t"; 1744 1745 // We cannot accurately backward compute #VGPRs used from 1746 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1747 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1748 // simply calculate the inverse of what the assembler does. 1749 1750 uint32_t GranulatedWorkitemVGPRCount = 1751 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1752 1753 uint32_t NextFreeVGPR = 1754 (GranulatedWorkitemVGPRCount + 1) * 1755 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1756 1757 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1758 1759 // We cannot backward compute values used to calculate 1760 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1761 // directives can't be computed: 1762 // .amdhsa_reserve_vcc 1763 // .amdhsa_reserve_flat_scratch 1764 // .amdhsa_reserve_xnack_mask 1765 // They take their respective default values if not specified in the assembly. 1766 // 1767 // GRANULATED_WAVEFRONT_SGPR_COUNT 1768 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1769 // 1770 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1771 // are set to 0. So while disassembling we consider that: 1772 // 1773 // GRANULATED_WAVEFRONT_SGPR_COUNT 1774 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1775 // 1776 // The disassembler cannot recover the original values of those 3 directives. 1777 1778 uint32_t GranulatedWavefrontSGPRCount = 1779 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1780 1781 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1782 return MCDisassembler::Fail; 1783 1784 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1785 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1786 1787 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1788 if (!hasArchitectedFlatScratch()) 1789 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1790 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1791 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1792 1793 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1794 return MCDisassembler::Fail; 1795 1796 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1797 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1798 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1799 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1800 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1801 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1802 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1803 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1804 1805 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1806 return MCDisassembler::Fail; 1807 1808 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1809 1810 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1811 return MCDisassembler::Fail; 1812 1813 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1814 1815 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1816 return MCDisassembler::Fail; 1817 1818 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1819 return MCDisassembler::Fail; 1820 1821 if (isGFX9Plus()) 1822 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1823 1824 if (!isGFX9Plus()) 1825 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1826 return MCDisassembler::Fail; 1827 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1828 return MCDisassembler::Fail; 1829 if (!isGFX10Plus()) 1830 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1831 return MCDisassembler::Fail; 1832 1833 if (isGFX10Plus()) { 1834 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1835 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1836 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1837 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1838 } 1839 return MCDisassembler::Success; 1840 } 1841 1842 // NOLINTNEXTLINE(readability-identifier-naming) 1843 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1844 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1845 using namespace amdhsa; 1846 StringRef Indent = "\t"; 1847 if (hasArchitectedFlatScratch()) 1848 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1849 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1850 else 1851 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1852 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1853 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1854 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1855 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1856 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1857 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1858 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1859 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1860 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1861 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1862 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1863 1864 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1865 return MCDisassembler::Fail; 1866 1867 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1868 return MCDisassembler::Fail; 1869 1870 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1871 return MCDisassembler::Fail; 1872 1873 PRINT_DIRECTIVE( 1874 ".amdhsa_exception_fp_ieee_invalid_op", 1875 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1876 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1877 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1878 PRINT_DIRECTIVE( 1879 ".amdhsa_exception_fp_ieee_div_zero", 1880 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1881 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1882 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1883 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1884 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1885 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1886 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1887 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1888 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1889 1890 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1891 return MCDisassembler::Fail; 1892 1893 return MCDisassembler::Success; 1894 } 1895 1896 // NOLINTNEXTLINE(readability-identifier-naming) 1897 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 1898 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1899 using namespace amdhsa; 1900 StringRef Indent = "\t"; 1901 if (isGFX90A()) { 1902 KdStream << Indent << ".amdhsa_accum_offset " 1903 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 1904 << '\n'; 1905 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 1906 return MCDisassembler::Fail; 1907 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 1908 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 1909 return MCDisassembler::Fail; 1910 } else if (isGFX10Plus()) { 1911 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 1912 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 1913 COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1914 } else { 1915 PRINT_PSEUDO_DIRECTIVE_COMMENT( 1916 "SHARED_VGPR_COUNT", COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1917 } 1918 1919 if (isGFX11Plus()) { 1920 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 1921 COMPUTE_PGM_RSRC3_GFX11_PLUS_INST_PREF_SIZE); 1922 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 1923 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 1924 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 1925 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_END); 1926 } else { 1927 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED0) 1928 return MCDisassembler::Fail; 1929 } 1930 1931 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED1) 1932 return MCDisassembler::Fail; 1933 1934 if (isGFX11Plus()) { 1935 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 1936 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 1937 } else { 1938 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED2) 1939 return MCDisassembler::Fail; 1940 } 1941 } else if (FourByteBuffer) { 1942 return MCDisassembler::Fail; 1943 } 1944 return MCDisassembler::Success; 1945 } 1946 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 1947 #undef PRINT_DIRECTIVE 1948 #undef GET_FIELD 1949 1950 MCDisassembler::DecodeStatus 1951 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1952 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1953 raw_string_ostream &KdStream) const { 1954 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1955 do { \ 1956 KdStream << Indent << DIRECTIVE " " \ 1957 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1958 } while (0) 1959 1960 uint16_t TwoByteBuffer = 0; 1961 uint32_t FourByteBuffer = 0; 1962 1963 StringRef ReservedBytes; 1964 StringRef Indent = "\t"; 1965 1966 assert(Bytes.size() == 64); 1967 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1968 1969 switch (Cursor.tell()) { 1970 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1971 FourByteBuffer = DE.getU32(Cursor); 1972 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1973 << '\n'; 1974 return MCDisassembler::Success; 1975 1976 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1977 FourByteBuffer = DE.getU32(Cursor); 1978 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1979 << FourByteBuffer << '\n'; 1980 return MCDisassembler::Success; 1981 1982 case amdhsa::KERNARG_SIZE_OFFSET: 1983 FourByteBuffer = DE.getU32(Cursor); 1984 KdStream << Indent << ".amdhsa_kernarg_size " 1985 << FourByteBuffer << '\n'; 1986 return MCDisassembler::Success; 1987 1988 case amdhsa::RESERVED0_OFFSET: 1989 // 4 reserved bytes, must be 0. 1990 ReservedBytes = DE.getBytes(Cursor, 4); 1991 for (int I = 0; I < 4; ++I) { 1992 if (ReservedBytes[I] != 0) { 1993 return MCDisassembler::Fail; 1994 } 1995 } 1996 return MCDisassembler::Success; 1997 1998 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1999 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2000 // So far no directive controls this for Code Object V3, so simply skip for 2001 // disassembly. 2002 DE.skip(Cursor, 8); 2003 return MCDisassembler::Success; 2004 2005 case amdhsa::RESERVED1_OFFSET: 2006 // 20 reserved bytes, must be 0. 2007 ReservedBytes = DE.getBytes(Cursor, 20); 2008 for (int I = 0; I < 20; ++I) { 2009 if (ReservedBytes[I] != 0) { 2010 return MCDisassembler::Fail; 2011 } 2012 } 2013 return MCDisassembler::Success; 2014 2015 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2016 FourByteBuffer = DE.getU32(Cursor); 2017 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2018 2019 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2020 FourByteBuffer = DE.getU32(Cursor); 2021 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2022 2023 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2024 FourByteBuffer = DE.getU32(Cursor); 2025 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2026 2027 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2028 using namespace amdhsa; 2029 TwoByteBuffer = DE.getU16(Cursor); 2030 2031 if (!hasArchitectedFlatScratch()) 2032 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2033 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2034 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2035 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2036 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2037 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2038 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2039 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2040 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2041 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2042 if (!hasArchitectedFlatScratch()) 2043 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2044 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2045 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2046 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2047 2048 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2049 return MCDisassembler::Fail; 2050 2051 // Reserved for GFX9 2052 if (isGFX9() && 2053 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2054 return MCDisassembler::Fail; 2055 } else if (isGFX10Plus()) { 2056 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2057 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2058 } 2059 2060 if (AMDGPU::getAmdhsaCodeObjectVersion() >= AMDGPU::AMDHSA_COV5) 2061 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2062 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2063 2064 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2065 return MCDisassembler::Fail; 2066 2067 return MCDisassembler::Success; 2068 2069 case amdhsa::KERNARG_PRELOAD_OFFSET: 2070 using namespace amdhsa; 2071 TwoByteBuffer = DE.getU16(Cursor); 2072 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2073 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2074 KERNARG_PRELOAD_SPEC_LENGTH); 2075 } 2076 2077 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2078 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2079 KERNARG_PRELOAD_SPEC_OFFSET); 2080 } 2081 return MCDisassembler::Success; 2082 2083 case amdhsa::RESERVED3_OFFSET: 2084 // 4 bytes from here are reserved, must be 0. 2085 ReservedBytes = DE.getBytes(Cursor, 4); 2086 for (int I = 0; I < 4; ++I) { 2087 if (ReservedBytes[I] != 0) 2088 return MCDisassembler::Fail; 2089 } 2090 return MCDisassembler::Success; 2091 2092 default: 2093 llvm_unreachable("Unhandled index. Case statements cover everything."); 2094 return MCDisassembler::Fail; 2095 } 2096 #undef PRINT_DIRECTIVE 2097 } 2098 2099 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2100 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2101 // CP microcode requires the kernel descriptor to be 64 aligned. 2102 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2103 return MCDisassembler::Fail; 2104 2105 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2106 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2107 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2108 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2109 // when required. 2110 if (isGFX10Plus()) { 2111 uint16_t KernelCodeProperties = 2112 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2113 llvm::endianness::little); 2114 EnableWavefrontSize32 = 2115 AMDHSA_BITS_GET(KernelCodeProperties, 2116 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2117 } 2118 2119 std::string Kd; 2120 raw_string_ostream KdStream(Kd); 2121 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2122 2123 DataExtractor::Cursor C(0); 2124 while (C && C.tell() < Bytes.size()) { 2125 MCDisassembler::DecodeStatus Status = 2126 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2127 2128 cantFail(C.takeError()); 2129 2130 if (Status == MCDisassembler::Fail) 2131 return MCDisassembler::Fail; 2132 } 2133 KdStream << ".end_amdhsa_kernel\n"; 2134 outs() << KdStream.str(); 2135 return MCDisassembler::Success; 2136 } 2137 2138 std::optional<MCDisassembler::DecodeStatus> 2139 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2140 ArrayRef<uint8_t> Bytes, uint64_t Address, 2141 raw_ostream &CStream) const { 2142 // Right now only kernel descriptor needs to be handled. 2143 // We ignore all other symbols for target specific handling. 2144 // TODO: 2145 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2146 // Object V2 and V3 when symbols are marked protected. 2147 2148 // amd_kernel_code_t for Code Object V2. 2149 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2150 Size = 256; 2151 return MCDisassembler::Fail; 2152 } 2153 2154 // Code Object V3 kernel descriptors. 2155 StringRef Name = Symbol.Name; 2156 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2157 Size = 64; // Size = 64 regardless of success or failure. 2158 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2159 } 2160 return std::nullopt; 2161 } 2162 2163 //===----------------------------------------------------------------------===// 2164 // AMDGPUSymbolizer 2165 //===----------------------------------------------------------------------===// 2166 2167 // Try to find symbol name for specified label 2168 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2169 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2170 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2171 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2172 2173 if (!IsBranch) { 2174 return false; 2175 } 2176 2177 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2178 if (!Symbols) 2179 return false; 2180 2181 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2182 return Val.Addr == static_cast<uint64_t>(Value) && 2183 Val.Type == ELF::STT_NOTYPE; 2184 }); 2185 if (Result != Symbols->end()) { 2186 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2187 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2188 Inst.addOperand(MCOperand::createExpr(Add)); 2189 return true; 2190 } 2191 // Add to list of referenced addresses, so caller can synthesize a label. 2192 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2193 return false; 2194 } 2195 2196 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2197 int64_t Value, 2198 uint64_t Address) { 2199 llvm_unreachable("unimplemented"); 2200 } 2201 2202 //===----------------------------------------------------------------------===// 2203 // Initialization 2204 //===----------------------------------------------------------------------===// 2205 2206 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2207 LLVMOpInfoCallback /*GetOpInfo*/, 2208 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2209 void *DisInfo, 2210 MCContext *Ctx, 2211 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2212 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2213 } 2214 2215 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2216 const MCSubtargetInfo &STI, 2217 MCContext &Ctx) { 2218 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2219 } 2220 2221 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2222 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2223 createAMDGPUDisassembler); 2224 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2225 createAMDGPUSymbolizer); 2226 } 2227