1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "Disassembler/AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "SIDefines.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/Disassembler.h" 26 #include "llvm/ADT/APInt.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/Twine.h" 29 #include "llvm/BinaryFormat/ELF.h" 30 #include "llvm/MC/MCContext.h" 31 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 32 #include "llvm/MC/MCExpr.h" 33 #include "llvm/MC/MCFixedLenDisassembler.h" 34 #include "llvm/MC/MCInst.h" 35 #include "llvm/MC/MCSubtargetInfo.h" 36 #include "llvm/Support/Endian.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/TargetRegistry.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include <algorithm> 42 #include <cassert> 43 #include <cstddef> 44 #include <cstdint> 45 #include <iterator> 46 #include <tuple> 47 #include <vector> 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "amdgpu-disassembler" 52 53 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 54 55 inline static MCDisassembler::DecodeStatus 56 addOperand(MCInst &Inst, const MCOperand& Opnd) { 57 Inst.addOperand(Opnd); 58 return Opnd.isValid() ? 59 MCDisassembler::Success : 60 MCDisassembler::SoftFail; 61 } 62 63 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 64 uint16_t NameIdx) { 65 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 66 if (OpIdx != -1) { 67 auto I = MI.begin(); 68 std::advance(I, OpIdx); 69 MI.insert(I, Op); 70 } 71 return OpIdx; 72 } 73 74 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 75 uint64_t Addr, const void *Decoder) { 76 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 77 78 APInt SignedOffset(18, Imm * 4, true); 79 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 80 81 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 82 return MCDisassembler::Success; 83 return addOperand(Inst, MCOperand::createImm(Imm)); 84 } 85 86 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 87 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 88 unsigned Imm, \ 89 uint64_t /*Addr*/, \ 90 const void *Decoder) { \ 91 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 92 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 93 } 94 95 #define DECODE_OPERAND_REG(RegClass) \ 96 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 97 98 DECODE_OPERAND_REG(VGPR_32) 99 DECODE_OPERAND_REG(VS_32) 100 DECODE_OPERAND_REG(VS_64) 101 DECODE_OPERAND_REG(VS_128) 102 103 DECODE_OPERAND_REG(VReg_64) 104 DECODE_OPERAND_REG(VReg_96) 105 DECODE_OPERAND_REG(VReg_128) 106 107 DECODE_OPERAND_REG(SReg_32) 108 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 109 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 110 DECODE_OPERAND_REG(SReg_64) 111 DECODE_OPERAND_REG(SReg_64_XEXEC) 112 DECODE_OPERAND_REG(SReg_128) 113 DECODE_OPERAND_REG(SReg_256) 114 DECODE_OPERAND_REG(SReg_512) 115 116 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 117 unsigned Imm, 118 uint64_t Addr, 119 const void *Decoder) { 120 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 121 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 122 } 123 124 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 125 unsigned Imm, 126 uint64_t Addr, 127 const void *Decoder) { 128 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 129 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 130 } 131 132 #define DECODE_SDWA(DecName) \ 133 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 134 135 DECODE_SDWA(Src32) 136 DECODE_SDWA(Src16) 137 DECODE_SDWA(VopcDst) 138 139 #include "AMDGPUGenDisassemblerTables.inc" 140 141 //===----------------------------------------------------------------------===// 142 // 143 //===----------------------------------------------------------------------===// 144 145 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 146 assert(Bytes.size() >= sizeof(T)); 147 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 148 Bytes = Bytes.slice(sizeof(T)); 149 return Res; 150 } 151 152 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 153 MCInst &MI, 154 uint64_t Inst, 155 uint64_t Address) const { 156 assert(MI.getOpcode() == 0); 157 assert(MI.getNumOperands() == 0); 158 MCInst TmpInst; 159 HasLiteral = false; 160 const auto SavedBytes = Bytes; 161 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 162 MI = TmpInst; 163 return MCDisassembler::Success; 164 } 165 Bytes = SavedBytes; 166 return MCDisassembler::Fail; 167 } 168 169 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 170 ArrayRef<uint8_t> Bytes_, 171 uint64_t Address, 172 raw_ostream &WS, 173 raw_ostream &CS) const { 174 CommentStream = &CS; 175 bool IsSDWA = false; 176 177 // ToDo: AMDGPUDisassembler supports only VI ISA. 178 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding]) 179 report_fatal_error("Disassembly not yet supported for subtarget"); 180 181 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 182 Bytes = Bytes_.slice(0, MaxInstBytesNum); 183 184 DecodeStatus Res = MCDisassembler::Fail; 185 do { 186 // ToDo: better to switch encoding length using some bit predicate 187 // but it is unknown yet, so try all we can 188 189 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 190 // encodings 191 if (Bytes.size() >= 8) { 192 const uint64_t QW = eatBytes<uint64_t>(Bytes); 193 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 194 if (Res) break; 195 196 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 197 if (Res) { IsSDWA = true; break; } 198 199 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 200 if (Res) { IsSDWA = true; break; } 201 } 202 203 // Reinitialize Bytes as DPP64 could have eaten too much 204 Bytes = Bytes_.slice(0, MaxInstBytesNum); 205 206 // Try decode 32-bit instruction 207 if (Bytes.size() < 4) break; 208 const uint32_t DW = eatBytes<uint32_t>(Bytes); 209 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 210 if (Res) break; 211 212 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 213 if (Res) break; 214 215 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 216 if (Res) break; 217 218 if (Bytes.size() < 4) break; 219 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 220 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 221 if (Res) break; 222 223 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 224 if (Res) break; 225 226 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 227 } while (false); 228 229 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 230 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si || 231 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) { 232 // Insert dummy unused src2_modifiers. 233 insertNamedMCOperand(MI, MCOperand::createImm(0), 234 AMDGPU::OpName::src2_modifiers); 235 } 236 237 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 238 Res = convertMIMGInst(MI); 239 } 240 241 if (Res && IsSDWA) 242 Res = convertSDWAInst(MI); 243 244 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 245 return Res; 246 } 247 248 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 249 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 250 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 251 // VOPC - insert clamp 252 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 253 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 254 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 255 if (SDst != -1) { 256 // VOPC - insert VCC register as sdst 257 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 258 AMDGPU::OpName::sdst); 259 } else { 260 // VOP1/2 - insert omod if present in instruction 261 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 262 } 263 } 264 return MCDisassembler::Success; 265 } 266 267 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 268 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 269 AMDGPU::OpName::vdata); 270 271 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 272 AMDGPU::OpName::dmask); 273 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 274 if (DMask == 0) 275 return MCDisassembler::Success; 276 277 unsigned ChannelCount = countPopulation(DMask); 278 if (ChannelCount == 1) 279 return MCDisassembler::Success; 280 281 int NewOpcode = AMDGPU::getMaskedMIMGOp(*MCII, MI.getOpcode(), ChannelCount); 282 assert(NewOpcode != -1 && "could not find matching mimg channel instruction"); 283 auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 284 285 // Widen the register to the correct number of enabled channels. 286 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 287 auto NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 288 &MRI.getRegClass(RCID)); 289 if (NewVdata == AMDGPU::NoRegister) { 290 // It's possible to encode this such that the low register + enabled 291 // components exceeds the register count. 292 return MCDisassembler::Success; 293 } 294 295 MI.setOpcode(NewOpcode); 296 // vaddr will be always appear as a single VGPR. This will look different than 297 // how it is usually emitted because the number of register components is not 298 // in the instruction encoding. 299 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 300 return MCDisassembler::Success; 301 } 302 303 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 304 return getContext().getRegisterInfo()-> 305 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 306 } 307 308 inline 309 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 310 const Twine& ErrMsg) const { 311 *CommentStream << "Error: " + ErrMsg; 312 313 // ToDo: add support for error operands to MCInst.h 314 // return MCOperand::createError(V); 315 return MCOperand(); 316 } 317 318 inline 319 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 320 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 321 } 322 323 inline 324 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 325 unsigned Val) const { 326 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 327 if (Val >= RegCl.getNumRegs()) 328 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 329 ": unknown register " + Twine(Val)); 330 return createRegOperand(RegCl.getRegister(Val)); 331 } 332 333 inline 334 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 335 unsigned Val) const { 336 // ToDo: SI/CI have 104 SGPRs, VI - 102 337 // Valery: here we accepting as much as we can, let assembler sort it out 338 int shift = 0; 339 switch (SRegClassID) { 340 case AMDGPU::SGPR_32RegClassID: 341 case AMDGPU::TTMP_32RegClassID: 342 break; 343 case AMDGPU::SGPR_64RegClassID: 344 case AMDGPU::TTMP_64RegClassID: 345 shift = 1; 346 break; 347 case AMDGPU::SGPR_128RegClassID: 348 case AMDGPU::TTMP_128RegClassID: 349 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 350 // this bundle? 351 case AMDGPU::SGPR_256RegClassID: 352 case AMDGPU::TTMP_256RegClassID: 353 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 354 // this bundle? 355 case AMDGPU::SGPR_512RegClassID: 356 case AMDGPU::TTMP_512RegClassID: 357 shift = 2; 358 break; 359 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 360 // this bundle? 361 default: 362 llvm_unreachable("unhandled register class"); 363 } 364 365 if (Val % (1 << shift)) { 366 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 367 << ": scalar reg isn't aligned " << Val; 368 } 369 370 return createRegOperand(SRegClassID, Val >> shift); 371 } 372 373 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 374 return decodeSrcOp(OPW32, Val); 375 } 376 377 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 378 return decodeSrcOp(OPW64, Val); 379 } 380 381 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 382 return decodeSrcOp(OPW128, Val); 383 } 384 385 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 386 return decodeSrcOp(OPW16, Val); 387 } 388 389 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 390 return decodeSrcOp(OPWV216, Val); 391 } 392 393 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 394 // Some instructions have operand restrictions beyond what the encoding 395 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 396 // high bit. 397 Val &= 255; 398 399 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 400 } 401 402 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 403 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 404 } 405 406 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 407 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 408 } 409 410 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 411 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 412 } 413 414 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 415 // table-gen generated disassembler doesn't care about operand types 416 // leaving only registry class so SSrc_32 operand turns into SReg_32 417 // and therefore we accept immediates and literals here as well 418 return decodeSrcOp(OPW32, Val); 419 } 420 421 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 422 unsigned Val) const { 423 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 424 return decodeOperand_SReg_32(Val); 425 } 426 427 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 428 unsigned Val) const { 429 // SReg_32_XM0 is SReg_32 without EXEC_HI 430 return decodeOperand_SReg_32(Val); 431 } 432 433 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 434 return decodeSrcOp(OPW64, Val); 435 } 436 437 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 438 return decodeSrcOp(OPW64, Val); 439 } 440 441 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 442 return decodeSrcOp(OPW128, Val); 443 } 444 445 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 446 return decodeDstOp(OPW256, Val); 447 } 448 449 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 450 return decodeDstOp(OPW512, Val); 451 } 452 453 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 454 // For now all literal constants are supposed to be unsigned integer 455 // ToDo: deal with signed/unsigned 64-bit integer constants 456 // ToDo: deal with float/double constants 457 if (!HasLiteral) { 458 if (Bytes.size() < 4) { 459 return errOperand(0, "cannot read literal, inst bytes left " + 460 Twine(Bytes.size())); 461 } 462 HasLiteral = true; 463 Literal = eatBytes<uint32_t>(Bytes); 464 } 465 return MCOperand::createImm(Literal); 466 } 467 468 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 469 using namespace AMDGPU::EncValues; 470 471 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 472 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 473 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 474 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 475 // Cast prevents negative overflow. 476 } 477 478 static int64_t getInlineImmVal32(unsigned Imm) { 479 switch (Imm) { 480 case 240: 481 return FloatToBits(0.5f); 482 case 241: 483 return FloatToBits(-0.5f); 484 case 242: 485 return FloatToBits(1.0f); 486 case 243: 487 return FloatToBits(-1.0f); 488 case 244: 489 return FloatToBits(2.0f); 490 case 245: 491 return FloatToBits(-2.0f); 492 case 246: 493 return FloatToBits(4.0f); 494 case 247: 495 return FloatToBits(-4.0f); 496 case 248: // 1 / (2 * PI) 497 return 0x3e22f983; 498 default: 499 llvm_unreachable("invalid fp inline imm"); 500 } 501 } 502 503 static int64_t getInlineImmVal64(unsigned Imm) { 504 switch (Imm) { 505 case 240: 506 return DoubleToBits(0.5); 507 case 241: 508 return DoubleToBits(-0.5); 509 case 242: 510 return DoubleToBits(1.0); 511 case 243: 512 return DoubleToBits(-1.0); 513 case 244: 514 return DoubleToBits(2.0); 515 case 245: 516 return DoubleToBits(-2.0); 517 case 246: 518 return DoubleToBits(4.0); 519 case 247: 520 return DoubleToBits(-4.0); 521 case 248: // 1 / (2 * PI) 522 return 0x3fc45f306dc9c882; 523 default: 524 llvm_unreachable("invalid fp inline imm"); 525 } 526 } 527 528 static int64_t getInlineImmVal16(unsigned Imm) { 529 switch (Imm) { 530 case 240: 531 return 0x3800; 532 case 241: 533 return 0xB800; 534 case 242: 535 return 0x3C00; 536 case 243: 537 return 0xBC00; 538 case 244: 539 return 0x4000; 540 case 245: 541 return 0xC000; 542 case 246: 543 return 0x4400; 544 case 247: 545 return 0xC400; 546 case 248: // 1 / (2 * PI) 547 return 0x3118; 548 default: 549 llvm_unreachable("invalid fp inline imm"); 550 } 551 } 552 553 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 554 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 555 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 556 557 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 558 switch (Width) { 559 case OPW32: 560 return MCOperand::createImm(getInlineImmVal32(Imm)); 561 case OPW64: 562 return MCOperand::createImm(getInlineImmVal64(Imm)); 563 case OPW16: 564 case OPWV216: 565 return MCOperand::createImm(getInlineImmVal16(Imm)); 566 default: 567 llvm_unreachable("implement me"); 568 } 569 } 570 571 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 572 using namespace AMDGPU; 573 574 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 575 switch (Width) { 576 default: // fall 577 case OPW32: 578 case OPW16: 579 case OPWV216: 580 return VGPR_32RegClassID; 581 case OPW64: return VReg_64RegClassID; 582 case OPW128: return VReg_128RegClassID; 583 } 584 } 585 586 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 587 using namespace AMDGPU; 588 589 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 590 switch (Width) { 591 default: // fall 592 case OPW32: 593 case OPW16: 594 case OPWV216: 595 return SGPR_32RegClassID; 596 case OPW64: return SGPR_64RegClassID; 597 case OPW128: return SGPR_128RegClassID; 598 case OPW256: return SGPR_256RegClassID; 599 case OPW512: return SGPR_512RegClassID; 600 } 601 } 602 603 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 604 using namespace AMDGPU; 605 606 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 607 switch (Width) { 608 default: // fall 609 case OPW32: 610 case OPW16: 611 case OPWV216: 612 return TTMP_32RegClassID; 613 case OPW64: return TTMP_64RegClassID; 614 case OPW128: return TTMP_128RegClassID; 615 case OPW256: return TTMP_256RegClassID; 616 case OPW512: return TTMP_512RegClassID; 617 } 618 } 619 620 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 621 using namespace AMDGPU::EncValues; 622 623 unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN; 624 unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX; 625 626 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 627 } 628 629 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 630 using namespace AMDGPU::EncValues; 631 632 assert(Val < 512); // enum9 633 634 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 635 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); 636 } 637 if (Val <= SGPR_MAX) { 638 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 639 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 640 } 641 642 int TTmpIdx = getTTmpIdx(Val); 643 if (TTmpIdx >= 0) { 644 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 645 } 646 647 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 648 return decodeIntImmed(Val); 649 650 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 651 return decodeFPImmed(Width, Val); 652 653 if (Val == LITERAL_CONST) 654 return decodeLiteralConstant(); 655 656 switch (Width) { 657 case OPW32: 658 case OPW16: 659 case OPWV216: 660 return decodeSpecialReg32(Val); 661 case OPW64: 662 return decodeSpecialReg64(Val); 663 default: 664 llvm_unreachable("unexpected immediate type"); 665 } 666 } 667 668 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 669 using namespace AMDGPU::EncValues; 670 671 assert(Val < 128); 672 assert(Width == OPW256 || Width == OPW512); 673 674 if (Val <= SGPR_MAX) { 675 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 676 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 677 } 678 679 int TTmpIdx = getTTmpIdx(Val); 680 if (TTmpIdx >= 0) { 681 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 682 } 683 684 llvm_unreachable("unknown dst register"); 685 } 686 687 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 688 using namespace AMDGPU; 689 690 switch (Val) { 691 case 102: return createRegOperand(FLAT_SCR_LO); 692 case 103: return createRegOperand(FLAT_SCR_HI); 693 case 104: return createRegOperand(XNACK_MASK_LO); 694 case 105: return createRegOperand(XNACK_MASK_HI); 695 case 106: return createRegOperand(VCC_LO); 696 case 107: return createRegOperand(VCC_HI); 697 case 108: assert(!isGFX9()); return createRegOperand(TBA_LO); 698 case 109: assert(!isGFX9()); return createRegOperand(TBA_HI); 699 case 110: assert(!isGFX9()); return createRegOperand(TMA_LO); 700 case 111: assert(!isGFX9()); return createRegOperand(TMA_HI); 701 case 124: return createRegOperand(M0); 702 case 126: return createRegOperand(EXEC_LO); 703 case 127: return createRegOperand(EXEC_HI); 704 case 235: return createRegOperand(SRC_SHARED_BASE); 705 case 236: return createRegOperand(SRC_SHARED_LIMIT); 706 case 237: return createRegOperand(SRC_PRIVATE_BASE); 707 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 708 // TODO: SRC_POPS_EXITING_WAVE_ID 709 // ToDo: no support for vccz register 710 case 251: break; 711 // ToDo: no support for execz register 712 case 252: break; 713 case 253: return createRegOperand(SCC); 714 default: break; 715 } 716 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 717 } 718 719 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 720 using namespace AMDGPU; 721 722 switch (Val) { 723 case 102: return createRegOperand(FLAT_SCR); 724 case 104: return createRegOperand(XNACK_MASK); 725 case 106: return createRegOperand(VCC); 726 case 108: assert(!isGFX9()); return createRegOperand(TBA); 727 case 110: assert(!isGFX9()); return createRegOperand(TMA); 728 case 126: return createRegOperand(EXEC); 729 default: break; 730 } 731 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 732 } 733 734 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 735 const unsigned Val) const { 736 using namespace AMDGPU::SDWA; 737 using namespace AMDGPU::EncValues; 738 739 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 740 // XXX: static_cast<int> is needed to avoid stupid warning: 741 // compare with unsigned is always true 742 if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) && 743 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 744 return createRegOperand(getVgprClassId(Width), 745 Val - SDWA9EncValues::SRC_VGPR_MIN); 746 } 747 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 748 Val <= SDWA9EncValues::SRC_SGPR_MAX) { 749 return createSRegOperand(getSgprClassId(Width), 750 Val - SDWA9EncValues::SRC_SGPR_MIN); 751 } 752 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 753 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 754 return createSRegOperand(getTtmpClassId(Width), 755 Val - SDWA9EncValues::SRC_TTMP_MIN); 756 } 757 758 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 759 760 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 761 return decodeIntImmed(SVal); 762 763 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 764 return decodeFPImmed(Width, SVal); 765 766 return decodeSpecialReg32(SVal); 767 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 768 return createRegOperand(getVgprClassId(Width), Val); 769 } 770 llvm_unreachable("unsupported target"); 771 } 772 773 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 774 return decodeSDWASrc(OPW16, Val); 775 } 776 777 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 778 return decodeSDWASrc(OPW32, Val); 779 } 780 781 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 782 using namespace AMDGPU::SDWA; 783 784 assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] && 785 "SDWAVopcDst should be present only on GFX9"); 786 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 787 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 788 789 int TTmpIdx = getTTmpIdx(Val); 790 if (TTmpIdx >= 0) { 791 return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx); 792 } else if (Val > AMDGPU::EncValues::SGPR_MAX) { 793 return decodeSpecialReg64(Val); 794 } else { 795 return createSRegOperand(getSgprClassId(OPW64), Val); 796 } 797 } else { 798 return createRegOperand(AMDGPU::VCC); 799 } 800 } 801 802 bool AMDGPUDisassembler::isVI() const { 803 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 804 } 805 806 bool AMDGPUDisassembler::isGFX9() const { 807 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; 808 } 809 810 //===----------------------------------------------------------------------===// 811 // AMDGPUSymbolizer 812 //===----------------------------------------------------------------------===// 813 814 // Try to find symbol name for specified label 815 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 816 raw_ostream &/*cStream*/, int64_t Value, 817 uint64_t /*Address*/, bool IsBranch, 818 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 819 using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>; 820 using SectionSymbolsTy = std::vector<SymbolInfoTy>; 821 822 if (!IsBranch) { 823 return false; 824 } 825 826 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 827 auto Result = std::find_if(Symbols->begin(), Symbols->end(), 828 [Value](const SymbolInfoTy& Val) { 829 return std::get<0>(Val) == static_cast<uint64_t>(Value) 830 && std::get<2>(Val) == ELF::STT_NOTYPE; 831 }); 832 if (Result != Symbols->end()) { 833 auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result)); 834 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 835 Inst.addOperand(MCOperand::createExpr(Add)); 836 return true; 837 } 838 return false; 839 } 840 841 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 842 int64_t Value, 843 uint64_t Address) { 844 llvm_unreachable("unimplemented"); 845 } 846 847 //===----------------------------------------------------------------------===// 848 // Initialization 849 //===----------------------------------------------------------------------===// 850 851 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 852 LLVMOpInfoCallback /*GetOpInfo*/, 853 LLVMSymbolLookupCallback /*SymbolLookUp*/, 854 void *DisInfo, 855 MCContext *Ctx, 856 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 857 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 858 } 859 860 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 861 const MCSubtargetInfo &STI, 862 MCContext &Ctx) { 863 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 864 } 865 866 extern "C" void LLVMInitializeAMDGPUDisassembler() { 867 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 868 createAMDGPUDisassembler); 869 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 870 createAMDGPUSymbolizer); 871 } 872