1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VGPR_32_Lo128) 123 DECODE_OPERAND_REG(VRegOrLds_32) 124 DECODE_OPERAND_REG(VS_32) 125 DECODE_OPERAND_REG(VS_64) 126 DECODE_OPERAND_REG(VS_128) 127 128 DECODE_OPERAND_REG(VReg_64) 129 DECODE_OPERAND_REG(VReg_96) 130 DECODE_OPERAND_REG(VReg_128) 131 DECODE_OPERAND_REG(VReg_256) 132 DECODE_OPERAND_REG(VReg_512) 133 DECODE_OPERAND_REG(VReg_1024) 134 135 DECODE_OPERAND_REG(SReg_32) 136 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 137 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 138 DECODE_OPERAND_REG(SRegOrLds_32) 139 DECODE_OPERAND_REG(SReg_64) 140 DECODE_OPERAND_REG(SReg_64_XEXEC) 141 DECODE_OPERAND_REG(SReg_128) 142 DECODE_OPERAND_REG(SReg_256) 143 DECODE_OPERAND_REG(SReg_512) 144 145 DECODE_OPERAND_REG(AGPR_32) 146 DECODE_OPERAND_REG(AReg_64) 147 DECODE_OPERAND_REG(AReg_128) 148 DECODE_OPERAND_REG(AReg_256) 149 DECODE_OPERAND_REG(AReg_512) 150 DECODE_OPERAND_REG(AReg_1024) 151 DECODE_OPERAND_REG(AV_32) 152 DECODE_OPERAND_REG(AV_64) 153 DECODE_OPERAND_REG(AV_128) 154 DECODE_OPERAND_REG(AVDst_128) 155 DECODE_OPERAND_REG(AVDst_512) 156 157 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 158 uint64_t Addr, 159 const MCDisassembler *Decoder) { 160 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 161 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 162 } 163 164 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 165 uint64_t Addr, 166 const MCDisassembler *Decoder) { 167 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 168 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 169 } 170 171 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 172 uint64_t Addr, 173 const MCDisassembler *Decoder) { 174 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 175 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 176 } 177 178 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 179 uint64_t Addr, 180 const MCDisassembler *Decoder) { 181 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 182 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 183 } 184 185 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 186 uint64_t Addr, 187 const MCDisassembler *Decoder) { 188 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 189 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 190 } 191 192 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 193 uint64_t Addr, 194 const MCDisassembler *Decoder) { 195 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 196 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 197 } 198 199 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 200 uint64_t Addr, 201 const MCDisassembler *Decoder) { 202 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 203 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 204 } 205 206 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 207 uint64_t Addr, 208 const MCDisassembler *Decoder) { 209 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 210 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 211 } 212 213 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 214 uint64_t Addr, 215 const MCDisassembler *Decoder) { 216 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 217 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 218 } 219 220 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 221 uint64_t Addr, 222 const MCDisassembler *Decoder) { 223 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 224 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 225 } 226 227 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 228 uint64_t Addr, 229 const MCDisassembler *Decoder) { 230 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 231 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 232 } 233 234 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 235 uint64_t Addr, 236 const MCDisassembler *Decoder) { 237 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 238 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 239 } 240 241 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 242 uint64_t Addr, 243 const MCDisassembler *Decoder) { 244 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 245 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 246 } 247 248 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 249 uint64_t Addr, 250 const MCDisassembler *Decoder) { 251 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 252 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 253 } 254 255 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 256 uint64_t Addr, 257 const MCDisassembler *Decoder) { 258 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 259 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 260 } 261 262 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 263 uint64_t Addr, 264 const MCDisassembler *Decoder) { 265 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 266 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 267 } 268 269 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 270 uint64_t Addr, 271 const MCDisassembler *Decoder) { 272 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 273 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 274 } 275 276 static DecodeStatus 277 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 278 const MCDisassembler *Decoder) { 279 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 280 return addOperand( 281 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 282 } 283 284 static DecodeStatus 285 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 286 const MCDisassembler *Decoder) { 287 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 288 return addOperand( 289 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 290 } 291 292 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 293 uint64_t Addr, const void *Decoder) { 294 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 295 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 296 } 297 298 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 299 const MCRegisterInfo *MRI) { 300 if (OpIdx < 0) 301 return false; 302 303 const MCOperand &Op = Inst.getOperand(OpIdx); 304 if (!Op.isReg()) 305 return false; 306 307 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 308 auto Reg = Sub ? Sub : Op.getReg(); 309 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 310 } 311 312 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 313 AMDGPUDisassembler::OpWidthTy Opw, 314 const MCDisassembler *Decoder) { 315 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 316 if (!DAsm->isGFX90A()) { 317 Imm &= 511; 318 } else { 319 // If atomic has both vdata and vdst their register classes are tied. 320 // The bit is decoded along with the vdst, first operand. We need to 321 // change register class to AGPR if vdst was AGPR. 322 // If a DS instruction has both data0 and data1 their register classes 323 // are also tied. 324 unsigned Opc = Inst.getOpcode(); 325 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 326 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 327 : AMDGPU::OpName::vdata; 328 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 329 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 330 if ((int)Inst.getNumOperands() == DataIdx) { 331 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 332 if (IsAGPROperand(Inst, DstIdx, MRI)) 333 Imm |= 512; 334 } 335 336 if (TSFlags & SIInstrFlags::DS) { 337 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 338 if ((int)Inst.getNumOperands() == Data2Idx && 339 IsAGPROperand(Inst, DataIdx, MRI)) 340 Imm |= 512; 341 } 342 } 343 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 344 } 345 346 static DecodeStatus 347 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 348 const MCDisassembler *Decoder) { 349 return decodeOperand_AVLdSt_Any(Inst, Imm, 350 AMDGPUDisassembler::OPW32, Decoder); 351 } 352 353 static DecodeStatus 354 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 355 const MCDisassembler *Decoder) { 356 return decodeOperand_AVLdSt_Any(Inst, Imm, 357 AMDGPUDisassembler::OPW64, Decoder); 358 } 359 360 static DecodeStatus 361 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 362 const MCDisassembler *Decoder) { 363 return decodeOperand_AVLdSt_Any(Inst, Imm, 364 AMDGPUDisassembler::OPW96, Decoder); 365 } 366 367 static DecodeStatus 368 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 369 const MCDisassembler *Decoder) { 370 return decodeOperand_AVLdSt_Any(Inst, Imm, 371 AMDGPUDisassembler::OPW128, Decoder); 372 } 373 374 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 375 uint64_t Addr, 376 const MCDisassembler *Decoder) { 377 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 378 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 379 } 380 381 #define DECODE_SDWA(DecName) \ 382 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 383 384 DECODE_SDWA(Src32) 385 DECODE_SDWA(Src16) 386 DECODE_SDWA(VopcDst) 387 388 #include "AMDGPUGenDisassemblerTables.inc" 389 390 //===----------------------------------------------------------------------===// 391 // 392 //===----------------------------------------------------------------------===// 393 394 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 395 assert(Bytes.size() >= sizeof(T)); 396 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 397 Bytes = Bytes.slice(sizeof(T)); 398 return Res; 399 } 400 401 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 402 assert(Bytes.size() >= 12); 403 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 404 Bytes.data()); 405 Bytes = Bytes.slice(8); 406 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 407 Bytes.data()); 408 Bytes = Bytes.slice(4); 409 return DecoderUInt128(Lo, Hi); 410 } 411 412 // The disassembler is greedy, so we need to check FI operand value to 413 // not parse a dpp if the correct literal is not set. For dpp16 the 414 // autogenerated decoder checks the dpp literal 415 static bool isValidDPP8(const MCInst &MI) { 416 using namespace llvm::AMDGPU::DPP; 417 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 418 assert(FiIdx != -1); 419 if ((unsigned)FiIdx >= MI.getNumOperands()) 420 return false; 421 unsigned Fi = MI.getOperand(FiIdx).getImm(); 422 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 423 } 424 425 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 426 ArrayRef<uint8_t> Bytes_, 427 uint64_t Address, 428 raw_ostream &CS) const { 429 CommentStream = &CS; 430 bool IsSDWA = false; 431 432 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 433 Bytes = Bytes_.slice(0, MaxInstBytesNum); 434 435 DecodeStatus Res = MCDisassembler::Fail; 436 do { 437 // ToDo: better to switch encoding length using some bit predicate 438 // but it is unknown yet, so try all we can 439 440 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 441 // encodings 442 if (isGFX11Plus() && Bytes.size() >= 12 ) { 443 DecoderUInt128 DecW = eat12Bytes(Bytes); 444 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 445 Address); 446 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 447 break; 448 MI = MCInst(); // clear 449 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 450 Address); 451 if (Res) { 452 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 453 convertVOP3PDPPInst(MI); 454 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 455 convertVOPCDPPInst(MI); // Special VOP3 case 456 else { 457 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 458 convertVOP3DPPInst(MI); // Regular VOP3 case 459 } 460 break; 461 } 462 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address); 463 if (Res) 464 break; 465 } 466 // Reinitialize Bytes 467 Bytes = Bytes_.slice(0, MaxInstBytesNum); 468 469 if (Bytes.size() >= 8) { 470 const uint64_t QW = eatBytes<uint64_t>(Bytes); 471 472 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 473 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 474 if (Res) { 475 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 476 == -1) 477 break; 478 if (convertDPP8Inst(MI) == MCDisassembler::Success) 479 break; 480 MI = MCInst(); // clear 481 } 482 } 483 484 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 485 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 486 break; 487 MI = MCInst(); // clear 488 489 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 490 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 491 break; 492 MI = MCInst(); // clear 493 494 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 495 if (Res) break; 496 497 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 498 if (Res) { 499 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 500 convertVOPCDPPInst(MI); 501 break; 502 } 503 504 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 505 if (Res) { IsSDWA = true; break; } 506 507 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 508 if (Res) { IsSDWA = true; break; } 509 510 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 511 if (Res) { IsSDWA = true; break; } 512 513 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 514 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 515 if (Res) 516 break; 517 } 518 519 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 520 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 521 // table first so we print the correct name. 522 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 523 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 524 if (Res) 525 break; 526 } 527 } 528 529 // Reinitialize Bytes as DPP64 could have eaten too much 530 Bytes = Bytes_.slice(0, MaxInstBytesNum); 531 532 // Try decode 32-bit instruction 533 if (Bytes.size() < 4) break; 534 const uint32_t DW = eatBytes<uint32_t>(Bytes); 535 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 536 if (Res) break; 537 538 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 539 if (Res) break; 540 541 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 542 if (Res) break; 543 544 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 545 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 546 if (Res) 547 break; 548 } 549 550 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 551 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 552 if (Res) break; 553 } 554 555 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 556 if (Res) break; 557 558 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 559 if (Res) break; 560 561 if (Bytes.size() < 4) break; 562 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 563 564 if (STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts]) { 565 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address); 566 if (Res) 567 break; 568 } 569 570 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 571 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 572 if (Res) 573 break; 574 } 575 576 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 577 if (Res) break; 578 579 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 580 if (Res) break; 581 582 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 583 if (Res) break; 584 585 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 586 if (Res) break; 587 588 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 589 if (Res) 590 break; 591 592 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address); 593 } while (false); 594 595 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 596 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 597 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 598 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 599 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 600 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 601 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 602 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 603 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 604 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 || 605 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 606 MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || 607 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 || 608 MI.getOpcode() == AMDGPU::V_FMAC_F16_t16_e64_gfx11)) { 609 // Insert dummy unused src2_modifiers. 610 insertNamedMCOperand(MI, MCOperand::createImm(0), 611 AMDGPU::OpName::src2_modifiers); 612 } 613 614 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 615 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 616 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 617 AMDGPU::OpName::cpol); 618 if (CPolPos != -1) { 619 unsigned CPol = 620 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 621 AMDGPU::CPol::GLC : 0; 622 if (MI.getNumOperands() <= (unsigned)CPolPos) { 623 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 624 AMDGPU::OpName::cpol); 625 } else if (CPol) { 626 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 627 } 628 } 629 } 630 631 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 632 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 633 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 634 // GFX90A lost TFE, its place is occupied by ACC. 635 int TFEOpIdx = 636 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 637 if (TFEOpIdx != -1) { 638 auto TFEIter = MI.begin(); 639 std::advance(TFEIter, TFEOpIdx); 640 MI.insert(TFEIter, MCOperand::createImm(0)); 641 } 642 } 643 644 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 645 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 646 int SWZOpIdx = 647 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 648 if (SWZOpIdx != -1) { 649 auto SWZIter = MI.begin(); 650 std::advance(SWZIter, SWZOpIdx); 651 MI.insert(SWZIter, MCOperand::createImm(0)); 652 } 653 } 654 655 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 656 int VAddr0Idx = 657 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 658 int RsrcIdx = 659 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 660 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 661 if (VAddr0Idx >= 0 && NSAArgs > 0) { 662 unsigned NSAWords = (NSAArgs + 3) / 4; 663 if (Bytes.size() < 4 * NSAWords) { 664 Res = MCDisassembler::Fail; 665 } else { 666 for (unsigned i = 0; i < NSAArgs; ++i) { 667 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 668 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 669 MI.insert(MI.begin() + VAddrIdx, 670 createRegOperand(VAddrRCID, Bytes[i])); 671 } 672 Bytes = Bytes.slice(4 * NSAWords); 673 } 674 } 675 676 if (Res) 677 Res = convertMIMGInst(MI); 678 } 679 680 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 681 Res = convertEXPInst(MI); 682 683 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 684 Res = convertVINTERPInst(MI); 685 686 if (Res && IsSDWA) 687 Res = convertSDWAInst(MI); 688 689 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 690 AMDGPU::OpName::vdst_in); 691 if (VDstIn_Idx != -1) { 692 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 693 MCOI::OperandConstraint::TIED_TO); 694 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 695 !MI.getOperand(VDstIn_Idx).isReg() || 696 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 697 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 698 MI.erase(&MI.getOperand(VDstIn_Idx)); 699 insertNamedMCOperand(MI, 700 MCOperand::createReg(MI.getOperand(Tied).getReg()), 701 AMDGPU::OpName::vdst_in); 702 } 703 } 704 705 int ImmLitIdx = 706 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 707 if (Res && ImmLitIdx != -1) 708 Res = convertFMAanyK(MI, ImmLitIdx); 709 710 // if the opcode was not recognized we'll assume a Size of 4 bytes 711 // (unless there are fewer bytes left) 712 Size = Res ? (MaxInstBytesNum - Bytes.size()) 713 : std::min((size_t)4, Bytes_.size()); 714 return Res; 715 } 716 717 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 718 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 719 // The MCInst still has these fields even though they are no longer encoded 720 // in the GFX11 instruction. 721 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 722 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 723 } 724 return MCDisassembler::Success; 725 } 726 727 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 728 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 729 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 730 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 731 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 732 // The MCInst has this field that is not directly encoded in the 733 // instruction. 734 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 735 } 736 return MCDisassembler::Success; 737 } 738 739 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 740 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 741 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 742 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 743 // VOPC - insert clamp 744 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 745 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 746 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 747 if (SDst != -1) { 748 // VOPC - insert VCC register as sdst 749 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 750 AMDGPU::OpName::sdst); 751 } else { 752 // VOP1/2 - insert omod if present in instruction 753 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 754 } 755 } 756 return MCDisassembler::Success; 757 } 758 759 struct VOPModifiers { 760 unsigned OpSel = 0; 761 unsigned OpSelHi = 0; 762 unsigned NegLo = 0; 763 unsigned NegHi = 0; 764 }; 765 766 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 767 // Note that these values do not affect disassembler output, 768 // so this is only necessary for consistency with src_modifiers. 769 static VOPModifiers collectVOPModifiers(const MCInst &MI, 770 bool IsVOP3P = false) { 771 VOPModifiers Modifiers; 772 unsigned Opc = MI.getOpcode(); 773 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 774 AMDGPU::OpName::src1_modifiers, 775 AMDGPU::OpName::src2_modifiers}; 776 for (int J = 0; J < 3; ++J) { 777 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 778 if (OpIdx == -1) 779 continue; 780 781 unsigned Val = MI.getOperand(OpIdx).getImm(); 782 783 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 784 if (IsVOP3P) { 785 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 786 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 787 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 788 } else if (J == 0) { 789 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 790 } 791 } 792 793 return Modifiers; 794 } 795 796 // We must check FI == literal to reject not genuine dpp8 insts, and we must 797 // first add optional MI operands to check FI 798 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 799 unsigned Opc = MI.getOpcode(); 800 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 801 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 802 convertVOP3PDPPInst(MI); 803 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 804 AMDGPU::isVOPC64DPP(Opc)) { 805 convertVOPCDPPInst(MI); 806 } else if (MI.getNumOperands() < DescNumOps && 807 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { 808 auto Mods = collectVOPModifiers(MI); 809 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 810 AMDGPU::OpName::op_sel); 811 } else { 812 // Insert dummy unused src modifiers. 813 if (MI.getNumOperands() < DescNumOps && 814 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 815 insertNamedMCOperand(MI, MCOperand::createImm(0), 816 AMDGPU::OpName::src0_modifiers); 817 818 if (MI.getNumOperands() < DescNumOps && 819 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 820 insertNamedMCOperand(MI, MCOperand::createImm(0), 821 AMDGPU::OpName::src1_modifiers); 822 } 823 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 824 } 825 826 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 827 unsigned Opc = MI.getOpcode(); 828 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 829 if (MI.getNumOperands() < DescNumOps && 830 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { 831 auto Mods = collectVOPModifiers(MI); 832 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 833 AMDGPU::OpName::op_sel); 834 } 835 return MCDisassembler::Success; 836 } 837 838 // Note that before gfx10, the MIMG encoding provided no information about 839 // VADDR size. Consequently, decoded instructions always show address as if it 840 // has 1 dword, which could be not really so. 841 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 842 843 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 844 AMDGPU::OpName::vdst); 845 846 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 847 AMDGPU::OpName::vdata); 848 int VAddr0Idx = 849 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 850 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 851 AMDGPU::OpName::dmask); 852 853 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 854 AMDGPU::OpName::tfe); 855 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 856 AMDGPU::OpName::d16); 857 858 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 859 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 860 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 861 862 assert(VDataIdx != -1); 863 if (BaseOpcode->BVH) { 864 // Add A16 operand for intersect_ray instructions 865 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 866 addOperand(MI, MCOperand::createImm(1)); 867 } 868 return MCDisassembler::Success; 869 } 870 871 bool IsAtomic = (VDstIdx != -1); 872 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 873 bool IsNSA = false; 874 unsigned AddrSize = Info->VAddrDwords; 875 876 if (isGFX10Plus()) { 877 unsigned DimIdx = 878 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 879 int A16Idx = 880 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 881 const AMDGPU::MIMGDimInfo *Dim = 882 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 883 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 884 885 AddrSize = 886 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 887 888 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 889 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 890 if (!IsNSA) { 891 if (AddrSize > 8) 892 AddrSize = 16; 893 } else { 894 if (AddrSize > Info->VAddrDwords) { 895 // The NSA encoding does not contain enough operands for the combination 896 // of base opcode / dimension. Should this be an error? 897 return MCDisassembler::Success; 898 } 899 } 900 } 901 902 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 903 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 904 905 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 906 if (D16 && AMDGPU::hasPackedD16(STI)) { 907 DstSize = (DstSize + 1) / 2; 908 } 909 910 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 911 DstSize += 1; 912 913 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 914 return MCDisassembler::Success; 915 916 int NewOpcode = 917 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 918 if (NewOpcode == -1) 919 return MCDisassembler::Success; 920 921 // Widen the register to the correct number of enabled channels. 922 unsigned NewVdata = AMDGPU::NoRegister; 923 if (DstSize != Info->VDataDwords) { 924 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 925 926 // Get first subregister of VData 927 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 928 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 929 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 930 931 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 932 &MRI.getRegClass(DataRCID)); 933 if (NewVdata == AMDGPU::NoRegister) { 934 // It's possible to encode this such that the low register + enabled 935 // components exceeds the register count. 936 return MCDisassembler::Success; 937 } 938 } 939 940 // If not using NSA on GFX10+, widen address register to correct size. 941 unsigned NewVAddr0 = AMDGPU::NoRegister; 942 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 943 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 944 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 945 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 946 947 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 948 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 949 &MRI.getRegClass(AddrRCID)); 950 if (NewVAddr0 == AMDGPU::NoRegister) 951 return MCDisassembler::Success; 952 } 953 954 MI.setOpcode(NewOpcode); 955 956 if (NewVdata != AMDGPU::NoRegister) { 957 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 958 959 if (IsAtomic) { 960 // Atomic operations have an additional operand (a copy of data) 961 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 962 } 963 } 964 965 if (NewVAddr0 != AMDGPU::NoRegister) { 966 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 967 } else if (IsNSA) { 968 assert(AddrSize <= Info->VAddrDwords); 969 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 970 MI.begin() + VAddr0Idx + Info->VAddrDwords); 971 } 972 973 return MCDisassembler::Success; 974 } 975 976 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 977 // decoder only adds to src_modifiers, so manually add the bits to the other 978 // operands. 979 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 980 unsigned Opc = MI.getOpcode(); 981 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 982 auto Mods = collectVOPModifiers(MI, true); 983 984 if (MI.getNumOperands() < DescNumOps && 985 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) 986 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 987 988 if (MI.getNumOperands() < DescNumOps && 989 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) 990 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 991 AMDGPU::OpName::op_sel); 992 if (MI.getNumOperands() < DescNumOps && 993 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi) != -1) 994 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 995 AMDGPU::OpName::op_sel_hi); 996 if (MI.getNumOperands() < DescNumOps && 997 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1) 998 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 999 AMDGPU::OpName::neg_lo); 1000 if (MI.getNumOperands() < DescNumOps && 1001 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1) 1002 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1003 AMDGPU::OpName::neg_hi); 1004 1005 return MCDisassembler::Success; 1006 } 1007 1008 // Create dummy old operand and insert optional operands 1009 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1010 unsigned Opc = MI.getOpcode(); 1011 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1012 1013 if (MI.getNumOperands() < DescNumOps && 1014 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1) 1015 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1016 1017 if (MI.getNumOperands() < DescNumOps && 1018 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 1019 insertNamedMCOperand(MI, MCOperand::createImm(0), 1020 AMDGPU::OpName::src0_modifiers); 1021 1022 if (MI.getNumOperands() < DescNumOps && 1023 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 1024 insertNamedMCOperand(MI, MCOperand::createImm(0), 1025 AMDGPU::OpName::src1_modifiers); 1026 return MCDisassembler::Success; 1027 } 1028 1029 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1030 int ImmLitIdx) const { 1031 assert(HasLiteral && "Should have decoded a literal"); 1032 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1033 unsigned DescNumOps = Desc.getNumOperands(); 1034 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1035 AMDGPU::OpName::immDeferred); 1036 assert(DescNumOps == MI.getNumOperands()); 1037 for (unsigned I = 0; I < DescNumOps; ++I) { 1038 auto &Op = MI.getOperand(I); 1039 auto OpType = Desc.OpInfo[I].OperandType; 1040 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1041 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1042 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1043 IsDeferredOp) 1044 Op.setImm(Literal); 1045 } 1046 return MCDisassembler::Success; 1047 } 1048 1049 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1050 return getContext().getRegisterInfo()-> 1051 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1052 } 1053 1054 inline 1055 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1056 const Twine& ErrMsg) const { 1057 *CommentStream << "Error: " + ErrMsg; 1058 1059 // ToDo: add support for error operands to MCInst.h 1060 // return MCOperand::createError(V); 1061 return MCOperand(); 1062 } 1063 1064 inline 1065 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1066 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1067 } 1068 1069 inline 1070 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1071 unsigned Val) const { 1072 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1073 if (Val >= RegCl.getNumRegs()) 1074 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1075 ": unknown register " + Twine(Val)); 1076 return createRegOperand(RegCl.getRegister(Val)); 1077 } 1078 1079 inline 1080 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1081 unsigned Val) const { 1082 // ToDo: SI/CI have 104 SGPRs, VI - 102 1083 // Valery: here we accepting as much as we can, let assembler sort it out 1084 int shift = 0; 1085 switch (SRegClassID) { 1086 case AMDGPU::SGPR_32RegClassID: 1087 case AMDGPU::TTMP_32RegClassID: 1088 break; 1089 case AMDGPU::SGPR_64RegClassID: 1090 case AMDGPU::TTMP_64RegClassID: 1091 shift = 1; 1092 break; 1093 case AMDGPU::SGPR_128RegClassID: 1094 case AMDGPU::TTMP_128RegClassID: 1095 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1096 // this bundle? 1097 case AMDGPU::SGPR_256RegClassID: 1098 case AMDGPU::TTMP_256RegClassID: 1099 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1100 // this bundle? 1101 case AMDGPU::SGPR_512RegClassID: 1102 case AMDGPU::TTMP_512RegClassID: 1103 shift = 2; 1104 break; 1105 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1106 // this bundle? 1107 default: 1108 llvm_unreachable("unhandled register class"); 1109 } 1110 1111 if (Val % (1 << shift)) { 1112 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1113 << ": scalar reg isn't aligned " << Val; 1114 } 1115 1116 return createRegOperand(SRegClassID, Val >> shift); 1117 } 1118 1119 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 1120 return decodeSrcOp(OPW32, Val); 1121 } 1122 1123 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 1124 return decodeSrcOp(OPW64, Val); 1125 } 1126 1127 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 1128 return decodeSrcOp(OPW128, Val); 1129 } 1130 1131 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 1132 return decodeSrcOp(OPW16, Val); 1133 } 1134 1135 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 1136 return decodeSrcOp(OPWV216, Val); 1137 } 1138 1139 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 1140 return decodeSrcOp(OPWV232, Val); 1141 } 1142 1143 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32_Lo128(unsigned Val) const { 1144 return createRegOperand(AMDGPU::VGPR_32_Lo128RegClassID, Val); 1145 } 1146 1147 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 1148 // Some instructions have operand restrictions beyond what the encoding 1149 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1150 // high bit. 1151 Val &= 255; 1152 1153 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1154 } 1155 1156 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1157 return decodeSrcOp(OPW32, Val); 1158 } 1159 1160 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1161 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1162 } 1163 1164 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1165 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1166 } 1167 1168 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1169 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1170 } 1171 1172 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1173 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1174 } 1175 1176 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1177 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1178 } 1179 1180 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1181 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1182 } 1183 1184 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1185 return decodeSrcOp(OPW32, Val); 1186 } 1187 1188 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1189 return decodeSrcOp(OPW64, Val); 1190 } 1191 1192 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1193 return decodeSrcOp(OPW128, Val); 1194 } 1195 1196 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1197 using namespace AMDGPU::EncValues; 1198 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1199 return decodeSrcOp(OPW128, Val | IS_VGPR); 1200 } 1201 1202 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1203 using namespace AMDGPU::EncValues; 1204 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1205 return decodeSrcOp(OPW512, Val | IS_VGPR); 1206 } 1207 1208 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1209 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1210 } 1211 1212 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1213 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1214 } 1215 1216 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1217 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1218 } 1219 1220 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1221 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1222 } 1223 1224 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1225 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1226 } 1227 1228 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1229 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1230 } 1231 1232 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1233 // table-gen generated disassembler doesn't care about operand types 1234 // leaving only registry class so SSrc_32 operand turns into SReg_32 1235 // and therefore we accept immediates and literals here as well 1236 return decodeSrcOp(OPW32, Val); 1237 } 1238 1239 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1240 unsigned Val) const { 1241 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1242 return decodeOperand_SReg_32(Val); 1243 } 1244 1245 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1246 unsigned Val) const { 1247 // SReg_32_XM0 is SReg_32 without EXEC_HI 1248 return decodeOperand_SReg_32(Val); 1249 } 1250 1251 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1252 // table-gen generated disassembler doesn't care about operand types 1253 // leaving only registry class so SSrc_32 operand turns into SReg_32 1254 // and therefore we accept immediates and literals here as well 1255 return decodeSrcOp(OPW32, Val); 1256 } 1257 1258 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1259 return decodeSrcOp(OPW64, Val); 1260 } 1261 1262 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1263 return decodeSrcOp(OPW64, Val); 1264 } 1265 1266 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1267 return decodeSrcOp(OPW128, Val); 1268 } 1269 1270 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1271 return decodeDstOp(OPW256, Val); 1272 } 1273 1274 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1275 return decodeDstOp(OPW512, Val); 1276 } 1277 1278 // Decode Literals for insts which always have a literal in the encoding 1279 MCOperand 1280 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1281 if (HasLiteral) { 1282 assert( 1283 AMDGPU::hasVOPD(STI) && 1284 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1285 if (Literal != Val) 1286 return errOperand(Val, "More than one unique literal is illegal"); 1287 } 1288 HasLiteral = true; 1289 Literal = Val; 1290 return MCOperand::createImm(Literal); 1291 } 1292 1293 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1294 // For now all literal constants are supposed to be unsigned integer 1295 // ToDo: deal with signed/unsigned 64-bit integer constants 1296 // ToDo: deal with float/double constants 1297 if (!HasLiteral) { 1298 if (Bytes.size() < 4) { 1299 return errOperand(0, "cannot read literal, inst bytes left " + 1300 Twine(Bytes.size())); 1301 } 1302 HasLiteral = true; 1303 Literal = eatBytes<uint32_t>(Bytes); 1304 } 1305 return MCOperand::createImm(Literal); 1306 } 1307 1308 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1309 using namespace AMDGPU::EncValues; 1310 1311 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1312 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1313 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1314 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1315 // Cast prevents negative overflow. 1316 } 1317 1318 static int64_t getInlineImmVal32(unsigned Imm) { 1319 switch (Imm) { 1320 case 240: 1321 return FloatToBits(0.5f); 1322 case 241: 1323 return FloatToBits(-0.5f); 1324 case 242: 1325 return FloatToBits(1.0f); 1326 case 243: 1327 return FloatToBits(-1.0f); 1328 case 244: 1329 return FloatToBits(2.0f); 1330 case 245: 1331 return FloatToBits(-2.0f); 1332 case 246: 1333 return FloatToBits(4.0f); 1334 case 247: 1335 return FloatToBits(-4.0f); 1336 case 248: // 1 / (2 * PI) 1337 return 0x3e22f983; 1338 default: 1339 llvm_unreachable("invalid fp inline imm"); 1340 } 1341 } 1342 1343 static int64_t getInlineImmVal64(unsigned Imm) { 1344 switch (Imm) { 1345 case 240: 1346 return DoubleToBits(0.5); 1347 case 241: 1348 return DoubleToBits(-0.5); 1349 case 242: 1350 return DoubleToBits(1.0); 1351 case 243: 1352 return DoubleToBits(-1.0); 1353 case 244: 1354 return DoubleToBits(2.0); 1355 case 245: 1356 return DoubleToBits(-2.0); 1357 case 246: 1358 return DoubleToBits(4.0); 1359 case 247: 1360 return DoubleToBits(-4.0); 1361 case 248: // 1 / (2 * PI) 1362 return 0x3fc45f306dc9c882; 1363 default: 1364 llvm_unreachable("invalid fp inline imm"); 1365 } 1366 } 1367 1368 static int64_t getInlineImmVal16(unsigned Imm) { 1369 switch (Imm) { 1370 case 240: 1371 return 0x3800; 1372 case 241: 1373 return 0xB800; 1374 case 242: 1375 return 0x3C00; 1376 case 243: 1377 return 0xBC00; 1378 case 244: 1379 return 0x4000; 1380 case 245: 1381 return 0xC000; 1382 case 246: 1383 return 0x4400; 1384 case 247: 1385 return 0xC400; 1386 case 248: // 1 / (2 * PI) 1387 return 0x3118; 1388 default: 1389 llvm_unreachable("invalid fp inline imm"); 1390 } 1391 } 1392 1393 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1394 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1395 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1396 1397 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1398 switch (Width) { 1399 case OPW32: 1400 case OPW128: // splat constants 1401 case OPW512: 1402 case OPW1024: 1403 case OPWV232: 1404 return MCOperand::createImm(getInlineImmVal32(Imm)); 1405 case OPW64: 1406 case OPW256: 1407 return MCOperand::createImm(getInlineImmVal64(Imm)); 1408 case OPW16: 1409 case OPWV216: 1410 return MCOperand::createImm(getInlineImmVal16(Imm)); 1411 default: 1412 llvm_unreachable("implement me"); 1413 } 1414 } 1415 1416 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1417 using namespace AMDGPU; 1418 1419 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1420 switch (Width) { 1421 default: // fall 1422 case OPW32: 1423 case OPW16: 1424 case OPWV216: 1425 return VGPR_32RegClassID; 1426 case OPW64: 1427 case OPWV232: return VReg_64RegClassID; 1428 case OPW96: return VReg_96RegClassID; 1429 case OPW128: return VReg_128RegClassID; 1430 case OPW160: return VReg_160RegClassID; 1431 case OPW256: return VReg_256RegClassID; 1432 case OPW512: return VReg_512RegClassID; 1433 case OPW1024: return VReg_1024RegClassID; 1434 } 1435 } 1436 1437 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1438 using namespace AMDGPU; 1439 1440 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1441 switch (Width) { 1442 default: // fall 1443 case OPW32: 1444 case OPW16: 1445 case OPWV216: 1446 return AGPR_32RegClassID; 1447 case OPW64: 1448 case OPWV232: return AReg_64RegClassID; 1449 case OPW96: return AReg_96RegClassID; 1450 case OPW128: return AReg_128RegClassID; 1451 case OPW160: return AReg_160RegClassID; 1452 case OPW256: return AReg_256RegClassID; 1453 case OPW512: return AReg_512RegClassID; 1454 case OPW1024: return AReg_1024RegClassID; 1455 } 1456 } 1457 1458 1459 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1460 using namespace AMDGPU; 1461 1462 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1463 switch (Width) { 1464 default: // fall 1465 case OPW32: 1466 case OPW16: 1467 case OPWV216: 1468 return SGPR_32RegClassID; 1469 case OPW64: 1470 case OPWV232: return SGPR_64RegClassID; 1471 case OPW96: return SGPR_96RegClassID; 1472 case OPW128: return SGPR_128RegClassID; 1473 case OPW160: return SGPR_160RegClassID; 1474 case OPW256: return SGPR_256RegClassID; 1475 case OPW512: return SGPR_512RegClassID; 1476 } 1477 } 1478 1479 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1480 using namespace AMDGPU; 1481 1482 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1483 switch (Width) { 1484 default: // fall 1485 case OPW32: 1486 case OPW16: 1487 case OPWV216: 1488 return TTMP_32RegClassID; 1489 case OPW64: 1490 case OPWV232: return TTMP_64RegClassID; 1491 case OPW128: return TTMP_128RegClassID; 1492 case OPW256: return TTMP_256RegClassID; 1493 case OPW512: return TTMP_512RegClassID; 1494 } 1495 } 1496 1497 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1498 using namespace AMDGPU::EncValues; 1499 1500 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1501 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1502 1503 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1504 } 1505 1506 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1507 bool MandatoryLiteral) const { 1508 using namespace AMDGPU::EncValues; 1509 1510 assert(Val < 1024); // enum10 1511 1512 bool IsAGPR = Val & 512; 1513 Val &= 511; 1514 1515 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1516 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1517 : getVgprClassId(Width), Val - VGPR_MIN); 1518 } 1519 if (Val <= SGPR_MAX) { 1520 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1521 static_assert(SGPR_MIN == 0); 1522 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1523 } 1524 1525 int TTmpIdx = getTTmpIdx(Val); 1526 if (TTmpIdx >= 0) { 1527 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1528 } 1529 1530 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1531 return decodeIntImmed(Val); 1532 1533 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1534 return decodeFPImmed(Width, Val); 1535 1536 if (Val == LITERAL_CONST) { 1537 if (MandatoryLiteral) 1538 // Keep a sentinel value for deferred setting 1539 return MCOperand::createImm(LITERAL_CONST); 1540 else 1541 return decodeLiteralConstant(); 1542 } 1543 1544 switch (Width) { 1545 case OPW32: 1546 case OPW16: 1547 case OPWV216: 1548 return decodeSpecialReg32(Val); 1549 case OPW64: 1550 case OPWV232: 1551 return decodeSpecialReg64(Val); 1552 default: 1553 llvm_unreachable("unexpected immediate type"); 1554 } 1555 } 1556 1557 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1558 using namespace AMDGPU::EncValues; 1559 1560 assert(Val < 128); 1561 assert(Width == OPW256 || Width == OPW512); 1562 1563 if (Val <= SGPR_MAX) { 1564 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1565 static_assert(SGPR_MIN == 0); 1566 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1567 } 1568 1569 int TTmpIdx = getTTmpIdx(Val); 1570 if (TTmpIdx >= 0) { 1571 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1572 } 1573 1574 llvm_unreachable("unknown dst register"); 1575 } 1576 1577 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1578 // opposite of bit 0 of DstX. 1579 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1580 unsigned Val) const { 1581 int VDstXInd = 1582 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1583 assert(VDstXInd != -1); 1584 assert(Inst.getOperand(VDstXInd).isReg()); 1585 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1586 Val |= ~XDstReg & 1; 1587 auto Width = llvm::AMDGPUDisassembler::OPW32; 1588 return createRegOperand(getVgprClassId(Width), Val); 1589 } 1590 1591 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1592 using namespace AMDGPU; 1593 1594 switch (Val) { 1595 case 102: return createRegOperand(FLAT_SCR_LO); 1596 case 103: return createRegOperand(FLAT_SCR_HI); 1597 case 104: return createRegOperand(XNACK_MASK_LO); 1598 case 105: return createRegOperand(XNACK_MASK_HI); 1599 case 106: return createRegOperand(VCC_LO); 1600 case 107: return createRegOperand(VCC_HI); 1601 case 108: return createRegOperand(TBA_LO); 1602 case 109: return createRegOperand(TBA_HI); 1603 case 110: return createRegOperand(TMA_LO); 1604 case 111: return createRegOperand(TMA_HI); 1605 case 124: 1606 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1607 case 125: 1608 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1609 case 126: return createRegOperand(EXEC_LO); 1610 case 127: return createRegOperand(EXEC_HI); 1611 case 235: return createRegOperand(SRC_SHARED_BASE); 1612 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1613 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1614 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1615 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1616 case 251: return createRegOperand(SRC_VCCZ); 1617 case 252: return createRegOperand(SRC_EXECZ); 1618 case 253: return createRegOperand(SRC_SCC); 1619 case 254: return createRegOperand(LDS_DIRECT); 1620 default: break; 1621 } 1622 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1623 } 1624 1625 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1626 using namespace AMDGPU; 1627 1628 switch (Val) { 1629 case 102: return createRegOperand(FLAT_SCR); 1630 case 104: return createRegOperand(XNACK_MASK); 1631 case 106: return createRegOperand(VCC); 1632 case 108: return createRegOperand(TBA); 1633 case 110: return createRegOperand(TMA); 1634 case 124: 1635 if (isGFX11Plus()) 1636 return createRegOperand(SGPR_NULL); 1637 break; 1638 case 125: 1639 if (!isGFX11Plus()) 1640 return createRegOperand(SGPR_NULL); 1641 break; 1642 case 126: return createRegOperand(EXEC); 1643 case 235: return createRegOperand(SRC_SHARED_BASE); 1644 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1645 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1646 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1647 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1648 case 251: return createRegOperand(SRC_VCCZ); 1649 case 252: return createRegOperand(SRC_EXECZ); 1650 case 253: return createRegOperand(SRC_SCC); 1651 default: break; 1652 } 1653 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1654 } 1655 1656 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1657 const unsigned Val) const { 1658 using namespace AMDGPU::SDWA; 1659 using namespace AMDGPU::EncValues; 1660 1661 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1662 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1663 // XXX: cast to int is needed to avoid stupid warning: 1664 // compare with unsigned is always true 1665 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1666 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1667 return createRegOperand(getVgprClassId(Width), 1668 Val - SDWA9EncValues::SRC_VGPR_MIN); 1669 } 1670 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1671 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1672 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1673 return createSRegOperand(getSgprClassId(Width), 1674 Val - SDWA9EncValues::SRC_SGPR_MIN); 1675 } 1676 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1677 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1678 return createSRegOperand(getTtmpClassId(Width), 1679 Val - SDWA9EncValues::SRC_TTMP_MIN); 1680 } 1681 1682 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1683 1684 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1685 return decodeIntImmed(SVal); 1686 1687 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1688 return decodeFPImmed(Width, SVal); 1689 1690 return decodeSpecialReg32(SVal); 1691 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1692 return createRegOperand(getVgprClassId(Width), Val); 1693 } 1694 llvm_unreachable("unsupported target"); 1695 } 1696 1697 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1698 return decodeSDWASrc(OPW16, Val); 1699 } 1700 1701 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1702 return decodeSDWASrc(OPW32, Val); 1703 } 1704 1705 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1706 using namespace AMDGPU::SDWA; 1707 1708 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1709 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1710 "SDWAVopcDst should be present only on GFX9+"); 1711 1712 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1713 1714 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1715 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1716 1717 int TTmpIdx = getTTmpIdx(Val); 1718 if (TTmpIdx >= 0) { 1719 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1720 return createSRegOperand(TTmpClsId, TTmpIdx); 1721 } else if (Val > SGPR_MAX) { 1722 return IsWave64 ? decodeSpecialReg64(Val) 1723 : decodeSpecialReg32(Val); 1724 } else { 1725 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1726 } 1727 } else { 1728 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1729 } 1730 } 1731 1732 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1733 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1734 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1735 } 1736 1737 bool AMDGPUDisassembler::isVI() const { 1738 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1739 } 1740 1741 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1742 1743 bool AMDGPUDisassembler::isGFX90A() const { 1744 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1745 } 1746 1747 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1748 1749 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1750 1751 bool AMDGPUDisassembler::isGFX10Plus() const { 1752 return AMDGPU::isGFX10Plus(STI); 1753 } 1754 1755 bool AMDGPUDisassembler::isGFX11() const { 1756 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1757 } 1758 1759 bool AMDGPUDisassembler::isGFX11Plus() const { 1760 return AMDGPU::isGFX11Plus(STI); 1761 } 1762 1763 1764 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1765 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1766 } 1767 1768 //===----------------------------------------------------------------------===// 1769 // AMDGPU specific symbol handling 1770 //===----------------------------------------------------------------------===// 1771 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1772 do { \ 1773 KdStream << Indent << DIRECTIVE " " \ 1774 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1775 } while (0) 1776 1777 // NOLINTNEXTLINE(readability-identifier-naming) 1778 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1779 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1780 using namespace amdhsa; 1781 StringRef Indent = "\t"; 1782 1783 // We cannot accurately backward compute #VGPRs used from 1784 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1785 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1786 // simply calculate the inverse of what the assembler does. 1787 1788 uint32_t GranulatedWorkitemVGPRCount = 1789 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1790 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1791 1792 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1793 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1794 1795 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1796 1797 // We cannot backward compute values used to calculate 1798 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1799 // directives can't be computed: 1800 // .amdhsa_reserve_vcc 1801 // .amdhsa_reserve_flat_scratch 1802 // .amdhsa_reserve_xnack_mask 1803 // They take their respective default values if not specified in the assembly. 1804 // 1805 // GRANULATED_WAVEFRONT_SGPR_COUNT 1806 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1807 // 1808 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1809 // are set to 0. So while disassembling we consider that: 1810 // 1811 // GRANULATED_WAVEFRONT_SGPR_COUNT 1812 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1813 // 1814 // The disassembler cannot recover the original values of those 3 directives. 1815 1816 uint32_t GranulatedWavefrontSGPRCount = 1817 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1818 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1819 1820 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1821 return MCDisassembler::Fail; 1822 1823 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1824 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1825 1826 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1827 if (!hasArchitectedFlatScratch()) 1828 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1829 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1830 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1831 1832 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1833 return MCDisassembler::Fail; 1834 1835 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1836 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1837 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1838 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1839 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1840 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1841 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1842 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1843 1844 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1845 return MCDisassembler::Fail; 1846 1847 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1848 1849 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1850 return MCDisassembler::Fail; 1851 1852 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1853 1854 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1855 return MCDisassembler::Fail; 1856 1857 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1858 return MCDisassembler::Fail; 1859 1860 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1861 1862 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1863 return MCDisassembler::Fail; 1864 1865 if (isGFX10Plus()) { 1866 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1867 COMPUTE_PGM_RSRC1_WGP_MODE); 1868 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1869 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1870 } 1871 return MCDisassembler::Success; 1872 } 1873 1874 // NOLINTNEXTLINE(readability-identifier-naming) 1875 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1876 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1877 using namespace amdhsa; 1878 StringRef Indent = "\t"; 1879 if (hasArchitectedFlatScratch()) 1880 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1881 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1882 else 1883 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1884 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1885 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1886 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1887 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1888 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1889 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1890 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1891 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1892 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1893 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1894 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1895 1896 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1897 return MCDisassembler::Fail; 1898 1899 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1900 return MCDisassembler::Fail; 1901 1902 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1903 return MCDisassembler::Fail; 1904 1905 PRINT_DIRECTIVE( 1906 ".amdhsa_exception_fp_ieee_invalid_op", 1907 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1908 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1909 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1910 PRINT_DIRECTIVE( 1911 ".amdhsa_exception_fp_ieee_div_zero", 1912 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1913 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1914 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1915 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1916 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1917 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1918 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1919 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1920 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1921 1922 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1923 return MCDisassembler::Fail; 1924 1925 return MCDisassembler::Success; 1926 } 1927 1928 #undef PRINT_DIRECTIVE 1929 1930 MCDisassembler::DecodeStatus 1931 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1932 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1933 raw_string_ostream &KdStream) const { 1934 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1935 do { \ 1936 KdStream << Indent << DIRECTIVE " " \ 1937 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1938 } while (0) 1939 1940 uint16_t TwoByteBuffer = 0; 1941 uint32_t FourByteBuffer = 0; 1942 1943 StringRef ReservedBytes; 1944 StringRef Indent = "\t"; 1945 1946 assert(Bytes.size() == 64); 1947 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1948 1949 switch (Cursor.tell()) { 1950 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1951 FourByteBuffer = DE.getU32(Cursor); 1952 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1953 << '\n'; 1954 return MCDisassembler::Success; 1955 1956 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1957 FourByteBuffer = DE.getU32(Cursor); 1958 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1959 << FourByteBuffer << '\n'; 1960 return MCDisassembler::Success; 1961 1962 case amdhsa::KERNARG_SIZE_OFFSET: 1963 FourByteBuffer = DE.getU32(Cursor); 1964 KdStream << Indent << ".amdhsa_kernarg_size " 1965 << FourByteBuffer << '\n'; 1966 return MCDisassembler::Success; 1967 1968 case amdhsa::RESERVED0_OFFSET: 1969 // 4 reserved bytes, must be 0. 1970 ReservedBytes = DE.getBytes(Cursor, 4); 1971 for (int I = 0; I < 4; ++I) { 1972 if (ReservedBytes[I] != 0) { 1973 return MCDisassembler::Fail; 1974 } 1975 } 1976 return MCDisassembler::Success; 1977 1978 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1979 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1980 // So far no directive controls this for Code Object V3, so simply skip for 1981 // disassembly. 1982 DE.skip(Cursor, 8); 1983 return MCDisassembler::Success; 1984 1985 case amdhsa::RESERVED1_OFFSET: 1986 // 20 reserved bytes, must be 0. 1987 ReservedBytes = DE.getBytes(Cursor, 20); 1988 for (int I = 0; I < 20; ++I) { 1989 if (ReservedBytes[I] != 0) { 1990 return MCDisassembler::Fail; 1991 } 1992 } 1993 return MCDisassembler::Success; 1994 1995 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1996 // COMPUTE_PGM_RSRC3 1997 // - Only set for GFX10, GFX6-9 have this to be 0. 1998 // - Currently no directives directly control this. 1999 FourByteBuffer = DE.getU32(Cursor); 2000 if (!isGFX10Plus() && FourByteBuffer) { 2001 return MCDisassembler::Fail; 2002 } 2003 return MCDisassembler::Success; 2004 2005 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2006 FourByteBuffer = DE.getU32(Cursor); 2007 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 2008 MCDisassembler::Fail) { 2009 return MCDisassembler::Fail; 2010 } 2011 return MCDisassembler::Success; 2012 2013 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2014 FourByteBuffer = DE.getU32(Cursor); 2015 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 2016 MCDisassembler::Fail) { 2017 return MCDisassembler::Fail; 2018 } 2019 return MCDisassembler::Success; 2020 2021 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2022 using namespace amdhsa; 2023 TwoByteBuffer = DE.getU16(Cursor); 2024 2025 if (!hasArchitectedFlatScratch()) 2026 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2027 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2028 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2029 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2030 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2031 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2032 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2033 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2034 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2035 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2036 if (!hasArchitectedFlatScratch()) 2037 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2038 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2039 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2040 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2041 2042 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2043 return MCDisassembler::Fail; 2044 2045 // Reserved for GFX9 2046 if (isGFX9() && 2047 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2048 return MCDisassembler::Fail; 2049 } else if (isGFX10Plus()) { 2050 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2051 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2052 } 2053 2054 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2055 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2056 2057 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2058 return MCDisassembler::Fail; 2059 2060 return MCDisassembler::Success; 2061 2062 case amdhsa::RESERVED2_OFFSET: 2063 // 6 bytes from here are reserved, must be 0. 2064 ReservedBytes = DE.getBytes(Cursor, 6); 2065 for (int I = 0; I < 6; ++I) { 2066 if (ReservedBytes[I] != 0) 2067 return MCDisassembler::Fail; 2068 } 2069 return MCDisassembler::Success; 2070 2071 default: 2072 llvm_unreachable("Unhandled index. Case statements cover everything."); 2073 return MCDisassembler::Fail; 2074 } 2075 #undef PRINT_DIRECTIVE 2076 } 2077 2078 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2079 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2080 // CP microcode requires the kernel descriptor to be 64 aligned. 2081 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2082 return MCDisassembler::Fail; 2083 2084 std::string Kd; 2085 raw_string_ostream KdStream(Kd); 2086 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2087 2088 DataExtractor::Cursor C(0); 2089 while (C && C.tell() < Bytes.size()) { 2090 MCDisassembler::DecodeStatus Status = 2091 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2092 2093 cantFail(C.takeError()); 2094 2095 if (Status == MCDisassembler::Fail) 2096 return MCDisassembler::Fail; 2097 } 2098 KdStream << ".end_amdhsa_kernel\n"; 2099 outs() << KdStream.str(); 2100 return MCDisassembler::Success; 2101 } 2102 2103 Optional<MCDisassembler::DecodeStatus> 2104 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2105 ArrayRef<uint8_t> Bytes, uint64_t Address, 2106 raw_ostream &CStream) const { 2107 // Right now only kernel descriptor needs to be handled. 2108 // We ignore all other symbols for target specific handling. 2109 // TODO: 2110 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2111 // Object V2 and V3 when symbols are marked protected. 2112 2113 // amd_kernel_code_t for Code Object V2. 2114 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2115 Size = 256; 2116 return MCDisassembler::Fail; 2117 } 2118 2119 // Code Object V3 kernel descriptors. 2120 StringRef Name = Symbol.Name; 2121 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2122 Size = 64; // Size = 64 regardless of success or failure. 2123 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2124 } 2125 return None; 2126 } 2127 2128 //===----------------------------------------------------------------------===// 2129 // AMDGPUSymbolizer 2130 //===----------------------------------------------------------------------===// 2131 2132 // Try to find symbol name for specified label 2133 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2134 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2135 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2136 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2137 2138 if (!IsBranch) { 2139 return false; 2140 } 2141 2142 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2143 if (!Symbols) 2144 return false; 2145 2146 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2147 return Val.Addr == static_cast<uint64_t>(Value) && 2148 Val.Type == ELF::STT_NOTYPE; 2149 }); 2150 if (Result != Symbols->end()) { 2151 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2152 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2153 Inst.addOperand(MCOperand::createExpr(Add)); 2154 return true; 2155 } 2156 // Add to list of referenced addresses, so caller can synthesize a label. 2157 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2158 return false; 2159 } 2160 2161 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2162 int64_t Value, 2163 uint64_t Address) { 2164 llvm_unreachable("unimplemented"); 2165 } 2166 2167 //===----------------------------------------------------------------------===// 2168 // Initialization 2169 //===----------------------------------------------------------------------===// 2170 2171 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2172 LLVMOpInfoCallback /*GetOpInfo*/, 2173 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2174 void *DisInfo, 2175 MCContext *Ctx, 2176 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2177 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2178 } 2179 2180 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2181 const MCSubtargetInfo &STI, 2182 MCContext &Ctx) { 2183 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2184 } 2185 2186 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2187 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2188 createAMDGPUDisassembler); 2189 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2190 createAMDGPUSymbolizer); 2191 } 2192