xref: /llvm-project/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (revision 528057c19755ad842052fba3a42dcbf7deafc6de)
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
19 #include "Disassembler/AMDGPUDisassembler.h"
20 #include "AMDGPU.h"
21 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
22 #include "SIDefines.h"
23 #include "TargetInfo/AMDGPUTargetInfo.h"
24 #include "Utils/AMDGPUBaseInfo.h"
25 #include "llvm-c/Disassembler.h"
26 #include "llvm/ADT/APInt.h"
27 #include "llvm/ADT/ArrayRef.h"
28 #include "llvm/ADT/Twine.h"
29 #include "llvm/BinaryFormat/ELF.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCContext.h"
32 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
33 #include "llvm/MC/MCExpr.h"
34 #include "llvm/MC/MCFixedLenDisassembler.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSubtargetInfo.h"
37 #include "llvm/Support/AMDHSAKernelDescriptor.h"
38 #include "llvm/Support/Endian.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include <algorithm>
44 #include <cassert>
45 #include <cstddef>
46 #include <cstdint>
47 #include <iterator>
48 #include <tuple>
49 #include <vector>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "amdgpu-disassembler"
54 
55 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
56                             : AMDGPU::EncValues::SGPR_MAX_SI)
57 
58 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
59 
60 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
61                                        MCContext &Ctx,
62                                        MCInstrInfo const *MCII) :
63   MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
64   TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
65 
66   // ToDo: AMDGPUDisassembler supports only VI ISA.
67   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
68     report_fatal_error("Disassembly not yet supported for subtarget");
69 }
70 
71 inline static MCDisassembler::DecodeStatus
72 addOperand(MCInst &Inst, const MCOperand& Opnd) {
73   Inst.addOperand(Opnd);
74   return Opnd.isValid() ?
75     MCDisassembler::Success :
76     MCDisassembler::Fail;
77 }
78 
79 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
80                                 uint16_t NameIdx) {
81   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
82   if (OpIdx != -1) {
83     auto I = MI.begin();
84     std::advance(I, OpIdx);
85     MI.insert(I, Op);
86   }
87   return OpIdx;
88 }
89 
90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
91                                        uint64_t Addr, const void *Decoder) {
92   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
93 
94   // Our branches take a simm16, but we need two extra bits to account for the
95   // factor of 4.
96   APInt SignedOffset(18, Imm * 4, true);
97   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
98 
99   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
100     return MCDisassembler::Success;
101   return addOperand(Inst, MCOperand::createImm(Imm));
102 }
103 
104 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm,
105                                      uint64_t Addr, const void *Decoder) {
106   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
107   int64_t Offset;
108   if (DAsm->isVI()) {         // VI supports 20-bit unsigned offsets.
109     Offset = Imm & 0xFFFFF;
110   } else {                    // GFX9+ supports 21-bit signed offsets.
111     Offset = SignExtend64<21>(Imm);
112   }
113   return addOperand(Inst, MCOperand::createImm(Offset));
114 }
115 
116 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
117                                   uint64_t Addr, const void *Decoder) {
118   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
119   return addOperand(Inst, DAsm->decodeBoolReg(Val));
120 }
121 
122 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
123 static DecodeStatus StaticDecoderName(MCInst &Inst, \
124                                        unsigned Imm, \
125                                        uint64_t /*Addr*/, \
126                                        const void *Decoder) { \
127   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
128   return addOperand(Inst, DAsm->DecoderName(Imm)); \
129 }
130 
131 #define DECODE_OPERAND_REG(RegClass) \
132 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
133 
134 DECODE_OPERAND_REG(VGPR_32)
135 DECODE_OPERAND_REG(VRegOrLds_32)
136 DECODE_OPERAND_REG(VS_32)
137 DECODE_OPERAND_REG(VS_64)
138 DECODE_OPERAND_REG(VS_128)
139 
140 DECODE_OPERAND_REG(VReg_64)
141 DECODE_OPERAND_REG(VReg_96)
142 DECODE_OPERAND_REG(VReg_128)
143 DECODE_OPERAND_REG(VReg_256)
144 DECODE_OPERAND_REG(VReg_512)
145 
146 DECODE_OPERAND_REG(SReg_32)
147 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
148 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
149 DECODE_OPERAND_REG(SRegOrLds_32)
150 DECODE_OPERAND_REG(SReg_64)
151 DECODE_OPERAND_REG(SReg_64_XEXEC)
152 DECODE_OPERAND_REG(SReg_128)
153 DECODE_OPERAND_REG(SReg_256)
154 DECODE_OPERAND_REG(SReg_512)
155 
156 DECODE_OPERAND_REG(AGPR_32)
157 DECODE_OPERAND_REG(AReg_128)
158 DECODE_OPERAND_REG(AReg_512)
159 DECODE_OPERAND_REG(AReg_1024)
160 DECODE_OPERAND_REG(AV_32)
161 DECODE_OPERAND_REG(AV_64)
162 
163 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
164                                          unsigned Imm,
165                                          uint64_t Addr,
166                                          const void *Decoder) {
167   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
168   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
169 }
170 
171 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
172                                          unsigned Imm,
173                                          uint64_t Addr,
174                                          const void *Decoder) {
175   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
176   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
177 }
178 
179 static DecodeStatus decodeOperand_VS_16(MCInst &Inst,
180                                         unsigned Imm,
181                                         uint64_t Addr,
182                                         const void *Decoder) {
183   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
184   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
185 }
186 
187 static DecodeStatus decodeOperand_VS_32(MCInst &Inst,
188                                         unsigned Imm,
189                                         uint64_t Addr,
190                                         const void *Decoder) {
191   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
192   return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm));
193 }
194 
195 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst,
196                                            unsigned Imm,
197                                            uint64_t Addr,
198                                            const void *Decoder) {
199   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
200   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512));
201 }
202 
203 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst,
204                                            unsigned Imm,
205                                            uint64_t Addr,
206                                            const void *Decoder) {
207   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
208   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512));
209 }
210 
211 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst,
212                                             unsigned Imm,
213                                             uint64_t Addr,
214                                             const void *Decoder) {
215   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
216   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512));
217 }
218 
219 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst,
220                                           unsigned Imm,
221                                           uint64_t Addr,
222                                           const void *Decoder) {
223   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
224   return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm));
225 }
226 
227 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst,
228                                          unsigned Imm,
229                                          uint64_t Addr,
230                                          const void *Decoder) {
231   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
232   return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm));
233 }
234 
235 #define DECODE_SDWA(DecName) \
236 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
237 
238 DECODE_SDWA(Src32)
239 DECODE_SDWA(Src16)
240 DECODE_SDWA(VopcDst)
241 
242 #include "AMDGPUGenDisassemblerTables.inc"
243 
244 //===----------------------------------------------------------------------===//
245 //
246 //===----------------------------------------------------------------------===//
247 
248 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
249   assert(Bytes.size() >= sizeof(T));
250   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
251   Bytes = Bytes.slice(sizeof(T));
252   return Res;
253 }
254 
255 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
256                                                MCInst &MI,
257                                                uint64_t Inst,
258                                                uint64_t Address) const {
259   assert(MI.getOpcode() == 0);
260   assert(MI.getNumOperands() == 0);
261   MCInst TmpInst;
262   HasLiteral = false;
263   const auto SavedBytes = Bytes;
264   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
265     MI = TmpInst;
266     return MCDisassembler::Success;
267   }
268   Bytes = SavedBytes;
269   return MCDisassembler::Fail;
270 }
271 
272 static bool isValidDPP8(const MCInst &MI) {
273   using namespace llvm::AMDGPU::DPP;
274   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
275   assert(FiIdx != -1);
276   if ((unsigned)FiIdx >= MI.getNumOperands())
277     return false;
278   unsigned Fi = MI.getOperand(FiIdx).getImm();
279   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
280 }
281 
282 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
283                                                 ArrayRef<uint8_t> Bytes_,
284                                                 uint64_t Address,
285                                                 raw_ostream &CS) const {
286   CommentStream = &CS;
287   bool IsSDWA = false;
288 
289   unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
290   Bytes = Bytes_.slice(0, MaxInstBytesNum);
291 
292   DecodeStatus Res = MCDisassembler::Fail;
293   do {
294     // ToDo: better to switch encoding length using some bit predicate
295     // but it is unknown yet, so try all we can
296 
297     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
298     // encodings
299     if (Bytes.size() >= 8) {
300       const uint64_t QW = eatBytes<uint64_t>(Bytes);
301 
302       if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
303         Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address);
304         if (Res) {
305           if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8)
306               == -1)
307             break;
308           if (convertDPP8Inst(MI) == MCDisassembler::Success)
309             break;
310           MI = MCInst(); // clear
311         }
312       }
313 
314       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
315       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
316         break;
317 
318       MI = MCInst(); // clear
319 
320       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
321       if (Res) break;
322 
323       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
324       if (Res) { IsSDWA = true;  break; }
325 
326       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
327       if (Res) { IsSDWA = true;  break; }
328 
329       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
330       if (Res) { IsSDWA = true;  break; }
331 
332       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
333         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
334         if (Res)
335           break;
336       }
337 
338       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
339       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
340       // table first so we print the correct name.
341       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
342         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
343         if (Res)
344           break;
345       }
346     }
347 
348     // Reinitialize Bytes as DPP64 could have eaten too much
349     Bytes = Bytes_.slice(0, MaxInstBytesNum);
350 
351     // Try decode 32-bit instruction
352     if (Bytes.size() < 4) break;
353     const uint32_t DW = eatBytes<uint32_t>(Bytes);
354     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
355     if (Res) break;
356 
357     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
358     if (Res) break;
359 
360     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
361     if (Res) break;
362 
363     if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) {
364       Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address);
365       if (Res) break;
366     }
367 
368     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
369     if (Res) break;
370 
371     if (Bytes.size() < 4) break;
372     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
373     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
374     if (Res) break;
375 
376     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
377     if (Res) break;
378 
379     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
380     if (Res) break;
381 
382     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
383   } while (false);
384 
385   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
386               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
387               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
388               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
389               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
390               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
391               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
392     // Insert dummy unused src2_modifiers.
393     insertNamedMCOperand(MI, MCOperand::createImm(0),
394                          AMDGPU::OpName::src2_modifiers);
395   }
396 
397   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
398     int VAddr0Idx =
399         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
400     int RsrcIdx =
401         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
402     unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
403     if (VAddr0Idx >= 0 && NSAArgs > 0) {
404       unsigned NSAWords = (NSAArgs + 3) / 4;
405       if (Bytes.size() < 4 * NSAWords) {
406         Res = MCDisassembler::Fail;
407       } else {
408         for (unsigned i = 0; i < NSAArgs; ++i) {
409           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
410                     decodeOperand_VGPR_32(Bytes[i]));
411         }
412         Bytes = Bytes.slice(4 * NSAWords);
413       }
414     }
415 
416     if (Res)
417       Res = convertMIMGInst(MI);
418   }
419 
420   if (Res && IsSDWA)
421     Res = convertSDWAInst(MI);
422 
423   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
424                                               AMDGPU::OpName::vdst_in);
425   if (VDstIn_Idx != -1) {
426     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
427                            MCOI::OperandConstraint::TIED_TO);
428     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
429          !MI.getOperand(VDstIn_Idx).isReg() ||
430          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
431       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
432         MI.erase(&MI.getOperand(VDstIn_Idx));
433       insertNamedMCOperand(MI,
434         MCOperand::createReg(MI.getOperand(Tied).getReg()),
435         AMDGPU::OpName::vdst_in);
436     }
437   }
438 
439   // if the opcode was not recognized we'll assume a Size of 4 bytes
440   // (unless there are fewer bytes left)
441   Size = Res ? (MaxInstBytesNum - Bytes.size())
442              : std::min((size_t)4, Bytes_.size());
443   return Res;
444 }
445 
446 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
447   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
448       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
449     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
450       // VOPC - insert clamp
451       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
452   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
453     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
454     if (SDst != -1) {
455       // VOPC - insert VCC register as sdst
456       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
457                            AMDGPU::OpName::sdst);
458     } else {
459       // VOP1/2 - insert omod if present in instruction
460       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
461     }
462   }
463   return MCDisassembler::Success;
464 }
465 
466 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
467   unsigned Opc = MI.getOpcode();
468   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
469 
470   // Insert dummy unused src modifiers.
471   if (MI.getNumOperands() < DescNumOps &&
472       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
473     insertNamedMCOperand(MI, MCOperand::createImm(0),
474                          AMDGPU::OpName::src0_modifiers);
475 
476   if (MI.getNumOperands() < DescNumOps &&
477       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
478     insertNamedMCOperand(MI, MCOperand::createImm(0),
479                          AMDGPU::OpName::src1_modifiers);
480 
481   return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail;
482 }
483 
484 // Note that before gfx10, the MIMG encoding provided no information about
485 // VADDR size. Consequently, decoded instructions always show address as if it
486 // has 1 dword, which could be not really so.
487 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
488 
489   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
490                                            AMDGPU::OpName::vdst);
491 
492   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
493                                             AMDGPU::OpName::vdata);
494   int VAddr0Idx =
495       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
496   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
497                                             AMDGPU::OpName::dmask);
498 
499   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
500                                             AMDGPU::OpName::tfe);
501   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
502                                             AMDGPU::OpName::d16);
503 
504   assert(VDataIdx != -1);
505   if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray
506     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) {
507       assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa ||
508              MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa ||
509              MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa ||
510              MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa);
511       addOperand(MI, MCOperand::createImm(1));
512     }
513     return MCDisassembler::Success;
514   }
515 
516   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
517   bool IsAtomic = (VDstIdx != -1);
518   bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
519 
520   bool IsNSA = false;
521   unsigned AddrSize = Info->VAddrDwords;
522 
523   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
524     unsigned DimIdx =
525         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
526     const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
527         AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
528     const AMDGPU::MIMGDimInfo *Dim =
529         AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
530 
531     AddrSize = BaseOpcode->NumExtraArgs +
532                (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
533                (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
534                (BaseOpcode->LodOrClampOrMip ? 1 : 0);
535     IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
536     if (!IsNSA) {
537       if (AddrSize > 8)
538         AddrSize = 16;
539       else if (AddrSize > 4)
540         AddrSize = 8;
541     } else {
542       if (AddrSize > Info->VAddrDwords) {
543         // The NSA encoding does not contain enough operands for the combination
544         // of base opcode / dimension. Should this be an error?
545         return MCDisassembler::Success;
546       }
547     }
548   }
549 
550   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
551   unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
552 
553   bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
554   if (D16 && AMDGPU::hasPackedD16(STI)) {
555     DstSize = (DstSize + 1) / 2;
556   }
557 
558   // FIXME: Add tfe support
559   if (MI.getOperand(TFEIdx).getImm())
560     return MCDisassembler::Success;
561 
562   if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
563     return MCDisassembler::Success;
564 
565   int NewOpcode =
566       AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
567   if (NewOpcode == -1)
568     return MCDisassembler::Success;
569 
570   // Widen the register to the correct number of enabled channels.
571   unsigned NewVdata = AMDGPU::NoRegister;
572   if (DstSize != Info->VDataDwords) {
573     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
574 
575     // Get first subregister of VData
576     unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
577     unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
578     Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
579 
580     NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
581                                        &MRI.getRegClass(DataRCID));
582     if (NewVdata == AMDGPU::NoRegister) {
583       // It's possible to encode this such that the low register + enabled
584       // components exceeds the register count.
585       return MCDisassembler::Success;
586     }
587   }
588 
589   unsigned NewVAddr0 = AMDGPU::NoRegister;
590   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
591       AddrSize != Info->VAddrDwords) {
592     unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
593     unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
594     VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
595 
596     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
597     NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
598                                         &MRI.getRegClass(AddrRCID));
599     if (NewVAddr0 == AMDGPU::NoRegister)
600       return MCDisassembler::Success;
601   }
602 
603   MI.setOpcode(NewOpcode);
604 
605   if (NewVdata != AMDGPU::NoRegister) {
606     MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
607 
608     if (IsAtomic) {
609       // Atomic operations have an additional operand (a copy of data)
610       MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
611     }
612   }
613 
614   if (NewVAddr0 != AMDGPU::NoRegister) {
615     MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
616   } else if (IsNSA) {
617     assert(AddrSize <= Info->VAddrDwords);
618     MI.erase(MI.begin() + VAddr0Idx + AddrSize,
619              MI.begin() + VAddr0Idx + Info->VAddrDwords);
620   }
621 
622   return MCDisassembler::Success;
623 }
624 
625 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
626   return getContext().getRegisterInfo()->
627     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
628 }
629 
630 inline
631 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
632                                          const Twine& ErrMsg) const {
633   *CommentStream << "Error: " + ErrMsg;
634 
635   // ToDo: add support for error operands to MCInst.h
636   // return MCOperand::createError(V);
637   return MCOperand();
638 }
639 
640 inline
641 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
642   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
643 }
644 
645 inline
646 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
647                                                unsigned Val) const {
648   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
649   if (Val >= RegCl.getNumRegs())
650     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
651                            ": unknown register " + Twine(Val));
652   return createRegOperand(RegCl.getRegister(Val));
653 }
654 
655 inline
656 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
657                                                 unsigned Val) const {
658   // ToDo: SI/CI have 104 SGPRs, VI - 102
659   // Valery: here we accepting as much as we can, let assembler sort it out
660   int shift = 0;
661   switch (SRegClassID) {
662   case AMDGPU::SGPR_32RegClassID:
663   case AMDGPU::TTMP_32RegClassID:
664     break;
665   case AMDGPU::SGPR_64RegClassID:
666   case AMDGPU::TTMP_64RegClassID:
667     shift = 1;
668     break;
669   case AMDGPU::SGPR_128RegClassID:
670   case AMDGPU::TTMP_128RegClassID:
671   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
672   // this bundle?
673   case AMDGPU::SGPR_256RegClassID:
674   case AMDGPU::TTMP_256RegClassID:
675     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
676   // this bundle?
677   case AMDGPU::SGPR_512RegClassID:
678   case AMDGPU::TTMP_512RegClassID:
679     shift = 2;
680     break;
681   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
682   // this bundle?
683   default:
684     llvm_unreachable("unhandled register class");
685   }
686 
687   if (Val % (1 << shift)) {
688     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
689                    << ": scalar reg isn't aligned " << Val;
690   }
691 
692   return createRegOperand(SRegClassID, Val >> shift);
693 }
694 
695 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
696   return decodeSrcOp(OPW32, Val);
697 }
698 
699 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
700   return decodeSrcOp(OPW64, Val);
701 }
702 
703 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
704   return decodeSrcOp(OPW128, Val);
705 }
706 
707 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
708   return decodeSrcOp(OPW16, Val);
709 }
710 
711 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
712   return decodeSrcOp(OPWV216, Val);
713 }
714 
715 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
716   // Some instructions have operand restrictions beyond what the encoding
717   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
718   // high bit.
719   Val &= 255;
720 
721   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
722 }
723 
724 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
725   return decodeSrcOp(OPW32, Val);
726 }
727 
728 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const {
729   return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255);
730 }
731 
732 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const {
733   return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255);
734 }
735 
736 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const {
737   return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255);
738 }
739 
740 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const {
741   return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255);
742 }
743 
744 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const {
745   return decodeSrcOp(OPW32, Val);
746 }
747 
748 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const {
749   return decodeSrcOp(OPW64, Val);
750 }
751 
752 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
753   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
754 }
755 
756 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
757   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
758 }
759 
760 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
761   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
762 }
763 
764 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const {
765   return createRegOperand(AMDGPU::VReg_256RegClassID, Val);
766 }
767 
768 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const {
769   return createRegOperand(AMDGPU::VReg_512RegClassID, Val);
770 }
771 
772 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
773   // table-gen generated disassembler doesn't care about operand types
774   // leaving only registry class so SSrc_32 operand turns into SReg_32
775   // and therefore we accept immediates and literals here as well
776   return decodeSrcOp(OPW32, Val);
777 }
778 
779 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
780   unsigned Val) const {
781   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
782   return decodeOperand_SReg_32(Val);
783 }
784 
785 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
786   unsigned Val) const {
787   // SReg_32_XM0 is SReg_32 without EXEC_HI
788   return decodeOperand_SReg_32(Val);
789 }
790 
791 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
792   // table-gen generated disassembler doesn't care about operand types
793   // leaving only registry class so SSrc_32 operand turns into SReg_32
794   // and therefore we accept immediates and literals here as well
795   return decodeSrcOp(OPW32, Val);
796 }
797 
798 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
799   return decodeSrcOp(OPW64, Val);
800 }
801 
802 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
803   return decodeSrcOp(OPW64, Val);
804 }
805 
806 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
807   return decodeSrcOp(OPW128, Val);
808 }
809 
810 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
811   return decodeDstOp(OPW256, Val);
812 }
813 
814 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
815   return decodeDstOp(OPW512, Val);
816 }
817 
818 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
819   // For now all literal constants are supposed to be unsigned integer
820   // ToDo: deal with signed/unsigned 64-bit integer constants
821   // ToDo: deal with float/double constants
822   if (!HasLiteral) {
823     if (Bytes.size() < 4) {
824       return errOperand(0, "cannot read literal, inst bytes left " +
825                         Twine(Bytes.size()));
826     }
827     HasLiteral = true;
828     Literal = eatBytes<uint32_t>(Bytes);
829   }
830   return MCOperand::createImm(Literal);
831 }
832 
833 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
834   using namespace AMDGPU::EncValues;
835 
836   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
837   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
838     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
839     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
840       // Cast prevents negative overflow.
841 }
842 
843 static int64_t getInlineImmVal32(unsigned Imm) {
844   switch (Imm) {
845   case 240:
846     return FloatToBits(0.5f);
847   case 241:
848     return FloatToBits(-0.5f);
849   case 242:
850     return FloatToBits(1.0f);
851   case 243:
852     return FloatToBits(-1.0f);
853   case 244:
854     return FloatToBits(2.0f);
855   case 245:
856     return FloatToBits(-2.0f);
857   case 246:
858     return FloatToBits(4.0f);
859   case 247:
860     return FloatToBits(-4.0f);
861   case 248: // 1 / (2 * PI)
862     return 0x3e22f983;
863   default:
864     llvm_unreachable("invalid fp inline imm");
865   }
866 }
867 
868 static int64_t getInlineImmVal64(unsigned Imm) {
869   switch (Imm) {
870   case 240:
871     return DoubleToBits(0.5);
872   case 241:
873     return DoubleToBits(-0.5);
874   case 242:
875     return DoubleToBits(1.0);
876   case 243:
877     return DoubleToBits(-1.0);
878   case 244:
879     return DoubleToBits(2.0);
880   case 245:
881     return DoubleToBits(-2.0);
882   case 246:
883     return DoubleToBits(4.0);
884   case 247:
885     return DoubleToBits(-4.0);
886   case 248: // 1 / (2 * PI)
887     return 0x3fc45f306dc9c882;
888   default:
889     llvm_unreachable("invalid fp inline imm");
890   }
891 }
892 
893 static int64_t getInlineImmVal16(unsigned Imm) {
894   switch (Imm) {
895   case 240:
896     return 0x3800;
897   case 241:
898     return 0xB800;
899   case 242:
900     return 0x3C00;
901   case 243:
902     return 0xBC00;
903   case 244:
904     return 0x4000;
905   case 245:
906     return 0xC000;
907   case 246:
908     return 0x4400;
909   case 247:
910     return 0xC400;
911   case 248: // 1 / (2 * PI)
912     return 0x3118;
913   default:
914     llvm_unreachable("invalid fp inline imm");
915   }
916 }
917 
918 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
919   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
920       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
921 
922   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
923   switch (Width) {
924   case OPW32:
925   case OPW128: // splat constants
926   case OPW512:
927   case OPW1024:
928     return MCOperand::createImm(getInlineImmVal32(Imm));
929   case OPW64:
930     return MCOperand::createImm(getInlineImmVal64(Imm));
931   case OPW16:
932   case OPWV216:
933     return MCOperand::createImm(getInlineImmVal16(Imm));
934   default:
935     llvm_unreachable("implement me");
936   }
937 }
938 
939 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
940   using namespace AMDGPU;
941 
942   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
943   switch (Width) {
944   default: // fall
945   case OPW32:
946   case OPW16:
947   case OPWV216:
948     return VGPR_32RegClassID;
949   case OPW64: return VReg_64RegClassID;
950   case OPW128: return VReg_128RegClassID;
951   }
952 }
953 
954 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const {
955   using namespace AMDGPU;
956 
957   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
958   switch (Width) {
959   default: // fall
960   case OPW32:
961   case OPW16:
962   case OPWV216:
963     return AGPR_32RegClassID;
964   case OPW64: return AReg_64RegClassID;
965   case OPW128: return AReg_128RegClassID;
966   case OPW256: return AReg_256RegClassID;
967   case OPW512: return AReg_512RegClassID;
968   case OPW1024: return AReg_1024RegClassID;
969   }
970 }
971 
972 
973 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
974   using namespace AMDGPU;
975 
976   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
977   switch (Width) {
978   default: // fall
979   case OPW32:
980   case OPW16:
981   case OPWV216:
982     return SGPR_32RegClassID;
983   case OPW64: return SGPR_64RegClassID;
984   case OPW128: return SGPR_128RegClassID;
985   case OPW256: return SGPR_256RegClassID;
986   case OPW512: return SGPR_512RegClassID;
987   }
988 }
989 
990 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
991   using namespace AMDGPU;
992 
993   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
994   switch (Width) {
995   default: // fall
996   case OPW32:
997   case OPW16:
998   case OPWV216:
999     return TTMP_32RegClassID;
1000   case OPW64: return TTMP_64RegClassID;
1001   case OPW128: return TTMP_128RegClassID;
1002   case OPW256: return TTMP_256RegClassID;
1003   case OPW512: return TTMP_512RegClassID;
1004   }
1005 }
1006 
1007 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
1008   using namespace AMDGPU::EncValues;
1009 
1010   unsigned TTmpMin =
1011       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
1012   unsigned TTmpMax =
1013       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
1014 
1015   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
1016 }
1017 
1018 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
1019   using namespace AMDGPU::EncValues;
1020 
1021   assert(Val < 1024); // enum10
1022 
1023   bool IsAGPR = Val & 512;
1024   Val &= 511;
1025 
1026   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
1027     return createRegOperand(IsAGPR ? getAgprClassId(Width)
1028                                    : getVgprClassId(Width), Val - VGPR_MIN);
1029   }
1030   if (Val <= SGPR_MAX) {
1031     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1032     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1033   }
1034 
1035   int TTmpIdx = getTTmpIdx(Val);
1036   if (TTmpIdx >= 0) {
1037     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1038   }
1039 
1040   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
1041     return decodeIntImmed(Val);
1042 
1043   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
1044     return decodeFPImmed(Width, Val);
1045 
1046   if (Val == LITERAL_CONST)
1047     return decodeLiteralConstant();
1048 
1049   switch (Width) {
1050   case OPW32:
1051   case OPW16:
1052   case OPWV216:
1053     return decodeSpecialReg32(Val);
1054   case OPW64:
1055     return decodeSpecialReg64(Val);
1056   default:
1057     llvm_unreachable("unexpected immediate type");
1058   }
1059 }
1060 
1061 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
1062   using namespace AMDGPU::EncValues;
1063 
1064   assert(Val < 128);
1065   assert(Width == OPW256 || Width == OPW512);
1066 
1067   if (Val <= SGPR_MAX) {
1068     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
1069     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
1070   }
1071 
1072   int TTmpIdx = getTTmpIdx(Val);
1073   if (TTmpIdx >= 0) {
1074     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
1075   }
1076 
1077   llvm_unreachable("unknown dst register");
1078 }
1079 
1080 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
1081   using namespace AMDGPU;
1082 
1083   switch (Val) {
1084   case 102: return createRegOperand(FLAT_SCR_LO);
1085   case 103: return createRegOperand(FLAT_SCR_HI);
1086   case 104: return createRegOperand(XNACK_MASK_LO);
1087   case 105: return createRegOperand(XNACK_MASK_HI);
1088   case 106: return createRegOperand(VCC_LO);
1089   case 107: return createRegOperand(VCC_HI);
1090   case 108: return createRegOperand(TBA_LO);
1091   case 109: return createRegOperand(TBA_HI);
1092   case 110: return createRegOperand(TMA_LO);
1093   case 111: return createRegOperand(TMA_HI);
1094   case 124: return createRegOperand(M0);
1095   case 125: return createRegOperand(SGPR_NULL);
1096   case 126: return createRegOperand(EXEC_LO);
1097   case 127: return createRegOperand(EXEC_HI);
1098   case 235: return createRegOperand(SRC_SHARED_BASE);
1099   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1100   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1101   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1102   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1103   case 251: return createRegOperand(SRC_VCCZ);
1104   case 252: return createRegOperand(SRC_EXECZ);
1105   case 253: return createRegOperand(SRC_SCC);
1106   case 254: return createRegOperand(LDS_DIRECT);
1107   default: break;
1108   }
1109   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1110 }
1111 
1112 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
1113   using namespace AMDGPU;
1114 
1115   switch (Val) {
1116   case 102: return createRegOperand(FLAT_SCR);
1117   case 104: return createRegOperand(XNACK_MASK);
1118   case 106: return createRegOperand(VCC);
1119   case 108: return createRegOperand(TBA);
1120   case 110: return createRegOperand(TMA);
1121   case 125: return createRegOperand(SGPR_NULL);
1122   case 126: return createRegOperand(EXEC);
1123   case 235: return createRegOperand(SRC_SHARED_BASE);
1124   case 236: return createRegOperand(SRC_SHARED_LIMIT);
1125   case 237: return createRegOperand(SRC_PRIVATE_BASE);
1126   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
1127   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
1128   case 251: return createRegOperand(SRC_VCCZ);
1129   case 252: return createRegOperand(SRC_EXECZ);
1130   case 253: return createRegOperand(SRC_SCC);
1131   default: break;
1132   }
1133   return errOperand(Val, "unknown operand encoding " + Twine(Val));
1134 }
1135 
1136 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
1137                                             const unsigned Val) const {
1138   using namespace AMDGPU::SDWA;
1139   using namespace AMDGPU::EncValues;
1140 
1141   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1142       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1143     // XXX: cast to int is needed to avoid stupid warning:
1144     // compare with unsigned is always true
1145     if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1146         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1147       return createRegOperand(getVgprClassId(Width),
1148                               Val - SDWA9EncValues::SRC_VGPR_MIN);
1149     }
1150     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1151         Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1152                           : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1153       return createSRegOperand(getSgprClassId(Width),
1154                                Val - SDWA9EncValues::SRC_SGPR_MIN);
1155     }
1156     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1157         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1158       return createSRegOperand(getTtmpClassId(Width),
1159                                Val - SDWA9EncValues::SRC_TTMP_MIN);
1160     }
1161 
1162     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1163 
1164     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1165       return decodeIntImmed(SVal);
1166 
1167     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1168       return decodeFPImmed(Width, SVal);
1169 
1170     return decodeSpecialReg32(SVal);
1171   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1172     return createRegOperand(getVgprClassId(Width), Val);
1173   }
1174   llvm_unreachable("unsupported target");
1175 }
1176 
1177 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1178   return decodeSDWASrc(OPW16, Val);
1179 }
1180 
1181 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1182   return decodeSDWASrc(OPW32, Val);
1183 }
1184 
1185 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1186   using namespace AMDGPU::SDWA;
1187 
1188   assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1189           STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1190          "SDWAVopcDst should be present only on GFX9+");
1191 
1192   bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1193 
1194   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1195     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1196 
1197     int TTmpIdx = getTTmpIdx(Val);
1198     if (TTmpIdx >= 0) {
1199       auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32);
1200       return createSRegOperand(TTmpClsId, TTmpIdx);
1201     } else if (Val > SGPR_MAX) {
1202       return IsWave64 ? decodeSpecialReg64(Val)
1203                       : decodeSpecialReg32(Val);
1204     } else {
1205       return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1206     }
1207   } else {
1208     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1209   }
1210 }
1211 
1212 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1213   return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1214     decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
1215 }
1216 
1217 bool AMDGPUDisassembler::isVI() const {
1218   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1219 }
1220 
1221 bool AMDGPUDisassembler::isGFX9() const {
1222   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1223 }
1224 
1225 bool AMDGPUDisassembler::isGFX10() const {
1226   return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1227 }
1228 
1229 //===----------------------------------------------------------------------===//
1230 // AMDGPU specific symbol handling
1231 //===----------------------------------------------------------------------===//
1232 #define PRINT_DIRECTIVE(DIRECTIVE, MASK)                                       \
1233   do {                                                                         \
1234     KdStream << Indent << DIRECTIVE " "                                        \
1235              << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n';           \
1236   } while (0)
1237 
1238 // NOLINTNEXTLINE(readability-identifier-naming)
1239 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(
1240     uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1241   using namespace amdhsa;
1242   StringRef Indent = "\t";
1243 
1244   // We cannot accurately backward compute #VGPRs used from
1245   // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same
1246   // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we
1247   // simply calculate the inverse of what the assembler does.
1248 
1249   uint32_t GranulatedWorkitemVGPRCount =
1250       (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >>
1251       COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT;
1252 
1253   uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) *
1254                           AMDGPU::IsaInfo::getVGPREncodingGranule(&STI);
1255 
1256   KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n';
1257 
1258   // We cannot backward compute values used to calculate
1259   // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following
1260   // directives can't be computed:
1261   // .amdhsa_reserve_vcc
1262   // .amdhsa_reserve_flat_scratch
1263   // .amdhsa_reserve_xnack_mask
1264   // They take their respective default values if not specified in the assembly.
1265   //
1266   // GRANULATED_WAVEFRONT_SGPR_COUNT
1267   //    = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK)
1268   //
1269   // We compute the inverse as though all directives apart from NEXT_FREE_SGPR
1270   // are set to 0. So while disassembling we consider that:
1271   //
1272   // GRANULATED_WAVEFRONT_SGPR_COUNT
1273   //    = f(NEXT_FREE_SGPR + 0 + 0 + 0)
1274   //
1275   // The disassembler cannot recover the original values of those 3 directives.
1276 
1277   uint32_t GranulatedWavefrontSGPRCount =
1278       (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >>
1279       COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT;
1280 
1281   if (isGFX10() && GranulatedWavefrontSGPRCount)
1282     return MCDisassembler::Fail;
1283 
1284   uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
1285                           AMDGPU::IsaInfo::getSGPREncodingGranule(&STI);
1286 
1287   KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n';
1288   KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n';
1289   KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n';
1290   KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n";
1291 
1292   if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY)
1293     return MCDisassembler::Fail;
1294 
1295   PRINT_DIRECTIVE(".amdhsa_float_round_mode_32",
1296                   COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
1297   PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64",
1298                   COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
1299   PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32",
1300                   COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
1301   PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64",
1302                   COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
1303 
1304   if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV)
1305     return MCDisassembler::Fail;
1306 
1307   PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
1308 
1309   if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE)
1310     return MCDisassembler::Fail;
1311 
1312   PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
1313 
1314   if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY)
1315     return MCDisassembler::Fail;
1316 
1317   if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER)
1318     return MCDisassembler::Fail;
1319 
1320   PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL);
1321 
1322   if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
1323     return MCDisassembler::Fail;
1324 
1325   if (isGFX10()) {
1326     PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode",
1327                     COMPUTE_PGM_RSRC1_WGP_MODE);
1328     PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
1329     PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS);
1330   }
1331   return MCDisassembler::Success;
1332 }
1333 
1334 // NOLINTNEXTLINE(readability-identifier-naming)
1335 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2(
1336     uint32_t FourByteBuffer, raw_string_ostream &KdStream) const {
1337   using namespace amdhsa;
1338   StringRef Indent = "\t";
1339   PRINT_DIRECTIVE(
1340       ".amdhsa_system_sgpr_private_segment_wavefront_offset",
1341       COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET);
1342   PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x",
1343                   COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
1344   PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y",
1345                   COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
1346   PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z",
1347                   COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
1348   PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info",
1349                   COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
1350   PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id",
1351                   COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
1352 
1353   if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH)
1354     return MCDisassembler::Fail;
1355 
1356   if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY)
1357     return MCDisassembler::Fail;
1358 
1359   if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE)
1360     return MCDisassembler::Fail;
1361 
1362   PRINT_DIRECTIVE(
1363       ".amdhsa_exception_fp_ieee_invalid_op",
1364       COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
1365   PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src",
1366                   COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
1367   PRINT_DIRECTIVE(
1368       ".amdhsa_exception_fp_ieee_div_zero",
1369       COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
1370   PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow",
1371                   COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
1372   PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow",
1373                   COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
1374   PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact",
1375                   COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
1376   PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero",
1377                   COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
1378 
1379   if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0)
1380     return MCDisassembler::Fail;
1381 
1382   return MCDisassembler::Success;
1383 }
1384 
1385 #undef PRINT_DIRECTIVE
1386 
1387 MCDisassembler::DecodeStatus
1388 AMDGPUDisassembler::decodeKernelDescriptorDirective(
1389     DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes,
1390     raw_string_ostream &KdStream) const {
1391 #define PRINT_DIRECTIVE(DIRECTIVE, MASK)                                       \
1392   do {                                                                         \
1393     KdStream << Indent << DIRECTIVE " "                                        \
1394              << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n';            \
1395   } while (0)
1396 
1397   uint16_t TwoByteBuffer = 0;
1398   uint32_t FourByteBuffer = 0;
1399   uint64_t EightByteBuffer = 0;
1400 
1401   StringRef ReservedBytes;
1402   StringRef Indent = "\t";
1403 
1404   assert(Bytes.size() == 64);
1405   DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8);
1406 
1407   switch (Cursor.tell()) {
1408   case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET:
1409     FourByteBuffer = DE.getU32(Cursor);
1410     KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer
1411              << '\n';
1412     return MCDisassembler::Success;
1413 
1414   case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET:
1415     FourByteBuffer = DE.getU32(Cursor);
1416     KdStream << Indent << ".amdhsa_private_segment_fixed_size "
1417              << FourByteBuffer << '\n';
1418     return MCDisassembler::Success;
1419 
1420   case amdhsa::RESERVED0_OFFSET:
1421     // 8 reserved bytes, must be 0.
1422     EightByteBuffer = DE.getU64(Cursor);
1423     if (EightByteBuffer) {
1424       return MCDisassembler::Fail;
1425     }
1426     return MCDisassembler::Success;
1427 
1428   case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET:
1429     // KERNEL_CODE_ENTRY_BYTE_OFFSET
1430     // So far no directive controls this for Code Object V3, so simply skip for
1431     // disassembly.
1432     DE.skip(Cursor, 8);
1433     return MCDisassembler::Success;
1434 
1435   case amdhsa::RESERVED1_OFFSET:
1436     // 20 reserved bytes, must be 0.
1437     ReservedBytes = DE.getBytes(Cursor, 20);
1438     for (int I = 0; I < 20; ++I) {
1439       if (ReservedBytes[I] != 0) {
1440         return MCDisassembler::Fail;
1441       }
1442     }
1443     return MCDisassembler::Success;
1444 
1445   case amdhsa::COMPUTE_PGM_RSRC3_OFFSET:
1446     // COMPUTE_PGM_RSRC3
1447     //  - Only set for GFX10, GFX6-9 have this to be 0.
1448     //  - Currently no directives directly control this.
1449     FourByteBuffer = DE.getU32(Cursor);
1450     if (!isGFX10() && FourByteBuffer) {
1451       return MCDisassembler::Fail;
1452     }
1453     return MCDisassembler::Success;
1454 
1455   case amdhsa::COMPUTE_PGM_RSRC1_OFFSET:
1456     FourByteBuffer = DE.getU32(Cursor);
1457     if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) ==
1458         MCDisassembler::Fail) {
1459       return MCDisassembler::Fail;
1460     }
1461     return MCDisassembler::Success;
1462 
1463   case amdhsa::COMPUTE_PGM_RSRC2_OFFSET:
1464     FourByteBuffer = DE.getU32(Cursor);
1465     if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) ==
1466         MCDisassembler::Fail) {
1467       return MCDisassembler::Fail;
1468     }
1469     return MCDisassembler::Success;
1470 
1471   case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET:
1472     using namespace amdhsa;
1473     TwoByteBuffer = DE.getU16(Cursor);
1474 
1475     PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer",
1476                     KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
1477     PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr",
1478                     KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
1479     PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr",
1480                     KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
1481     PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr",
1482                     KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
1483     PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id",
1484                     KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
1485     PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init",
1486                     KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
1487     PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size",
1488                     KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
1489 
1490     if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0)
1491       return MCDisassembler::Fail;
1492 
1493     // Reserved for GFX9
1494     if (isGFX9() &&
1495         (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
1496       return MCDisassembler::Fail;
1497     } else if (isGFX10()) {
1498       PRINT_DIRECTIVE(".amdhsa_wavefront_size32",
1499                       KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
1500     }
1501 
1502     if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1)
1503       return MCDisassembler::Fail;
1504 
1505     return MCDisassembler::Success;
1506 
1507   case amdhsa::RESERVED2_OFFSET:
1508     // 6 bytes from here are reserved, must be 0.
1509     ReservedBytes = DE.getBytes(Cursor, 6);
1510     for (int I = 0; I < 6; ++I) {
1511       if (ReservedBytes[I] != 0)
1512         return MCDisassembler::Fail;
1513     }
1514     return MCDisassembler::Success;
1515 
1516   default:
1517     llvm_unreachable("Unhandled index. Case statements cover everything.");
1518     return MCDisassembler::Fail;
1519   }
1520 #undef PRINT_DIRECTIVE
1521 }
1522 
1523 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor(
1524     StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const {
1525   // CP microcode requires the kernel descriptor to be 64 aligned.
1526   if (Bytes.size() != 64 || KdAddress % 64 != 0)
1527     return MCDisassembler::Fail;
1528 
1529   std::string Kd;
1530   raw_string_ostream KdStream(Kd);
1531   KdStream << ".amdhsa_kernel " << KdName << '\n';
1532 
1533   DataExtractor::Cursor C(0);
1534   while (C && C.tell() < Bytes.size()) {
1535     MCDisassembler::DecodeStatus Status =
1536         decodeKernelDescriptorDirective(C, Bytes, KdStream);
1537 
1538     cantFail(C.takeError());
1539 
1540     if (Status == MCDisassembler::Fail)
1541       return MCDisassembler::Fail;
1542   }
1543   KdStream << ".end_amdhsa_kernel\n";
1544   outs() << KdStream.str();
1545   return MCDisassembler::Success;
1546 }
1547 
1548 Optional<MCDisassembler::DecodeStatus>
1549 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size,
1550                                   ArrayRef<uint8_t> Bytes, uint64_t Address,
1551                                   raw_ostream &CStream) const {
1552   // Right now only kernel descriptor needs to be handled.
1553   // We ignore all other symbols for target specific handling.
1554   // TODO:
1555   // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code
1556   // Object V2 and V3 when symbols are marked protected.
1557 
1558   // amd_kernel_code_t for Code Object V2.
1559   if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) {
1560     Size = 256;
1561     return MCDisassembler::Fail;
1562   }
1563 
1564   // Code Object V3 kernel descriptors.
1565   StringRef Name = Symbol.Name;
1566   if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) {
1567     Size = 64; // Size = 64 regardless of success or failure.
1568     return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address);
1569   }
1570   return None;
1571 }
1572 
1573 //===----------------------------------------------------------------------===//
1574 // AMDGPUSymbolizer
1575 //===----------------------------------------------------------------------===//
1576 
1577 // Try to find symbol name for specified label
1578 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
1579                                 raw_ostream &/*cStream*/, int64_t Value,
1580                                 uint64_t /*Address*/, bool IsBranch,
1581                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1582 
1583   if (!IsBranch) {
1584     return false;
1585   }
1586 
1587   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1588   if (!Symbols)
1589     return false;
1590 
1591   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1592                              [Value](const SymbolInfoTy& Val) {
1593                                 return Val.Addr == static_cast<uint64_t>(Value)
1594                                     && Val.Type == ELF::STT_NOTYPE;
1595                              });
1596   if (Result != Symbols->end()) {
1597     auto *Sym = Ctx.getOrCreateSymbol(Result->Name);
1598     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1599     Inst.addOperand(MCOperand::createExpr(Add));
1600     return true;
1601   }
1602   return false;
1603 }
1604 
1605 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
1606                                                        int64_t Value,
1607                                                        uint64_t Address) {
1608   llvm_unreachable("unimplemented");
1609 }
1610 
1611 //===----------------------------------------------------------------------===//
1612 // Initialization
1613 //===----------------------------------------------------------------------===//
1614 
1615 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
1616                               LLVMOpInfoCallback /*GetOpInfo*/,
1617                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
1618                               void *DisInfo,
1619                               MCContext *Ctx,
1620                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1621   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1622 }
1623 
1624 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
1625                                                 const MCSubtargetInfo &STI,
1626                                                 MCContext &Ctx) {
1627   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1628 }
1629 
1630 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() {
1631   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
1632                                          createAMDGPUDisassembler);
1633   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
1634                                        createAMDGPUSymbolizer);
1635 }
1636