1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/BinaryFormat/ELF.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCExpr.h" 28 #include "llvm/MC/MCFixedLenDisassembler.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/AMDHSAKernelDescriptor.h" 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 #define SGPR_MAX \ 40 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 41 : AMDGPU::EncValues::SGPR_MAX_SI) 42 43 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 44 45 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 46 MCContext &Ctx, 47 MCInstrInfo const *MCII) : 48 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 49 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 50 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, const void *Decoder) { 77 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 78 79 // Our branches take a simm16, but we need two extra bits to account for the 80 // factor of 4. 81 APInt SignedOffset(18, Imm * 4, true); 82 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 83 84 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 85 return MCDisassembler::Success; 86 return addOperand(Inst, MCOperand::createImm(Imm)); 87 } 88 89 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, 90 uint64_t Addr, const void *Decoder) { 91 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 92 int64_t Offset; 93 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 94 Offset = Imm & 0xFFFFF; 95 } else { // GFX9+ supports 21-bit signed offsets. 96 Offset = SignExtend64<21>(Imm); 97 } 98 return addOperand(Inst, MCOperand::createImm(Offset)); 99 } 100 101 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, 102 uint64_t Addr, const void *Decoder) { 103 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 104 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 105 } 106 107 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 108 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 109 unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const void *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 #define DECODE_OPERAND_REG(RegClass) \ 117 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 118 119 DECODE_OPERAND_REG(VGPR_32) 120 DECODE_OPERAND_REG(VRegOrLds_32) 121 DECODE_OPERAND_REG(VS_32) 122 DECODE_OPERAND_REG(VS_64) 123 DECODE_OPERAND_REG(VS_128) 124 125 DECODE_OPERAND_REG(VReg_64) 126 DECODE_OPERAND_REG(VReg_96) 127 DECODE_OPERAND_REG(VReg_128) 128 DECODE_OPERAND_REG(VReg_256) 129 DECODE_OPERAND_REG(VReg_512) 130 DECODE_OPERAND_REG(VReg_1024) 131 132 DECODE_OPERAND_REG(SReg_32) 133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 135 DECODE_OPERAND_REG(SRegOrLds_32) 136 DECODE_OPERAND_REG(SReg_64) 137 DECODE_OPERAND_REG(SReg_64_XEXEC) 138 DECODE_OPERAND_REG(SReg_128) 139 DECODE_OPERAND_REG(SReg_256) 140 DECODE_OPERAND_REG(SReg_512) 141 142 DECODE_OPERAND_REG(AGPR_32) 143 DECODE_OPERAND_REG(AReg_64) 144 DECODE_OPERAND_REG(AReg_128) 145 DECODE_OPERAND_REG(AReg_256) 146 DECODE_OPERAND_REG(AReg_512) 147 DECODE_OPERAND_REG(AReg_1024) 148 DECODE_OPERAND_REG(AV_32) 149 DECODE_OPERAND_REG(AV_64) 150 151 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 152 unsigned Imm, 153 uint64_t Addr, 154 const void *Decoder) { 155 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 156 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 157 } 158 159 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 160 unsigned Imm, 161 uint64_t Addr, 162 const void *Decoder) { 163 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 164 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 165 } 166 167 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, 168 unsigned Imm, 169 uint64_t Addr, 170 const void *Decoder) { 171 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 172 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 173 } 174 175 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, 176 unsigned Imm, 177 uint64_t Addr, 178 const void *Decoder) { 179 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 180 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 181 } 182 183 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, 184 unsigned Imm, 185 uint64_t Addr, 186 const void *Decoder) { 187 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 188 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 189 } 190 191 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, 192 unsigned Imm, 193 uint64_t Addr, 194 const void *Decoder) { 195 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 196 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 197 } 198 199 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, 200 unsigned Imm, 201 uint64_t Addr, 202 const void *Decoder) { 203 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 204 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 205 } 206 207 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, 208 unsigned Imm, 209 uint64_t Addr, 210 const void *Decoder) { 211 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 212 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 213 } 214 215 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, 216 unsigned Imm, 217 uint64_t Addr, 218 const void *Decoder) { 219 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 220 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 221 } 222 223 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, 224 unsigned Imm, 225 uint64_t Addr, 226 const void *Decoder) { 227 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 228 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 229 } 230 231 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, 232 unsigned Imm, 233 uint64_t Addr, 234 const void *Decoder) { 235 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 236 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 237 } 238 239 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, 240 unsigned Imm, 241 uint64_t Addr, 242 const void *Decoder) { 243 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 244 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 245 } 246 247 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, 248 unsigned Imm, 249 uint64_t Addr, 250 const void *Decoder) { 251 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 252 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 253 } 254 255 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, 256 unsigned Imm, 257 uint64_t Addr, 258 const void *Decoder) { 259 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 260 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 261 } 262 263 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, 264 unsigned Imm, 265 uint64_t Addr, 266 const void *Decoder) { 267 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 268 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 269 } 270 271 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 272 uint64_t Addr, const void *Decoder) { 273 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 274 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 275 } 276 277 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 278 uint64_t Addr, const void *Decoder) { 279 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 280 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 281 } 282 283 static DecodeStatus decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, 284 uint64_t Addr, 285 const void *Decoder) { 286 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand( 288 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 289 } 290 291 static DecodeStatus decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, 292 uint64_t Addr, 293 const void *Decoder) { 294 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 295 return addOperand( 296 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 297 } 298 299 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 300 const MCRegisterInfo *MRI) { 301 if (OpIdx < 0) 302 return false; 303 304 const MCOperand &Op = Inst.getOperand(OpIdx); 305 if (!Op.isReg()) 306 return false; 307 308 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 309 auto Reg = Sub ? Sub : Op.getReg(); 310 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 311 } 312 313 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, 314 unsigned Imm, 315 AMDGPUDisassembler::OpWidthTy Opw, 316 const void *Decoder) { 317 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 318 if (!DAsm->isGFX90A()) { 319 Imm &= 511; 320 } else { 321 // If atomic has both vdata and vdst their register classes are tied. 322 // The bit is decoded along with the vdst, first operand. We need to 323 // change register class to AGPR if vdst was AGPR. 324 // If a DS instruction has both data0 and data1 their register classes 325 // are also tied. 326 unsigned Opc = Inst.getOpcode(); 327 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 328 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 329 : AMDGPU::OpName::vdata; 330 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 331 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 332 if ((int)Inst.getNumOperands() == DataIdx) { 333 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 334 if (IsAGPROperand(Inst, DstIdx, MRI)) 335 Imm |= 512; 336 } 337 338 if (TSFlags & SIInstrFlags::DS) { 339 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 340 if ((int)Inst.getNumOperands() == Data2Idx && 341 IsAGPROperand(Inst, DataIdx, MRI)) 342 Imm |= 512; 343 } 344 } 345 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 346 } 347 348 static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, 349 unsigned Imm, 350 uint64_t Addr, 351 const void *Decoder) { 352 return decodeOperand_AVLdSt_Any(Inst, Imm, 353 AMDGPUDisassembler::OPW32, Decoder); 354 } 355 356 static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, 357 unsigned Imm, 358 uint64_t Addr, 359 const void *Decoder) { 360 return decodeOperand_AVLdSt_Any(Inst, Imm, 361 AMDGPUDisassembler::OPW64, Decoder); 362 } 363 364 static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, 365 unsigned Imm, 366 uint64_t Addr, 367 const void *Decoder) { 368 return decodeOperand_AVLdSt_Any(Inst, Imm, 369 AMDGPUDisassembler::OPW96, Decoder); 370 } 371 372 static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, 373 unsigned Imm, 374 uint64_t Addr, 375 const void *Decoder) { 376 return decodeOperand_AVLdSt_Any(Inst, Imm, 377 AMDGPUDisassembler::OPW128, Decoder); 378 } 379 380 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, 381 unsigned Imm, 382 uint64_t Addr, 383 const void *Decoder) { 384 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 385 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 386 } 387 388 #define DECODE_SDWA(DecName) \ 389 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 390 391 DECODE_SDWA(Src32) 392 DECODE_SDWA(Src16) 393 DECODE_SDWA(VopcDst) 394 395 #include "AMDGPUGenDisassemblerTables.inc" 396 397 //===----------------------------------------------------------------------===// 398 // 399 //===----------------------------------------------------------------------===// 400 401 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 402 assert(Bytes.size() >= sizeof(T)); 403 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 404 Bytes = Bytes.slice(sizeof(T)); 405 return Res; 406 } 407 408 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 409 MCInst &MI, 410 uint64_t Inst, 411 uint64_t Address) const { 412 assert(MI.getOpcode() == 0); 413 assert(MI.getNumOperands() == 0); 414 MCInst TmpInst; 415 HasLiteral = false; 416 const auto SavedBytes = Bytes; 417 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 418 MI = TmpInst; 419 return MCDisassembler::Success; 420 } 421 Bytes = SavedBytes; 422 return MCDisassembler::Fail; 423 } 424 425 // The disassembler is greedy, so we need to check FI operand value to 426 // not parse a dpp if the correct literal is not set. For dpp16 the 427 // autogenerated decoder checks the dpp literal 428 static bool isValidDPP8(const MCInst &MI) { 429 using namespace llvm::AMDGPU::DPP; 430 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 431 assert(FiIdx != -1); 432 if ((unsigned)FiIdx >= MI.getNumOperands()) 433 return false; 434 unsigned Fi = MI.getOperand(FiIdx).getImm(); 435 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 436 } 437 438 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 439 ArrayRef<uint8_t> Bytes_, 440 uint64_t Address, 441 raw_ostream &CS) const { 442 CommentStream = &CS; 443 bool IsSDWA = false; 444 445 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 446 Bytes = Bytes_.slice(0, MaxInstBytesNum); 447 448 DecodeStatus Res = MCDisassembler::Fail; 449 do { 450 // ToDo: better to switch encoding length using some bit predicate 451 // but it is unknown yet, so try all we can 452 453 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 454 // encodings 455 if (Bytes.size() >= 8) { 456 const uint64_t QW = eatBytes<uint64_t>(Bytes); 457 458 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 459 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 460 if (Res) { 461 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 462 == -1) 463 break; 464 if (convertDPP8Inst(MI) == MCDisassembler::Success) 465 break; 466 MI = MCInst(); // clear 467 } 468 } 469 470 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 471 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 472 break; 473 474 MI = MCInst(); // clear 475 476 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 477 if (Res) break; 478 479 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 480 if (Res) { IsSDWA = true; break; } 481 482 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 483 if (Res) { IsSDWA = true; break; } 484 485 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 486 if (Res) { IsSDWA = true; break; } 487 488 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 489 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 490 if (Res) 491 break; 492 } 493 494 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 495 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 496 // table first so we print the correct name. 497 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 498 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 499 if (Res) 500 break; 501 } 502 } 503 504 // Reinitialize Bytes as DPP64 could have eaten too much 505 Bytes = Bytes_.slice(0, MaxInstBytesNum); 506 507 // Try decode 32-bit instruction 508 if (Bytes.size() < 4) break; 509 const uint32_t DW = eatBytes<uint32_t>(Bytes); 510 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 511 if (Res) break; 512 513 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 514 if (Res) break; 515 516 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 517 if (Res) break; 518 519 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 520 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 521 if (Res) 522 break; 523 } 524 525 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 526 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 527 if (Res) break; 528 } 529 530 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 531 if (Res) break; 532 533 if (Bytes.size() < 4) break; 534 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 535 536 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 537 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 538 if (Res) 539 break; 540 } 541 542 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 543 if (Res) break; 544 545 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 546 if (Res) break; 547 548 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 549 if (Res) break; 550 551 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 552 } while (false); 553 554 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 555 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 556 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 557 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 558 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 559 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 560 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 561 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 562 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 563 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 564 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 565 // Insert dummy unused src2_modifiers. 566 insertNamedMCOperand(MI, MCOperand::createImm(0), 567 AMDGPU::OpName::src2_modifiers); 568 } 569 570 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 571 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 572 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 573 AMDGPU::OpName::cpol); 574 if (CPolPos != -1) { 575 unsigned CPol = 576 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 577 AMDGPU::CPol::GLC : 0; 578 if (MI.getNumOperands() <= (unsigned)CPolPos) { 579 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 580 AMDGPU::OpName::cpol); 581 } else if (CPol) { 582 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 583 } 584 } 585 } 586 587 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 588 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 589 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 590 // GFX90A lost TFE, its place is occupied by ACC. 591 int TFEOpIdx = 592 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 593 if (TFEOpIdx != -1) { 594 auto TFEIter = MI.begin(); 595 std::advance(TFEIter, TFEOpIdx); 596 MI.insert(TFEIter, MCOperand::createImm(0)); 597 } 598 } 599 600 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 601 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 602 int SWZOpIdx = 603 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 604 if (SWZOpIdx != -1) { 605 auto SWZIter = MI.begin(); 606 std::advance(SWZIter, SWZOpIdx); 607 MI.insert(SWZIter, MCOperand::createImm(0)); 608 } 609 } 610 611 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 612 int VAddr0Idx = 613 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 614 int RsrcIdx = 615 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 616 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 617 if (VAddr0Idx >= 0 && NSAArgs > 0) { 618 unsigned NSAWords = (NSAArgs + 3) / 4; 619 if (Bytes.size() < 4 * NSAWords) { 620 Res = MCDisassembler::Fail; 621 } else { 622 for (unsigned i = 0; i < NSAArgs; ++i) { 623 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 624 decodeOperand_VGPR_32(Bytes[i])); 625 } 626 Bytes = Bytes.slice(4 * NSAWords); 627 } 628 } 629 630 if (Res) 631 Res = convertMIMGInst(MI); 632 } 633 634 if (Res && IsSDWA) 635 Res = convertSDWAInst(MI); 636 637 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 638 AMDGPU::OpName::vdst_in); 639 if (VDstIn_Idx != -1) { 640 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 641 MCOI::OperandConstraint::TIED_TO); 642 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 643 !MI.getOperand(VDstIn_Idx).isReg() || 644 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 645 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 646 MI.erase(&MI.getOperand(VDstIn_Idx)); 647 insertNamedMCOperand(MI, 648 MCOperand::createReg(MI.getOperand(Tied).getReg()), 649 AMDGPU::OpName::vdst_in); 650 } 651 } 652 653 int ImmLitIdx = 654 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 655 if (Res && ImmLitIdx != -1) 656 Res = convertFMAanyK(MI, ImmLitIdx); 657 658 // if the opcode was not recognized we'll assume a Size of 4 bytes 659 // (unless there are fewer bytes left) 660 Size = Res ? (MaxInstBytesNum - Bytes.size()) 661 : std::min((size_t)4, Bytes_.size()); 662 return Res; 663 } 664 665 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 666 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 667 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 668 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 669 // VOPC - insert clamp 670 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 671 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 672 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 673 if (SDst != -1) { 674 // VOPC - insert VCC register as sdst 675 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 676 AMDGPU::OpName::sdst); 677 } else { 678 // VOP1/2 - insert omod if present in instruction 679 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 680 } 681 } 682 return MCDisassembler::Success; 683 } 684 685 // We must check FI == literal to reject not genuine dpp8 insts, and we must 686 // first add optional MI operands to check FI 687 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 688 unsigned Opc = MI.getOpcode(); 689 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 690 691 // Insert dummy unused src modifiers. 692 if (MI.getNumOperands() < DescNumOps && 693 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 694 insertNamedMCOperand(MI, MCOperand::createImm(0), 695 AMDGPU::OpName::src0_modifiers); 696 697 if (MI.getNumOperands() < DescNumOps && 698 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 699 insertNamedMCOperand(MI, MCOperand::createImm(0), 700 AMDGPU::OpName::src1_modifiers); 701 702 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 703 } 704 705 // Note that before gfx10, the MIMG encoding provided no information about 706 // VADDR size. Consequently, decoded instructions always show address as if it 707 // has 1 dword, which could be not really so. 708 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 709 710 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 711 AMDGPU::OpName::vdst); 712 713 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 714 AMDGPU::OpName::vdata); 715 int VAddr0Idx = 716 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 717 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 718 AMDGPU::OpName::dmask); 719 720 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 721 AMDGPU::OpName::tfe); 722 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 723 AMDGPU::OpName::d16); 724 725 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 726 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 727 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 728 729 assert(VDataIdx != -1); 730 if (BaseOpcode->BVH) { 731 // Add A16 operand for intersect_ray instructions 732 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 733 addOperand(MI, MCOperand::createImm(1)); 734 } 735 return MCDisassembler::Success; 736 } 737 738 bool IsAtomic = (VDstIdx != -1); 739 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 740 bool IsNSA = false; 741 unsigned AddrSize = Info->VAddrDwords; 742 743 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 744 unsigned DimIdx = 745 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 746 int A16Idx = 747 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 748 const AMDGPU::MIMGDimInfo *Dim = 749 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 750 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 751 752 AddrSize = 753 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 754 755 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 756 if (!IsNSA) { 757 if (AddrSize > 8) 758 AddrSize = 16; 759 } else { 760 if (AddrSize > Info->VAddrDwords) { 761 // The NSA encoding does not contain enough operands for the combination 762 // of base opcode / dimension. Should this be an error? 763 return MCDisassembler::Success; 764 } 765 } 766 } 767 768 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 769 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 770 771 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 772 if (D16 && AMDGPU::hasPackedD16(STI)) { 773 DstSize = (DstSize + 1) / 2; 774 } 775 776 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 777 DstSize += 1; 778 779 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 780 return MCDisassembler::Success; 781 782 int NewOpcode = 783 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 784 if (NewOpcode == -1) 785 return MCDisassembler::Success; 786 787 // Widen the register to the correct number of enabled channels. 788 unsigned NewVdata = AMDGPU::NoRegister; 789 if (DstSize != Info->VDataDwords) { 790 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 791 792 // Get first subregister of VData 793 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 794 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 795 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 796 797 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 798 &MRI.getRegClass(DataRCID)); 799 if (NewVdata == AMDGPU::NoRegister) { 800 // It's possible to encode this such that the low register + enabled 801 // components exceeds the register count. 802 return MCDisassembler::Success; 803 } 804 } 805 806 unsigned NewVAddr0 = AMDGPU::NoRegister; 807 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 808 AddrSize != Info->VAddrDwords) { 809 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 810 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 811 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 812 813 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 814 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 815 &MRI.getRegClass(AddrRCID)); 816 if (NewVAddr0 == AMDGPU::NoRegister) 817 return MCDisassembler::Success; 818 } 819 820 MI.setOpcode(NewOpcode); 821 822 if (NewVdata != AMDGPU::NoRegister) { 823 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 824 825 if (IsAtomic) { 826 // Atomic operations have an additional operand (a copy of data) 827 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 828 } 829 } 830 831 if (NewVAddr0 != AMDGPU::NoRegister) { 832 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 833 } else if (IsNSA) { 834 assert(AddrSize <= Info->VAddrDwords); 835 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 836 MI.begin() + VAddr0Idx + Info->VAddrDwords); 837 } 838 839 return MCDisassembler::Success; 840 } 841 842 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 843 int ImmLitIdx) const { 844 assert(HasLiteral && "Should have decoded a literal"); 845 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 846 unsigned DescNumOps = Desc.getNumOperands(); 847 assert(DescNumOps == MI.getNumOperands()); 848 for (unsigned I = 0; I < DescNumOps; ++I) { 849 auto &Op = MI.getOperand(I); 850 auto OpType = Desc.OpInfo[I].OperandType; 851 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 852 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 853 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 854 IsDeferredOp) 855 Op.setImm(Literal); 856 } 857 return MCDisassembler::Success; 858 } 859 860 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 861 return getContext().getRegisterInfo()-> 862 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 863 } 864 865 inline 866 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 867 const Twine& ErrMsg) const { 868 *CommentStream << "Error: " + ErrMsg; 869 870 // ToDo: add support for error operands to MCInst.h 871 // return MCOperand::createError(V); 872 return MCOperand(); 873 } 874 875 inline 876 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 877 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 878 } 879 880 inline 881 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 882 unsigned Val) const { 883 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 884 if (Val >= RegCl.getNumRegs()) 885 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 886 ": unknown register " + Twine(Val)); 887 return createRegOperand(RegCl.getRegister(Val)); 888 } 889 890 inline 891 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 892 unsigned Val) const { 893 // ToDo: SI/CI have 104 SGPRs, VI - 102 894 // Valery: here we accepting as much as we can, let assembler sort it out 895 int shift = 0; 896 switch (SRegClassID) { 897 case AMDGPU::SGPR_32RegClassID: 898 case AMDGPU::TTMP_32RegClassID: 899 break; 900 case AMDGPU::SGPR_64RegClassID: 901 case AMDGPU::TTMP_64RegClassID: 902 shift = 1; 903 break; 904 case AMDGPU::SGPR_128RegClassID: 905 case AMDGPU::TTMP_128RegClassID: 906 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 907 // this bundle? 908 case AMDGPU::SGPR_256RegClassID: 909 case AMDGPU::TTMP_256RegClassID: 910 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 911 // this bundle? 912 case AMDGPU::SGPR_512RegClassID: 913 case AMDGPU::TTMP_512RegClassID: 914 shift = 2; 915 break; 916 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 917 // this bundle? 918 default: 919 llvm_unreachable("unhandled register class"); 920 } 921 922 if (Val % (1 << shift)) { 923 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 924 << ": scalar reg isn't aligned " << Val; 925 } 926 927 return createRegOperand(SRegClassID, Val >> shift); 928 } 929 930 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 931 return decodeSrcOp(OPW32, Val); 932 } 933 934 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 935 return decodeSrcOp(OPW64, Val); 936 } 937 938 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 939 return decodeSrcOp(OPW128, Val); 940 } 941 942 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 943 return decodeSrcOp(OPW16, Val); 944 } 945 946 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 947 return decodeSrcOp(OPWV216, Val); 948 } 949 950 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 951 return decodeSrcOp(OPWV232, Val); 952 } 953 954 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 955 // Some instructions have operand restrictions beyond what the encoding 956 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 957 // high bit. 958 Val &= 255; 959 960 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 961 } 962 963 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 964 return decodeSrcOp(OPW32, Val); 965 } 966 967 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 968 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 969 } 970 971 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 972 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 973 } 974 975 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 976 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 977 } 978 979 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 980 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 981 } 982 983 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 984 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 985 } 986 987 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 988 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 989 } 990 991 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 992 return decodeSrcOp(OPW32, Val); 993 } 994 995 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 996 return decodeSrcOp(OPW64, Val); 997 } 998 999 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1000 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1001 } 1002 1003 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1004 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1005 } 1006 1007 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1008 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1009 } 1010 1011 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1012 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1013 } 1014 1015 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1016 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1017 } 1018 1019 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1020 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1021 } 1022 1023 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1024 // table-gen generated disassembler doesn't care about operand types 1025 // leaving only registry class so SSrc_32 operand turns into SReg_32 1026 // and therefore we accept immediates and literals here as well 1027 return decodeSrcOp(OPW32, Val); 1028 } 1029 1030 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1031 unsigned Val) const { 1032 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1033 return decodeOperand_SReg_32(Val); 1034 } 1035 1036 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1037 unsigned Val) const { 1038 // SReg_32_XM0 is SReg_32 without EXEC_HI 1039 return decodeOperand_SReg_32(Val); 1040 } 1041 1042 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1043 // table-gen generated disassembler doesn't care about operand types 1044 // leaving only registry class so SSrc_32 operand turns into SReg_32 1045 // and therefore we accept immediates and literals here as well 1046 return decodeSrcOp(OPW32, Val); 1047 } 1048 1049 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1050 return decodeSrcOp(OPW64, Val); 1051 } 1052 1053 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1054 return decodeSrcOp(OPW64, Val); 1055 } 1056 1057 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1058 return decodeSrcOp(OPW128, Val); 1059 } 1060 1061 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1062 return decodeDstOp(OPW256, Val); 1063 } 1064 1065 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1066 return decodeDstOp(OPW512, Val); 1067 } 1068 1069 // Decode Literals for insts which always have a literal in the encoding 1070 MCOperand 1071 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1072 if (HasLiteral) { 1073 if (Literal != Val) 1074 return errOperand(Val, "More than one unique literal is illegal"); 1075 } 1076 HasLiteral = true; 1077 Literal = Val; 1078 return MCOperand::createImm(Literal); 1079 } 1080 1081 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1082 // For now all literal constants are supposed to be unsigned integer 1083 // ToDo: deal with signed/unsigned 64-bit integer constants 1084 // ToDo: deal with float/double constants 1085 if (!HasLiteral) { 1086 if (Bytes.size() < 4) { 1087 return errOperand(0, "cannot read literal, inst bytes left " + 1088 Twine(Bytes.size())); 1089 } 1090 HasLiteral = true; 1091 Literal = eatBytes<uint32_t>(Bytes); 1092 } 1093 return MCOperand::createImm(Literal); 1094 } 1095 1096 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1097 using namespace AMDGPU::EncValues; 1098 1099 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1100 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1101 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1102 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1103 // Cast prevents negative overflow. 1104 } 1105 1106 static int64_t getInlineImmVal32(unsigned Imm) { 1107 switch (Imm) { 1108 case 240: 1109 return FloatToBits(0.5f); 1110 case 241: 1111 return FloatToBits(-0.5f); 1112 case 242: 1113 return FloatToBits(1.0f); 1114 case 243: 1115 return FloatToBits(-1.0f); 1116 case 244: 1117 return FloatToBits(2.0f); 1118 case 245: 1119 return FloatToBits(-2.0f); 1120 case 246: 1121 return FloatToBits(4.0f); 1122 case 247: 1123 return FloatToBits(-4.0f); 1124 case 248: // 1 / (2 * PI) 1125 return 0x3e22f983; 1126 default: 1127 llvm_unreachable("invalid fp inline imm"); 1128 } 1129 } 1130 1131 static int64_t getInlineImmVal64(unsigned Imm) { 1132 switch (Imm) { 1133 case 240: 1134 return DoubleToBits(0.5); 1135 case 241: 1136 return DoubleToBits(-0.5); 1137 case 242: 1138 return DoubleToBits(1.0); 1139 case 243: 1140 return DoubleToBits(-1.0); 1141 case 244: 1142 return DoubleToBits(2.0); 1143 case 245: 1144 return DoubleToBits(-2.0); 1145 case 246: 1146 return DoubleToBits(4.0); 1147 case 247: 1148 return DoubleToBits(-4.0); 1149 case 248: // 1 / (2 * PI) 1150 return 0x3fc45f306dc9c882; 1151 default: 1152 llvm_unreachable("invalid fp inline imm"); 1153 } 1154 } 1155 1156 static int64_t getInlineImmVal16(unsigned Imm) { 1157 switch (Imm) { 1158 case 240: 1159 return 0x3800; 1160 case 241: 1161 return 0xB800; 1162 case 242: 1163 return 0x3C00; 1164 case 243: 1165 return 0xBC00; 1166 case 244: 1167 return 0x4000; 1168 case 245: 1169 return 0xC000; 1170 case 246: 1171 return 0x4400; 1172 case 247: 1173 return 0xC400; 1174 case 248: // 1 / (2 * PI) 1175 return 0x3118; 1176 default: 1177 llvm_unreachable("invalid fp inline imm"); 1178 } 1179 } 1180 1181 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1182 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1183 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1184 1185 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1186 switch (Width) { 1187 case OPW32: 1188 case OPW128: // splat constants 1189 case OPW512: 1190 case OPW1024: 1191 case OPWV232: 1192 return MCOperand::createImm(getInlineImmVal32(Imm)); 1193 case OPW64: 1194 case OPW256: 1195 return MCOperand::createImm(getInlineImmVal64(Imm)); 1196 case OPW16: 1197 case OPWV216: 1198 return MCOperand::createImm(getInlineImmVal16(Imm)); 1199 default: 1200 llvm_unreachable("implement me"); 1201 } 1202 } 1203 1204 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1205 using namespace AMDGPU; 1206 1207 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1208 switch (Width) { 1209 default: // fall 1210 case OPW32: 1211 case OPW16: 1212 case OPWV216: 1213 return VGPR_32RegClassID; 1214 case OPW64: 1215 case OPWV232: return VReg_64RegClassID; 1216 case OPW96: return VReg_96RegClassID; 1217 case OPW128: return VReg_128RegClassID; 1218 case OPW160: return VReg_160RegClassID; 1219 case OPW256: return VReg_256RegClassID; 1220 case OPW512: return VReg_512RegClassID; 1221 case OPW1024: return VReg_1024RegClassID; 1222 } 1223 } 1224 1225 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1226 using namespace AMDGPU; 1227 1228 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1229 switch (Width) { 1230 default: // fall 1231 case OPW32: 1232 case OPW16: 1233 case OPWV216: 1234 return AGPR_32RegClassID; 1235 case OPW64: 1236 case OPWV232: return AReg_64RegClassID; 1237 case OPW96: return AReg_96RegClassID; 1238 case OPW128: return AReg_128RegClassID; 1239 case OPW160: return AReg_160RegClassID; 1240 case OPW256: return AReg_256RegClassID; 1241 case OPW512: return AReg_512RegClassID; 1242 case OPW1024: return AReg_1024RegClassID; 1243 } 1244 } 1245 1246 1247 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1248 using namespace AMDGPU; 1249 1250 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1251 switch (Width) { 1252 default: // fall 1253 case OPW32: 1254 case OPW16: 1255 case OPWV216: 1256 return SGPR_32RegClassID; 1257 case OPW64: 1258 case OPWV232: return SGPR_64RegClassID; 1259 case OPW96: return SGPR_96RegClassID; 1260 case OPW128: return SGPR_128RegClassID; 1261 case OPW160: return SGPR_160RegClassID; 1262 case OPW256: return SGPR_256RegClassID; 1263 case OPW512: return SGPR_512RegClassID; 1264 } 1265 } 1266 1267 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1268 using namespace AMDGPU; 1269 1270 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1271 switch (Width) { 1272 default: // fall 1273 case OPW32: 1274 case OPW16: 1275 case OPWV216: 1276 return TTMP_32RegClassID; 1277 case OPW64: 1278 case OPWV232: return TTMP_64RegClassID; 1279 case OPW128: return TTMP_128RegClassID; 1280 case OPW256: return TTMP_256RegClassID; 1281 case OPW512: return TTMP_512RegClassID; 1282 } 1283 } 1284 1285 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1286 using namespace AMDGPU::EncValues; 1287 1288 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1289 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1290 1291 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1292 } 1293 1294 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1295 bool MandatoryLiteral) const { 1296 using namespace AMDGPU::EncValues; 1297 1298 assert(Val < 1024); // enum10 1299 1300 bool IsAGPR = Val & 512; 1301 Val &= 511; 1302 1303 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1304 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1305 : getVgprClassId(Width), Val - VGPR_MIN); 1306 } 1307 if (Val <= SGPR_MAX) { 1308 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1309 static_assert(SGPR_MIN == 0, ""); 1310 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1311 } 1312 1313 int TTmpIdx = getTTmpIdx(Val); 1314 if (TTmpIdx >= 0) { 1315 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1316 } 1317 1318 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1319 return decodeIntImmed(Val); 1320 1321 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1322 return decodeFPImmed(Width, Val); 1323 1324 if (Val == LITERAL_CONST) { 1325 if (MandatoryLiteral) 1326 // Keep a sentinel value for deferred setting 1327 return MCOperand::createImm(LITERAL_CONST); 1328 else 1329 return decodeLiteralConstant(); 1330 } 1331 1332 switch (Width) { 1333 case OPW32: 1334 case OPW16: 1335 case OPWV216: 1336 return decodeSpecialReg32(Val); 1337 case OPW64: 1338 case OPWV232: 1339 return decodeSpecialReg64(Val); 1340 default: 1341 llvm_unreachable("unexpected immediate type"); 1342 } 1343 } 1344 1345 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1346 using namespace AMDGPU::EncValues; 1347 1348 assert(Val < 128); 1349 assert(Width == OPW256 || Width == OPW512); 1350 1351 if (Val <= SGPR_MAX) { 1352 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1353 static_assert(SGPR_MIN == 0, ""); 1354 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1355 } 1356 1357 int TTmpIdx = getTTmpIdx(Val); 1358 if (TTmpIdx >= 0) { 1359 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1360 } 1361 1362 llvm_unreachable("unknown dst register"); 1363 } 1364 1365 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1366 using namespace AMDGPU; 1367 1368 switch (Val) { 1369 case 102: return createRegOperand(FLAT_SCR_LO); 1370 case 103: return createRegOperand(FLAT_SCR_HI); 1371 case 104: return createRegOperand(XNACK_MASK_LO); 1372 case 105: return createRegOperand(XNACK_MASK_HI); 1373 case 106: return createRegOperand(VCC_LO); 1374 case 107: return createRegOperand(VCC_HI); 1375 case 108: return createRegOperand(TBA_LO); 1376 case 109: return createRegOperand(TBA_HI); 1377 case 110: return createRegOperand(TMA_LO); 1378 case 111: return createRegOperand(TMA_HI); 1379 case 124: return createRegOperand(M0); 1380 case 125: return createRegOperand(SGPR_NULL); 1381 case 126: return createRegOperand(EXEC_LO); 1382 case 127: return createRegOperand(EXEC_HI); 1383 case 235: return createRegOperand(SRC_SHARED_BASE); 1384 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1385 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1386 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1387 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1388 case 251: return createRegOperand(SRC_VCCZ); 1389 case 252: return createRegOperand(SRC_EXECZ); 1390 case 253: return createRegOperand(SRC_SCC); 1391 case 254: return createRegOperand(LDS_DIRECT); 1392 default: break; 1393 } 1394 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1395 } 1396 1397 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1398 using namespace AMDGPU; 1399 1400 switch (Val) { 1401 case 102: return createRegOperand(FLAT_SCR); 1402 case 104: return createRegOperand(XNACK_MASK); 1403 case 106: return createRegOperand(VCC); 1404 case 108: return createRegOperand(TBA); 1405 case 110: return createRegOperand(TMA); 1406 case 125: return createRegOperand(SGPR_NULL); 1407 case 126: return createRegOperand(EXEC); 1408 case 235: return createRegOperand(SRC_SHARED_BASE); 1409 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1410 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1411 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1412 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1413 case 251: return createRegOperand(SRC_VCCZ); 1414 case 252: return createRegOperand(SRC_EXECZ); 1415 case 253: return createRegOperand(SRC_SCC); 1416 default: break; 1417 } 1418 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1419 } 1420 1421 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1422 const unsigned Val) const { 1423 using namespace AMDGPU::SDWA; 1424 using namespace AMDGPU::EncValues; 1425 1426 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1427 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1428 // XXX: cast to int is needed to avoid stupid warning: 1429 // compare with unsigned is always true 1430 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1431 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1432 return createRegOperand(getVgprClassId(Width), 1433 Val - SDWA9EncValues::SRC_VGPR_MIN); 1434 } 1435 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1436 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1437 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1438 return createSRegOperand(getSgprClassId(Width), 1439 Val - SDWA9EncValues::SRC_SGPR_MIN); 1440 } 1441 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1442 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1443 return createSRegOperand(getTtmpClassId(Width), 1444 Val - SDWA9EncValues::SRC_TTMP_MIN); 1445 } 1446 1447 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1448 1449 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1450 return decodeIntImmed(SVal); 1451 1452 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1453 return decodeFPImmed(Width, SVal); 1454 1455 return decodeSpecialReg32(SVal); 1456 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1457 return createRegOperand(getVgprClassId(Width), Val); 1458 } 1459 llvm_unreachable("unsupported target"); 1460 } 1461 1462 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1463 return decodeSDWASrc(OPW16, Val); 1464 } 1465 1466 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1467 return decodeSDWASrc(OPW32, Val); 1468 } 1469 1470 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1471 using namespace AMDGPU::SDWA; 1472 1473 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1474 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1475 "SDWAVopcDst should be present only on GFX9+"); 1476 1477 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1478 1479 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1480 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1481 1482 int TTmpIdx = getTTmpIdx(Val); 1483 if (TTmpIdx >= 0) { 1484 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1485 return createSRegOperand(TTmpClsId, TTmpIdx); 1486 } else if (Val > SGPR_MAX) { 1487 return IsWave64 ? decodeSpecialReg64(Val) 1488 : decodeSpecialReg32(Val); 1489 } else { 1490 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1491 } 1492 } else { 1493 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1494 } 1495 } 1496 1497 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1498 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1499 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1500 } 1501 1502 bool AMDGPUDisassembler::isVI() const { 1503 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1504 } 1505 1506 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1507 1508 bool AMDGPUDisassembler::isGFX90A() const { 1509 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1510 } 1511 1512 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1513 1514 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1515 1516 bool AMDGPUDisassembler::isGFX10Plus() const { 1517 return AMDGPU::isGFX10Plus(STI); 1518 } 1519 1520 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1521 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1522 } 1523 1524 //===----------------------------------------------------------------------===// 1525 // AMDGPU specific symbol handling 1526 //===----------------------------------------------------------------------===// 1527 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1528 do { \ 1529 KdStream << Indent << DIRECTIVE " " \ 1530 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1531 } while (0) 1532 1533 // NOLINTNEXTLINE(readability-identifier-naming) 1534 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1535 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1536 using namespace amdhsa; 1537 StringRef Indent = "\t"; 1538 1539 // We cannot accurately backward compute #VGPRs used from 1540 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1541 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1542 // simply calculate the inverse of what the assembler does. 1543 1544 uint32_t GranulatedWorkitemVGPRCount = 1545 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1546 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1547 1548 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1549 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1550 1551 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1552 1553 // We cannot backward compute values used to calculate 1554 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1555 // directives can't be computed: 1556 // .amdhsa_reserve_vcc 1557 // .amdhsa_reserve_flat_scratch 1558 // .amdhsa_reserve_xnack_mask 1559 // They take their respective default values if not specified in the assembly. 1560 // 1561 // GRANULATED_WAVEFRONT_SGPR_COUNT 1562 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1563 // 1564 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1565 // are set to 0. So while disassembling we consider that: 1566 // 1567 // GRANULATED_WAVEFRONT_SGPR_COUNT 1568 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1569 // 1570 // The disassembler cannot recover the original values of those 3 directives. 1571 1572 uint32_t GranulatedWavefrontSGPRCount = 1573 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1574 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1575 1576 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1577 return MCDisassembler::Fail; 1578 1579 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1580 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1581 1582 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1583 if (!hasArchitectedFlatScratch()) 1584 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1585 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1586 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1587 1588 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1589 return MCDisassembler::Fail; 1590 1591 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1592 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1593 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1594 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1595 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1596 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1597 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1598 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1599 1600 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1601 return MCDisassembler::Fail; 1602 1603 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1604 1605 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1606 return MCDisassembler::Fail; 1607 1608 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1609 1610 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1611 return MCDisassembler::Fail; 1612 1613 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1614 return MCDisassembler::Fail; 1615 1616 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1617 1618 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1619 return MCDisassembler::Fail; 1620 1621 if (isGFX10Plus()) { 1622 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1623 COMPUTE_PGM_RSRC1_WGP_MODE); 1624 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1625 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1626 } 1627 return MCDisassembler::Success; 1628 } 1629 1630 // NOLINTNEXTLINE(readability-identifier-naming) 1631 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1632 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1633 using namespace amdhsa; 1634 StringRef Indent = "\t"; 1635 if (hasArchitectedFlatScratch()) 1636 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1637 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1638 else 1639 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1640 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1641 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1642 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1643 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1644 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1645 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1646 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1647 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1648 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1649 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1650 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1651 1652 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1653 return MCDisassembler::Fail; 1654 1655 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1656 return MCDisassembler::Fail; 1657 1658 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1659 return MCDisassembler::Fail; 1660 1661 PRINT_DIRECTIVE( 1662 ".amdhsa_exception_fp_ieee_invalid_op", 1663 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1664 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1665 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1666 PRINT_DIRECTIVE( 1667 ".amdhsa_exception_fp_ieee_div_zero", 1668 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1669 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1670 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1671 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1672 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1673 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1674 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1675 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1676 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1677 1678 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1679 return MCDisassembler::Fail; 1680 1681 return MCDisassembler::Success; 1682 } 1683 1684 #undef PRINT_DIRECTIVE 1685 1686 MCDisassembler::DecodeStatus 1687 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1688 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1689 raw_string_ostream &KdStream) const { 1690 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1691 do { \ 1692 KdStream << Indent << DIRECTIVE " " \ 1693 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1694 } while (0) 1695 1696 uint16_t TwoByteBuffer = 0; 1697 uint32_t FourByteBuffer = 0; 1698 1699 StringRef ReservedBytes; 1700 StringRef Indent = "\t"; 1701 1702 assert(Bytes.size() == 64); 1703 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1704 1705 switch (Cursor.tell()) { 1706 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1707 FourByteBuffer = DE.getU32(Cursor); 1708 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1709 << '\n'; 1710 return MCDisassembler::Success; 1711 1712 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1713 FourByteBuffer = DE.getU32(Cursor); 1714 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1715 << FourByteBuffer << '\n'; 1716 return MCDisassembler::Success; 1717 1718 case amdhsa::KERNARG_SIZE_OFFSET: 1719 FourByteBuffer = DE.getU32(Cursor); 1720 KdStream << Indent << ".amdhsa_kernarg_size " 1721 << FourByteBuffer << '\n'; 1722 return MCDisassembler::Success; 1723 1724 case amdhsa::RESERVED0_OFFSET: 1725 // 4 reserved bytes, must be 0. 1726 ReservedBytes = DE.getBytes(Cursor, 4); 1727 for (int I = 0; I < 4; ++I) { 1728 if (ReservedBytes[I] != 0) { 1729 return MCDisassembler::Fail; 1730 } 1731 } 1732 return MCDisassembler::Success; 1733 1734 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1735 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1736 // So far no directive controls this for Code Object V3, so simply skip for 1737 // disassembly. 1738 DE.skip(Cursor, 8); 1739 return MCDisassembler::Success; 1740 1741 case amdhsa::RESERVED1_OFFSET: 1742 // 20 reserved bytes, must be 0. 1743 ReservedBytes = DE.getBytes(Cursor, 20); 1744 for (int I = 0; I < 20; ++I) { 1745 if (ReservedBytes[I] != 0) { 1746 return MCDisassembler::Fail; 1747 } 1748 } 1749 return MCDisassembler::Success; 1750 1751 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1752 // COMPUTE_PGM_RSRC3 1753 // - Only set for GFX10, GFX6-9 have this to be 0. 1754 // - Currently no directives directly control this. 1755 FourByteBuffer = DE.getU32(Cursor); 1756 if (!isGFX10Plus() && FourByteBuffer) { 1757 return MCDisassembler::Fail; 1758 } 1759 return MCDisassembler::Success; 1760 1761 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1762 FourByteBuffer = DE.getU32(Cursor); 1763 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1764 MCDisassembler::Fail) { 1765 return MCDisassembler::Fail; 1766 } 1767 return MCDisassembler::Success; 1768 1769 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1770 FourByteBuffer = DE.getU32(Cursor); 1771 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1772 MCDisassembler::Fail) { 1773 return MCDisassembler::Fail; 1774 } 1775 return MCDisassembler::Success; 1776 1777 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1778 using namespace amdhsa; 1779 TwoByteBuffer = DE.getU16(Cursor); 1780 1781 if (!hasArchitectedFlatScratch()) 1782 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1783 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1784 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1785 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1786 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1787 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1788 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1789 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1790 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1791 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1792 if (!hasArchitectedFlatScratch()) 1793 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1794 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1795 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1796 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1797 1798 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1799 return MCDisassembler::Fail; 1800 1801 // Reserved for GFX9 1802 if (isGFX9() && 1803 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1804 return MCDisassembler::Fail; 1805 } else if (isGFX10Plus()) { 1806 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1807 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1808 } 1809 1810 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1811 return MCDisassembler::Fail; 1812 1813 return MCDisassembler::Success; 1814 1815 case amdhsa::RESERVED2_OFFSET: 1816 // 6 bytes from here are reserved, must be 0. 1817 ReservedBytes = DE.getBytes(Cursor, 6); 1818 for (int I = 0; I < 6; ++I) { 1819 if (ReservedBytes[I] != 0) 1820 return MCDisassembler::Fail; 1821 } 1822 return MCDisassembler::Success; 1823 1824 default: 1825 llvm_unreachable("Unhandled index. Case statements cover everything."); 1826 return MCDisassembler::Fail; 1827 } 1828 #undef PRINT_DIRECTIVE 1829 } 1830 1831 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1832 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1833 // CP microcode requires the kernel descriptor to be 64 aligned. 1834 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1835 return MCDisassembler::Fail; 1836 1837 std::string Kd; 1838 raw_string_ostream KdStream(Kd); 1839 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1840 1841 DataExtractor::Cursor C(0); 1842 while (C && C.tell() < Bytes.size()) { 1843 MCDisassembler::DecodeStatus Status = 1844 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1845 1846 cantFail(C.takeError()); 1847 1848 if (Status == MCDisassembler::Fail) 1849 return MCDisassembler::Fail; 1850 } 1851 KdStream << ".end_amdhsa_kernel\n"; 1852 outs() << KdStream.str(); 1853 return MCDisassembler::Success; 1854 } 1855 1856 Optional<MCDisassembler::DecodeStatus> 1857 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1858 ArrayRef<uint8_t> Bytes, uint64_t Address, 1859 raw_ostream &CStream) const { 1860 // Right now only kernel descriptor needs to be handled. 1861 // We ignore all other symbols for target specific handling. 1862 // TODO: 1863 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1864 // Object V2 and V3 when symbols are marked protected. 1865 1866 // amd_kernel_code_t for Code Object V2. 1867 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1868 Size = 256; 1869 return MCDisassembler::Fail; 1870 } 1871 1872 // Code Object V3 kernel descriptors. 1873 StringRef Name = Symbol.Name; 1874 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1875 Size = 64; // Size = 64 regardless of success or failure. 1876 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1877 } 1878 return None; 1879 } 1880 1881 //===----------------------------------------------------------------------===// 1882 // AMDGPUSymbolizer 1883 //===----------------------------------------------------------------------===// 1884 1885 // Try to find symbol name for specified label 1886 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1887 raw_ostream &/*cStream*/, int64_t Value, 1888 uint64_t /*Address*/, bool IsBranch, 1889 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1890 1891 if (!IsBranch) { 1892 return false; 1893 } 1894 1895 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1896 if (!Symbols) 1897 return false; 1898 1899 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1900 return Val.Addr == static_cast<uint64_t>(Value) && 1901 Val.Type == ELF::STT_NOTYPE; 1902 }); 1903 if (Result != Symbols->end()) { 1904 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1905 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1906 Inst.addOperand(MCOperand::createExpr(Add)); 1907 return true; 1908 } 1909 // Add to list of referenced addresses, so caller can synthesize a label. 1910 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1911 return false; 1912 } 1913 1914 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1915 int64_t Value, 1916 uint64_t Address) { 1917 llvm_unreachable("unimplemented"); 1918 } 1919 1920 //===----------------------------------------------------------------------===// 1921 // Initialization 1922 //===----------------------------------------------------------------------===// 1923 1924 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1925 LLVMOpInfoCallback /*GetOpInfo*/, 1926 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1927 void *DisInfo, 1928 MCContext *Ctx, 1929 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1930 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1931 } 1932 1933 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1934 const MCSubtargetInfo &STI, 1935 MCContext &Ctx) { 1936 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1937 } 1938 1939 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1940 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1941 createAMDGPUDisassembler); 1942 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1943 createAMDGPUSymbolizer); 1944 } 1945