1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VRegOrLds_32) 123 DECODE_OPERAND_REG(VS_32) 124 DECODE_OPERAND_REG(VS_64) 125 DECODE_OPERAND_REG(VS_128) 126 127 DECODE_OPERAND_REG(VReg_64) 128 DECODE_OPERAND_REG(VReg_96) 129 DECODE_OPERAND_REG(VReg_128) 130 DECODE_OPERAND_REG(VReg_256) 131 DECODE_OPERAND_REG(VReg_512) 132 DECODE_OPERAND_REG(VReg_1024) 133 134 DECODE_OPERAND_REG(SReg_32) 135 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 136 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 137 DECODE_OPERAND_REG(SRegOrLds_32) 138 DECODE_OPERAND_REG(SReg_64) 139 DECODE_OPERAND_REG(SReg_64_XEXEC) 140 DECODE_OPERAND_REG(SReg_128) 141 DECODE_OPERAND_REG(SReg_256) 142 DECODE_OPERAND_REG(SReg_512) 143 144 DECODE_OPERAND_REG(AGPR_32) 145 DECODE_OPERAND_REG(AReg_64) 146 DECODE_OPERAND_REG(AReg_128) 147 DECODE_OPERAND_REG(AReg_256) 148 DECODE_OPERAND_REG(AReg_512) 149 DECODE_OPERAND_REG(AReg_1024) 150 DECODE_OPERAND_REG(AV_32) 151 DECODE_OPERAND_REG(AV_64) 152 DECODE_OPERAND_REG(AV_128) 153 DECODE_OPERAND_REG(AVDst_128) 154 DECODE_OPERAND_REG(AVDst_512) 155 156 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 157 uint64_t Addr, 158 const MCDisassembler *Decoder) { 159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 160 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 161 } 162 163 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 164 uint64_t Addr, 165 const MCDisassembler *Decoder) { 166 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 167 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 168 } 169 170 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, 172 const MCDisassembler *Decoder) { 173 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 174 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 175 } 176 177 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, 179 const MCDisassembler *Decoder) { 180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 181 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 182 } 183 184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, 186 const MCDisassembler *Decoder) { 187 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 188 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 189 } 190 191 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, 193 const MCDisassembler *Decoder) { 194 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 195 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 196 } 197 198 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const MCDisassembler *Decoder) { 201 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 202 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 203 } 204 205 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, 207 const MCDisassembler *Decoder) { 208 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 209 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 210 } 211 212 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, 214 const MCDisassembler *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 220 uint64_t Addr, 221 const MCDisassembler *Decoder) { 222 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 223 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 224 } 225 226 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 227 uint64_t Addr, 228 const MCDisassembler *Decoder) { 229 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 230 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 231 } 232 233 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 234 uint64_t Addr, 235 const MCDisassembler *Decoder) { 236 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 237 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 238 } 239 240 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 241 uint64_t Addr, 242 const MCDisassembler *Decoder) { 243 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 244 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 245 } 246 247 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 248 uint64_t Addr, 249 const MCDisassembler *Decoder) { 250 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 251 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 252 } 253 254 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 255 uint64_t Addr, 256 const MCDisassembler *Decoder) { 257 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 258 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 259 } 260 261 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 262 uint64_t Addr, 263 const MCDisassembler *Decoder) { 264 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 265 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 266 } 267 268 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 269 uint64_t Addr, 270 const MCDisassembler *Decoder) { 271 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 272 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 273 } 274 275 static DecodeStatus 276 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 277 const MCDisassembler *Decoder) { 278 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 279 return addOperand( 280 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 281 } 282 283 static DecodeStatus 284 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 285 const MCDisassembler *Decoder) { 286 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand( 288 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 289 } 290 291 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 292 uint64_t Addr, const void *Decoder) { 293 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 294 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 295 } 296 297 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 298 const MCRegisterInfo *MRI) { 299 if (OpIdx < 0) 300 return false; 301 302 const MCOperand &Op = Inst.getOperand(OpIdx); 303 if (!Op.isReg()) 304 return false; 305 306 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 307 auto Reg = Sub ? Sub : Op.getReg(); 308 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 309 } 310 311 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 312 AMDGPUDisassembler::OpWidthTy Opw, 313 const MCDisassembler *Decoder) { 314 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 315 if (!DAsm->isGFX90A()) { 316 Imm &= 511; 317 } else { 318 // If atomic has both vdata and vdst their register classes are tied. 319 // The bit is decoded along with the vdst, first operand. We need to 320 // change register class to AGPR if vdst was AGPR. 321 // If a DS instruction has both data0 and data1 their register classes 322 // are also tied. 323 unsigned Opc = Inst.getOpcode(); 324 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 325 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 326 : AMDGPU::OpName::vdata; 327 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 328 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 329 if ((int)Inst.getNumOperands() == DataIdx) { 330 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 331 if (IsAGPROperand(Inst, DstIdx, MRI)) 332 Imm |= 512; 333 } 334 335 if (TSFlags & SIInstrFlags::DS) { 336 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 337 if ((int)Inst.getNumOperands() == Data2Idx && 338 IsAGPROperand(Inst, DataIdx, MRI)) 339 Imm |= 512; 340 } 341 } 342 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 343 } 344 345 static DecodeStatus 346 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 347 const MCDisassembler *Decoder) { 348 return decodeOperand_AVLdSt_Any(Inst, Imm, 349 AMDGPUDisassembler::OPW32, Decoder); 350 } 351 352 static DecodeStatus 353 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 354 const MCDisassembler *Decoder) { 355 return decodeOperand_AVLdSt_Any(Inst, Imm, 356 AMDGPUDisassembler::OPW64, Decoder); 357 } 358 359 static DecodeStatus 360 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 361 const MCDisassembler *Decoder) { 362 return decodeOperand_AVLdSt_Any(Inst, Imm, 363 AMDGPUDisassembler::OPW96, Decoder); 364 } 365 366 static DecodeStatus 367 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 368 const MCDisassembler *Decoder) { 369 return decodeOperand_AVLdSt_Any(Inst, Imm, 370 AMDGPUDisassembler::OPW128, Decoder); 371 } 372 373 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 374 uint64_t Addr, 375 const MCDisassembler *Decoder) { 376 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 377 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 378 } 379 380 #define DECODE_SDWA(DecName) \ 381 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 382 383 DECODE_SDWA(Src32) 384 DECODE_SDWA(Src16) 385 DECODE_SDWA(VopcDst) 386 387 #include "AMDGPUGenDisassemblerTables.inc" 388 389 //===----------------------------------------------------------------------===// 390 // 391 //===----------------------------------------------------------------------===// 392 393 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 394 assert(Bytes.size() >= sizeof(T)); 395 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 396 Bytes = Bytes.slice(sizeof(T)); 397 return Res; 398 } 399 400 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 401 assert(Bytes.size() >= 12); 402 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 403 Bytes.data()); 404 Bytes = Bytes.slice(8); 405 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 406 Bytes.data()); 407 Bytes = Bytes.slice(4); 408 return DecoderUInt128(Lo, Hi); 409 } 410 411 // The disassembler is greedy, so we need to check FI operand value to 412 // not parse a dpp if the correct literal is not set. For dpp16 the 413 // autogenerated decoder checks the dpp literal 414 static bool isValidDPP8(const MCInst &MI) { 415 using namespace llvm::AMDGPU::DPP; 416 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 417 assert(FiIdx != -1); 418 if ((unsigned)FiIdx >= MI.getNumOperands()) 419 return false; 420 unsigned Fi = MI.getOperand(FiIdx).getImm(); 421 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 422 } 423 424 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 425 ArrayRef<uint8_t> Bytes_, 426 uint64_t Address, 427 raw_ostream &CS) const { 428 CommentStream = &CS; 429 bool IsSDWA = false; 430 431 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 432 Bytes = Bytes_.slice(0, MaxInstBytesNum); 433 434 DecodeStatus Res = MCDisassembler::Fail; 435 do { 436 // ToDo: better to switch encoding length using some bit predicate 437 // but it is unknown yet, so try all we can 438 439 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 440 // encodings 441 if (isGFX11Plus() && Bytes.size() >= 12 ) { 442 DecoderUInt128 DecW = eat12Bytes(Bytes); 443 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 444 Address); 445 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 446 break; 447 MI = MCInst(); // clear 448 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 449 Address); 450 if (Res) { 451 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 452 convertVOP3PDPPInst(MI); 453 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 454 convertVOPCDPPInst(MI); 455 break; 456 } 457 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address); 458 if (Res) 459 break; 460 } 461 // Reinitialize Bytes 462 Bytes = Bytes_.slice(0, MaxInstBytesNum); 463 464 if (Bytes.size() >= 8) { 465 const uint64_t QW = eatBytes<uint64_t>(Bytes); 466 467 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 468 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 469 if (Res) { 470 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 471 == -1) 472 break; 473 if (convertDPP8Inst(MI) == MCDisassembler::Success) 474 break; 475 MI = MCInst(); // clear 476 } 477 } 478 479 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 480 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 481 break; 482 MI = MCInst(); // clear 483 484 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 485 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 486 break; 487 MI = MCInst(); // clear 488 489 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 490 if (Res) break; 491 492 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 493 if (Res) { 494 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 495 convertVOPCDPPInst(MI); 496 break; 497 } 498 499 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 500 if (Res) { IsSDWA = true; break; } 501 502 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 503 if (Res) { IsSDWA = true; break; } 504 505 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 506 if (Res) { IsSDWA = true; break; } 507 508 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 509 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 510 if (Res) 511 break; 512 } 513 514 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 515 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 516 // table first so we print the correct name. 517 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 518 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 519 if (Res) 520 break; 521 } 522 } 523 524 // Reinitialize Bytes as DPP64 could have eaten too much 525 Bytes = Bytes_.slice(0, MaxInstBytesNum); 526 527 // Try decode 32-bit instruction 528 if (Bytes.size() < 4) break; 529 const uint32_t DW = eatBytes<uint32_t>(Bytes); 530 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 531 if (Res) break; 532 533 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 534 if (Res) break; 535 536 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 537 if (Res) break; 538 539 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 540 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 541 if (Res) 542 break; 543 } 544 545 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 546 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 547 if (Res) break; 548 } 549 550 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 551 if (Res) break; 552 553 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 554 if (Res) break; 555 556 if (Bytes.size() < 4) break; 557 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 558 559 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 560 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 561 if (Res) 562 break; 563 } 564 565 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 566 if (Res) break; 567 568 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 569 if (Res) break; 570 571 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 572 if (Res) break; 573 574 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 575 if (Res) break; 576 577 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 578 if (Res) 579 break; 580 581 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address); 582 } while (false); 583 584 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 585 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 586 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 587 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 588 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 589 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 590 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 591 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 592 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 593 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 || 594 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 595 MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || 596 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 || 597 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx11)) { 598 // Insert dummy unused src2_modifiers. 599 insertNamedMCOperand(MI, MCOperand::createImm(0), 600 AMDGPU::OpName::src2_modifiers); 601 } 602 603 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 604 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 605 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 606 AMDGPU::OpName::cpol); 607 if (CPolPos != -1) { 608 unsigned CPol = 609 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 610 AMDGPU::CPol::GLC : 0; 611 if (MI.getNumOperands() <= (unsigned)CPolPos) { 612 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 613 AMDGPU::OpName::cpol); 614 } else if (CPol) { 615 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 616 } 617 } 618 } 619 620 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 621 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 622 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 623 // GFX90A lost TFE, its place is occupied by ACC. 624 int TFEOpIdx = 625 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 626 if (TFEOpIdx != -1) { 627 auto TFEIter = MI.begin(); 628 std::advance(TFEIter, TFEOpIdx); 629 MI.insert(TFEIter, MCOperand::createImm(0)); 630 } 631 } 632 633 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 634 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 635 int SWZOpIdx = 636 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 637 if (SWZOpIdx != -1) { 638 auto SWZIter = MI.begin(); 639 std::advance(SWZIter, SWZOpIdx); 640 MI.insert(SWZIter, MCOperand::createImm(0)); 641 } 642 } 643 644 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 645 int VAddr0Idx = 646 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 647 int RsrcIdx = 648 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 649 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 650 if (VAddr0Idx >= 0 && NSAArgs > 0) { 651 unsigned NSAWords = (NSAArgs + 3) / 4; 652 if (Bytes.size() < 4 * NSAWords) { 653 Res = MCDisassembler::Fail; 654 } else { 655 for (unsigned i = 0; i < NSAArgs; ++i) { 656 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 657 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 658 MI.insert(MI.begin() + VAddrIdx, 659 createRegOperand(VAddrRCID, Bytes[i])); 660 } 661 Bytes = Bytes.slice(4 * NSAWords); 662 } 663 } 664 665 if (Res) 666 Res = convertMIMGInst(MI); 667 } 668 669 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 670 Res = convertEXPInst(MI); 671 672 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 673 Res = convertVINTERPInst(MI); 674 675 if (Res && IsSDWA) 676 Res = convertSDWAInst(MI); 677 678 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 679 AMDGPU::OpName::vdst_in); 680 if (VDstIn_Idx != -1) { 681 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 682 MCOI::OperandConstraint::TIED_TO); 683 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 684 !MI.getOperand(VDstIn_Idx).isReg() || 685 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 686 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 687 MI.erase(&MI.getOperand(VDstIn_Idx)); 688 insertNamedMCOperand(MI, 689 MCOperand::createReg(MI.getOperand(Tied).getReg()), 690 AMDGPU::OpName::vdst_in); 691 } 692 } 693 694 int ImmLitIdx = 695 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 696 if (Res && ImmLitIdx != -1) 697 Res = convertFMAanyK(MI, ImmLitIdx); 698 699 // if the opcode was not recognized we'll assume a Size of 4 bytes 700 // (unless there are fewer bytes left) 701 Size = Res ? (MaxInstBytesNum - Bytes.size()) 702 : std::min((size_t)4, Bytes_.size()); 703 return Res; 704 } 705 706 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 707 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 708 // The MCInst still has these fields even though they are no longer encoded 709 // in the GFX11 instruction. 710 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 711 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 712 } 713 return MCDisassembler::Success; 714 } 715 716 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 717 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 718 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 719 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 720 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 721 // The MCInst has this field that is not directly encoded in the 722 // instruction. 723 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 724 } 725 return MCDisassembler::Success; 726 } 727 728 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 729 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 730 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 731 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 732 // VOPC - insert clamp 733 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 734 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 735 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 736 if (SDst != -1) { 737 // VOPC - insert VCC register as sdst 738 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 739 AMDGPU::OpName::sdst); 740 } else { 741 // VOP1/2 - insert omod if present in instruction 742 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 743 } 744 } 745 return MCDisassembler::Success; 746 } 747 748 // We must check FI == literal to reject not genuine dpp8 insts, and we must 749 // first add optional MI operands to check FI 750 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 751 unsigned Opc = MI.getOpcode(); 752 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 753 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 754 convertVOP3PDPPInst(MI); 755 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 756 AMDGPU::isVOPC64DPP(Opc)) { 757 convertVOPCDPPInst(MI); 758 } else { 759 // Insert dummy unused src modifiers. 760 if (MI.getNumOperands() < DescNumOps && 761 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 762 insertNamedMCOperand(MI, MCOperand::createImm(0), 763 AMDGPU::OpName::src0_modifiers); 764 765 if (MI.getNumOperands() < DescNumOps && 766 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 767 insertNamedMCOperand(MI, MCOperand::createImm(0), 768 AMDGPU::OpName::src1_modifiers); 769 } 770 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 771 } 772 773 // Note that before gfx10, the MIMG encoding provided no information about 774 // VADDR size. Consequently, decoded instructions always show address as if it 775 // has 1 dword, which could be not really so. 776 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 777 778 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 779 AMDGPU::OpName::vdst); 780 781 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 782 AMDGPU::OpName::vdata); 783 int VAddr0Idx = 784 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 785 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 786 AMDGPU::OpName::dmask); 787 788 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 789 AMDGPU::OpName::tfe); 790 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 791 AMDGPU::OpName::d16); 792 793 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 794 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 795 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 796 797 assert(VDataIdx != -1); 798 if (BaseOpcode->BVH) { 799 // Add A16 operand for intersect_ray instructions 800 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 801 addOperand(MI, MCOperand::createImm(1)); 802 } 803 return MCDisassembler::Success; 804 } 805 806 bool IsAtomic = (VDstIdx != -1); 807 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 808 bool IsNSA = false; 809 unsigned AddrSize = Info->VAddrDwords; 810 811 if (isGFX10Plus()) { 812 unsigned DimIdx = 813 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 814 int A16Idx = 815 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 816 const AMDGPU::MIMGDimInfo *Dim = 817 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 818 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 819 820 AddrSize = 821 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 822 823 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 824 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 825 if (!IsNSA) { 826 if (AddrSize > 8) 827 AddrSize = 16; 828 } else { 829 if (AddrSize > Info->VAddrDwords) { 830 // The NSA encoding does not contain enough operands for the combination 831 // of base opcode / dimension. Should this be an error? 832 return MCDisassembler::Success; 833 } 834 } 835 } 836 837 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 838 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 839 840 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 841 if (D16 && AMDGPU::hasPackedD16(STI)) { 842 DstSize = (DstSize + 1) / 2; 843 } 844 845 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 846 DstSize += 1; 847 848 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 849 return MCDisassembler::Success; 850 851 int NewOpcode = 852 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 853 if (NewOpcode == -1) 854 return MCDisassembler::Success; 855 856 // Widen the register to the correct number of enabled channels. 857 unsigned NewVdata = AMDGPU::NoRegister; 858 if (DstSize != Info->VDataDwords) { 859 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 860 861 // Get first subregister of VData 862 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 863 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 864 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 865 866 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 867 &MRI.getRegClass(DataRCID)); 868 if (NewVdata == AMDGPU::NoRegister) { 869 // It's possible to encode this such that the low register + enabled 870 // components exceeds the register count. 871 return MCDisassembler::Success; 872 } 873 } 874 875 // If not using NSA on GFX10+, widen address register to correct size. 876 unsigned NewVAddr0 = AMDGPU::NoRegister; 877 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 878 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 879 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 880 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 881 882 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 883 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 884 &MRI.getRegClass(AddrRCID)); 885 if (NewVAddr0 == AMDGPU::NoRegister) 886 return MCDisassembler::Success; 887 } 888 889 MI.setOpcode(NewOpcode); 890 891 if (NewVdata != AMDGPU::NoRegister) { 892 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 893 894 if (IsAtomic) { 895 // Atomic operations have an additional operand (a copy of data) 896 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 897 } 898 } 899 900 if (NewVAddr0 != AMDGPU::NoRegister) { 901 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 902 } else if (IsNSA) { 903 assert(AddrSize <= Info->VAddrDwords); 904 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 905 MI.begin() + VAddr0Idx + Info->VAddrDwords); 906 } 907 908 return MCDisassembler::Success; 909 } 910 911 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 912 // decoder only adds to src_modifiers, so manually add the bits to the other 913 // operands. 914 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 915 unsigned Opc = MI.getOpcode(); 916 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 917 918 if (MI.getNumOperands() < DescNumOps && 919 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) 920 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 921 922 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 923 AMDGPU::OpName::src1_modifiers, 924 AMDGPU::OpName::src2_modifiers}; 925 unsigned OpSel = 0; 926 unsigned OpSelHi = 0; 927 unsigned NegLo = 0; 928 unsigned NegHi = 0; 929 for (int J = 0; J < 3; ++J) { 930 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 931 if (OpIdx == -1) 932 break; 933 unsigned Val = MI.getOperand(OpIdx).getImm(); 934 935 OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 936 OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 937 NegLo |= !!(Val & SISrcMods::NEG) << J; 938 NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 939 } 940 941 if (MI.getNumOperands() < DescNumOps && 942 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) 943 insertNamedMCOperand(MI, MCOperand::createImm(OpSel), 944 AMDGPU::OpName::op_sel); 945 if (MI.getNumOperands() < DescNumOps && 946 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi) != -1) 947 insertNamedMCOperand(MI, MCOperand::createImm(OpSelHi), 948 AMDGPU::OpName::op_sel_hi); 949 if (MI.getNumOperands() < DescNumOps && 950 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1) 951 insertNamedMCOperand(MI, MCOperand::createImm(NegLo), 952 AMDGPU::OpName::neg_lo); 953 if (MI.getNumOperands() < DescNumOps && 954 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1) 955 insertNamedMCOperand(MI, MCOperand::createImm(NegHi), 956 AMDGPU::OpName::neg_hi); 957 958 return MCDisassembler::Success; 959 } 960 961 // Create dummy old operand and insert optional operands 962 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 963 unsigned Opc = MI.getOpcode(); 964 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 965 966 if (MI.getNumOperands() < DescNumOps && 967 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1) 968 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 969 970 if (MI.getNumOperands() < DescNumOps && 971 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 972 insertNamedMCOperand(MI, MCOperand::createImm(0), 973 AMDGPU::OpName::src0_modifiers); 974 975 if (MI.getNumOperands() < DescNumOps && 976 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 977 insertNamedMCOperand(MI, MCOperand::createImm(0), 978 AMDGPU::OpName::src1_modifiers); 979 return MCDisassembler::Success; 980 } 981 982 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 983 int ImmLitIdx) const { 984 assert(HasLiteral && "Should have decoded a literal"); 985 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 986 unsigned DescNumOps = Desc.getNumOperands(); 987 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 988 AMDGPU::OpName::immDeferred); 989 assert(DescNumOps == MI.getNumOperands()); 990 for (unsigned I = 0; I < DescNumOps; ++I) { 991 auto &Op = MI.getOperand(I); 992 auto OpType = Desc.OpInfo[I].OperandType; 993 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 994 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 995 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 996 IsDeferredOp) 997 Op.setImm(Literal); 998 } 999 return MCDisassembler::Success; 1000 } 1001 1002 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1003 return getContext().getRegisterInfo()-> 1004 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1005 } 1006 1007 inline 1008 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1009 const Twine& ErrMsg) const { 1010 *CommentStream << "Error: " + ErrMsg; 1011 1012 // ToDo: add support for error operands to MCInst.h 1013 // return MCOperand::createError(V); 1014 return MCOperand(); 1015 } 1016 1017 inline 1018 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1019 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1020 } 1021 1022 inline 1023 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1024 unsigned Val) const { 1025 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1026 if (Val >= RegCl.getNumRegs()) 1027 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1028 ": unknown register " + Twine(Val)); 1029 return createRegOperand(RegCl.getRegister(Val)); 1030 } 1031 1032 inline 1033 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1034 unsigned Val) const { 1035 // ToDo: SI/CI have 104 SGPRs, VI - 102 1036 // Valery: here we accepting as much as we can, let assembler sort it out 1037 int shift = 0; 1038 switch (SRegClassID) { 1039 case AMDGPU::SGPR_32RegClassID: 1040 case AMDGPU::TTMP_32RegClassID: 1041 break; 1042 case AMDGPU::SGPR_64RegClassID: 1043 case AMDGPU::TTMP_64RegClassID: 1044 shift = 1; 1045 break; 1046 case AMDGPU::SGPR_128RegClassID: 1047 case AMDGPU::TTMP_128RegClassID: 1048 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1049 // this bundle? 1050 case AMDGPU::SGPR_256RegClassID: 1051 case AMDGPU::TTMP_256RegClassID: 1052 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1053 // this bundle? 1054 case AMDGPU::SGPR_512RegClassID: 1055 case AMDGPU::TTMP_512RegClassID: 1056 shift = 2; 1057 break; 1058 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1059 // this bundle? 1060 default: 1061 llvm_unreachable("unhandled register class"); 1062 } 1063 1064 if (Val % (1 << shift)) { 1065 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1066 << ": scalar reg isn't aligned " << Val; 1067 } 1068 1069 return createRegOperand(SRegClassID, Val >> shift); 1070 } 1071 1072 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 1073 return decodeSrcOp(OPW32, Val); 1074 } 1075 1076 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 1077 return decodeSrcOp(OPW64, Val); 1078 } 1079 1080 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 1081 return decodeSrcOp(OPW128, Val); 1082 } 1083 1084 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 1085 return decodeSrcOp(OPW16, Val); 1086 } 1087 1088 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 1089 return decodeSrcOp(OPWV216, Val); 1090 } 1091 1092 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 1093 return decodeSrcOp(OPWV232, Val); 1094 } 1095 1096 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 1097 // Some instructions have operand restrictions beyond what the encoding 1098 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1099 // high bit. 1100 Val &= 255; 1101 1102 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1103 } 1104 1105 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1106 return decodeSrcOp(OPW32, Val); 1107 } 1108 1109 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1110 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1111 } 1112 1113 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1114 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1115 } 1116 1117 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1118 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1119 } 1120 1121 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1122 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1123 } 1124 1125 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1126 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1127 } 1128 1129 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1130 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1131 } 1132 1133 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1134 return decodeSrcOp(OPW32, Val); 1135 } 1136 1137 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1138 return decodeSrcOp(OPW64, Val); 1139 } 1140 1141 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1142 return decodeSrcOp(OPW128, Val); 1143 } 1144 1145 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1146 using namespace AMDGPU::EncValues; 1147 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1148 return decodeSrcOp(OPW128, Val | IS_VGPR); 1149 } 1150 1151 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1152 using namespace AMDGPU::EncValues; 1153 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1154 return decodeSrcOp(OPW512, Val | IS_VGPR); 1155 } 1156 1157 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1158 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1159 } 1160 1161 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1162 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1163 } 1164 1165 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1166 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1167 } 1168 1169 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1170 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1171 } 1172 1173 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1174 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1175 } 1176 1177 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1178 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1179 } 1180 1181 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1182 // table-gen generated disassembler doesn't care about operand types 1183 // leaving only registry class so SSrc_32 operand turns into SReg_32 1184 // and therefore we accept immediates and literals here as well 1185 return decodeSrcOp(OPW32, Val); 1186 } 1187 1188 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1189 unsigned Val) const { 1190 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1191 return decodeOperand_SReg_32(Val); 1192 } 1193 1194 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1195 unsigned Val) const { 1196 // SReg_32_XM0 is SReg_32 without EXEC_HI 1197 return decodeOperand_SReg_32(Val); 1198 } 1199 1200 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1201 // table-gen generated disassembler doesn't care about operand types 1202 // leaving only registry class so SSrc_32 operand turns into SReg_32 1203 // and therefore we accept immediates and literals here as well 1204 return decodeSrcOp(OPW32, Val); 1205 } 1206 1207 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1208 return decodeSrcOp(OPW64, Val); 1209 } 1210 1211 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1212 return decodeSrcOp(OPW64, Val); 1213 } 1214 1215 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1216 return decodeSrcOp(OPW128, Val); 1217 } 1218 1219 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1220 return decodeDstOp(OPW256, Val); 1221 } 1222 1223 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1224 return decodeDstOp(OPW512, Val); 1225 } 1226 1227 // Decode Literals for insts which always have a literal in the encoding 1228 MCOperand 1229 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1230 if (HasLiteral) { 1231 assert( 1232 AMDGPU::hasVOPD(STI) && 1233 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1234 if (Literal != Val) 1235 return errOperand(Val, "More than one unique literal is illegal"); 1236 } 1237 HasLiteral = true; 1238 Literal = Val; 1239 return MCOperand::createImm(Literal); 1240 } 1241 1242 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1243 // For now all literal constants are supposed to be unsigned integer 1244 // ToDo: deal with signed/unsigned 64-bit integer constants 1245 // ToDo: deal with float/double constants 1246 if (!HasLiteral) { 1247 if (Bytes.size() < 4) { 1248 return errOperand(0, "cannot read literal, inst bytes left " + 1249 Twine(Bytes.size())); 1250 } 1251 HasLiteral = true; 1252 Literal = eatBytes<uint32_t>(Bytes); 1253 } 1254 return MCOperand::createImm(Literal); 1255 } 1256 1257 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1258 using namespace AMDGPU::EncValues; 1259 1260 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1261 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1262 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1263 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1264 // Cast prevents negative overflow. 1265 } 1266 1267 static int64_t getInlineImmVal32(unsigned Imm) { 1268 switch (Imm) { 1269 case 240: 1270 return FloatToBits(0.5f); 1271 case 241: 1272 return FloatToBits(-0.5f); 1273 case 242: 1274 return FloatToBits(1.0f); 1275 case 243: 1276 return FloatToBits(-1.0f); 1277 case 244: 1278 return FloatToBits(2.0f); 1279 case 245: 1280 return FloatToBits(-2.0f); 1281 case 246: 1282 return FloatToBits(4.0f); 1283 case 247: 1284 return FloatToBits(-4.0f); 1285 case 248: // 1 / (2 * PI) 1286 return 0x3e22f983; 1287 default: 1288 llvm_unreachable("invalid fp inline imm"); 1289 } 1290 } 1291 1292 static int64_t getInlineImmVal64(unsigned Imm) { 1293 switch (Imm) { 1294 case 240: 1295 return DoubleToBits(0.5); 1296 case 241: 1297 return DoubleToBits(-0.5); 1298 case 242: 1299 return DoubleToBits(1.0); 1300 case 243: 1301 return DoubleToBits(-1.0); 1302 case 244: 1303 return DoubleToBits(2.0); 1304 case 245: 1305 return DoubleToBits(-2.0); 1306 case 246: 1307 return DoubleToBits(4.0); 1308 case 247: 1309 return DoubleToBits(-4.0); 1310 case 248: // 1 / (2 * PI) 1311 return 0x3fc45f306dc9c882; 1312 default: 1313 llvm_unreachable("invalid fp inline imm"); 1314 } 1315 } 1316 1317 static int64_t getInlineImmVal16(unsigned Imm) { 1318 switch (Imm) { 1319 case 240: 1320 return 0x3800; 1321 case 241: 1322 return 0xB800; 1323 case 242: 1324 return 0x3C00; 1325 case 243: 1326 return 0xBC00; 1327 case 244: 1328 return 0x4000; 1329 case 245: 1330 return 0xC000; 1331 case 246: 1332 return 0x4400; 1333 case 247: 1334 return 0xC400; 1335 case 248: // 1 / (2 * PI) 1336 return 0x3118; 1337 default: 1338 llvm_unreachable("invalid fp inline imm"); 1339 } 1340 } 1341 1342 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1343 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1344 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1345 1346 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1347 switch (Width) { 1348 case OPW32: 1349 case OPW128: // splat constants 1350 case OPW512: 1351 case OPW1024: 1352 case OPWV232: 1353 return MCOperand::createImm(getInlineImmVal32(Imm)); 1354 case OPW64: 1355 case OPW256: 1356 return MCOperand::createImm(getInlineImmVal64(Imm)); 1357 case OPW16: 1358 case OPWV216: 1359 return MCOperand::createImm(getInlineImmVal16(Imm)); 1360 default: 1361 llvm_unreachable("implement me"); 1362 } 1363 } 1364 1365 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1366 using namespace AMDGPU; 1367 1368 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1369 switch (Width) { 1370 default: // fall 1371 case OPW32: 1372 case OPW16: 1373 case OPWV216: 1374 return VGPR_32RegClassID; 1375 case OPW64: 1376 case OPWV232: return VReg_64RegClassID; 1377 case OPW96: return VReg_96RegClassID; 1378 case OPW128: return VReg_128RegClassID; 1379 case OPW160: return VReg_160RegClassID; 1380 case OPW256: return VReg_256RegClassID; 1381 case OPW512: return VReg_512RegClassID; 1382 case OPW1024: return VReg_1024RegClassID; 1383 } 1384 } 1385 1386 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1387 using namespace AMDGPU; 1388 1389 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1390 switch (Width) { 1391 default: // fall 1392 case OPW32: 1393 case OPW16: 1394 case OPWV216: 1395 return AGPR_32RegClassID; 1396 case OPW64: 1397 case OPWV232: return AReg_64RegClassID; 1398 case OPW96: return AReg_96RegClassID; 1399 case OPW128: return AReg_128RegClassID; 1400 case OPW160: return AReg_160RegClassID; 1401 case OPW256: return AReg_256RegClassID; 1402 case OPW512: return AReg_512RegClassID; 1403 case OPW1024: return AReg_1024RegClassID; 1404 } 1405 } 1406 1407 1408 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1409 using namespace AMDGPU; 1410 1411 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1412 switch (Width) { 1413 default: // fall 1414 case OPW32: 1415 case OPW16: 1416 case OPWV216: 1417 return SGPR_32RegClassID; 1418 case OPW64: 1419 case OPWV232: return SGPR_64RegClassID; 1420 case OPW96: return SGPR_96RegClassID; 1421 case OPW128: return SGPR_128RegClassID; 1422 case OPW160: return SGPR_160RegClassID; 1423 case OPW256: return SGPR_256RegClassID; 1424 case OPW512: return SGPR_512RegClassID; 1425 } 1426 } 1427 1428 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1429 using namespace AMDGPU; 1430 1431 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1432 switch (Width) { 1433 default: // fall 1434 case OPW32: 1435 case OPW16: 1436 case OPWV216: 1437 return TTMP_32RegClassID; 1438 case OPW64: 1439 case OPWV232: return TTMP_64RegClassID; 1440 case OPW128: return TTMP_128RegClassID; 1441 case OPW256: return TTMP_256RegClassID; 1442 case OPW512: return TTMP_512RegClassID; 1443 } 1444 } 1445 1446 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1447 using namespace AMDGPU::EncValues; 1448 1449 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1450 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1451 1452 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1453 } 1454 1455 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1456 bool MandatoryLiteral) const { 1457 using namespace AMDGPU::EncValues; 1458 1459 assert(Val < 1024); // enum10 1460 1461 bool IsAGPR = Val & 512; 1462 Val &= 511; 1463 1464 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1465 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1466 : getVgprClassId(Width), Val - VGPR_MIN); 1467 } 1468 if (Val <= SGPR_MAX) { 1469 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1470 static_assert(SGPR_MIN == 0, ""); 1471 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1472 } 1473 1474 int TTmpIdx = getTTmpIdx(Val); 1475 if (TTmpIdx >= 0) { 1476 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1477 } 1478 1479 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1480 return decodeIntImmed(Val); 1481 1482 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1483 return decodeFPImmed(Width, Val); 1484 1485 if (Val == LITERAL_CONST) { 1486 if (MandatoryLiteral) 1487 // Keep a sentinel value for deferred setting 1488 return MCOperand::createImm(LITERAL_CONST); 1489 else 1490 return decodeLiteralConstant(); 1491 } 1492 1493 switch (Width) { 1494 case OPW32: 1495 case OPW16: 1496 case OPWV216: 1497 return decodeSpecialReg32(Val); 1498 case OPW64: 1499 case OPWV232: 1500 return decodeSpecialReg64(Val); 1501 default: 1502 llvm_unreachable("unexpected immediate type"); 1503 } 1504 } 1505 1506 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1507 using namespace AMDGPU::EncValues; 1508 1509 assert(Val < 128); 1510 assert(Width == OPW256 || Width == OPW512); 1511 1512 if (Val <= SGPR_MAX) { 1513 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1514 static_assert(SGPR_MIN == 0, ""); 1515 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1516 } 1517 1518 int TTmpIdx = getTTmpIdx(Val); 1519 if (TTmpIdx >= 0) { 1520 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1521 } 1522 1523 llvm_unreachable("unknown dst register"); 1524 } 1525 1526 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1527 // opposite of bit 0 of DstX. 1528 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1529 unsigned Val) const { 1530 int VDstXInd = 1531 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1532 assert(VDstXInd != -1); 1533 assert(Inst.getOperand(VDstXInd).isReg()); 1534 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1535 Val |= ~XDstReg & 1; 1536 auto Width = llvm::AMDGPUDisassembler::OPW32; 1537 return createRegOperand(getVgprClassId(Width), Val); 1538 } 1539 1540 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1541 using namespace AMDGPU; 1542 1543 switch (Val) { 1544 case 102: return createRegOperand(FLAT_SCR_LO); 1545 case 103: return createRegOperand(FLAT_SCR_HI); 1546 case 104: return createRegOperand(XNACK_MASK_LO); 1547 case 105: return createRegOperand(XNACK_MASK_HI); 1548 case 106: return createRegOperand(VCC_LO); 1549 case 107: return createRegOperand(VCC_HI); 1550 case 108: return createRegOperand(TBA_LO); 1551 case 109: return createRegOperand(TBA_HI); 1552 case 110: return createRegOperand(TMA_LO); 1553 case 111: return createRegOperand(TMA_HI); 1554 case 124: 1555 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1556 case 125: 1557 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1558 case 126: return createRegOperand(EXEC_LO); 1559 case 127: return createRegOperand(EXEC_HI); 1560 case 235: return createRegOperand(SRC_SHARED_BASE); 1561 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1562 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1563 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1564 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1565 case 251: return createRegOperand(SRC_VCCZ); 1566 case 252: return createRegOperand(SRC_EXECZ); 1567 case 253: return createRegOperand(SRC_SCC); 1568 case 254: return createRegOperand(LDS_DIRECT); 1569 default: break; 1570 } 1571 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1572 } 1573 1574 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1575 using namespace AMDGPU; 1576 1577 switch (Val) { 1578 case 102: return createRegOperand(FLAT_SCR); 1579 case 104: return createRegOperand(XNACK_MASK); 1580 case 106: return createRegOperand(VCC); 1581 case 108: return createRegOperand(TBA); 1582 case 110: return createRegOperand(TMA); 1583 case 124: 1584 if (isGFX11Plus()) 1585 return createRegOperand(SGPR_NULL); 1586 break; 1587 case 125: 1588 if (!isGFX11Plus()) 1589 return createRegOperand(SGPR_NULL); 1590 break; 1591 case 126: return createRegOperand(EXEC); 1592 case 235: return createRegOperand(SRC_SHARED_BASE); 1593 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1594 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1595 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1596 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1597 case 251: return createRegOperand(SRC_VCCZ); 1598 case 252: return createRegOperand(SRC_EXECZ); 1599 case 253: return createRegOperand(SRC_SCC); 1600 default: break; 1601 } 1602 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1603 } 1604 1605 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1606 const unsigned Val) const { 1607 using namespace AMDGPU::SDWA; 1608 using namespace AMDGPU::EncValues; 1609 1610 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1611 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1612 // XXX: cast to int is needed to avoid stupid warning: 1613 // compare with unsigned is always true 1614 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1615 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1616 return createRegOperand(getVgprClassId(Width), 1617 Val - SDWA9EncValues::SRC_VGPR_MIN); 1618 } 1619 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1620 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1621 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1622 return createSRegOperand(getSgprClassId(Width), 1623 Val - SDWA9EncValues::SRC_SGPR_MIN); 1624 } 1625 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1626 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1627 return createSRegOperand(getTtmpClassId(Width), 1628 Val - SDWA9EncValues::SRC_TTMP_MIN); 1629 } 1630 1631 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1632 1633 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1634 return decodeIntImmed(SVal); 1635 1636 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1637 return decodeFPImmed(Width, SVal); 1638 1639 return decodeSpecialReg32(SVal); 1640 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1641 return createRegOperand(getVgprClassId(Width), Val); 1642 } 1643 llvm_unreachable("unsupported target"); 1644 } 1645 1646 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1647 return decodeSDWASrc(OPW16, Val); 1648 } 1649 1650 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1651 return decodeSDWASrc(OPW32, Val); 1652 } 1653 1654 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1655 using namespace AMDGPU::SDWA; 1656 1657 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1658 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1659 "SDWAVopcDst should be present only on GFX9+"); 1660 1661 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1662 1663 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1664 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1665 1666 int TTmpIdx = getTTmpIdx(Val); 1667 if (TTmpIdx >= 0) { 1668 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1669 return createSRegOperand(TTmpClsId, TTmpIdx); 1670 } else if (Val > SGPR_MAX) { 1671 return IsWave64 ? decodeSpecialReg64(Val) 1672 : decodeSpecialReg32(Val); 1673 } else { 1674 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1675 } 1676 } else { 1677 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1678 } 1679 } 1680 1681 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1682 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1683 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1684 } 1685 1686 bool AMDGPUDisassembler::isVI() const { 1687 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1688 } 1689 1690 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1691 1692 bool AMDGPUDisassembler::isGFX90A() const { 1693 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1694 } 1695 1696 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1697 1698 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1699 1700 bool AMDGPUDisassembler::isGFX10Plus() const { 1701 return AMDGPU::isGFX10Plus(STI); 1702 } 1703 1704 bool AMDGPUDisassembler::isGFX11() const { 1705 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1706 } 1707 1708 bool AMDGPUDisassembler::isGFX11Plus() const { 1709 return AMDGPU::isGFX11Plus(STI); 1710 } 1711 1712 1713 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1714 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1715 } 1716 1717 //===----------------------------------------------------------------------===// 1718 // AMDGPU specific symbol handling 1719 //===----------------------------------------------------------------------===// 1720 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1721 do { \ 1722 KdStream << Indent << DIRECTIVE " " \ 1723 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1724 } while (0) 1725 1726 // NOLINTNEXTLINE(readability-identifier-naming) 1727 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1728 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1729 using namespace amdhsa; 1730 StringRef Indent = "\t"; 1731 1732 // We cannot accurately backward compute #VGPRs used from 1733 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1734 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1735 // simply calculate the inverse of what the assembler does. 1736 1737 uint32_t GranulatedWorkitemVGPRCount = 1738 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1739 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1740 1741 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1742 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1743 1744 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1745 1746 // We cannot backward compute values used to calculate 1747 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1748 // directives can't be computed: 1749 // .amdhsa_reserve_vcc 1750 // .amdhsa_reserve_flat_scratch 1751 // .amdhsa_reserve_xnack_mask 1752 // They take their respective default values if not specified in the assembly. 1753 // 1754 // GRANULATED_WAVEFRONT_SGPR_COUNT 1755 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1756 // 1757 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1758 // are set to 0. So while disassembling we consider that: 1759 // 1760 // GRANULATED_WAVEFRONT_SGPR_COUNT 1761 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1762 // 1763 // The disassembler cannot recover the original values of those 3 directives. 1764 1765 uint32_t GranulatedWavefrontSGPRCount = 1766 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1767 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1768 1769 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1770 return MCDisassembler::Fail; 1771 1772 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1773 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1774 1775 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1776 if (!hasArchitectedFlatScratch()) 1777 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1778 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1779 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1780 1781 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1782 return MCDisassembler::Fail; 1783 1784 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1785 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1786 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1787 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1788 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1789 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1790 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1791 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1792 1793 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1794 return MCDisassembler::Fail; 1795 1796 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1797 1798 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1799 return MCDisassembler::Fail; 1800 1801 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1802 1803 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1804 return MCDisassembler::Fail; 1805 1806 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1807 return MCDisassembler::Fail; 1808 1809 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1810 1811 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1812 return MCDisassembler::Fail; 1813 1814 if (isGFX10Plus()) { 1815 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1816 COMPUTE_PGM_RSRC1_WGP_MODE); 1817 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1818 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1819 } 1820 return MCDisassembler::Success; 1821 } 1822 1823 // NOLINTNEXTLINE(readability-identifier-naming) 1824 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1825 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1826 using namespace amdhsa; 1827 StringRef Indent = "\t"; 1828 if (hasArchitectedFlatScratch()) 1829 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1830 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1831 else 1832 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1833 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1834 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1835 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1836 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1837 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1838 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1839 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1840 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1841 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1842 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1843 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1844 1845 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1846 return MCDisassembler::Fail; 1847 1848 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1849 return MCDisassembler::Fail; 1850 1851 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1852 return MCDisassembler::Fail; 1853 1854 PRINT_DIRECTIVE( 1855 ".amdhsa_exception_fp_ieee_invalid_op", 1856 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1857 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1858 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1859 PRINT_DIRECTIVE( 1860 ".amdhsa_exception_fp_ieee_div_zero", 1861 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1862 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1863 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1864 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1865 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1866 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1867 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1868 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1869 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1870 1871 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1872 return MCDisassembler::Fail; 1873 1874 return MCDisassembler::Success; 1875 } 1876 1877 #undef PRINT_DIRECTIVE 1878 1879 MCDisassembler::DecodeStatus 1880 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1881 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1882 raw_string_ostream &KdStream) const { 1883 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1884 do { \ 1885 KdStream << Indent << DIRECTIVE " " \ 1886 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1887 } while (0) 1888 1889 uint16_t TwoByteBuffer = 0; 1890 uint32_t FourByteBuffer = 0; 1891 1892 StringRef ReservedBytes; 1893 StringRef Indent = "\t"; 1894 1895 assert(Bytes.size() == 64); 1896 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1897 1898 switch (Cursor.tell()) { 1899 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1900 FourByteBuffer = DE.getU32(Cursor); 1901 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1902 << '\n'; 1903 return MCDisassembler::Success; 1904 1905 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1906 FourByteBuffer = DE.getU32(Cursor); 1907 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1908 << FourByteBuffer << '\n'; 1909 return MCDisassembler::Success; 1910 1911 case amdhsa::KERNARG_SIZE_OFFSET: 1912 FourByteBuffer = DE.getU32(Cursor); 1913 KdStream << Indent << ".amdhsa_kernarg_size " 1914 << FourByteBuffer << '\n'; 1915 return MCDisassembler::Success; 1916 1917 case amdhsa::RESERVED0_OFFSET: 1918 // 4 reserved bytes, must be 0. 1919 ReservedBytes = DE.getBytes(Cursor, 4); 1920 for (int I = 0; I < 4; ++I) { 1921 if (ReservedBytes[I] != 0) { 1922 return MCDisassembler::Fail; 1923 } 1924 } 1925 return MCDisassembler::Success; 1926 1927 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1928 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1929 // So far no directive controls this for Code Object V3, so simply skip for 1930 // disassembly. 1931 DE.skip(Cursor, 8); 1932 return MCDisassembler::Success; 1933 1934 case amdhsa::RESERVED1_OFFSET: 1935 // 20 reserved bytes, must be 0. 1936 ReservedBytes = DE.getBytes(Cursor, 20); 1937 for (int I = 0; I < 20; ++I) { 1938 if (ReservedBytes[I] != 0) { 1939 return MCDisassembler::Fail; 1940 } 1941 } 1942 return MCDisassembler::Success; 1943 1944 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1945 // COMPUTE_PGM_RSRC3 1946 // - Only set for GFX10, GFX6-9 have this to be 0. 1947 // - Currently no directives directly control this. 1948 FourByteBuffer = DE.getU32(Cursor); 1949 if (!isGFX10Plus() && FourByteBuffer) { 1950 return MCDisassembler::Fail; 1951 } 1952 return MCDisassembler::Success; 1953 1954 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1955 FourByteBuffer = DE.getU32(Cursor); 1956 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1957 MCDisassembler::Fail) { 1958 return MCDisassembler::Fail; 1959 } 1960 return MCDisassembler::Success; 1961 1962 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1963 FourByteBuffer = DE.getU32(Cursor); 1964 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1965 MCDisassembler::Fail) { 1966 return MCDisassembler::Fail; 1967 } 1968 return MCDisassembler::Success; 1969 1970 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1971 using namespace amdhsa; 1972 TwoByteBuffer = DE.getU16(Cursor); 1973 1974 if (!hasArchitectedFlatScratch()) 1975 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1976 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1977 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1978 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1979 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1980 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1981 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1982 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1983 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1984 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1985 if (!hasArchitectedFlatScratch()) 1986 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1987 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1988 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1989 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1990 1991 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1992 return MCDisassembler::Fail; 1993 1994 // Reserved for GFX9 1995 if (isGFX9() && 1996 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1997 return MCDisassembler::Fail; 1998 } else if (isGFX10Plus()) { 1999 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2000 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2001 } 2002 2003 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2004 return MCDisassembler::Fail; 2005 2006 return MCDisassembler::Success; 2007 2008 case amdhsa::RESERVED2_OFFSET: 2009 // 6 bytes from here are reserved, must be 0. 2010 ReservedBytes = DE.getBytes(Cursor, 6); 2011 for (int I = 0; I < 6; ++I) { 2012 if (ReservedBytes[I] != 0) 2013 return MCDisassembler::Fail; 2014 } 2015 return MCDisassembler::Success; 2016 2017 default: 2018 llvm_unreachable("Unhandled index. Case statements cover everything."); 2019 return MCDisassembler::Fail; 2020 } 2021 #undef PRINT_DIRECTIVE 2022 } 2023 2024 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2025 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2026 // CP microcode requires the kernel descriptor to be 64 aligned. 2027 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2028 return MCDisassembler::Fail; 2029 2030 std::string Kd; 2031 raw_string_ostream KdStream(Kd); 2032 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2033 2034 DataExtractor::Cursor C(0); 2035 while (C && C.tell() < Bytes.size()) { 2036 MCDisassembler::DecodeStatus Status = 2037 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2038 2039 cantFail(C.takeError()); 2040 2041 if (Status == MCDisassembler::Fail) 2042 return MCDisassembler::Fail; 2043 } 2044 KdStream << ".end_amdhsa_kernel\n"; 2045 outs() << KdStream.str(); 2046 return MCDisassembler::Success; 2047 } 2048 2049 Optional<MCDisassembler::DecodeStatus> 2050 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2051 ArrayRef<uint8_t> Bytes, uint64_t Address, 2052 raw_ostream &CStream) const { 2053 // Right now only kernel descriptor needs to be handled. 2054 // We ignore all other symbols for target specific handling. 2055 // TODO: 2056 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2057 // Object V2 and V3 when symbols are marked protected. 2058 2059 // amd_kernel_code_t for Code Object V2. 2060 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2061 Size = 256; 2062 return MCDisassembler::Fail; 2063 } 2064 2065 // Code Object V3 kernel descriptors. 2066 StringRef Name = Symbol.Name; 2067 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2068 Size = 64; // Size = 64 regardless of success or failure. 2069 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2070 } 2071 return None; 2072 } 2073 2074 //===----------------------------------------------------------------------===// 2075 // AMDGPUSymbolizer 2076 //===----------------------------------------------------------------------===// 2077 2078 // Try to find symbol name for specified label 2079 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2080 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2081 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2082 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2083 2084 if (!IsBranch) { 2085 return false; 2086 } 2087 2088 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2089 if (!Symbols) 2090 return false; 2091 2092 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2093 return Val.Addr == static_cast<uint64_t>(Value) && 2094 Val.Type == ELF::STT_NOTYPE; 2095 }); 2096 if (Result != Symbols->end()) { 2097 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2098 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2099 Inst.addOperand(MCOperand::createExpr(Add)); 2100 return true; 2101 } 2102 // Add to list of referenced addresses, so caller can synthesize a label. 2103 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2104 return false; 2105 } 2106 2107 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2108 int64_t Value, 2109 uint64_t Address) { 2110 llvm_unreachable("unimplemented"); 2111 } 2112 2113 //===----------------------------------------------------------------------===// 2114 // Initialization 2115 //===----------------------------------------------------------------------===// 2116 2117 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2118 LLVMOpInfoCallback /*GetOpInfo*/, 2119 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2120 void *DisInfo, 2121 MCContext *Ctx, 2122 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2123 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2124 } 2125 2126 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2127 const MCSubtargetInfo &STI, 2128 MCContext &Ctx) { 2129 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2130 } 2131 2132 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2133 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2134 createAMDGPUDisassembler); 2135 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2136 createAMDGPUSymbolizer); 2137 } 2138