1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VGPR_32_Lo128) 123 DECODE_OPERAND_REG(VRegOrLds_32) 124 DECODE_OPERAND_REG(VS_32) 125 DECODE_OPERAND_REG(VS_64) 126 DECODE_OPERAND_REG(VS_128) 127 128 DECODE_OPERAND_REG(VReg_64) 129 DECODE_OPERAND_REG(VReg_96) 130 DECODE_OPERAND_REG(VReg_128) 131 DECODE_OPERAND_REG(VReg_256) 132 DECODE_OPERAND_REG(VReg_512) 133 DECODE_OPERAND_REG(VReg_1024) 134 135 DECODE_OPERAND_REG(SReg_32) 136 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 137 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 138 DECODE_OPERAND_REG(SRegOrLds_32) 139 DECODE_OPERAND_REG(SReg_64) 140 DECODE_OPERAND_REG(SReg_64_XEXEC) 141 DECODE_OPERAND_REG(SReg_128) 142 DECODE_OPERAND_REG(SReg_256) 143 DECODE_OPERAND_REG(SReg_512) 144 145 DECODE_OPERAND_REG(AGPR_32) 146 DECODE_OPERAND_REG(AReg_64) 147 DECODE_OPERAND_REG(AReg_128) 148 DECODE_OPERAND_REG(AReg_256) 149 DECODE_OPERAND_REG(AReg_512) 150 DECODE_OPERAND_REG(AReg_1024) 151 DECODE_OPERAND_REG(AV_32) 152 DECODE_OPERAND_REG(AV_64) 153 DECODE_OPERAND_REG(AV_128) 154 DECODE_OPERAND_REG(AVDst_128) 155 DECODE_OPERAND_REG(AVDst_512) 156 157 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 158 uint64_t Addr, 159 const MCDisassembler *Decoder) { 160 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 161 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 162 } 163 164 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 165 uint64_t Addr, 166 const MCDisassembler *Decoder) { 167 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 168 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 169 } 170 171 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 172 uint64_t Addr, 173 const MCDisassembler *Decoder) { 174 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 175 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 176 } 177 178 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 179 uint64_t Addr, 180 const MCDisassembler *Decoder) { 181 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 182 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 183 } 184 185 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 186 uint64_t Addr, 187 const MCDisassembler *Decoder) { 188 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 189 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 190 } 191 192 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 193 uint64_t Addr, 194 const MCDisassembler *Decoder) { 195 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 196 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 197 } 198 199 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 200 uint64_t Addr, 201 const MCDisassembler *Decoder) { 202 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 203 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 204 } 205 206 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 207 uint64_t Addr, 208 const MCDisassembler *Decoder) { 209 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 210 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 211 } 212 213 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 214 uint64_t Addr, 215 const MCDisassembler *Decoder) { 216 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 217 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 218 } 219 220 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 221 uint64_t Addr, 222 const MCDisassembler *Decoder) { 223 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 224 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 225 } 226 227 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 228 uint64_t Addr, 229 const MCDisassembler *Decoder) { 230 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 231 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 232 } 233 234 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 235 uint64_t Addr, 236 const MCDisassembler *Decoder) { 237 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 238 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 239 } 240 241 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 242 uint64_t Addr, 243 const MCDisassembler *Decoder) { 244 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 245 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 246 } 247 248 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 249 uint64_t Addr, 250 const MCDisassembler *Decoder) { 251 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 252 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 253 } 254 255 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 256 uint64_t Addr, 257 const MCDisassembler *Decoder) { 258 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 259 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 260 } 261 262 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 263 uint64_t Addr, 264 const MCDisassembler *Decoder) { 265 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 266 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 267 } 268 269 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 270 uint64_t Addr, 271 const MCDisassembler *Decoder) { 272 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 273 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 274 } 275 276 static DecodeStatus 277 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 278 const MCDisassembler *Decoder) { 279 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 280 return addOperand( 281 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 282 } 283 284 static DecodeStatus 285 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 286 const MCDisassembler *Decoder) { 287 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 288 return addOperand( 289 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 290 } 291 292 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 293 uint64_t Addr, const void *Decoder) { 294 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 295 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 296 } 297 298 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 299 const MCRegisterInfo *MRI) { 300 if (OpIdx < 0) 301 return false; 302 303 const MCOperand &Op = Inst.getOperand(OpIdx); 304 if (!Op.isReg()) 305 return false; 306 307 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 308 auto Reg = Sub ? Sub : Op.getReg(); 309 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 310 } 311 312 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 313 AMDGPUDisassembler::OpWidthTy Opw, 314 const MCDisassembler *Decoder) { 315 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 316 if (!DAsm->isGFX90A()) { 317 Imm &= 511; 318 } else { 319 // If atomic has both vdata and vdst their register classes are tied. 320 // The bit is decoded along with the vdst, first operand. We need to 321 // change register class to AGPR if vdst was AGPR. 322 // If a DS instruction has both data0 and data1 their register classes 323 // are also tied. 324 unsigned Opc = Inst.getOpcode(); 325 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 326 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 327 : AMDGPU::OpName::vdata; 328 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 329 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 330 if ((int)Inst.getNumOperands() == DataIdx) { 331 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 332 if (IsAGPROperand(Inst, DstIdx, MRI)) 333 Imm |= 512; 334 } 335 336 if (TSFlags & SIInstrFlags::DS) { 337 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 338 if ((int)Inst.getNumOperands() == Data2Idx && 339 IsAGPROperand(Inst, DataIdx, MRI)) 340 Imm |= 512; 341 } 342 } 343 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 344 } 345 346 static DecodeStatus 347 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 348 const MCDisassembler *Decoder) { 349 return decodeOperand_AVLdSt_Any(Inst, Imm, 350 AMDGPUDisassembler::OPW32, Decoder); 351 } 352 353 static DecodeStatus 354 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 355 const MCDisassembler *Decoder) { 356 return decodeOperand_AVLdSt_Any(Inst, Imm, 357 AMDGPUDisassembler::OPW64, Decoder); 358 } 359 360 static DecodeStatus 361 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 362 const MCDisassembler *Decoder) { 363 return decodeOperand_AVLdSt_Any(Inst, Imm, 364 AMDGPUDisassembler::OPW96, Decoder); 365 } 366 367 static DecodeStatus 368 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 369 const MCDisassembler *Decoder) { 370 return decodeOperand_AVLdSt_Any(Inst, Imm, 371 AMDGPUDisassembler::OPW128, Decoder); 372 } 373 374 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 375 uint64_t Addr, 376 const MCDisassembler *Decoder) { 377 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 378 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 379 } 380 381 #define DECODE_SDWA(DecName) \ 382 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 383 384 DECODE_SDWA(Src32) 385 DECODE_SDWA(Src16) 386 DECODE_SDWA(VopcDst) 387 388 #include "AMDGPUGenDisassemblerTables.inc" 389 390 //===----------------------------------------------------------------------===// 391 // 392 //===----------------------------------------------------------------------===// 393 394 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 395 assert(Bytes.size() >= sizeof(T)); 396 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 397 Bytes = Bytes.slice(sizeof(T)); 398 return Res; 399 } 400 401 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 402 assert(Bytes.size() >= 12); 403 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 404 Bytes.data()); 405 Bytes = Bytes.slice(8); 406 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 407 Bytes.data()); 408 Bytes = Bytes.slice(4); 409 return DecoderUInt128(Lo, Hi); 410 } 411 412 // The disassembler is greedy, so we need to check FI operand value to 413 // not parse a dpp if the correct literal is not set. For dpp16 the 414 // autogenerated decoder checks the dpp literal 415 static bool isValidDPP8(const MCInst &MI) { 416 using namespace llvm::AMDGPU::DPP; 417 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 418 assert(FiIdx != -1); 419 if ((unsigned)FiIdx >= MI.getNumOperands()) 420 return false; 421 unsigned Fi = MI.getOperand(FiIdx).getImm(); 422 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 423 } 424 425 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 426 ArrayRef<uint8_t> Bytes_, 427 uint64_t Address, 428 raw_ostream &CS) const { 429 CommentStream = &CS; 430 bool IsSDWA = false; 431 432 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 433 Bytes = Bytes_.slice(0, MaxInstBytesNum); 434 435 DecodeStatus Res = MCDisassembler::Fail; 436 do { 437 // ToDo: better to switch encoding length using some bit predicate 438 // but it is unknown yet, so try all we can 439 440 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 441 // encodings 442 if (isGFX11Plus() && Bytes.size() >= 12 ) { 443 DecoderUInt128 DecW = eat12Bytes(Bytes); 444 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 445 Address); 446 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 447 break; 448 MI = MCInst(); // clear 449 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 450 Address); 451 if (Res) { 452 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 453 convertVOP3PDPPInst(MI); 454 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 455 convertVOPCDPPInst(MI); // Special VOP3 case 456 else { 457 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 458 convertVOP3DPPInst(MI); // Regular VOP3 case 459 } 460 break; 461 } 462 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address); 463 if (Res) 464 break; 465 } 466 // Reinitialize Bytes 467 Bytes = Bytes_.slice(0, MaxInstBytesNum); 468 469 if (Bytes.size() >= 8) { 470 const uint64_t QW = eatBytes<uint64_t>(Bytes); 471 472 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 473 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 474 if (Res) { 475 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 476 == -1) 477 break; 478 if (convertDPP8Inst(MI) == MCDisassembler::Success) 479 break; 480 MI = MCInst(); // clear 481 } 482 } 483 484 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 485 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 486 break; 487 MI = MCInst(); // clear 488 489 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 490 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 491 break; 492 MI = MCInst(); // clear 493 494 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 495 if (Res) break; 496 497 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 498 if (Res) { 499 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 500 convertVOPCDPPInst(MI); 501 break; 502 } 503 504 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 505 if (Res) { IsSDWA = true; break; } 506 507 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 508 if (Res) { IsSDWA = true; break; } 509 510 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 511 if (Res) { IsSDWA = true; break; } 512 513 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 514 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 515 if (Res) 516 break; 517 } 518 519 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 520 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 521 // table first so we print the correct name. 522 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 523 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 524 if (Res) 525 break; 526 } 527 } 528 529 // Reinitialize Bytes as DPP64 could have eaten too much 530 Bytes = Bytes_.slice(0, MaxInstBytesNum); 531 532 // Try decode 32-bit instruction 533 if (Bytes.size() < 4) break; 534 const uint32_t DW = eatBytes<uint32_t>(Bytes); 535 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 536 if (Res) break; 537 538 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 539 if (Res) break; 540 541 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 542 if (Res) break; 543 544 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 545 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 546 if (Res) 547 break; 548 } 549 550 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 551 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 552 if (Res) break; 553 } 554 555 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 556 if (Res) break; 557 558 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 559 if (Res) break; 560 561 if (Bytes.size() < 4) break; 562 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 563 564 if (STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts]) { 565 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address); 566 if (Res) 567 break; 568 } 569 570 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 571 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 572 if (Res) 573 break; 574 } 575 576 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 577 if (Res) break; 578 579 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 580 if (Res) break; 581 582 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 583 if (Res) break; 584 585 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 586 if (Res) break; 587 588 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 589 if (Res) 590 break; 591 592 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address); 593 } while (false); 594 595 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 596 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 597 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 598 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 599 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 600 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 601 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 602 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 603 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 604 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 || 605 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 606 MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || 607 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 || 608 MI.getOpcode() == AMDGPU::V_FMAC_F16_t16_e64_gfx11)) { 609 // Insert dummy unused src2_modifiers. 610 insertNamedMCOperand(MI, MCOperand::createImm(0), 611 AMDGPU::OpName::src2_modifiers); 612 } 613 614 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 615 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 616 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 617 AMDGPU::OpName::cpol); 618 if (CPolPos != -1) { 619 unsigned CPol = 620 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 621 AMDGPU::CPol::GLC : 0; 622 if (MI.getNumOperands() <= (unsigned)CPolPos) { 623 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 624 AMDGPU::OpName::cpol); 625 } else if (CPol) { 626 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 627 } 628 } 629 } 630 631 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 632 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 633 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 634 // GFX90A lost TFE, its place is occupied by ACC. 635 int TFEOpIdx = 636 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 637 if (TFEOpIdx != -1) { 638 auto TFEIter = MI.begin(); 639 std::advance(TFEIter, TFEOpIdx); 640 MI.insert(TFEIter, MCOperand::createImm(0)); 641 } 642 } 643 644 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 645 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 646 int SWZOpIdx = 647 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 648 if (SWZOpIdx != -1) { 649 auto SWZIter = MI.begin(); 650 std::advance(SWZIter, SWZOpIdx); 651 MI.insert(SWZIter, MCOperand::createImm(0)); 652 } 653 } 654 655 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 656 int VAddr0Idx = 657 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 658 int RsrcIdx = 659 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 660 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 661 if (VAddr0Idx >= 0 && NSAArgs > 0) { 662 unsigned NSAWords = (NSAArgs + 3) / 4; 663 if (Bytes.size() < 4 * NSAWords) { 664 Res = MCDisassembler::Fail; 665 } else { 666 for (unsigned i = 0; i < NSAArgs; ++i) { 667 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 668 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 669 MI.insert(MI.begin() + VAddrIdx, 670 createRegOperand(VAddrRCID, Bytes[i])); 671 } 672 Bytes = Bytes.slice(4 * NSAWords); 673 } 674 } 675 676 if (Res) 677 Res = convertMIMGInst(MI); 678 } 679 680 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 681 Res = convertEXPInst(MI); 682 683 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 684 Res = convertVINTERPInst(MI); 685 686 if (Res && IsSDWA) 687 Res = convertSDWAInst(MI); 688 689 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 690 AMDGPU::OpName::vdst_in); 691 if (VDstIn_Idx != -1) { 692 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 693 MCOI::OperandConstraint::TIED_TO); 694 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 695 !MI.getOperand(VDstIn_Idx).isReg() || 696 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 697 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 698 MI.erase(&MI.getOperand(VDstIn_Idx)); 699 insertNamedMCOperand(MI, 700 MCOperand::createReg(MI.getOperand(Tied).getReg()), 701 AMDGPU::OpName::vdst_in); 702 } 703 } 704 705 int ImmLitIdx = 706 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 707 bool isVOP2 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP2; 708 if (Res && ImmLitIdx != -1 && (isVOP2 || AMDGPU::isVOPD(MI.getOpcode()))) 709 Res = convertFMAanyK(MI, ImmLitIdx); 710 711 // if the opcode was not recognized we'll assume a Size of 4 bytes 712 // (unless there are fewer bytes left) 713 Size = Res ? (MaxInstBytesNum - Bytes.size()) 714 : std::min((size_t)4, Bytes_.size()); 715 return Res; 716 } 717 718 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 719 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 720 // The MCInst still has these fields even though they are no longer encoded 721 // in the GFX11 instruction. 722 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 723 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 724 } 725 return MCDisassembler::Success; 726 } 727 728 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 729 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 730 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 731 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 732 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 733 // The MCInst has this field that is not directly encoded in the 734 // instruction. 735 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 736 } 737 return MCDisassembler::Success; 738 } 739 740 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 741 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 742 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 743 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 744 // VOPC - insert clamp 745 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 746 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 747 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 748 if (SDst != -1) { 749 // VOPC - insert VCC register as sdst 750 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 751 AMDGPU::OpName::sdst); 752 } else { 753 // VOP1/2 - insert omod if present in instruction 754 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 755 } 756 } 757 return MCDisassembler::Success; 758 } 759 760 struct VOPModifiers { 761 unsigned OpSel = 0; 762 unsigned OpSelHi = 0; 763 unsigned NegLo = 0; 764 unsigned NegHi = 0; 765 }; 766 767 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 768 // Note that these values do not affect disassembler output, 769 // so this is only necessary for consistency with src_modifiers. 770 static VOPModifiers collectVOPModifiers(const MCInst &MI, 771 bool IsVOP3P = false) { 772 VOPModifiers Modifiers; 773 unsigned Opc = MI.getOpcode(); 774 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 775 AMDGPU::OpName::src1_modifiers, 776 AMDGPU::OpName::src2_modifiers}; 777 for (int J = 0; J < 3; ++J) { 778 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 779 if (OpIdx == -1) 780 continue; 781 782 unsigned Val = MI.getOperand(OpIdx).getImm(); 783 784 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 785 if (IsVOP3P) { 786 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 787 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 788 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 789 } else if (J == 0) { 790 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 791 } 792 } 793 794 return Modifiers; 795 } 796 797 // We must check FI == literal to reject not genuine dpp8 insts, and we must 798 // first add optional MI operands to check FI 799 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 800 unsigned Opc = MI.getOpcode(); 801 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 802 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 803 convertVOP3PDPPInst(MI); 804 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 805 AMDGPU::isVOPC64DPP(Opc)) { 806 convertVOPCDPPInst(MI); 807 } else if (MI.getNumOperands() < DescNumOps && 808 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { 809 auto Mods = collectVOPModifiers(MI); 810 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 811 AMDGPU::OpName::op_sel); 812 } else { 813 // Insert dummy unused src modifiers. 814 if (MI.getNumOperands() < DescNumOps && 815 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 816 insertNamedMCOperand(MI, MCOperand::createImm(0), 817 AMDGPU::OpName::src0_modifiers); 818 819 if (MI.getNumOperands() < DescNumOps && 820 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 821 insertNamedMCOperand(MI, MCOperand::createImm(0), 822 AMDGPU::OpName::src1_modifiers); 823 } 824 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 825 } 826 827 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 828 unsigned Opc = MI.getOpcode(); 829 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 830 if (MI.getNumOperands() < DescNumOps && 831 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { 832 auto Mods = collectVOPModifiers(MI); 833 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 834 AMDGPU::OpName::op_sel); 835 } 836 return MCDisassembler::Success; 837 } 838 839 // Note that before gfx10, the MIMG encoding provided no information about 840 // VADDR size. Consequently, decoded instructions always show address as if it 841 // has 1 dword, which could be not really so. 842 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 843 844 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 845 AMDGPU::OpName::vdst); 846 847 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 848 AMDGPU::OpName::vdata); 849 int VAddr0Idx = 850 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 851 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 852 AMDGPU::OpName::dmask); 853 854 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 855 AMDGPU::OpName::tfe); 856 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 857 AMDGPU::OpName::d16); 858 859 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 860 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 861 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 862 863 assert(VDataIdx != -1); 864 if (BaseOpcode->BVH) { 865 // Add A16 operand for intersect_ray instructions 866 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 867 addOperand(MI, MCOperand::createImm(1)); 868 } 869 return MCDisassembler::Success; 870 } 871 872 bool IsAtomic = (VDstIdx != -1); 873 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 874 bool IsNSA = false; 875 unsigned AddrSize = Info->VAddrDwords; 876 877 if (isGFX10Plus()) { 878 unsigned DimIdx = 879 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 880 int A16Idx = 881 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 882 const AMDGPU::MIMGDimInfo *Dim = 883 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 884 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 885 886 AddrSize = 887 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 888 889 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 890 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 891 if (!IsNSA) { 892 if (AddrSize > 8) 893 AddrSize = 16; 894 } else { 895 if (AddrSize > Info->VAddrDwords) { 896 // The NSA encoding does not contain enough operands for the combination 897 // of base opcode / dimension. Should this be an error? 898 return MCDisassembler::Success; 899 } 900 } 901 } 902 903 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 904 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 905 906 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 907 if (D16 && AMDGPU::hasPackedD16(STI)) { 908 DstSize = (DstSize + 1) / 2; 909 } 910 911 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 912 DstSize += 1; 913 914 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 915 return MCDisassembler::Success; 916 917 int NewOpcode = 918 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 919 if (NewOpcode == -1) 920 return MCDisassembler::Success; 921 922 // Widen the register to the correct number of enabled channels. 923 unsigned NewVdata = AMDGPU::NoRegister; 924 if (DstSize != Info->VDataDwords) { 925 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 926 927 // Get first subregister of VData 928 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 929 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 930 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 931 932 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 933 &MRI.getRegClass(DataRCID)); 934 if (NewVdata == AMDGPU::NoRegister) { 935 // It's possible to encode this such that the low register + enabled 936 // components exceeds the register count. 937 return MCDisassembler::Success; 938 } 939 } 940 941 // If not using NSA on GFX10+, widen address register to correct size. 942 unsigned NewVAddr0 = AMDGPU::NoRegister; 943 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 944 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 945 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 946 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 947 948 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 949 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 950 &MRI.getRegClass(AddrRCID)); 951 if (NewVAddr0 == AMDGPU::NoRegister) 952 return MCDisassembler::Success; 953 } 954 955 MI.setOpcode(NewOpcode); 956 957 if (NewVdata != AMDGPU::NoRegister) { 958 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 959 960 if (IsAtomic) { 961 // Atomic operations have an additional operand (a copy of data) 962 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 963 } 964 } 965 966 if (NewVAddr0 != AMDGPU::NoRegister) { 967 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 968 } else if (IsNSA) { 969 assert(AddrSize <= Info->VAddrDwords); 970 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 971 MI.begin() + VAddr0Idx + Info->VAddrDwords); 972 } 973 974 return MCDisassembler::Success; 975 } 976 977 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 978 // decoder only adds to src_modifiers, so manually add the bits to the other 979 // operands. 980 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 981 unsigned Opc = MI.getOpcode(); 982 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 983 auto Mods = collectVOPModifiers(MI, true); 984 985 if (MI.getNumOperands() < DescNumOps && 986 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) 987 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 988 989 if (MI.getNumOperands() < DescNumOps && 990 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) 991 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 992 AMDGPU::OpName::op_sel); 993 if (MI.getNumOperands() < DescNumOps && 994 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi) != -1) 995 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 996 AMDGPU::OpName::op_sel_hi); 997 if (MI.getNumOperands() < DescNumOps && 998 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1) 999 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1000 AMDGPU::OpName::neg_lo); 1001 if (MI.getNumOperands() < DescNumOps && 1002 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1) 1003 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1004 AMDGPU::OpName::neg_hi); 1005 1006 return MCDisassembler::Success; 1007 } 1008 1009 // Create dummy old operand and insert optional operands 1010 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1011 unsigned Opc = MI.getOpcode(); 1012 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1013 1014 if (MI.getNumOperands() < DescNumOps && 1015 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1) 1016 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1017 1018 if (MI.getNumOperands() < DescNumOps && 1019 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 1020 insertNamedMCOperand(MI, MCOperand::createImm(0), 1021 AMDGPU::OpName::src0_modifiers); 1022 1023 if (MI.getNumOperands() < DescNumOps && 1024 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 1025 insertNamedMCOperand(MI, MCOperand::createImm(0), 1026 AMDGPU::OpName::src1_modifiers); 1027 return MCDisassembler::Success; 1028 } 1029 1030 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1031 int ImmLitIdx) const { 1032 assert(HasLiteral && "Should have decoded a literal"); 1033 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1034 unsigned DescNumOps = Desc.getNumOperands(); 1035 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1036 AMDGPU::OpName::immDeferred); 1037 assert(DescNumOps == MI.getNumOperands()); 1038 for (unsigned I = 0; I < DescNumOps; ++I) { 1039 auto &Op = MI.getOperand(I); 1040 auto OpType = Desc.OpInfo[I].OperandType; 1041 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1042 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1043 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1044 IsDeferredOp) 1045 Op.setImm(Literal); 1046 } 1047 return MCDisassembler::Success; 1048 } 1049 1050 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1051 return getContext().getRegisterInfo()-> 1052 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1053 } 1054 1055 inline 1056 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1057 const Twine& ErrMsg) const { 1058 *CommentStream << "Error: " + ErrMsg; 1059 1060 // ToDo: add support for error operands to MCInst.h 1061 // return MCOperand::createError(V); 1062 return MCOperand(); 1063 } 1064 1065 inline 1066 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1067 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1068 } 1069 1070 inline 1071 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1072 unsigned Val) const { 1073 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1074 if (Val >= RegCl.getNumRegs()) 1075 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1076 ": unknown register " + Twine(Val)); 1077 return createRegOperand(RegCl.getRegister(Val)); 1078 } 1079 1080 inline 1081 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1082 unsigned Val) const { 1083 // ToDo: SI/CI have 104 SGPRs, VI - 102 1084 // Valery: here we accepting as much as we can, let assembler sort it out 1085 int shift = 0; 1086 switch (SRegClassID) { 1087 case AMDGPU::SGPR_32RegClassID: 1088 case AMDGPU::TTMP_32RegClassID: 1089 break; 1090 case AMDGPU::SGPR_64RegClassID: 1091 case AMDGPU::TTMP_64RegClassID: 1092 shift = 1; 1093 break; 1094 case AMDGPU::SGPR_128RegClassID: 1095 case AMDGPU::TTMP_128RegClassID: 1096 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1097 // this bundle? 1098 case AMDGPU::SGPR_256RegClassID: 1099 case AMDGPU::TTMP_256RegClassID: 1100 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1101 // this bundle? 1102 case AMDGPU::SGPR_512RegClassID: 1103 case AMDGPU::TTMP_512RegClassID: 1104 shift = 2; 1105 break; 1106 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1107 // this bundle? 1108 default: 1109 llvm_unreachable("unhandled register class"); 1110 } 1111 1112 if (Val % (1 << shift)) { 1113 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1114 << ": scalar reg isn't aligned " << Val; 1115 } 1116 1117 return createRegOperand(SRegClassID, Val >> shift); 1118 } 1119 1120 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 1121 return decodeSrcOp(OPW32, Val); 1122 } 1123 1124 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 1125 return decodeSrcOp(OPW64, Val); 1126 } 1127 1128 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 1129 return decodeSrcOp(OPW128, Val); 1130 } 1131 1132 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 1133 return decodeSrcOp(OPW16, Val); 1134 } 1135 1136 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 1137 return decodeSrcOp(OPWV216, Val); 1138 } 1139 1140 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 1141 return decodeSrcOp(OPWV232, Val); 1142 } 1143 1144 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32_Lo128(unsigned Val) const { 1145 return createRegOperand(AMDGPU::VGPR_32_Lo128RegClassID, Val); 1146 } 1147 1148 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 1149 // Some instructions have operand restrictions beyond what the encoding 1150 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1151 // high bit. 1152 Val &= 255; 1153 1154 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1155 } 1156 1157 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1158 return decodeSrcOp(OPW32, Val); 1159 } 1160 1161 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1162 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1163 } 1164 1165 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1166 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1167 } 1168 1169 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1170 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1171 } 1172 1173 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1174 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1175 } 1176 1177 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1178 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1179 } 1180 1181 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1182 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1183 } 1184 1185 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1186 return decodeSrcOp(OPW32, Val); 1187 } 1188 1189 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1190 return decodeSrcOp(OPW64, Val); 1191 } 1192 1193 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1194 return decodeSrcOp(OPW128, Val); 1195 } 1196 1197 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1198 using namespace AMDGPU::EncValues; 1199 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1200 return decodeSrcOp(OPW128, Val | IS_VGPR); 1201 } 1202 1203 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1204 using namespace AMDGPU::EncValues; 1205 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1206 return decodeSrcOp(OPW512, Val | IS_VGPR); 1207 } 1208 1209 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1210 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1211 } 1212 1213 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1214 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1215 } 1216 1217 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1218 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1219 } 1220 1221 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1222 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1223 } 1224 1225 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1226 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1227 } 1228 1229 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1230 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1231 } 1232 1233 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1234 // table-gen generated disassembler doesn't care about operand types 1235 // leaving only registry class so SSrc_32 operand turns into SReg_32 1236 // and therefore we accept immediates and literals here as well 1237 return decodeSrcOp(OPW32, Val); 1238 } 1239 1240 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1241 unsigned Val) const { 1242 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1243 return decodeOperand_SReg_32(Val); 1244 } 1245 1246 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1247 unsigned Val) const { 1248 // SReg_32_XM0 is SReg_32 without EXEC_HI 1249 return decodeOperand_SReg_32(Val); 1250 } 1251 1252 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1253 // table-gen generated disassembler doesn't care about operand types 1254 // leaving only registry class so SSrc_32 operand turns into SReg_32 1255 // and therefore we accept immediates and literals here as well 1256 return decodeSrcOp(OPW32, Val); 1257 } 1258 1259 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1260 return decodeSrcOp(OPW64, Val); 1261 } 1262 1263 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1264 return decodeSrcOp(OPW64, Val); 1265 } 1266 1267 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1268 return decodeSrcOp(OPW128, Val); 1269 } 1270 1271 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1272 return decodeDstOp(OPW256, Val); 1273 } 1274 1275 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1276 return decodeDstOp(OPW512, Val); 1277 } 1278 1279 // Decode Literals for insts which always have a literal in the encoding 1280 MCOperand 1281 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1282 if (HasLiteral) { 1283 assert( 1284 AMDGPU::hasVOPD(STI) && 1285 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1286 if (Literal != Val) 1287 return errOperand(Val, "More than one unique literal is illegal"); 1288 } 1289 HasLiteral = true; 1290 Literal = Val; 1291 return MCOperand::createImm(Literal); 1292 } 1293 1294 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1295 // For now all literal constants are supposed to be unsigned integer 1296 // ToDo: deal with signed/unsigned 64-bit integer constants 1297 // ToDo: deal with float/double constants 1298 if (!HasLiteral) { 1299 if (Bytes.size() < 4) { 1300 return errOperand(0, "cannot read literal, inst bytes left " + 1301 Twine(Bytes.size())); 1302 } 1303 HasLiteral = true; 1304 Literal = eatBytes<uint32_t>(Bytes); 1305 } 1306 return MCOperand::createImm(Literal); 1307 } 1308 1309 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1310 using namespace AMDGPU::EncValues; 1311 1312 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1313 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1314 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1315 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1316 // Cast prevents negative overflow. 1317 } 1318 1319 static int64_t getInlineImmVal32(unsigned Imm) { 1320 switch (Imm) { 1321 case 240: 1322 return FloatToBits(0.5f); 1323 case 241: 1324 return FloatToBits(-0.5f); 1325 case 242: 1326 return FloatToBits(1.0f); 1327 case 243: 1328 return FloatToBits(-1.0f); 1329 case 244: 1330 return FloatToBits(2.0f); 1331 case 245: 1332 return FloatToBits(-2.0f); 1333 case 246: 1334 return FloatToBits(4.0f); 1335 case 247: 1336 return FloatToBits(-4.0f); 1337 case 248: // 1 / (2 * PI) 1338 return 0x3e22f983; 1339 default: 1340 llvm_unreachable("invalid fp inline imm"); 1341 } 1342 } 1343 1344 static int64_t getInlineImmVal64(unsigned Imm) { 1345 switch (Imm) { 1346 case 240: 1347 return DoubleToBits(0.5); 1348 case 241: 1349 return DoubleToBits(-0.5); 1350 case 242: 1351 return DoubleToBits(1.0); 1352 case 243: 1353 return DoubleToBits(-1.0); 1354 case 244: 1355 return DoubleToBits(2.0); 1356 case 245: 1357 return DoubleToBits(-2.0); 1358 case 246: 1359 return DoubleToBits(4.0); 1360 case 247: 1361 return DoubleToBits(-4.0); 1362 case 248: // 1 / (2 * PI) 1363 return 0x3fc45f306dc9c882; 1364 default: 1365 llvm_unreachable("invalid fp inline imm"); 1366 } 1367 } 1368 1369 static int64_t getInlineImmVal16(unsigned Imm) { 1370 switch (Imm) { 1371 case 240: 1372 return 0x3800; 1373 case 241: 1374 return 0xB800; 1375 case 242: 1376 return 0x3C00; 1377 case 243: 1378 return 0xBC00; 1379 case 244: 1380 return 0x4000; 1381 case 245: 1382 return 0xC000; 1383 case 246: 1384 return 0x4400; 1385 case 247: 1386 return 0xC400; 1387 case 248: // 1 / (2 * PI) 1388 return 0x3118; 1389 default: 1390 llvm_unreachable("invalid fp inline imm"); 1391 } 1392 } 1393 1394 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1395 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1396 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1397 1398 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1399 switch (Width) { 1400 case OPW32: 1401 case OPW128: // splat constants 1402 case OPW512: 1403 case OPW1024: 1404 case OPWV232: 1405 return MCOperand::createImm(getInlineImmVal32(Imm)); 1406 case OPW64: 1407 case OPW256: 1408 return MCOperand::createImm(getInlineImmVal64(Imm)); 1409 case OPW16: 1410 case OPWV216: 1411 return MCOperand::createImm(getInlineImmVal16(Imm)); 1412 default: 1413 llvm_unreachable("implement me"); 1414 } 1415 } 1416 1417 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1418 using namespace AMDGPU; 1419 1420 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1421 switch (Width) { 1422 default: // fall 1423 case OPW32: 1424 case OPW16: 1425 case OPWV216: 1426 return VGPR_32RegClassID; 1427 case OPW64: 1428 case OPWV232: return VReg_64RegClassID; 1429 case OPW96: return VReg_96RegClassID; 1430 case OPW128: return VReg_128RegClassID; 1431 case OPW160: return VReg_160RegClassID; 1432 case OPW256: return VReg_256RegClassID; 1433 case OPW512: return VReg_512RegClassID; 1434 case OPW1024: return VReg_1024RegClassID; 1435 } 1436 } 1437 1438 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1439 using namespace AMDGPU; 1440 1441 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1442 switch (Width) { 1443 default: // fall 1444 case OPW32: 1445 case OPW16: 1446 case OPWV216: 1447 return AGPR_32RegClassID; 1448 case OPW64: 1449 case OPWV232: return AReg_64RegClassID; 1450 case OPW96: return AReg_96RegClassID; 1451 case OPW128: return AReg_128RegClassID; 1452 case OPW160: return AReg_160RegClassID; 1453 case OPW256: return AReg_256RegClassID; 1454 case OPW512: return AReg_512RegClassID; 1455 case OPW1024: return AReg_1024RegClassID; 1456 } 1457 } 1458 1459 1460 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1461 using namespace AMDGPU; 1462 1463 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1464 switch (Width) { 1465 default: // fall 1466 case OPW32: 1467 case OPW16: 1468 case OPWV216: 1469 return SGPR_32RegClassID; 1470 case OPW64: 1471 case OPWV232: return SGPR_64RegClassID; 1472 case OPW96: return SGPR_96RegClassID; 1473 case OPW128: return SGPR_128RegClassID; 1474 case OPW160: return SGPR_160RegClassID; 1475 case OPW256: return SGPR_256RegClassID; 1476 case OPW512: return SGPR_512RegClassID; 1477 } 1478 } 1479 1480 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1481 using namespace AMDGPU; 1482 1483 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1484 switch (Width) { 1485 default: // fall 1486 case OPW32: 1487 case OPW16: 1488 case OPWV216: 1489 return TTMP_32RegClassID; 1490 case OPW64: 1491 case OPWV232: return TTMP_64RegClassID; 1492 case OPW128: return TTMP_128RegClassID; 1493 case OPW256: return TTMP_256RegClassID; 1494 case OPW512: return TTMP_512RegClassID; 1495 } 1496 } 1497 1498 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1499 using namespace AMDGPU::EncValues; 1500 1501 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1502 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1503 1504 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1505 } 1506 1507 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1508 bool MandatoryLiteral) const { 1509 using namespace AMDGPU::EncValues; 1510 1511 assert(Val < 1024); // enum10 1512 1513 bool IsAGPR = Val & 512; 1514 Val &= 511; 1515 1516 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1517 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1518 : getVgprClassId(Width), Val - VGPR_MIN); 1519 } 1520 if (Val <= SGPR_MAX) { 1521 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1522 static_assert(SGPR_MIN == 0); 1523 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1524 } 1525 1526 int TTmpIdx = getTTmpIdx(Val); 1527 if (TTmpIdx >= 0) { 1528 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1529 } 1530 1531 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1532 return decodeIntImmed(Val); 1533 1534 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1535 return decodeFPImmed(Width, Val); 1536 1537 if (Val == LITERAL_CONST) { 1538 if (MandatoryLiteral) 1539 // Keep a sentinel value for deferred setting 1540 return MCOperand::createImm(LITERAL_CONST); 1541 else 1542 return decodeLiteralConstant(); 1543 } 1544 1545 switch (Width) { 1546 case OPW32: 1547 case OPW16: 1548 case OPWV216: 1549 return decodeSpecialReg32(Val); 1550 case OPW64: 1551 case OPWV232: 1552 return decodeSpecialReg64(Val); 1553 default: 1554 llvm_unreachable("unexpected immediate type"); 1555 } 1556 } 1557 1558 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1559 using namespace AMDGPU::EncValues; 1560 1561 assert(Val < 128); 1562 assert(Width == OPW256 || Width == OPW512); 1563 1564 if (Val <= SGPR_MAX) { 1565 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1566 static_assert(SGPR_MIN == 0); 1567 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1568 } 1569 1570 int TTmpIdx = getTTmpIdx(Val); 1571 if (TTmpIdx >= 0) { 1572 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1573 } 1574 1575 llvm_unreachable("unknown dst register"); 1576 } 1577 1578 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1579 // opposite of bit 0 of DstX. 1580 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1581 unsigned Val) const { 1582 int VDstXInd = 1583 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1584 assert(VDstXInd != -1); 1585 assert(Inst.getOperand(VDstXInd).isReg()); 1586 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1587 Val |= ~XDstReg & 1; 1588 auto Width = llvm::AMDGPUDisassembler::OPW32; 1589 return createRegOperand(getVgprClassId(Width), Val); 1590 } 1591 1592 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1593 using namespace AMDGPU; 1594 1595 switch (Val) { 1596 case 102: return createRegOperand(FLAT_SCR_LO); 1597 case 103: return createRegOperand(FLAT_SCR_HI); 1598 case 104: return createRegOperand(XNACK_MASK_LO); 1599 case 105: return createRegOperand(XNACK_MASK_HI); 1600 case 106: return createRegOperand(VCC_LO); 1601 case 107: return createRegOperand(VCC_HI); 1602 case 108: return createRegOperand(TBA_LO); 1603 case 109: return createRegOperand(TBA_HI); 1604 case 110: return createRegOperand(TMA_LO); 1605 case 111: return createRegOperand(TMA_HI); 1606 case 124: 1607 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1608 case 125: 1609 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1610 case 126: return createRegOperand(EXEC_LO); 1611 case 127: return createRegOperand(EXEC_HI); 1612 case 235: return createRegOperand(SRC_SHARED_BASE); 1613 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1614 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1615 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1616 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1617 case 251: return createRegOperand(SRC_VCCZ); 1618 case 252: return createRegOperand(SRC_EXECZ); 1619 case 253: return createRegOperand(SRC_SCC); 1620 case 254: return createRegOperand(LDS_DIRECT); 1621 default: break; 1622 } 1623 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1624 } 1625 1626 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1627 using namespace AMDGPU; 1628 1629 switch (Val) { 1630 case 102: return createRegOperand(FLAT_SCR); 1631 case 104: return createRegOperand(XNACK_MASK); 1632 case 106: return createRegOperand(VCC); 1633 case 108: return createRegOperand(TBA); 1634 case 110: return createRegOperand(TMA); 1635 case 124: 1636 if (isGFX11Plus()) 1637 return createRegOperand(SGPR_NULL); 1638 break; 1639 case 125: 1640 if (!isGFX11Plus()) 1641 return createRegOperand(SGPR_NULL); 1642 break; 1643 case 126: return createRegOperand(EXEC); 1644 case 235: return createRegOperand(SRC_SHARED_BASE); 1645 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1646 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1647 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1648 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1649 case 251: return createRegOperand(SRC_VCCZ); 1650 case 252: return createRegOperand(SRC_EXECZ); 1651 case 253: return createRegOperand(SRC_SCC); 1652 default: break; 1653 } 1654 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1655 } 1656 1657 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1658 const unsigned Val) const { 1659 using namespace AMDGPU::SDWA; 1660 using namespace AMDGPU::EncValues; 1661 1662 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1663 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1664 // XXX: cast to int is needed to avoid stupid warning: 1665 // compare with unsigned is always true 1666 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1667 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1668 return createRegOperand(getVgprClassId(Width), 1669 Val - SDWA9EncValues::SRC_VGPR_MIN); 1670 } 1671 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1672 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1673 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1674 return createSRegOperand(getSgprClassId(Width), 1675 Val - SDWA9EncValues::SRC_SGPR_MIN); 1676 } 1677 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1678 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1679 return createSRegOperand(getTtmpClassId(Width), 1680 Val - SDWA9EncValues::SRC_TTMP_MIN); 1681 } 1682 1683 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1684 1685 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1686 return decodeIntImmed(SVal); 1687 1688 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1689 return decodeFPImmed(Width, SVal); 1690 1691 return decodeSpecialReg32(SVal); 1692 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1693 return createRegOperand(getVgprClassId(Width), Val); 1694 } 1695 llvm_unreachable("unsupported target"); 1696 } 1697 1698 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1699 return decodeSDWASrc(OPW16, Val); 1700 } 1701 1702 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1703 return decodeSDWASrc(OPW32, Val); 1704 } 1705 1706 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1707 using namespace AMDGPU::SDWA; 1708 1709 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1710 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1711 "SDWAVopcDst should be present only on GFX9+"); 1712 1713 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1714 1715 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1716 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1717 1718 int TTmpIdx = getTTmpIdx(Val); 1719 if (TTmpIdx >= 0) { 1720 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1721 return createSRegOperand(TTmpClsId, TTmpIdx); 1722 } else if (Val > SGPR_MAX) { 1723 return IsWave64 ? decodeSpecialReg64(Val) 1724 : decodeSpecialReg32(Val); 1725 } else { 1726 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1727 } 1728 } else { 1729 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1730 } 1731 } 1732 1733 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1734 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1735 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1736 } 1737 1738 bool AMDGPUDisassembler::isVI() const { 1739 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1740 } 1741 1742 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1743 1744 bool AMDGPUDisassembler::isGFX90A() const { 1745 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1746 } 1747 1748 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1749 1750 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1751 1752 bool AMDGPUDisassembler::isGFX10Plus() const { 1753 return AMDGPU::isGFX10Plus(STI); 1754 } 1755 1756 bool AMDGPUDisassembler::isGFX11() const { 1757 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1758 } 1759 1760 bool AMDGPUDisassembler::isGFX11Plus() const { 1761 return AMDGPU::isGFX11Plus(STI); 1762 } 1763 1764 1765 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1766 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1767 } 1768 1769 //===----------------------------------------------------------------------===// 1770 // AMDGPU specific symbol handling 1771 //===----------------------------------------------------------------------===// 1772 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1773 do { \ 1774 KdStream << Indent << DIRECTIVE " " \ 1775 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1776 } while (0) 1777 1778 // NOLINTNEXTLINE(readability-identifier-naming) 1779 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1780 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1781 using namespace amdhsa; 1782 StringRef Indent = "\t"; 1783 1784 // We cannot accurately backward compute #VGPRs used from 1785 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1786 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1787 // simply calculate the inverse of what the assembler does. 1788 1789 uint32_t GranulatedWorkitemVGPRCount = 1790 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1791 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1792 1793 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1794 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1795 1796 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1797 1798 // We cannot backward compute values used to calculate 1799 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1800 // directives can't be computed: 1801 // .amdhsa_reserve_vcc 1802 // .amdhsa_reserve_flat_scratch 1803 // .amdhsa_reserve_xnack_mask 1804 // They take their respective default values if not specified in the assembly. 1805 // 1806 // GRANULATED_WAVEFRONT_SGPR_COUNT 1807 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1808 // 1809 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1810 // are set to 0. So while disassembling we consider that: 1811 // 1812 // GRANULATED_WAVEFRONT_SGPR_COUNT 1813 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1814 // 1815 // The disassembler cannot recover the original values of those 3 directives. 1816 1817 uint32_t GranulatedWavefrontSGPRCount = 1818 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1819 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1820 1821 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1822 return MCDisassembler::Fail; 1823 1824 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1825 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1826 1827 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1828 if (!hasArchitectedFlatScratch()) 1829 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1830 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1831 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1832 1833 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1834 return MCDisassembler::Fail; 1835 1836 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1837 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1838 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1839 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1840 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1841 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1842 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1843 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1844 1845 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1846 return MCDisassembler::Fail; 1847 1848 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1849 1850 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1851 return MCDisassembler::Fail; 1852 1853 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1854 1855 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1856 return MCDisassembler::Fail; 1857 1858 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1859 return MCDisassembler::Fail; 1860 1861 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1862 1863 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1864 return MCDisassembler::Fail; 1865 1866 if (isGFX10Plus()) { 1867 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1868 COMPUTE_PGM_RSRC1_WGP_MODE); 1869 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1870 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1871 } 1872 return MCDisassembler::Success; 1873 } 1874 1875 // NOLINTNEXTLINE(readability-identifier-naming) 1876 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1877 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1878 using namespace amdhsa; 1879 StringRef Indent = "\t"; 1880 if (hasArchitectedFlatScratch()) 1881 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1882 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1883 else 1884 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1885 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1886 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1887 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1888 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1889 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1890 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1891 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1892 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1893 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1894 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1895 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1896 1897 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1898 return MCDisassembler::Fail; 1899 1900 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1901 return MCDisassembler::Fail; 1902 1903 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1904 return MCDisassembler::Fail; 1905 1906 PRINT_DIRECTIVE( 1907 ".amdhsa_exception_fp_ieee_invalid_op", 1908 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1909 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1910 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1911 PRINT_DIRECTIVE( 1912 ".amdhsa_exception_fp_ieee_div_zero", 1913 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1914 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1915 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1916 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1917 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1918 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1919 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1920 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1921 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1922 1923 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1924 return MCDisassembler::Fail; 1925 1926 return MCDisassembler::Success; 1927 } 1928 1929 #undef PRINT_DIRECTIVE 1930 1931 MCDisassembler::DecodeStatus 1932 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1933 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1934 raw_string_ostream &KdStream) const { 1935 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1936 do { \ 1937 KdStream << Indent << DIRECTIVE " " \ 1938 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1939 } while (0) 1940 1941 uint16_t TwoByteBuffer = 0; 1942 uint32_t FourByteBuffer = 0; 1943 1944 StringRef ReservedBytes; 1945 StringRef Indent = "\t"; 1946 1947 assert(Bytes.size() == 64); 1948 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1949 1950 switch (Cursor.tell()) { 1951 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1952 FourByteBuffer = DE.getU32(Cursor); 1953 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1954 << '\n'; 1955 return MCDisassembler::Success; 1956 1957 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1958 FourByteBuffer = DE.getU32(Cursor); 1959 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1960 << FourByteBuffer << '\n'; 1961 return MCDisassembler::Success; 1962 1963 case amdhsa::KERNARG_SIZE_OFFSET: 1964 FourByteBuffer = DE.getU32(Cursor); 1965 KdStream << Indent << ".amdhsa_kernarg_size " 1966 << FourByteBuffer << '\n'; 1967 return MCDisassembler::Success; 1968 1969 case amdhsa::RESERVED0_OFFSET: 1970 // 4 reserved bytes, must be 0. 1971 ReservedBytes = DE.getBytes(Cursor, 4); 1972 for (int I = 0; I < 4; ++I) { 1973 if (ReservedBytes[I] != 0) { 1974 return MCDisassembler::Fail; 1975 } 1976 } 1977 return MCDisassembler::Success; 1978 1979 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1980 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1981 // So far no directive controls this for Code Object V3, so simply skip for 1982 // disassembly. 1983 DE.skip(Cursor, 8); 1984 return MCDisassembler::Success; 1985 1986 case amdhsa::RESERVED1_OFFSET: 1987 // 20 reserved bytes, must be 0. 1988 ReservedBytes = DE.getBytes(Cursor, 20); 1989 for (int I = 0; I < 20; ++I) { 1990 if (ReservedBytes[I] != 0) { 1991 return MCDisassembler::Fail; 1992 } 1993 } 1994 return MCDisassembler::Success; 1995 1996 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1997 // COMPUTE_PGM_RSRC3 1998 // - Only set for GFX10, GFX6-9 have this to be 0. 1999 // - Currently no directives directly control this. 2000 FourByteBuffer = DE.getU32(Cursor); 2001 if (!isGFX10Plus() && FourByteBuffer) { 2002 return MCDisassembler::Fail; 2003 } 2004 return MCDisassembler::Success; 2005 2006 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2007 FourByteBuffer = DE.getU32(Cursor); 2008 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 2009 MCDisassembler::Fail) { 2010 return MCDisassembler::Fail; 2011 } 2012 return MCDisassembler::Success; 2013 2014 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2015 FourByteBuffer = DE.getU32(Cursor); 2016 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 2017 MCDisassembler::Fail) { 2018 return MCDisassembler::Fail; 2019 } 2020 return MCDisassembler::Success; 2021 2022 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2023 using namespace amdhsa; 2024 TwoByteBuffer = DE.getU16(Cursor); 2025 2026 if (!hasArchitectedFlatScratch()) 2027 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2028 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2029 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2030 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2031 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2032 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2033 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2034 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2035 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2036 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2037 if (!hasArchitectedFlatScratch()) 2038 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2039 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2040 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2041 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2042 2043 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2044 return MCDisassembler::Fail; 2045 2046 // Reserved for GFX9 2047 if (isGFX9() && 2048 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2049 return MCDisassembler::Fail; 2050 } else if (isGFX10Plus()) { 2051 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2052 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2053 } 2054 2055 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2056 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2057 2058 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2059 return MCDisassembler::Fail; 2060 2061 return MCDisassembler::Success; 2062 2063 case amdhsa::RESERVED2_OFFSET: 2064 // 6 bytes from here are reserved, must be 0. 2065 ReservedBytes = DE.getBytes(Cursor, 6); 2066 for (int I = 0; I < 6; ++I) { 2067 if (ReservedBytes[I] != 0) 2068 return MCDisassembler::Fail; 2069 } 2070 return MCDisassembler::Success; 2071 2072 default: 2073 llvm_unreachable("Unhandled index. Case statements cover everything."); 2074 return MCDisassembler::Fail; 2075 } 2076 #undef PRINT_DIRECTIVE 2077 } 2078 2079 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2080 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2081 // CP microcode requires the kernel descriptor to be 64 aligned. 2082 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2083 return MCDisassembler::Fail; 2084 2085 std::string Kd; 2086 raw_string_ostream KdStream(Kd); 2087 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2088 2089 DataExtractor::Cursor C(0); 2090 while (C && C.tell() < Bytes.size()) { 2091 MCDisassembler::DecodeStatus Status = 2092 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2093 2094 cantFail(C.takeError()); 2095 2096 if (Status == MCDisassembler::Fail) 2097 return MCDisassembler::Fail; 2098 } 2099 KdStream << ".end_amdhsa_kernel\n"; 2100 outs() << KdStream.str(); 2101 return MCDisassembler::Success; 2102 } 2103 2104 Optional<MCDisassembler::DecodeStatus> 2105 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2106 ArrayRef<uint8_t> Bytes, uint64_t Address, 2107 raw_ostream &CStream) const { 2108 // Right now only kernel descriptor needs to be handled. 2109 // We ignore all other symbols for target specific handling. 2110 // TODO: 2111 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2112 // Object V2 and V3 when symbols are marked protected. 2113 2114 // amd_kernel_code_t for Code Object V2. 2115 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2116 Size = 256; 2117 return MCDisassembler::Fail; 2118 } 2119 2120 // Code Object V3 kernel descriptors. 2121 StringRef Name = Symbol.Name; 2122 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2123 Size = 64; // Size = 64 regardless of success or failure. 2124 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2125 } 2126 return None; 2127 } 2128 2129 //===----------------------------------------------------------------------===// 2130 // AMDGPUSymbolizer 2131 //===----------------------------------------------------------------------===// 2132 2133 // Try to find symbol name for specified label 2134 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2135 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2136 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2137 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2138 2139 if (!IsBranch) { 2140 return false; 2141 } 2142 2143 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2144 if (!Symbols) 2145 return false; 2146 2147 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2148 return Val.Addr == static_cast<uint64_t>(Value) && 2149 Val.Type == ELF::STT_NOTYPE; 2150 }); 2151 if (Result != Symbols->end()) { 2152 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2153 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2154 Inst.addOperand(MCOperand::createExpr(Add)); 2155 return true; 2156 } 2157 // Add to list of referenced addresses, so caller can synthesize a label. 2158 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2159 return false; 2160 } 2161 2162 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2163 int64_t Value, 2164 uint64_t Address) { 2165 llvm_unreachable("unimplemented"); 2166 } 2167 2168 //===----------------------------------------------------------------------===// 2169 // Initialization 2170 //===----------------------------------------------------------------------===// 2171 2172 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2173 LLVMOpInfoCallback /*GetOpInfo*/, 2174 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2175 void *DisInfo, 2176 MCContext *Ctx, 2177 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2178 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2179 } 2180 2181 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2182 const MCSubtargetInfo &STI, 2183 MCContext &Ctx) { 2184 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2185 } 2186 2187 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2188 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2189 createAMDGPUDisassembler); 2190 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2191 createAMDGPUSymbolizer); 2192 } 2193