1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "Utils/AMDGPUBaseInfo.h" 24 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCFixedLenDisassembler.h" 27 #include "llvm/MC/MCInst.h" 28 #include "llvm/MC/MCInstrDesc.h" 29 #include "llvm/MC/MCSubtargetInfo.h" 30 #include "llvm/Support/Endian.h" 31 #include "llvm/Support/Debug.h" 32 #include "llvm/Support/TargetRegistry.h" 33 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 40 41 42 inline static MCDisassembler::DecodeStatus 43 addOperand(MCInst &Inst, const MCOperand& Opnd) { 44 Inst.addOperand(Opnd); 45 return Opnd.isValid() ? 46 MCDisassembler::Success : 47 MCDisassembler::SoftFail; 48 } 49 50 #define DECODE_OPERAND2(RegClass, DecName) \ 51 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \ 52 unsigned Imm, \ 53 uint64_t /*Addr*/, \ 54 const void *Decoder) { \ 55 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 56 return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \ 57 } 58 59 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) 60 61 DECODE_OPERAND(VGPR_32) 62 DECODE_OPERAND(VS_32) 63 DECODE_OPERAND(VS_64) 64 65 DECODE_OPERAND(VReg_64) 66 DECODE_OPERAND(VReg_96) 67 DECODE_OPERAND(VReg_128) 68 69 //DECODE_OPERAND(SGPR_32) 70 DECODE_OPERAND(SReg_32) 71 DECODE_OPERAND(SReg_64) 72 DECODE_OPERAND(SReg_128) 73 DECODE_OPERAND(SReg_256) 74 //DECODE_OPERAND(SReg_512) 75 76 #define GET_SUBTARGETINFO_ENUM 77 #include "AMDGPUGenSubtargetInfo.inc" 78 #undef GET_SUBTARGETINFO_ENUM 79 80 #include "AMDGPUGenDisassemblerTables.inc" 81 82 //===----------------------------------------------------------------------===// 83 // 84 //===----------------------------------------------------------------------===// 85 86 static inline uint32_t eatB32(ArrayRef<uint8_t>& Bytes) { 87 assert(Bytes.size() >= sizeof eatB32(Bytes)); 88 const auto Res = support::endian::read32le(Bytes.data()); 89 Bytes = Bytes.slice(sizeof Res); 90 return Res; 91 } 92 93 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 94 MCInst &MI, 95 uint64_t Inst, 96 uint64_t Address) const { 97 assert(MI.getOpcode() == 0); 98 assert(MI.getNumOperands() == 0); 99 MCInst TmpInst; 100 const auto SavedBytes = Bytes; 101 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 102 MI = TmpInst; 103 return MCDisassembler::Success; 104 } 105 Bytes = SavedBytes; 106 return MCDisassembler::Fail; 107 } 108 109 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 110 ArrayRef<uint8_t> Bytes_, 111 uint64_t Address, 112 raw_ostream &WS, 113 raw_ostream &CS) const { 114 CommentStream = &CS; 115 116 // ToDo: AMDGPUDisassembler supports only VI ISA. 117 assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA."); 118 119 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 120 Bytes = Bytes_.slice(0, MaxInstBytesNum); 121 122 DecodeStatus Res = MCDisassembler::Fail; 123 do { 124 // ToDo: better to switch enc len using some bit predicate 125 // but it is unknown yet, so try all we can 126 if (Bytes.size() < 4) break; 127 const uint32_t DW = eatB32(Bytes); 128 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 129 if (Res) break; 130 131 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 132 if (Res) break; 133 134 if (Bytes.size() < 4) break; 135 const uint64_t QW = ((uint64_t)eatB32(Bytes) << 32) | DW; 136 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 137 if (Res) break; 138 139 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 140 } while (false); 141 142 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 143 return Res; 144 } 145 146 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 147 return getContext().getRegisterInfo()-> 148 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 149 } 150 151 inline 152 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 153 const Twine& ErrMsg) const { 154 *CommentStream << "Error: " + ErrMsg; 155 156 // ToDo: add support for error operands to MCInst.h 157 // return MCOperand::createError(V); 158 return MCOperand(); 159 } 160 161 inline 162 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 163 return MCOperand::createReg(RegId); 164 } 165 166 inline 167 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 168 unsigned Val) const { 169 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 170 if (Val >= RegCl.getNumRegs()) 171 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 172 ": unknown register " + Twine(Val)); 173 return createRegOperand(RegCl.getRegister(Val)); 174 } 175 176 inline 177 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 178 unsigned Val) const { 179 // ToDo: SI/CI have 104 SGPRs, VI - 102 180 // Valery: here we accepting as much as we can, let assembler sort it out 181 int shift = 0; 182 switch (SRegClassID) { 183 case AMDGPU::SGPR_32RegClassID: 184 case AMDGPU::SReg_32RegClassID: break; 185 case AMDGPU::SGPR_64RegClassID: 186 case AMDGPU::SReg_64RegClassID: shift = 1; break; 187 case AMDGPU::SReg_128RegClassID: 188 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 189 // this bundle? 190 case AMDGPU::SReg_256RegClassID: 191 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 192 // this bundle? 193 case AMDGPU::SReg_512RegClassID: shift = 2; break; 194 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 195 // this bundle? 196 default: assert(false); break; 197 } 198 if (Val % (1 << shift)) 199 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 200 << ": scalar reg isn't aligned " << Val; 201 return createRegOperand(SRegClassID, Val >> shift); 202 } 203 204 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 205 return decodeSrcOp(OP32, Val); 206 } 207 208 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 209 return decodeSrcOp(OP64, Val); 210 } 211 212 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 213 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 214 } 215 216 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 217 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 218 } 219 220 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 221 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 222 } 223 224 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 225 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 226 } 227 228 MCOperand AMDGPUDisassembler::decodeOperand_SGPR_32(unsigned Val) const { 229 return createSRegOperand(AMDGPU::SGPR_32RegClassID, Val); 230 } 231 232 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 233 // table-gen generated disassembler doesn't care about operand types 234 // leaving only registry class so SSrc_32 operand turns into SReg_32 235 // and therefore we accept immediates and literals here as well 236 return decodeSrcOp(OP32, Val); 237 } 238 239 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 240 // see decodeOperand_SReg_32 comment 241 return decodeSrcOp(OP64, Val); 242 } 243 244 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 245 return createSRegOperand(AMDGPU::SReg_128RegClassID, Val); 246 } 247 248 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 249 return createSRegOperand(AMDGPU::SReg_256RegClassID, Val); 250 } 251 252 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 253 return createSRegOperand(AMDGPU::SReg_512RegClassID, Val); 254 } 255 256 257 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 258 // For now all literal constants are supposed to be unsigned integer 259 // ToDo: deal with signed/unsigned 64-bit integer constants 260 // ToDo: deal with float/double constants 261 if (Bytes.size() < 4) 262 return errOperand(0, "cannot read literal, inst bytes left " + 263 Twine(Bytes.size())); 264 return MCOperand::createImm(eatB32(Bytes)); 265 } 266 267 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 268 assert(Imm >= 128 && Imm <= 208); 269 return MCOperand::createImm((Imm <= 192) ? (Imm - 128) : (192 - Imm)); 270 } 271 272 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) { 273 assert(Imm >= 240 && Imm <= 248); 274 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 275 // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as 276 // literal constant. 277 float V = 0.0f; 278 switch (Imm) { 279 case 240: V = 0.5f; break; 280 case 241: V = -0.5f; break; 281 case 242: V = 1.0f; break; 282 case 243: V = -1.0f; break; 283 case 244: V = 2.0f; break; 284 case 245: V = -2.0f; break; 285 case 246: V = 4.0f; break; 286 case 247: V = -4.0f; break; 287 case 248: return MCOperand::createImm(Is32 ? // 1/(2*PI) 288 0x3e22f983 : 289 0x3fc45f306dc9c882); 290 default: break; 291 } 292 return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V)); 293 } 294 295 MCOperand AMDGPUDisassembler::decodeSrcOp(bool Is32, unsigned Val) const { 296 using namespace AMDGPU; 297 assert(Val < 512); // enum9 298 299 if (Val >= 256) 300 return createRegOperand(Is32 ? VGPR_32RegClassID : VReg_64RegClassID, 301 Val - 256); 302 if (Val <= 101) 303 return createSRegOperand(Is32 ? SGPR_32RegClassID : SGPR_64RegClassID, 304 Val); 305 306 if (Val >= 128 && Val <= 208) 307 return decodeIntImmed(Val); 308 309 if (Val >= 240 && Val <= 248) 310 return decodeFPImmed(Is32, Val); 311 312 if (Val == 255) 313 return decodeLiteralConstant(); 314 315 return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val); 316 } 317 318 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 319 using namespace AMDGPU; 320 switch (Val) { 321 case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI)); 322 case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI)); 323 // ToDo: no support for xnack_mask_lo/_hi register 324 case 104: 325 case 105: break; 326 case 106: return createRegOperand(VCC_LO); 327 case 107: return createRegOperand(VCC_HI); 328 // ToDo: no support for tba_lo/_hi register 329 case 108: 330 case 109: break; 331 // ToDo: no support for tma_lo/_hi register 332 case 110: 333 case 111: break; 334 // ToDo: no support for ttmp[0:11] register 335 case 112: 336 case 113: 337 case 114: 338 case 115: 339 case 116: 340 case 117: 341 case 118: 342 case 119: 343 case 120: 344 case 121: 345 case 122: 346 case 123: break; 347 case 124: return createRegOperand(M0); 348 case 126: return createRegOperand(EXEC_LO); 349 case 127: return createRegOperand(EXEC_HI); 350 // ToDo: no support for vccz register 351 case 251: break; 352 // ToDo: no support for execz register 353 case 252: break; 354 case 253: return createRegOperand(SCC); 355 default: break; 356 } 357 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 358 } 359 360 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 361 using namespace AMDGPU; 362 switch (Val) { 363 case 102: return createRegOperand(getMCReg(FLAT_SCR, STI)); 364 case 106: return createRegOperand(VCC); 365 case 126: return createRegOperand(EXEC); 366 default: break; 367 } 368 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 369 } 370 371 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 372 const MCSubtargetInfo &STI, 373 MCContext &Ctx) { 374 return new AMDGPUDisassembler(STI, Ctx); 375 } 376 377 extern "C" void LLVMInitializeAMDGPUDisassembler() { 378 TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler); 379 } 380