1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)), 51 CodeObjectVersion(AMDGPU::getDefaultAMDHSACodeObjectVersion()) { 52 // ToDo: AMDGPUDisassembler supports only VI ISA. 53 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 54 report_fatal_error("Disassembly not yet supported for subtarget"); 55 } 56 57 void AMDGPUDisassembler::setABIVersion(unsigned Version) { 58 CodeObjectVersion = AMDGPU::getAMDHSACodeObjectVersion(Version); 59 } 60 61 inline static MCDisassembler::DecodeStatus 62 addOperand(MCInst &Inst, const MCOperand& Opnd) { 63 Inst.addOperand(Opnd); 64 return Opnd.isValid() ? 65 MCDisassembler::Success : 66 MCDisassembler::Fail; 67 } 68 69 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 70 uint16_t NameIdx) { 71 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 72 if (OpIdx != -1) { 73 auto I = MI.begin(); 74 std::advance(I, OpIdx); 75 MI.insert(I, Op); 76 } 77 return OpIdx; 78 } 79 80 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 81 uint64_t Addr, 82 const MCDisassembler *Decoder) { 83 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 84 85 // Our branches take a simm16, but we need two extra bits to account for the 86 // factor of 4. 87 APInt SignedOffset(18, Imm * 4, true); 88 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 89 90 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 91 return MCDisassembler::Success; 92 return addOperand(Inst, MCOperand::createImm(Imm)); 93 } 94 95 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 96 const MCDisassembler *Decoder) { 97 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 98 int64_t Offset; 99 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 100 Offset = SignExtend64<24>(Imm); 101 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 102 Offset = Imm & 0xFFFFF; 103 } else { // GFX9+ supports 21-bit signed offsets. 104 Offset = SignExtend64<21>(Imm); 105 } 106 return addOperand(Inst, MCOperand::createImm(Offset)); 107 } 108 109 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 110 const MCDisassembler *Decoder) { 111 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 112 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 113 } 114 115 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 116 uint64_t Addr, 117 const MCDisassembler *Decoder) { 118 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 119 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 120 } 121 122 static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr, 123 const MCDisassembler *Decoder) { 124 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 125 return addOperand(Inst, DAsm->decodeDpp8FI(Val)); 126 } 127 128 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 129 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 130 uint64_t /*Addr*/, \ 131 const MCDisassembler *Decoder) { \ 132 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 133 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 134 } 135 136 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 137 // number of register. Used by VGPR only and AGPR only operands. 138 #define DECODE_OPERAND_REG_8(RegClass) \ 139 static DecodeStatus Decode##RegClass##RegisterClass( \ 140 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 141 const MCDisassembler *Decoder) { \ 142 assert(Imm < (1 << 8) && "8-bit encoding"); \ 143 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 144 return addOperand( \ 145 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 146 } 147 148 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 149 ImmWidth) \ 150 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 151 const MCDisassembler *Decoder) { \ 152 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 153 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 154 return addOperand(Inst, \ 155 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 156 MandatoryLiteral, ImmWidth)); \ 157 } 158 159 static DecodeStatus decodeSrcOp(MCInst &Inst, unsigned EncSize, 160 AMDGPUDisassembler::OpWidthTy OpWidth, 161 unsigned Imm, unsigned EncImm, 162 bool MandatoryLiteral, unsigned ImmWidth, 163 AMDGPU::OperandSemantics Sema, 164 const MCDisassembler *Decoder) { 165 assert(Imm < (1U << EncSize) && "Operand doesn't fit encoding!"); 166 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 167 return addOperand(Inst, DAsm->decodeSrcOp(OpWidth, EncImm, MandatoryLiteral, 168 ImmWidth, Sema)); 169 } 170 171 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 172 // get register class. Used by SGPR only operands. 173 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 174 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 175 176 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 177 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 178 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 179 // Used by AV_ register classes (AGPR or VGPR only register operands). 180 template <AMDGPUDisassembler::OpWidthTy OpWidth> 181 static DecodeStatus decodeAV10(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 182 const MCDisassembler *Decoder) { 183 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm | AMDGPU::EncValues::IS_VGPR, 184 false, 0, AMDGPU::OperandSemantics::INT, Decoder); 185 } 186 187 // Decoder for Src(9-bit encoding) registers only. 188 template <AMDGPUDisassembler::OpWidthTy OpWidth> 189 static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm, 190 uint64_t /* Addr */, 191 const MCDisassembler *Decoder) { 192 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, 0, 193 AMDGPU::OperandSemantics::INT, Decoder); 194 } 195 196 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 197 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 198 // only. 199 template <AMDGPUDisassembler::OpWidthTy OpWidth> 200 static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */, 201 const MCDisassembler *Decoder) { 202 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, 0, 203 AMDGPU::OperandSemantics::INT, Decoder); 204 } 205 206 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 207 // Imm{9} is acc, registers only. 208 template <AMDGPUDisassembler::OpWidthTy OpWidth> 209 static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm, 210 uint64_t /* Addr */, 211 const MCDisassembler *Decoder) { 212 return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, false, 0, 213 AMDGPU::OperandSemantics::INT, Decoder); 214 } 215 216 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 217 // register from RegClass or immediate. Registers that don't belong to RegClass 218 // will be decoded and InstPrinter will report warning. Immediate will be 219 // decoded into constant of size ImmWidth, should match width of immediate used 220 // by OperandType (important for floating point types). 221 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 222 unsigned OperandSemantics> 223 static DecodeStatus decodeSrcRegOrImm9(MCInst &Inst, unsigned Imm, 224 uint64_t /* Addr */, 225 const MCDisassembler *Decoder) { 226 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, false, ImmWidth, 227 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 228 } 229 230 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 231 // and decode using 'enum10' from decodeSrcOp. 232 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 233 unsigned OperandSemantics> 234 static DecodeStatus decodeSrcRegOrImmA9(MCInst &Inst, unsigned Imm, 235 uint64_t /* Addr */, 236 const MCDisassembler *Decoder) { 237 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, false, ImmWidth, 238 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 239 } 240 241 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth, 242 unsigned OperandSemantics> 243 static DecodeStatus decodeSrcRegOrImmDeferred9(MCInst &Inst, unsigned Imm, 244 uint64_t /* Addr */, 245 const MCDisassembler *Decoder) { 246 return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm, true, ImmWidth, 247 (AMDGPU::OperandSemantics)OperandSemantics, Decoder); 248 } 249 250 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 251 // when RegisterClass is used as an operand. Most often used for destination 252 // operands. 253 254 DECODE_OPERAND_REG_8(VGPR_32) 255 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 256 DECODE_OPERAND_REG_8(VReg_64) 257 DECODE_OPERAND_REG_8(VReg_96) 258 DECODE_OPERAND_REG_8(VReg_128) 259 DECODE_OPERAND_REG_8(VReg_256) 260 DECODE_OPERAND_REG_8(VReg_288) 261 DECODE_OPERAND_REG_8(VReg_352) 262 DECODE_OPERAND_REG_8(VReg_384) 263 DECODE_OPERAND_REG_8(VReg_512) 264 DECODE_OPERAND_REG_8(VReg_1024) 265 266 DECODE_OPERAND_REG_7(SReg_32, OPW32) 267 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) 268 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 269 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 270 DECODE_OPERAND_REG_7(SReg_64, OPW64) 271 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 272 DECODE_OPERAND_REG_7(SReg_96, OPW96) 273 DECODE_OPERAND_REG_7(SReg_128, OPW128) 274 DECODE_OPERAND_REG_7(SReg_256, OPW256) 275 DECODE_OPERAND_REG_7(SReg_512, OPW512) 276 277 DECODE_OPERAND_REG_8(AGPR_32) 278 DECODE_OPERAND_REG_8(AReg_64) 279 DECODE_OPERAND_REG_8(AReg_128) 280 DECODE_OPERAND_REG_8(AReg_256) 281 DECODE_OPERAND_REG_8(AReg_512) 282 DECODE_OPERAND_REG_8(AReg_1024) 283 284 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 285 uint64_t /*Addr*/, 286 const MCDisassembler *Decoder) { 287 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 288 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 289 290 bool IsHi = Imm & (1 << 9); 291 unsigned RegIdx = Imm & 0xff; 292 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 293 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 294 } 295 296 static DecodeStatus 297 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 298 const MCDisassembler *Decoder) { 299 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 300 301 bool IsHi = Imm & (1 << 7); 302 unsigned RegIdx = Imm & 0x7f; 303 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 304 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 305 } 306 307 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 308 uint64_t /*Addr*/, 309 const MCDisassembler *Decoder) { 310 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 311 312 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 313 bool IsVGPR = Imm & (1 << 8); 314 if (IsVGPR) { 315 bool IsHi = Imm & (1 << 7); 316 unsigned RegIdx = Imm & 0x7f; 317 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 318 } 319 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 320 Imm & 0xFF, false, 16)); 321 } 322 323 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 324 uint64_t /*Addr*/, 325 const MCDisassembler *Decoder) { 326 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 327 328 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 329 bool IsVGPR = Imm & (1 << 8); 330 if (IsVGPR) { 331 bool IsHi = Imm & (1 << 9); 332 unsigned RegIdx = Imm & 0xff; 333 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 334 } 335 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 336 Imm & 0xFF, false, 16)); 337 } 338 339 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 340 uint64_t Addr, 341 const MCDisassembler *Decoder) { 342 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 343 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 344 } 345 346 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 347 uint64_t Addr, const void *Decoder) { 348 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 349 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 350 } 351 352 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 353 const MCRegisterInfo *MRI) { 354 if (OpIdx < 0) 355 return false; 356 357 const MCOperand &Op = Inst.getOperand(OpIdx); 358 if (!Op.isReg()) 359 return false; 360 361 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 362 auto Reg = Sub ? Sub : Op.getReg(); 363 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 364 } 365 366 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 367 AMDGPUDisassembler::OpWidthTy Opw, 368 const MCDisassembler *Decoder) { 369 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 370 if (!DAsm->isGFX90A()) { 371 Imm &= 511; 372 } else { 373 // If atomic has both vdata and vdst their register classes are tied. 374 // The bit is decoded along with the vdst, first operand. We need to 375 // change register class to AGPR if vdst was AGPR. 376 // If a DS instruction has both data0 and data1 their register classes 377 // are also tied. 378 unsigned Opc = Inst.getOpcode(); 379 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 380 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 381 : AMDGPU::OpName::vdata; 382 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 383 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 384 if ((int)Inst.getNumOperands() == DataIdx) { 385 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 386 if (IsAGPROperand(Inst, DstIdx, MRI)) 387 Imm |= 512; 388 } 389 390 if (TSFlags & SIInstrFlags::DS) { 391 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 392 if ((int)Inst.getNumOperands() == Data2Idx && 393 IsAGPROperand(Inst, DataIdx, MRI)) 394 Imm |= 512; 395 } 396 } 397 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 398 } 399 400 template <AMDGPUDisassembler::OpWidthTy Opw> 401 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 402 uint64_t /* Addr */, 403 const MCDisassembler *Decoder) { 404 return decodeAVLdSt(Inst, Imm, Opw, Decoder); 405 } 406 407 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 408 uint64_t Addr, 409 const MCDisassembler *Decoder) { 410 assert(Imm < (1 << 9) && "9-bit encoding"); 411 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 412 return addOperand(Inst, 413 DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, 414 AMDGPU::OperandSemantics::FP64)); 415 } 416 417 #define DECODE_SDWA(DecName) \ 418 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 419 420 DECODE_SDWA(Src32) 421 DECODE_SDWA(Src16) 422 DECODE_SDWA(VopcDst) 423 424 #include "AMDGPUGenDisassemblerTables.inc" 425 426 //===----------------------------------------------------------------------===// 427 // 428 //===----------------------------------------------------------------------===// 429 430 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 431 assert(Bytes.size() >= sizeof(T)); 432 const auto Res = 433 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 434 Bytes = Bytes.slice(sizeof(T)); 435 return Res; 436 } 437 438 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 439 assert(Bytes.size() >= 12); 440 uint64_t Lo = 441 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 442 Bytes = Bytes.slice(8); 443 uint64_t Hi = 444 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 445 Bytes = Bytes.slice(4); 446 return DecoderUInt128(Lo, Hi); 447 } 448 449 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 450 ArrayRef<uint8_t> Bytes_, 451 uint64_t Address, 452 raw_ostream &CS) const { 453 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 454 Bytes = Bytes_.slice(0, MaxInstBytesNum); 455 456 // In case the opcode is not recognized we'll assume a Size of 4 bytes (unless 457 // there are fewer bytes left). This will be overridden on success. 458 Size = std::min((size_t)4, Bytes_.size()); 459 460 do { 461 // ToDo: better to switch encoding length using some bit predicate 462 // but it is unknown yet, so try all we can 463 464 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 465 // encodings 466 if (isGFX11Plus() && Bytes.size() >= 12 ) { 467 DecoderUInt128 DecW = eat12Bytes(Bytes); 468 469 if (tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI, 470 DecW, Address, CS)) 471 break; 472 473 if (tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI, 474 DecW, Address, CS)) 475 break; 476 477 if (tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS)) 478 break; 479 } 480 481 // Reinitialize Bytes 482 Bytes = Bytes_.slice(0, MaxInstBytesNum); 483 484 if (Bytes.size() >= 8) { 485 const uint64_t QW = eatBytes<uint64_t>(Bytes); 486 487 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) && 488 tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS)) 489 break; 490 491 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && 492 tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS)) 493 break; 494 495 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 496 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 497 // table first so we print the correct name. 498 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts) && 499 tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS)) 500 break; 501 502 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts) && 503 tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS)) 504 break; 505 506 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) && 507 tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS)) 508 break; 509 510 if (tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS)) 511 break; 512 513 if (tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS)) 514 break; 515 516 if (tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS)) 517 break; 518 519 if (tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW, 520 Address, CS)) 521 break; 522 523 if (tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 524 Address, CS)) 525 break; 526 527 if (tryDecodeInst(DecoderTableGFX11W6464, MI, QW, Address, CS)) 528 break; 529 530 if (tryDecodeInst(DecoderTableGFX12W6464, MI, QW, Address, CS)) 531 break; 532 } 533 534 // Reinitialize Bytes 535 Bytes = Bytes_.slice(0, MaxInstBytesNum); 536 537 // Try decode 32-bit instruction 538 if (Bytes.size() >= 4) { 539 const uint32_t DW = eatBytes<uint32_t>(Bytes); 540 541 if (tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS)) 542 break; 543 544 if (tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS)) 545 break; 546 547 if (tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS)) 548 break; 549 550 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts) && 551 tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS)) 552 break; 553 554 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding) && 555 tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS)) 556 break; 557 558 if (tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS)) 559 break; 560 561 if (tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 562 Address, CS)) 563 break; 564 565 if (tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 566 Address, CS)) 567 break; 568 } 569 570 return MCDisassembler::Fail; 571 } while (false); 572 573 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DPP) { 574 if (isMacDPP(MI)) 575 convertMacDPPInst(MI); 576 577 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 578 convertVOP3PDPPInst(MI); 579 else if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) || 580 AMDGPU::isVOPC64DPP(MI.getOpcode())) 581 convertVOPCDPPInst(MI); // Special VOP3 case 582 else if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) != 583 -1) 584 convertDPP8Inst(MI); 585 else if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3) 586 convertVOP3DPPInst(MI); // Regular VOP3 case 587 } 588 589 if (AMDGPU::isMAC(MI.getOpcode())) { 590 // Insert dummy unused src2_modifiers. 591 insertNamedMCOperand(MI, MCOperand::createImm(0), 592 AMDGPU::OpName::src2_modifiers); 593 } 594 595 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp || 596 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp) { 597 // Insert dummy unused src2_modifiers. 598 insertNamedMCOperand(MI, MCOperand::createImm(0), 599 AMDGPU::OpName::src2_modifiers); 600 } 601 602 if ((MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && 603 !AMDGPU::hasGDS(STI)) { 604 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); 605 } 606 607 if (MCII->get(MI.getOpcode()).TSFlags & 608 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD)) { 609 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 610 AMDGPU::OpName::cpol); 611 if (CPolPos != -1) { 612 unsigned CPol = 613 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 614 AMDGPU::CPol::GLC : 0; 615 if (MI.getNumOperands() <= (unsigned)CPolPos) { 616 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 617 AMDGPU::OpName::cpol); 618 } else if (CPol) { 619 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 620 } 621 } 622 } 623 624 if ((MCII->get(MI.getOpcode()).TSFlags & 625 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 626 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 627 // GFX90A lost TFE, its place is occupied by ACC. 628 int TFEOpIdx = 629 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 630 if (TFEOpIdx != -1) { 631 auto TFEIter = MI.begin(); 632 std::advance(TFEIter, TFEOpIdx); 633 MI.insert(TFEIter, MCOperand::createImm(0)); 634 } 635 } 636 637 if (MCII->get(MI.getOpcode()).TSFlags & 638 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) { 639 int SWZOpIdx = 640 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 641 if (SWZOpIdx != -1) { 642 auto SWZIter = MI.begin(); 643 std::advance(SWZIter, SWZOpIdx); 644 MI.insert(SWZIter, MCOperand::createImm(0)); 645 } 646 } 647 648 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG) { 649 int VAddr0Idx = 650 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 651 int RsrcIdx = 652 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 653 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 654 if (VAddr0Idx >= 0 && NSAArgs > 0) { 655 unsigned NSAWords = (NSAArgs + 3) / 4; 656 if (Bytes.size() < 4 * NSAWords) 657 return MCDisassembler::Fail; 658 for (unsigned i = 0; i < NSAArgs; ++i) { 659 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 660 auto VAddrRCID = 661 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 662 MI.insert(MI.begin() + VAddrIdx, createRegOperand(VAddrRCID, Bytes[i])); 663 } 664 Bytes = Bytes.slice(4 * NSAWords); 665 } 666 667 convertMIMGInst(MI); 668 } 669 670 if (MCII->get(MI.getOpcode()).TSFlags & 671 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE)) 672 convertMIMGInst(MI); 673 674 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP) 675 convertEXPInst(MI); 676 677 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP) 678 convertVINTERPInst(MI); 679 680 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SDWA) 681 convertSDWAInst(MI); 682 683 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 684 AMDGPU::OpName::vdst_in); 685 if (VDstIn_Idx != -1) { 686 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 687 MCOI::OperandConstraint::TIED_TO); 688 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 689 !MI.getOperand(VDstIn_Idx).isReg() || 690 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 691 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 692 MI.erase(&MI.getOperand(VDstIn_Idx)); 693 insertNamedMCOperand(MI, 694 MCOperand::createReg(MI.getOperand(Tied).getReg()), 695 AMDGPU::OpName::vdst_in); 696 } 697 } 698 699 int ImmLitIdx = 700 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 701 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 702 if (ImmLitIdx != -1 && !IsSOPK) 703 convertFMAanyK(MI, ImmLitIdx); 704 705 Size = MaxInstBytesNum - Bytes.size(); 706 return MCDisassembler::Success; 707 } 708 709 void AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 710 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 711 // The MCInst still has these fields even though they are no longer encoded 712 // in the GFX11 instruction. 713 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 714 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 715 } 716 } 717 718 void AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 719 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 720 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 721 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 722 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 723 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 724 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 725 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 726 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 727 // The MCInst has this field that is not directly encoded in the 728 // instruction. 729 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 730 } 731 } 732 733 void AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 734 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 735 STI.hasFeature(AMDGPU::FeatureGFX10)) { 736 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 737 // VOPC - insert clamp 738 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 739 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 740 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 741 if (SDst != -1) { 742 // VOPC - insert VCC register as sdst 743 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 744 AMDGPU::OpName::sdst); 745 } else { 746 // VOP1/2 - insert omod if present in instruction 747 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 748 } 749 } 750 } 751 752 struct VOPModifiers { 753 unsigned OpSel = 0; 754 unsigned OpSelHi = 0; 755 unsigned NegLo = 0; 756 unsigned NegHi = 0; 757 }; 758 759 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 760 // Note that these values do not affect disassembler output, 761 // so this is only necessary for consistency with src_modifiers. 762 static VOPModifiers collectVOPModifiers(const MCInst &MI, 763 bool IsVOP3P = false) { 764 VOPModifiers Modifiers; 765 unsigned Opc = MI.getOpcode(); 766 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 767 AMDGPU::OpName::src1_modifiers, 768 AMDGPU::OpName::src2_modifiers}; 769 for (int J = 0; J < 3; ++J) { 770 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 771 if (OpIdx == -1) 772 continue; 773 774 unsigned Val = MI.getOperand(OpIdx).getImm(); 775 776 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 777 if (IsVOP3P) { 778 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 779 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 780 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 781 } else if (J == 0) { 782 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 783 } 784 } 785 786 return Modifiers; 787 } 788 789 // Instructions decode the op_sel/suffix bits into the src_modifier 790 // operands. Copy those bits into the src operands for true16 VGPRs. 791 void AMDGPUDisassembler::convertTrue16OpSel(MCInst &MI) const { 792 const unsigned Opc = MI.getOpcode(); 793 const MCRegisterClass &ConversionRC = 794 MRI.getRegClass(AMDGPU::VGPR_16RegClassID); 795 constexpr std::array<std::tuple<int, int, unsigned>, 4> OpAndOpMods = { 796 {{AMDGPU::OpName::src0, AMDGPU::OpName::src0_modifiers, 797 SISrcMods::OP_SEL_0}, 798 {AMDGPU::OpName::src1, AMDGPU::OpName::src1_modifiers, 799 SISrcMods::OP_SEL_0}, 800 {AMDGPU::OpName::src2, AMDGPU::OpName::src2_modifiers, 801 SISrcMods::OP_SEL_0}, 802 {AMDGPU::OpName::vdst, AMDGPU::OpName::src0_modifiers, 803 SISrcMods::DST_OP_SEL}}}; 804 for (const auto &[OpName, OpModsName, OpSelMask] : OpAndOpMods) { 805 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, OpName); 806 int OpModsIdx = AMDGPU::getNamedOperandIdx(Opc, OpModsName); 807 if (OpIdx == -1 || OpModsIdx == -1) 808 continue; 809 MCOperand &Op = MI.getOperand(OpIdx); 810 if (!Op.isReg()) 811 continue; 812 if (!ConversionRC.contains(Op.getReg())) 813 continue; 814 unsigned OpEnc = MRI.getEncodingValue(Op.getReg()); 815 const MCOperand &OpMods = MI.getOperand(OpModsIdx); 816 unsigned ModVal = OpMods.getImm(); 817 if (ModVal & OpSelMask) { // isHi 818 unsigned RegIdx = OpEnc & AMDGPU::HWEncoding::REG_IDX_MASK; 819 Op.setReg(ConversionRC.getRegister(RegIdx * 2 + 1)); 820 } 821 } 822 } 823 824 // MAC opcodes have special old and src2 operands. 825 // src2 is tied to dst, while old is not tied (but assumed to be). 826 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 827 constexpr int DST_IDX = 0; 828 auto Opcode = MI.getOpcode(); 829 const auto &Desc = MCII->get(Opcode); 830 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 831 832 if (OldIdx != -1 && Desc.getOperandConstraint( 833 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 834 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 835 assert(Desc.getOperandConstraint( 836 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 837 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 838 (void)DST_IDX; 839 return true; 840 } 841 842 return false; 843 } 844 845 // Create dummy old operand and insert dummy unused src2_modifiers 846 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 847 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 848 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 849 insertNamedMCOperand(MI, MCOperand::createImm(0), 850 AMDGPU::OpName::src2_modifiers); 851 } 852 853 void AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 854 unsigned Opc = MI.getOpcode(); 855 856 int VDstInIdx = 857 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 858 if (VDstInIdx != -1) 859 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 860 861 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 || 862 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12) 863 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 864 865 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 866 if (MI.getNumOperands() < DescNumOps && 867 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 868 convertTrue16OpSel(MI); 869 auto Mods = collectVOPModifiers(MI); 870 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 871 AMDGPU::OpName::op_sel); 872 } else { 873 // Insert dummy unused src modifiers. 874 if (MI.getNumOperands() < DescNumOps && 875 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 876 insertNamedMCOperand(MI, MCOperand::createImm(0), 877 AMDGPU::OpName::src0_modifiers); 878 879 if (MI.getNumOperands() < DescNumOps && 880 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 881 insertNamedMCOperand(MI, MCOperand::createImm(0), 882 AMDGPU::OpName::src1_modifiers); 883 } 884 } 885 886 void AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 887 convertTrue16OpSel(MI); 888 889 int VDstInIdx = 890 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 891 if (VDstInIdx != -1) 892 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 893 894 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 || 895 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12) 896 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 897 898 unsigned Opc = MI.getOpcode(); 899 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 900 if (MI.getNumOperands() < DescNumOps && 901 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 902 auto Mods = collectVOPModifiers(MI); 903 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 904 AMDGPU::OpName::op_sel); 905 } 906 } 907 908 // Note that before gfx10, the MIMG encoding provided no information about 909 // VADDR size. Consequently, decoded instructions always show address as if it 910 // has 1 dword, which could be not really so. 911 void AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 912 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 913 914 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 915 AMDGPU::OpName::vdst); 916 917 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 918 AMDGPU::OpName::vdata); 919 int VAddr0Idx = 920 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 921 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 922 : AMDGPU::OpName::rsrc; 923 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 924 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 925 AMDGPU::OpName::dmask); 926 927 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 928 AMDGPU::OpName::tfe); 929 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 930 AMDGPU::OpName::d16); 931 932 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 933 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 934 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 935 936 assert(VDataIdx != -1); 937 if (BaseOpcode->BVH) { 938 // Add A16 operand for intersect_ray instructions 939 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 940 return; 941 } 942 943 bool IsAtomic = (VDstIdx != -1); 944 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 945 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 946 bool IsNSA = false; 947 bool IsPartialNSA = false; 948 unsigned AddrSize = Info->VAddrDwords; 949 950 if (isGFX10Plus()) { 951 unsigned DimIdx = 952 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 953 int A16Idx = 954 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 955 const AMDGPU::MIMGDimInfo *Dim = 956 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 957 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 958 959 AddrSize = 960 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 961 962 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 963 // VIMAGE insts other than BVH never use vaddr4. 964 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 965 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 966 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 967 if (!IsNSA) { 968 if (!IsVSample && AddrSize > 12) 969 AddrSize = 16; 970 } else { 971 if (AddrSize > Info->VAddrDwords) { 972 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 973 // The NSA encoding does not contain enough operands for the 974 // combination of base opcode / dimension. Should this be an error? 975 return; 976 } 977 IsPartialNSA = true; 978 } 979 } 980 } 981 982 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 983 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 984 985 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 986 if (D16 && AMDGPU::hasPackedD16(STI)) { 987 DstSize = (DstSize + 1) / 2; 988 } 989 990 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 991 DstSize += 1; 992 993 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 994 return; 995 996 int NewOpcode = 997 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 998 if (NewOpcode == -1) 999 return; 1000 1001 // Widen the register to the correct number of enabled channels. 1002 unsigned NewVdata = AMDGPU::NoRegister; 1003 if (DstSize != Info->VDataDwords) { 1004 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1005 1006 // Get first subregister of VData 1007 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1008 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1009 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1010 1011 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1012 &MRI.getRegClass(DataRCID)); 1013 if (NewVdata == AMDGPU::NoRegister) { 1014 // It's possible to encode this such that the low register + enabled 1015 // components exceeds the register count. 1016 return; 1017 } 1018 } 1019 1020 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1021 // If using partial NSA on GFX11+ widen last address register. 1022 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1023 unsigned NewVAddrSA = AMDGPU::NoRegister; 1024 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1025 AddrSize != Info->VAddrDwords) { 1026 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1027 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1028 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1029 1030 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1031 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1032 &MRI.getRegClass(AddrRCID)); 1033 if (!NewVAddrSA) 1034 return; 1035 } 1036 1037 MI.setOpcode(NewOpcode); 1038 1039 if (NewVdata != AMDGPU::NoRegister) { 1040 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1041 1042 if (IsAtomic) { 1043 // Atomic operations have an additional operand (a copy of data) 1044 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1045 } 1046 } 1047 1048 if (NewVAddrSA) { 1049 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1050 } else if (IsNSA) { 1051 assert(AddrSize <= Info->VAddrDwords); 1052 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1053 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1054 } 1055 } 1056 1057 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1058 // decoder only adds to src_modifiers, so manually add the bits to the other 1059 // operands. 1060 void AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1061 unsigned Opc = MI.getOpcode(); 1062 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1063 auto Mods = collectVOPModifiers(MI, true); 1064 1065 if (MI.getNumOperands() < DescNumOps && 1066 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1067 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1068 1069 if (MI.getNumOperands() < DescNumOps && 1070 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1071 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1072 AMDGPU::OpName::op_sel); 1073 if (MI.getNumOperands() < DescNumOps && 1074 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1075 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1076 AMDGPU::OpName::op_sel_hi); 1077 if (MI.getNumOperands() < DescNumOps && 1078 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1079 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1080 AMDGPU::OpName::neg_lo); 1081 if (MI.getNumOperands() < DescNumOps && 1082 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1083 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1084 AMDGPU::OpName::neg_hi); 1085 } 1086 1087 // Create dummy old operand and insert optional operands 1088 void AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1089 unsigned Opc = MI.getOpcode(); 1090 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1091 1092 if (MI.getNumOperands() < DescNumOps && 1093 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1094 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1095 1096 if (MI.getNumOperands() < DescNumOps && 1097 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1098 insertNamedMCOperand(MI, MCOperand::createImm(0), 1099 AMDGPU::OpName::src0_modifiers); 1100 1101 if (MI.getNumOperands() < DescNumOps && 1102 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1103 insertNamedMCOperand(MI, MCOperand::createImm(0), 1104 AMDGPU::OpName::src1_modifiers); 1105 } 1106 1107 void AMDGPUDisassembler::convertFMAanyK(MCInst &MI, int ImmLitIdx) const { 1108 assert(HasLiteral && "Should have decoded a literal"); 1109 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1110 unsigned DescNumOps = Desc.getNumOperands(); 1111 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1112 AMDGPU::OpName::immDeferred); 1113 assert(DescNumOps == MI.getNumOperands()); 1114 for (unsigned I = 0; I < DescNumOps; ++I) { 1115 auto &Op = MI.getOperand(I); 1116 auto OpType = Desc.operands()[I].OperandType; 1117 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1118 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1119 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1120 IsDeferredOp) 1121 Op.setImm(Literal); 1122 } 1123 } 1124 1125 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1126 return getContext().getRegisterInfo()-> 1127 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1128 } 1129 1130 inline 1131 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1132 const Twine& ErrMsg) const { 1133 *CommentStream << "Error: " + ErrMsg; 1134 1135 // ToDo: add support for error operands to MCInst.h 1136 // return MCOperand::createError(V); 1137 return MCOperand(); 1138 } 1139 1140 inline 1141 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1142 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1143 } 1144 1145 inline 1146 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1147 unsigned Val) const { 1148 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1149 if (Val >= RegCl.getNumRegs()) 1150 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1151 ": unknown register " + Twine(Val)); 1152 return createRegOperand(RegCl.getRegister(Val)); 1153 } 1154 1155 inline 1156 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1157 unsigned Val) const { 1158 // ToDo: SI/CI have 104 SGPRs, VI - 102 1159 // Valery: here we accepting as much as we can, let assembler sort it out 1160 int shift = 0; 1161 switch (SRegClassID) { 1162 case AMDGPU::SGPR_32RegClassID: 1163 case AMDGPU::TTMP_32RegClassID: 1164 break; 1165 case AMDGPU::SGPR_64RegClassID: 1166 case AMDGPU::TTMP_64RegClassID: 1167 shift = 1; 1168 break; 1169 case AMDGPU::SGPR_96RegClassID: 1170 case AMDGPU::TTMP_96RegClassID: 1171 case AMDGPU::SGPR_128RegClassID: 1172 case AMDGPU::TTMP_128RegClassID: 1173 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1174 // this bundle? 1175 case AMDGPU::SGPR_256RegClassID: 1176 case AMDGPU::TTMP_256RegClassID: 1177 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1178 // this bundle? 1179 case AMDGPU::SGPR_288RegClassID: 1180 case AMDGPU::TTMP_288RegClassID: 1181 case AMDGPU::SGPR_320RegClassID: 1182 case AMDGPU::TTMP_320RegClassID: 1183 case AMDGPU::SGPR_352RegClassID: 1184 case AMDGPU::TTMP_352RegClassID: 1185 case AMDGPU::SGPR_384RegClassID: 1186 case AMDGPU::TTMP_384RegClassID: 1187 case AMDGPU::SGPR_512RegClassID: 1188 case AMDGPU::TTMP_512RegClassID: 1189 shift = 2; 1190 break; 1191 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1192 // this bundle? 1193 default: 1194 llvm_unreachable("unhandled register class"); 1195 } 1196 1197 if (Val % (1 << shift)) { 1198 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1199 << ": scalar reg isn't aligned " << Val; 1200 } 1201 1202 return createRegOperand(SRegClassID, Val >> shift); 1203 } 1204 1205 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1206 bool IsHi) const { 1207 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); 1208 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); 1209 } 1210 1211 // Decode Literals for insts which always have a literal in the encoding 1212 MCOperand 1213 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1214 if (HasLiteral) { 1215 assert( 1216 AMDGPU::hasVOPD(STI) && 1217 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1218 if (Literal != Val) 1219 return errOperand(Val, "More than one unique literal is illegal"); 1220 } 1221 HasLiteral = true; 1222 Literal = Val; 1223 return MCOperand::createImm(Literal); 1224 } 1225 1226 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1227 // For now all literal constants are supposed to be unsigned integer 1228 // ToDo: deal with signed/unsigned 64-bit integer constants 1229 // ToDo: deal with float/double constants 1230 if (!HasLiteral) { 1231 if (Bytes.size() < 4) { 1232 return errOperand(0, "cannot read literal, inst bytes left " + 1233 Twine(Bytes.size())); 1234 } 1235 HasLiteral = true; 1236 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1237 if (ExtendFP64) 1238 Literal64 <<= 32; 1239 } 1240 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1241 } 1242 1243 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1244 using namespace AMDGPU::EncValues; 1245 1246 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1247 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1248 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1249 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1250 // Cast prevents negative overflow. 1251 } 1252 1253 static int64_t getInlineImmVal32(unsigned Imm) { 1254 switch (Imm) { 1255 case 240: 1256 return llvm::bit_cast<uint32_t>(0.5f); 1257 case 241: 1258 return llvm::bit_cast<uint32_t>(-0.5f); 1259 case 242: 1260 return llvm::bit_cast<uint32_t>(1.0f); 1261 case 243: 1262 return llvm::bit_cast<uint32_t>(-1.0f); 1263 case 244: 1264 return llvm::bit_cast<uint32_t>(2.0f); 1265 case 245: 1266 return llvm::bit_cast<uint32_t>(-2.0f); 1267 case 246: 1268 return llvm::bit_cast<uint32_t>(4.0f); 1269 case 247: 1270 return llvm::bit_cast<uint32_t>(-4.0f); 1271 case 248: // 1 / (2 * PI) 1272 return 0x3e22f983; 1273 default: 1274 llvm_unreachable("invalid fp inline imm"); 1275 } 1276 } 1277 1278 static int64_t getInlineImmVal64(unsigned Imm) { 1279 switch (Imm) { 1280 case 240: 1281 return llvm::bit_cast<uint64_t>(0.5); 1282 case 241: 1283 return llvm::bit_cast<uint64_t>(-0.5); 1284 case 242: 1285 return llvm::bit_cast<uint64_t>(1.0); 1286 case 243: 1287 return llvm::bit_cast<uint64_t>(-1.0); 1288 case 244: 1289 return llvm::bit_cast<uint64_t>(2.0); 1290 case 245: 1291 return llvm::bit_cast<uint64_t>(-2.0); 1292 case 246: 1293 return llvm::bit_cast<uint64_t>(4.0); 1294 case 247: 1295 return llvm::bit_cast<uint64_t>(-4.0); 1296 case 248: // 1 / (2 * PI) 1297 return 0x3fc45f306dc9c882; 1298 default: 1299 llvm_unreachable("invalid fp inline imm"); 1300 } 1301 } 1302 1303 static int64_t getInlineImmValF16(unsigned Imm) { 1304 switch (Imm) { 1305 case 240: 1306 return 0x3800; 1307 case 241: 1308 return 0xB800; 1309 case 242: 1310 return 0x3C00; 1311 case 243: 1312 return 0xBC00; 1313 case 244: 1314 return 0x4000; 1315 case 245: 1316 return 0xC000; 1317 case 246: 1318 return 0x4400; 1319 case 247: 1320 return 0xC400; 1321 case 248: // 1 / (2 * PI) 1322 return 0x3118; 1323 default: 1324 llvm_unreachable("invalid fp inline imm"); 1325 } 1326 } 1327 1328 static int64_t getInlineImmValBF16(unsigned Imm) { 1329 switch (Imm) { 1330 case 240: 1331 return 0x3F00; 1332 case 241: 1333 return 0xBF00; 1334 case 242: 1335 return 0x3F80; 1336 case 243: 1337 return 0xBF80; 1338 case 244: 1339 return 0x4000; 1340 case 245: 1341 return 0xC000; 1342 case 246: 1343 return 0x4080; 1344 case 247: 1345 return 0xC080; 1346 case 248: // 1 / (2 * PI) 1347 return 0x3E22; 1348 default: 1349 llvm_unreachable("invalid fp inline imm"); 1350 } 1351 } 1352 1353 static int64_t getInlineImmVal16(unsigned Imm, AMDGPU::OperandSemantics Sema) { 1354 return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm) 1355 : getInlineImmValF16(Imm); 1356 } 1357 1358 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm, 1359 AMDGPU::OperandSemantics Sema) { 1360 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN && 1361 Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1362 1363 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1364 // ImmWidth 0 is a default case where operand should not allow immediates. 1365 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1366 // use it to print verbose error message. 1367 switch (ImmWidth) { 1368 case 0: 1369 case 32: 1370 return MCOperand::createImm(getInlineImmVal32(Imm)); 1371 case 64: 1372 return MCOperand::createImm(getInlineImmVal64(Imm)); 1373 case 16: 1374 return MCOperand::createImm(getInlineImmVal16(Imm, Sema)); 1375 default: 1376 llvm_unreachable("implement me"); 1377 } 1378 } 1379 1380 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1381 using namespace AMDGPU; 1382 1383 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1384 switch (Width) { 1385 default: // fall 1386 case OPW32: 1387 case OPW16: 1388 case OPWV216: 1389 return VGPR_32RegClassID; 1390 case OPW64: 1391 case OPWV232: return VReg_64RegClassID; 1392 case OPW96: return VReg_96RegClassID; 1393 case OPW128: return VReg_128RegClassID; 1394 case OPW160: return VReg_160RegClassID; 1395 case OPW256: return VReg_256RegClassID; 1396 case OPW288: return VReg_288RegClassID; 1397 case OPW320: return VReg_320RegClassID; 1398 case OPW352: return VReg_352RegClassID; 1399 case OPW384: return VReg_384RegClassID; 1400 case OPW512: return VReg_512RegClassID; 1401 case OPW1024: return VReg_1024RegClassID; 1402 } 1403 } 1404 1405 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1406 using namespace AMDGPU; 1407 1408 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1409 switch (Width) { 1410 default: // fall 1411 case OPW32: 1412 case OPW16: 1413 case OPWV216: 1414 return AGPR_32RegClassID; 1415 case OPW64: 1416 case OPWV232: return AReg_64RegClassID; 1417 case OPW96: return AReg_96RegClassID; 1418 case OPW128: return AReg_128RegClassID; 1419 case OPW160: return AReg_160RegClassID; 1420 case OPW256: return AReg_256RegClassID; 1421 case OPW288: return AReg_288RegClassID; 1422 case OPW320: return AReg_320RegClassID; 1423 case OPW352: return AReg_352RegClassID; 1424 case OPW384: return AReg_384RegClassID; 1425 case OPW512: return AReg_512RegClassID; 1426 case OPW1024: return AReg_1024RegClassID; 1427 } 1428 } 1429 1430 1431 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1432 using namespace AMDGPU; 1433 1434 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1435 switch (Width) { 1436 default: // fall 1437 case OPW32: 1438 case OPW16: 1439 case OPWV216: 1440 return SGPR_32RegClassID; 1441 case OPW64: 1442 case OPWV232: return SGPR_64RegClassID; 1443 case OPW96: return SGPR_96RegClassID; 1444 case OPW128: return SGPR_128RegClassID; 1445 case OPW160: return SGPR_160RegClassID; 1446 case OPW256: return SGPR_256RegClassID; 1447 case OPW288: return SGPR_288RegClassID; 1448 case OPW320: return SGPR_320RegClassID; 1449 case OPW352: return SGPR_352RegClassID; 1450 case OPW384: return SGPR_384RegClassID; 1451 case OPW512: return SGPR_512RegClassID; 1452 } 1453 } 1454 1455 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1456 using namespace AMDGPU; 1457 1458 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1459 switch (Width) { 1460 default: // fall 1461 case OPW32: 1462 case OPW16: 1463 case OPWV216: 1464 return TTMP_32RegClassID; 1465 case OPW64: 1466 case OPWV232: return TTMP_64RegClassID; 1467 case OPW128: return TTMP_128RegClassID; 1468 case OPW256: return TTMP_256RegClassID; 1469 case OPW288: return TTMP_288RegClassID; 1470 case OPW320: return TTMP_320RegClassID; 1471 case OPW352: return TTMP_352RegClassID; 1472 case OPW384: return TTMP_384RegClassID; 1473 case OPW512: return TTMP_512RegClassID; 1474 } 1475 } 1476 1477 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1478 using namespace AMDGPU::EncValues; 1479 1480 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1481 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1482 1483 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1484 } 1485 1486 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1487 bool MandatoryLiteral, 1488 unsigned ImmWidth, 1489 AMDGPU::OperandSemantics Sema) const { 1490 using namespace AMDGPU::EncValues; 1491 1492 assert(Val < 1024); // enum10 1493 1494 bool IsAGPR = Val & 512; 1495 Val &= 511; 1496 1497 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1498 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1499 : getVgprClassId(Width), Val - VGPR_MIN); 1500 } 1501 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1502 Sema); 1503 } 1504 1505 MCOperand 1506 AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, unsigned Val, 1507 bool MandatoryLiteral, unsigned ImmWidth, 1508 AMDGPU::OperandSemantics Sema) const { 1509 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1510 // decoded earlier. 1511 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1512 using namespace AMDGPU::EncValues; 1513 1514 if (Val <= SGPR_MAX) { 1515 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1516 static_assert(SGPR_MIN == 0); 1517 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1518 } 1519 1520 int TTmpIdx = getTTmpIdx(Val); 1521 if (TTmpIdx >= 0) { 1522 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1523 } 1524 1525 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1526 return decodeIntImmed(Val); 1527 1528 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1529 return decodeFPImmed(ImmWidth, Val, Sema); 1530 1531 if (Val == LITERAL_CONST) { 1532 if (MandatoryLiteral) 1533 // Keep a sentinel value for deferred setting 1534 return MCOperand::createImm(LITERAL_CONST); 1535 else 1536 return decodeLiteralConstant(Sema == AMDGPU::OperandSemantics::FP64); 1537 } 1538 1539 switch (Width) { 1540 case OPW32: 1541 case OPW16: 1542 case OPWV216: 1543 return decodeSpecialReg32(Val); 1544 case OPW64: 1545 case OPWV232: 1546 return decodeSpecialReg64(Val); 1547 default: 1548 llvm_unreachable("unexpected immediate type"); 1549 } 1550 } 1551 1552 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1553 // opposite of bit 0 of DstX. 1554 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1555 unsigned Val) const { 1556 int VDstXInd = 1557 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1558 assert(VDstXInd != -1); 1559 assert(Inst.getOperand(VDstXInd).isReg()); 1560 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1561 Val |= ~XDstReg & 1; 1562 auto Width = llvm::AMDGPUDisassembler::OPW32; 1563 return createRegOperand(getVgprClassId(Width), Val); 1564 } 1565 1566 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1567 using namespace AMDGPU; 1568 1569 switch (Val) { 1570 // clang-format off 1571 case 102: return createRegOperand(FLAT_SCR_LO); 1572 case 103: return createRegOperand(FLAT_SCR_HI); 1573 case 104: return createRegOperand(XNACK_MASK_LO); 1574 case 105: return createRegOperand(XNACK_MASK_HI); 1575 case 106: return createRegOperand(VCC_LO); 1576 case 107: return createRegOperand(VCC_HI); 1577 case 108: return createRegOperand(TBA_LO); 1578 case 109: return createRegOperand(TBA_HI); 1579 case 110: return createRegOperand(TMA_LO); 1580 case 111: return createRegOperand(TMA_HI); 1581 case 124: 1582 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1583 case 125: 1584 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1585 case 126: return createRegOperand(EXEC_LO); 1586 case 127: return createRegOperand(EXEC_HI); 1587 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1588 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1589 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1590 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1591 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1592 case 251: return createRegOperand(SRC_VCCZ); 1593 case 252: return createRegOperand(SRC_EXECZ); 1594 case 253: return createRegOperand(SRC_SCC); 1595 case 254: return createRegOperand(LDS_DIRECT); 1596 default: break; 1597 // clang-format on 1598 } 1599 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1600 } 1601 1602 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1603 using namespace AMDGPU; 1604 1605 switch (Val) { 1606 case 102: return createRegOperand(FLAT_SCR); 1607 case 104: return createRegOperand(XNACK_MASK); 1608 case 106: return createRegOperand(VCC); 1609 case 108: return createRegOperand(TBA); 1610 case 110: return createRegOperand(TMA); 1611 case 124: 1612 if (isGFX11Plus()) 1613 return createRegOperand(SGPR_NULL); 1614 break; 1615 case 125: 1616 if (!isGFX11Plus()) 1617 return createRegOperand(SGPR_NULL); 1618 break; 1619 case 126: return createRegOperand(EXEC); 1620 case 235: return createRegOperand(SRC_SHARED_BASE); 1621 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1622 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1623 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1624 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1625 case 251: return createRegOperand(SRC_VCCZ); 1626 case 252: return createRegOperand(SRC_EXECZ); 1627 case 253: return createRegOperand(SRC_SCC); 1628 default: break; 1629 } 1630 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1631 } 1632 1633 MCOperand 1634 AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, const unsigned Val, 1635 unsigned ImmWidth, 1636 AMDGPU::OperandSemantics Sema) const { 1637 using namespace AMDGPU::SDWA; 1638 using namespace AMDGPU::EncValues; 1639 1640 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1641 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1642 // XXX: cast to int is needed to avoid stupid warning: 1643 // compare with unsigned is always true 1644 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1645 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1646 return createRegOperand(getVgprClassId(Width), 1647 Val - SDWA9EncValues::SRC_VGPR_MIN); 1648 } 1649 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1650 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1651 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1652 return createSRegOperand(getSgprClassId(Width), 1653 Val - SDWA9EncValues::SRC_SGPR_MIN); 1654 } 1655 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1656 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1657 return createSRegOperand(getTtmpClassId(Width), 1658 Val - SDWA9EncValues::SRC_TTMP_MIN); 1659 } 1660 1661 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1662 1663 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1664 return decodeIntImmed(SVal); 1665 1666 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1667 return decodeFPImmed(ImmWidth, SVal, Sema); 1668 1669 return decodeSpecialReg32(SVal); 1670 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1671 return createRegOperand(getVgprClassId(Width), Val); 1672 } 1673 llvm_unreachable("unsupported target"); 1674 } 1675 1676 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1677 return decodeSDWASrc(OPW16, Val, 16, AMDGPU::OperandSemantics::FP16); 1678 } 1679 1680 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1681 return decodeSDWASrc(OPW32, Val, 32, AMDGPU::OperandSemantics::FP32); 1682 } 1683 1684 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1685 using namespace AMDGPU::SDWA; 1686 1687 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1688 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1689 "SDWAVopcDst should be present only on GFX9+"); 1690 1691 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1692 1693 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1694 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1695 1696 int TTmpIdx = getTTmpIdx(Val); 1697 if (TTmpIdx >= 0) { 1698 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1699 return createSRegOperand(TTmpClsId, TTmpIdx); 1700 } else if (Val > SGPR_MAX) { 1701 return IsWave64 ? decodeSpecialReg64(Val) 1702 : decodeSpecialReg32(Val); 1703 } else { 1704 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1705 } 1706 } else { 1707 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1708 } 1709 } 1710 1711 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1712 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1713 ? decodeSrcOp(OPW64, Val) 1714 : decodeSrcOp(OPW32, Val); 1715 } 1716 1717 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1718 return decodeSrcOp(OPW32, Val); 1719 } 1720 1721 MCOperand AMDGPUDisassembler::decodeDpp8FI(unsigned Val) const { 1722 if (Val != AMDGPU::DPP::DPP8_FI_0 && Val != AMDGPU::DPP::DPP8_FI_1) 1723 return MCOperand(); 1724 return MCOperand::createImm(Val); 1725 } 1726 1727 bool AMDGPUDisassembler::isVI() const { 1728 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1729 } 1730 1731 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1732 1733 bool AMDGPUDisassembler::isGFX90A() const { 1734 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1735 } 1736 1737 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1738 1739 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1740 1741 bool AMDGPUDisassembler::isGFX10Plus() const { 1742 return AMDGPU::isGFX10Plus(STI); 1743 } 1744 1745 bool AMDGPUDisassembler::isGFX11() const { 1746 return STI.hasFeature(AMDGPU::FeatureGFX11); 1747 } 1748 1749 bool AMDGPUDisassembler::isGFX11Plus() const { 1750 return AMDGPU::isGFX11Plus(STI); 1751 } 1752 1753 bool AMDGPUDisassembler::isGFX12Plus() const { 1754 return AMDGPU::isGFX12Plus(STI); 1755 } 1756 1757 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1758 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1759 } 1760 1761 bool AMDGPUDisassembler::hasKernargPreload() const { 1762 return AMDGPU::hasKernargPreload(STI); 1763 } 1764 1765 //===----------------------------------------------------------------------===// 1766 // AMDGPU specific symbol handling 1767 //===----------------------------------------------------------------------===// 1768 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1769 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1770 do { \ 1771 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1772 } while (0) 1773 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1774 do { \ 1775 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1776 << GET_FIELD(MASK) << '\n'; \ 1777 } while (0) 1778 1779 // NOLINTNEXTLINE(readability-identifier-naming) 1780 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1781 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1782 using namespace amdhsa; 1783 StringRef Indent = "\t"; 1784 1785 // We cannot accurately backward compute #VGPRs used from 1786 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1787 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1788 // simply calculate the inverse of what the assembler does. 1789 1790 uint32_t GranulatedWorkitemVGPRCount = 1791 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1792 1793 uint32_t NextFreeVGPR = 1794 (GranulatedWorkitemVGPRCount + 1) * 1795 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1796 1797 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1798 1799 // We cannot backward compute values used to calculate 1800 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1801 // directives can't be computed: 1802 // .amdhsa_reserve_vcc 1803 // .amdhsa_reserve_flat_scratch 1804 // .amdhsa_reserve_xnack_mask 1805 // They take their respective default values if not specified in the assembly. 1806 // 1807 // GRANULATED_WAVEFRONT_SGPR_COUNT 1808 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1809 // 1810 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1811 // are set to 0. So while disassembling we consider that: 1812 // 1813 // GRANULATED_WAVEFRONT_SGPR_COUNT 1814 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1815 // 1816 // The disassembler cannot recover the original values of those 3 directives. 1817 1818 uint32_t GranulatedWavefrontSGPRCount = 1819 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1820 1821 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1822 return MCDisassembler::Fail; 1823 1824 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1825 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1826 1827 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1828 if (!hasArchitectedFlatScratch()) 1829 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1830 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1831 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1832 1833 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1834 return MCDisassembler::Fail; 1835 1836 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1837 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1838 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1839 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1840 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1841 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1842 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1843 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1844 1845 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1846 return MCDisassembler::Fail; 1847 1848 if (!isGFX12Plus()) 1849 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1850 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1851 1852 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1853 return MCDisassembler::Fail; 1854 1855 if (!isGFX12Plus()) 1856 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1857 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1858 1859 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1860 return MCDisassembler::Fail; 1861 1862 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1863 return MCDisassembler::Fail; 1864 1865 if (isGFX9Plus()) 1866 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1867 1868 if (!isGFX9Plus()) 1869 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1870 return MCDisassembler::Fail; 1871 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1872 return MCDisassembler::Fail; 1873 if (!isGFX10Plus()) 1874 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1875 return MCDisassembler::Fail; 1876 1877 if (isGFX10Plus()) { 1878 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1879 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1880 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1881 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1882 } 1883 1884 if (isGFX12Plus()) 1885 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 1886 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 1887 1888 return MCDisassembler::Success; 1889 } 1890 1891 // NOLINTNEXTLINE(readability-identifier-naming) 1892 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1893 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1894 using namespace amdhsa; 1895 StringRef Indent = "\t"; 1896 if (hasArchitectedFlatScratch()) 1897 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1898 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1899 else 1900 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1901 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1902 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1903 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1904 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1905 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1906 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1907 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1908 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1909 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1910 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1911 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1912 1913 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1914 return MCDisassembler::Fail; 1915 1916 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1917 return MCDisassembler::Fail; 1918 1919 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1920 return MCDisassembler::Fail; 1921 1922 PRINT_DIRECTIVE( 1923 ".amdhsa_exception_fp_ieee_invalid_op", 1924 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1925 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1926 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1927 PRINT_DIRECTIVE( 1928 ".amdhsa_exception_fp_ieee_div_zero", 1929 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1930 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1931 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1932 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1933 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1934 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1935 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1936 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1937 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1938 1939 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1940 return MCDisassembler::Fail; 1941 1942 return MCDisassembler::Success; 1943 } 1944 1945 // NOLINTNEXTLINE(readability-identifier-naming) 1946 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 1947 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1948 using namespace amdhsa; 1949 StringRef Indent = "\t"; 1950 if (isGFX90A()) { 1951 KdStream << Indent << ".amdhsa_accum_offset " 1952 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 1953 << '\n'; 1954 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 1955 return MCDisassembler::Fail; 1956 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 1957 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 1958 return MCDisassembler::Fail; 1959 } else if (isGFX10Plus()) { 1960 // Bits [0-3]. 1961 if (!isGFX12Plus()) { 1962 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 1963 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 1964 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 1965 } else { 1966 PRINT_PSEUDO_DIRECTIVE_COMMENT( 1967 "SHARED_VGPR_COUNT", 1968 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 1969 } 1970 } else { 1971 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX12_PLUS_RESERVED0) 1972 return MCDisassembler::Fail; 1973 } 1974 1975 // Bits [4-11]. 1976 if (isGFX11()) { 1977 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 1978 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE); 1979 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 1980 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START); 1981 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 1982 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END); 1983 } else if (isGFX12Plus()) { 1984 PRINT_PSEUDO_DIRECTIVE_COMMENT( 1985 "INST_PREF_SIZE", COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE); 1986 } else { 1987 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED1) 1988 return MCDisassembler::Fail; 1989 } 1990 1991 // Bits [12]. 1992 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED2) 1993 return MCDisassembler::Fail; 1994 1995 // Bits [13]. 1996 if (isGFX12Plus()) { 1997 PRINT_PSEUDO_DIRECTIVE_COMMENT("GLG_EN", 1998 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN); 1999 } else { 2000 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_GFX11_RESERVED3) 2001 return MCDisassembler::Fail; 2002 } 2003 2004 // Bits [14-30]. 2005 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED4) 2006 return MCDisassembler::Fail; 2007 2008 // Bits [31]. 2009 if (isGFX11Plus()) { 2010 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2011 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP); 2012 } else { 2013 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED5) 2014 return MCDisassembler::Fail; 2015 } 2016 } else if (FourByteBuffer) { 2017 return MCDisassembler::Fail; 2018 } 2019 return MCDisassembler::Success; 2020 } 2021 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2022 #undef PRINT_DIRECTIVE 2023 #undef GET_FIELD 2024 2025 MCDisassembler::DecodeStatus 2026 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2027 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2028 raw_string_ostream &KdStream) const { 2029 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2030 do { \ 2031 KdStream << Indent << DIRECTIVE " " \ 2032 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2033 } while (0) 2034 2035 uint16_t TwoByteBuffer = 0; 2036 uint32_t FourByteBuffer = 0; 2037 2038 StringRef ReservedBytes; 2039 StringRef Indent = "\t"; 2040 2041 assert(Bytes.size() == 64); 2042 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2043 2044 switch (Cursor.tell()) { 2045 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2046 FourByteBuffer = DE.getU32(Cursor); 2047 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2048 << '\n'; 2049 return MCDisassembler::Success; 2050 2051 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2052 FourByteBuffer = DE.getU32(Cursor); 2053 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2054 << FourByteBuffer << '\n'; 2055 return MCDisassembler::Success; 2056 2057 case amdhsa::KERNARG_SIZE_OFFSET: 2058 FourByteBuffer = DE.getU32(Cursor); 2059 KdStream << Indent << ".amdhsa_kernarg_size " 2060 << FourByteBuffer << '\n'; 2061 return MCDisassembler::Success; 2062 2063 case amdhsa::RESERVED0_OFFSET: 2064 // 4 reserved bytes, must be 0. 2065 ReservedBytes = DE.getBytes(Cursor, 4); 2066 for (int I = 0; I < 4; ++I) { 2067 if (ReservedBytes[I] != 0) { 2068 return MCDisassembler::Fail; 2069 } 2070 } 2071 return MCDisassembler::Success; 2072 2073 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2074 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2075 // So far no directive controls this for Code Object V3, so simply skip for 2076 // disassembly. 2077 DE.skip(Cursor, 8); 2078 return MCDisassembler::Success; 2079 2080 case amdhsa::RESERVED1_OFFSET: 2081 // 20 reserved bytes, must be 0. 2082 ReservedBytes = DE.getBytes(Cursor, 20); 2083 for (int I = 0; I < 20; ++I) { 2084 if (ReservedBytes[I] != 0) { 2085 return MCDisassembler::Fail; 2086 } 2087 } 2088 return MCDisassembler::Success; 2089 2090 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2091 FourByteBuffer = DE.getU32(Cursor); 2092 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2093 2094 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2095 FourByteBuffer = DE.getU32(Cursor); 2096 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2097 2098 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2099 FourByteBuffer = DE.getU32(Cursor); 2100 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2101 2102 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2103 using namespace amdhsa; 2104 TwoByteBuffer = DE.getU16(Cursor); 2105 2106 if (!hasArchitectedFlatScratch()) 2107 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2108 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2109 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2110 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2111 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2112 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2113 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2114 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2115 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2116 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2117 if (!hasArchitectedFlatScratch()) 2118 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2119 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2120 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2121 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2122 2123 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2124 return MCDisassembler::Fail; 2125 2126 // Reserved for GFX9 2127 if (isGFX9() && 2128 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2129 return MCDisassembler::Fail; 2130 } else if (isGFX10Plus()) { 2131 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2132 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2133 } 2134 2135 if (CodeObjectVersion >= AMDGPU::AMDHSA_COV5) 2136 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2137 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2138 2139 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2140 return MCDisassembler::Fail; 2141 2142 return MCDisassembler::Success; 2143 2144 case amdhsa::KERNARG_PRELOAD_OFFSET: 2145 using namespace amdhsa; 2146 TwoByteBuffer = DE.getU16(Cursor); 2147 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2148 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2149 KERNARG_PRELOAD_SPEC_LENGTH); 2150 } 2151 2152 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2153 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2154 KERNARG_PRELOAD_SPEC_OFFSET); 2155 } 2156 return MCDisassembler::Success; 2157 2158 case amdhsa::RESERVED3_OFFSET: 2159 // 4 bytes from here are reserved, must be 0. 2160 ReservedBytes = DE.getBytes(Cursor, 4); 2161 for (int I = 0; I < 4; ++I) { 2162 if (ReservedBytes[I] != 0) 2163 return MCDisassembler::Fail; 2164 } 2165 return MCDisassembler::Success; 2166 2167 default: 2168 llvm_unreachable("Unhandled index. Case statements cover everything."); 2169 return MCDisassembler::Fail; 2170 } 2171 #undef PRINT_DIRECTIVE 2172 } 2173 2174 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2175 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2176 // CP microcode requires the kernel descriptor to be 64 aligned. 2177 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2178 return MCDisassembler::Fail; 2179 2180 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2181 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2182 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2183 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2184 // when required. 2185 if (isGFX10Plus()) { 2186 uint16_t KernelCodeProperties = 2187 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2188 llvm::endianness::little); 2189 EnableWavefrontSize32 = 2190 AMDHSA_BITS_GET(KernelCodeProperties, 2191 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2192 } 2193 2194 std::string Kd; 2195 raw_string_ostream KdStream(Kd); 2196 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2197 2198 DataExtractor::Cursor C(0); 2199 while (C && C.tell() < Bytes.size()) { 2200 MCDisassembler::DecodeStatus Status = 2201 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2202 2203 cantFail(C.takeError()); 2204 2205 if (Status == MCDisassembler::Fail) 2206 return MCDisassembler::Fail; 2207 } 2208 KdStream << ".end_amdhsa_kernel\n"; 2209 outs() << KdStream.str(); 2210 return MCDisassembler::Success; 2211 } 2212 2213 std::optional<MCDisassembler::DecodeStatus> 2214 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2215 ArrayRef<uint8_t> Bytes, uint64_t Address, 2216 raw_ostream &CStream) const { 2217 // Right now only kernel descriptor needs to be handled. 2218 // We ignore all other symbols for target specific handling. 2219 // TODO: 2220 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2221 // Object V2 and V3 when symbols are marked protected. 2222 2223 // amd_kernel_code_t for Code Object V2. 2224 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2225 Size = 256; 2226 return MCDisassembler::Fail; 2227 } 2228 2229 // Code Object V3 kernel descriptors. 2230 StringRef Name = Symbol.Name; 2231 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2232 Size = 64; // Size = 64 regardless of success or failure. 2233 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2234 } 2235 return std::nullopt; 2236 } 2237 2238 //===----------------------------------------------------------------------===// 2239 // AMDGPUSymbolizer 2240 //===----------------------------------------------------------------------===// 2241 2242 // Try to find symbol name for specified label 2243 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2244 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2245 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2246 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2247 2248 if (!IsBranch) { 2249 return false; 2250 } 2251 2252 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2253 if (!Symbols) 2254 return false; 2255 2256 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2257 return Val.Addr == static_cast<uint64_t>(Value) && 2258 Val.Type == ELF::STT_NOTYPE; 2259 }); 2260 if (Result != Symbols->end()) { 2261 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2262 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2263 Inst.addOperand(MCOperand::createExpr(Add)); 2264 return true; 2265 } 2266 // Add to list of referenced addresses, so caller can synthesize a label. 2267 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2268 return false; 2269 } 2270 2271 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2272 int64_t Value, 2273 uint64_t Address) { 2274 llvm_unreachable("unimplemented"); 2275 } 2276 2277 //===----------------------------------------------------------------------===// 2278 // Initialization 2279 //===----------------------------------------------------------------------===// 2280 2281 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2282 LLVMOpInfoCallback /*GetOpInfo*/, 2283 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2284 void *DisInfo, 2285 MCContext *Ctx, 2286 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2287 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2288 } 2289 2290 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2291 const MCSubtargetInfo &STI, 2292 MCContext &Ctx) { 2293 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2294 } 2295 2296 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2297 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2298 createAMDGPUDisassembler); 2299 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2300 createAMDGPUSymbolizer); 2301 } 2302