1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/MC/MCAsmInfo.h" 25 #include "llvm/MC/MCContext.h" 26 #include "llvm/MC/MCExpr.h" 27 #include "llvm/MC/MCFixedLenDisassembler.h" 28 #include "llvm/Support/AMDHSAKernelDescriptor.h" 29 #include "llvm/Support/TargetRegistry.h" 30 31 using namespace llvm; 32 33 #define DEBUG_TYPE "amdgpu-disassembler" 34 35 #define SGPR_MAX \ 36 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 37 : AMDGPU::EncValues::SGPR_MAX_SI) 38 39 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 40 41 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 42 MCContext &Ctx, 43 MCInstrInfo const *MCII) : 44 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 45 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 46 47 // ToDo: AMDGPUDisassembler supports only VI ISA. 48 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 49 report_fatal_error("Disassembly not yet supported for subtarget"); 50 } 51 52 inline static MCDisassembler::DecodeStatus 53 addOperand(MCInst &Inst, const MCOperand& Opnd) { 54 Inst.addOperand(Opnd); 55 return Opnd.isValid() ? 56 MCDisassembler::Success : 57 MCDisassembler::Fail; 58 } 59 60 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 61 uint16_t NameIdx) { 62 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 63 if (OpIdx != -1) { 64 auto I = MI.begin(); 65 std::advance(I, OpIdx); 66 MI.insert(I, Op); 67 } 68 return OpIdx; 69 } 70 71 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 72 uint64_t Addr, const void *Decoder) { 73 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 74 75 // Our branches take a simm16, but we need two extra bits to account for the 76 // factor of 4. 77 APInt SignedOffset(18, Imm * 4, true); 78 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 79 80 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 81 return MCDisassembler::Success; 82 return addOperand(Inst, MCOperand::createImm(Imm)); 83 } 84 85 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, 86 uint64_t Addr, const void *Decoder) { 87 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 88 int64_t Offset; 89 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 90 Offset = Imm & 0xFFFFF; 91 } else { // GFX9+ supports 21-bit signed offsets. 92 Offset = SignExtend64<21>(Imm); 93 } 94 return addOperand(Inst, MCOperand::createImm(Offset)); 95 } 96 97 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, 98 uint64_t Addr, const void *Decoder) { 99 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 100 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 101 } 102 103 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 104 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 105 unsigned Imm, \ 106 uint64_t /*Addr*/, \ 107 const void *Decoder) { \ 108 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 109 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 110 } 111 112 #define DECODE_OPERAND_REG(RegClass) \ 113 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 114 115 DECODE_OPERAND_REG(VGPR_32) 116 DECODE_OPERAND_REG(VRegOrLds_32) 117 DECODE_OPERAND_REG(VS_32) 118 DECODE_OPERAND_REG(VS_64) 119 DECODE_OPERAND_REG(VS_128) 120 121 DECODE_OPERAND_REG(VReg_64) 122 DECODE_OPERAND_REG(VReg_96) 123 DECODE_OPERAND_REG(VReg_128) 124 DECODE_OPERAND_REG(VReg_256) 125 DECODE_OPERAND_REG(VReg_512) 126 DECODE_OPERAND_REG(VReg_1024) 127 128 DECODE_OPERAND_REG(SReg_32) 129 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 130 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 131 DECODE_OPERAND_REG(SRegOrLds_32) 132 DECODE_OPERAND_REG(SReg_64) 133 DECODE_OPERAND_REG(SReg_64_XEXEC) 134 DECODE_OPERAND_REG(SReg_128) 135 DECODE_OPERAND_REG(SReg_256) 136 DECODE_OPERAND_REG(SReg_512) 137 138 DECODE_OPERAND_REG(AGPR_32) 139 DECODE_OPERAND_REG(AReg_64) 140 DECODE_OPERAND_REG(AReg_128) 141 DECODE_OPERAND_REG(AReg_256) 142 DECODE_OPERAND_REG(AReg_512) 143 DECODE_OPERAND_REG(AReg_1024) 144 DECODE_OPERAND_REG(AV_32) 145 DECODE_OPERAND_REG(AV_64) 146 147 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 148 unsigned Imm, 149 uint64_t Addr, 150 const void *Decoder) { 151 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 152 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 153 } 154 155 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 156 unsigned Imm, 157 uint64_t Addr, 158 const void *Decoder) { 159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 160 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 161 } 162 163 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, 164 unsigned Imm, 165 uint64_t Addr, 166 const void *Decoder) { 167 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 168 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 169 } 170 171 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, 172 unsigned Imm, 173 uint64_t Addr, 174 const void *Decoder) { 175 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 176 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 177 } 178 179 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, 180 unsigned Imm, 181 uint64_t Addr, 182 const void *Decoder) { 183 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 184 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 185 } 186 187 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, 188 unsigned Imm, 189 uint64_t Addr, 190 const void *Decoder) { 191 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 192 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 193 } 194 195 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, 196 unsigned Imm, 197 uint64_t Addr, 198 const void *Decoder) { 199 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 200 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 201 } 202 203 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, 204 unsigned Imm, 205 uint64_t Addr, 206 const void *Decoder) { 207 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 208 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 209 } 210 211 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, 212 unsigned Imm, 213 uint64_t Addr, 214 const void *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, 220 unsigned Imm, 221 uint64_t Addr, 222 const void *Decoder) { 223 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 224 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 225 } 226 227 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, 228 unsigned Imm, 229 uint64_t Addr, 230 const void *Decoder) { 231 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 232 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 233 } 234 235 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, 236 unsigned Imm, 237 uint64_t Addr, 238 const void *Decoder) { 239 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 240 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 241 } 242 243 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, 244 unsigned Imm, 245 uint64_t Addr, 246 const void *Decoder) { 247 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 248 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 249 } 250 251 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, 252 unsigned Imm, 253 uint64_t Addr, 254 const void *Decoder) { 255 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 256 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 257 } 258 259 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, 260 unsigned Imm, 261 uint64_t Addr, 262 const void *Decoder) { 263 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 264 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 265 } 266 267 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 268 const MCRegisterInfo *MRI) { 269 if (OpIdx < 0) 270 return false; 271 272 const MCOperand &Op = Inst.getOperand(OpIdx); 273 if (!Op.isReg()) 274 return false; 275 276 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 277 auto Reg = Sub ? Sub : Op.getReg(); 278 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 279 } 280 281 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, 282 unsigned Imm, 283 AMDGPUDisassembler::OpWidthTy Opw, 284 const void *Decoder) { 285 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 286 if (!DAsm->isGFX90A()) { 287 Imm &= 511; 288 } else { 289 // If atomic has both vdata and vdst their register classes are tied. 290 // The bit is decoded along with the vdst, first operand. We need to 291 // change register class to AGPR if vdst was AGPR. 292 // If a DS instruction has both data0 and data1 their register classes 293 // are also tied. 294 unsigned Opc = Inst.getOpcode(); 295 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 296 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 297 : AMDGPU::OpName::vdata; 298 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 299 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 300 if ((int)Inst.getNumOperands() == DataIdx) { 301 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 302 if (IsAGPROperand(Inst, DstIdx, MRI)) 303 Imm |= 512; 304 } 305 306 if (TSFlags & SIInstrFlags::DS) { 307 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 308 if ((int)Inst.getNumOperands() == Data2Idx && 309 IsAGPROperand(Inst, DataIdx, MRI)) 310 Imm |= 512; 311 } 312 } 313 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 314 } 315 316 static DecodeStatus DecodeAVLdSt_32RegisterClass(MCInst &Inst, 317 unsigned Imm, 318 uint64_t Addr, 319 const void *Decoder) { 320 return decodeOperand_AVLdSt_Any(Inst, Imm, 321 AMDGPUDisassembler::OPW32, Decoder); 322 } 323 324 static DecodeStatus DecodeAVLdSt_64RegisterClass(MCInst &Inst, 325 unsigned Imm, 326 uint64_t Addr, 327 const void *Decoder) { 328 return decodeOperand_AVLdSt_Any(Inst, Imm, 329 AMDGPUDisassembler::OPW64, Decoder); 330 } 331 332 static DecodeStatus DecodeAVLdSt_96RegisterClass(MCInst &Inst, 333 unsigned Imm, 334 uint64_t Addr, 335 const void *Decoder) { 336 return decodeOperand_AVLdSt_Any(Inst, Imm, 337 AMDGPUDisassembler::OPW96, Decoder); 338 } 339 340 static DecodeStatus DecodeAVLdSt_128RegisterClass(MCInst &Inst, 341 unsigned Imm, 342 uint64_t Addr, 343 const void *Decoder) { 344 return decodeOperand_AVLdSt_Any(Inst, Imm, 345 AMDGPUDisassembler::OPW128, Decoder); 346 } 347 348 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, 349 unsigned Imm, 350 uint64_t Addr, 351 const void *Decoder) { 352 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 353 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 354 } 355 356 static DecodeStatus decodeOperand_VGPR_32(MCInst &Inst, 357 unsigned Imm, 358 uint64_t Addr, 359 const void *Decoder) { 360 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 361 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW32, Imm)); 362 } 363 364 #define DECODE_SDWA(DecName) \ 365 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 366 367 DECODE_SDWA(Src32) 368 DECODE_SDWA(Src16) 369 DECODE_SDWA(VopcDst) 370 371 #include "AMDGPUGenDisassemblerTables.inc" 372 373 //===----------------------------------------------------------------------===// 374 // 375 //===----------------------------------------------------------------------===// 376 377 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 378 assert(Bytes.size() >= sizeof(T)); 379 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 380 Bytes = Bytes.slice(sizeof(T)); 381 return Res; 382 } 383 384 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 385 MCInst &MI, 386 uint64_t Inst, 387 uint64_t Address) const { 388 assert(MI.getOpcode() == 0); 389 assert(MI.getNumOperands() == 0); 390 MCInst TmpInst; 391 HasLiteral = false; 392 const auto SavedBytes = Bytes; 393 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 394 MI = TmpInst; 395 return MCDisassembler::Success; 396 } 397 Bytes = SavedBytes; 398 return MCDisassembler::Fail; 399 } 400 401 static bool isValidDPP8(const MCInst &MI) { 402 using namespace llvm::AMDGPU::DPP; 403 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 404 assert(FiIdx != -1); 405 if ((unsigned)FiIdx >= MI.getNumOperands()) 406 return false; 407 unsigned Fi = MI.getOperand(FiIdx).getImm(); 408 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 409 } 410 411 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 412 ArrayRef<uint8_t> Bytes_, 413 uint64_t Address, 414 raw_ostream &CS) const { 415 CommentStream = &CS; 416 bool IsSDWA = false; 417 418 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 419 Bytes = Bytes_.slice(0, MaxInstBytesNum); 420 421 DecodeStatus Res = MCDisassembler::Fail; 422 do { 423 // ToDo: better to switch encoding length using some bit predicate 424 // but it is unknown yet, so try all we can 425 426 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 427 // encodings 428 if (Bytes.size() >= 8) { 429 const uint64_t QW = eatBytes<uint64_t>(Bytes); 430 431 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 432 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 433 if (Res) { 434 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 435 == -1) 436 break; 437 if (convertDPP8Inst(MI) == MCDisassembler::Success) 438 break; 439 MI = MCInst(); // clear 440 } 441 } 442 443 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 444 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 445 break; 446 447 MI = MCInst(); // clear 448 449 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 450 if (Res) break; 451 452 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 453 if (Res) { IsSDWA = true; break; } 454 455 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 456 if (Res) { IsSDWA = true; break; } 457 458 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 459 if (Res) { IsSDWA = true; break; } 460 461 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 462 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 463 if (Res) 464 break; 465 } 466 467 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 468 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 469 // table first so we print the correct name. 470 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 471 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 472 if (Res) 473 break; 474 } 475 } 476 477 // Reinitialize Bytes as DPP64 could have eaten too much 478 Bytes = Bytes_.slice(0, MaxInstBytesNum); 479 480 // Try decode 32-bit instruction 481 if (Bytes.size() < 4) break; 482 const uint32_t DW = eatBytes<uint32_t>(Bytes); 483 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 484 if (Res) break; 485 486 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 487 if (Res) break; 488 489 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 490 if (Res) break; 491 492 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 493 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 494 if (Res) 495 break; 496 } 497 498 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 499 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 500 if (Res) break; 501 } 502 503 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 504 if (Res) break; 505 506 if (Bytes.size() < 4) break; 507 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 508 509 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 510 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 511 if (Res) 512 break; 513 } 514 515 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 516 if (Res) break; 517 518 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 519 if (Res) break; 520 521 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 522 if (Res) break; 523 524 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 525 } while (false); 526 527 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 528 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 529 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 530 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 531 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 532 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 533 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 534 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 535 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 536 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 537 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 538 // Insert dummy unused src2_modifiers. 539 insertNamedMCOperand(MI, MCOperand::createImm(0), 540 AMDGPU::OpName::src2_modifiers); 541 } 542 543 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 544 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 545 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 546 AMDGPU::OpName::cpol); 547 if (CPolPos != -1) { 548 unsigned CPol = 549 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 550 AMDGPU::CPol::GLC : 0; 551 if (MI.getNumOperands() <= (unsigned)CPolPos) { 552 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 553 AMDGPU::OpName::cpol); 554 } else if (CPol) { 555 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 556 } 557 } 558 } 559 560 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 561 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 562 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 563 // GFX90A lost TFE, its place is occupied by ACC. 564 int TFEOpIdx = 565 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 566 if (TFEOpIdx != -1) { 567 auto TFEIter = MI.begin(); 568 std::advance(TFEIter, TFEOpIdx); 569 MI.insert(TFEIter, MCOperand::createImm(0)); 570 } 571 } 572 573 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 574 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 575 int SWZOpIdx = 576 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 577 if (SWZOpIdx != -1) { 578 auto SWZIter = MI.begin(); 579 std::advance(SWZIter, SWZOpIdx); 580 MI.insert(SWZIter, MCOperand::createImm(0)); 581 } 582 } 583 584 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 585 int VAddr0Idx = 586 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 587 int RsrcIdx = 588 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 589 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 590 if (VAddr0Idx >= 0 && NSAArgs > 0) { 591 unsigned NSAWords = (NSAArgs + 3) / 4; 592 if (Bytes.size() < 4 * NSAWords) { 593 Res = MCDisassembler::Fail; 594 } else { 595 for (unsigned i = 0; i < NSAArgs; ++i) { 596 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 597 decodeOperand_VGPR_32(Bytes[i])); 598 } 599 Bytes = Bytes.slice(4 * NSAWords); 600 } 601 } 602 603 if (Res) 604 Res = convertMIMGInst(MI); 605 } 606 607 if (Res && IsSDWA) 608 Res = convertSDWAInst(MI); 609 610 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 611 AMDGPU::OpName::vdst_in); 612 if (VDstIn_Idx != -1) { 613 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 614 MCOI::OperandConstraint::TIED_TO); 615 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 616 !MI.getOperand(VDstIn_Idx).isReg() || 617 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 618 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 619 MI.erase(&MI.getOperand(VDstIn_Idx)); 620 insertNamedMCOperand(MI, 621 MCOperand::createReg(MI.getOperand(Tied).getReg()), 622 AMDGPU::OpName::vdst_in); 623 } 624 } 625 626 // if the opcode was not recognized we'll assume a Size of 4 bytes 627 // (unless there are fewer bytes left) 628 Size = Res ? (MaxInstBytesNum - Bytes.size()) 629 : std::min((size_t)4, Bytes_.size()); 630 return Res; 631 } 632 633 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 634 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 635 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 636 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 637 // VOPC - insert clamp 638 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 639 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 640 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 641 if (SDst != -1) { 642 // VOPC - insert VCC register as sdst 643 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 644 AMDGPU::OpName::sdst); 645 } else { 646 // VOP1/2 - insert omod if present in instruction 647 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 648 } 649 } 650 return MCDisassembler::Success; 651 } 652 653 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 654 unsigned Opc = MI.getOpcode(); 655 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 656 657 // Insert dummy unused src modifiers. 658 if (MI.getNumOperands() < DescNumOps && 659 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 660 insertNamedMCOperand(MI, MCOperand::createImm(0), 661 AMDGPU::OpName::src0_modifiers); 662 663 if (MI.getNumOperands() < DescNumOps && 664 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 665 insertNamedMCOperand(MI, MCOperand::createImm(0), 666 AMDGPU::OpName::src1_modifiers); 667 668 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 669 } 670 671 // Note that before gfx10, the MIMG encoding provided no information about 672 // VADDR size. Consequently, decoded instructions always show address as if it 673 // has 1 dword, which could be not really so. 674 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 675 676 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 677 AMDGPU::OpName::vdst); 678 679 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 680 AMDGPU::OpName::vdata); 681 int VAddr0Idx = 682 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 683 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 684 AMDGPU::OpName::dmask); 685 686 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 687 AMDGPU::OpName::tfe); 688 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 689 AMDGPU::OpName::d16); 690 691 assert(VDataIdx != -1); 692 if (DMaskIdx == -1 || TFEIdx == -1) {// intersect_ray 693 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 694 assert(MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_sa || 695 MI.getOpcode() == AMDGPU::IMAGE_BVH_INTERSECT_RAY_a16_nsa || 696 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_sa || 697 MI.getOpcode() == AMDGPU::IMAGE_BVH64_INTERSECT_RAY_a16_nsa); 698 addOperand(MI, MCOperand::createImm(1)); 699 } 700 return MCDisassembler::Success; 701 } 702 703 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 704 bool IsAtomic = (VDstIdx != -1); 705 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 706 707 bool IsNSA = false; 708 unsigned AddrSize = Info->VAddrDwords; 709 710 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 711 unsigned DimIdx = 712 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 713 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 714 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 715 const AMDGPU::MIMGDimInfo *Dim = 716 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 717 718 AddrSize = BaseOpcode->NumExtraArgs + 719 (BaseOpcode->Gradients ? Dim->NumGradients : 0) + 720 (BaseOpcode->Coordinates ? Dim->NumCoords : 0) + 721 (BaseOpcode->LodOrClampOrMip ? 1 : 0); 722 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 723 if (!IsNSA) { 724 if (AddrSize > 8) 725 AddrSize = 16; 726 else if (AddrSize > 4) 727 AddrSize = 8; 728 } else { 729 if (AddrSize > Info->VAddrDwords) { 730 // The NSA encoding does not contain enough operands for the combination 731 // of base opcode / dimension. Should this be an error? 732 return MCDisassembler::Success; 733 } 734 } 735 } 736 737 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 738 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 739 740 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 741 if (D16 && AMDGPU::hasPackedD16(STI)) { 742 DstSize = (DstSize + 1) / 2; 743 } 744 745 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 746 DstSize += 1; 747 748 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 749 return MCDisassembler::Success; 750 751 int NewOpcode = 752 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 753 if (NewOpcode == -1) 754 return MCDisassembler::Success; 755 756 // Widen the register to the correct number of enabled channels. 757 unsigned NewVdata = AMDGPU::NoRegister; 758 if (DstSize != Info->VDataDwords) { 759 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 760 761 // Get first subregister of VData 762 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 763 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 764 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 765 766 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 767 &MRI.getRegClass(DataRCID)); 768 if (NewVdata == AMDGPU::NoRegister) { 769 // It's possible to encode this such that the low register + enabled 770 // components exceeds the register count. 771 return MCDisassembler::Success; 772 } 773 } 774 775 unsigned NewVAddr0 = AMDGPU::NoRegister; 776 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 777 AddrSize != Info->VAddrDwords) { 778 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 779 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 780 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 781 782 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 783 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 784 &MRI.getRegClass(AddrRCID)); 785 if (NewVAddr0 == AMDGPU::NoRegister) 786 return MCDisassembler::Success; 787 } 788 789 MI.setOpcode(NewOpcode); 790 791 if (NewVdata != AMDGPU::NoRegister) { 792 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 793 794 if (IsAtomic) { 795 // Atomic operations have an additional operand (a copy of data) 796 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 797 } 798 } 799 800 if (NewVAddr0 != AMDGPU::NoRegister) { 801 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 802 } else if (IsNSA) { 803 assert(AddrSize <= Info->VAddrDwords); 804 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 805 MI.begin() + VAddr0Idx + Info->VAddrDwords); 806 } 807 808 return MCDisassembler::Success; 809 } 810 811 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 812 return getContext().getRegisterInfo()-> 813 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 814 } 815 816 inline 817 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 818 const Twine& ErrMsg) const { 819 *CommentStream << "Error: " + ErrMsg; 820 821 // ToDo: add support for error operands to MCInst.h 822 // return MCOperand::createError(V); 823 return MCOperand(); 824 } 825 826 inline 827 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 828 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 829 } 830 831 inline 832 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 833 unsigned Val) const { 834 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 835 if (Val >= RegCl.getNumRegs()) 836 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 837 ": unknown register " + Twine(Val)); 838 return createRegOperand(RegCl.getRegister(Val)); 839 } 840 841 inline 842 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 843 unsigned Val) const { 844 // ToDo: SI/CI have 104 SGPRs, VI - 102 845 // Valery: here we accepting as much as we can, let assembler sort it out 846 int shift = 0; 847 switch (SRegClassID) { 848 case AMDGPU::SGPR_32RegClassID: 849 case AMDGPU::TTMP_32RegClassID: 850 break; 851 case AMDGPU::SGPR_64RegClassID: 852 case AMDGPU::TTMP_64RegClassID: 853 shift = 1; 854 break; 855 case AMDGPU::SGPR_128RegClassID: 856 case AMDGPU::TTMP_128RegClassID: 857 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 858 // this bundle? 859 case AMDGPU::SGPR_256RegClassID: 860 case AMDGPU::TTMP_256RegClassID: 861 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 862 // this bundle? 863 case AMDGPU::SGPR_512RegClassID: 864 case AMDGPU::TTMP_512RegClassID: 865 shift = 2; 866 break; 867 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 868 // this bundle? 869 default: 870 llvm_unreachable("unhandled register class"); 871 } 872 873 if (Val % (1 << shift)) { 874 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 875 << ": scalar reg isn't aligned " << Val; 876 } 877 878 return createRegOperand(SRegClassID, Val >> shift); 879 } 880 881 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 882 return decodeSrcOp(OPW32, Val); 883 } 884 885 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 886 return decodeSrcOp(OPW64, Val); 887 } 888 889 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 890 return decodeSrcOp(OPW128, Val); 891 } 892 893 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 894 return decodeSrcOp(OPW16, Val); 895 } 896 897 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 898 return decodeSrcOp(OPWV216, Val); 899 } 900 901 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 902 return decodeSrcOp(OPWV232, Val); 903 } 904 905 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 906 // Some instructions have operand restrictions beyond what the encoding 907 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 908 // high bit. 909 Val &= 255; 910 911 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 912 } 913 914 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 915 return decodeSrcOp(OPW32, Val); 916 } 917 918 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 919 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 920 } 921 922 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 923 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 924 } 925 926 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 927 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 928 } 929 930 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 931 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 932 } 933 934 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 935 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 936 } 937 938 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 939 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 940 } 941 942 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 943 return decodeSrcOp(OPW32, Val); 944 } 945 946 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 947 return decodeSrcOp(OPW64, Val); 948 } 949 950 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 951 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 952 } 953 954 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 955 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 956 } 957 958 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 959 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 960 } 961 962 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 963 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 964 } 965 966 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 967 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 968 } 969 970 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 971 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 972 } 973 974 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 975 // table-gen generated disassembler doesn't care about operand types 976 // leaving only registry class so SSrc_32 operand turns into SReg_32 977 // and therefore we accept immediates and literals here as well 978 return decodeSrcOp(OPW32, Val); 979 } 980 981 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 982 unsigned Val) const { 983 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 984 return decodeOperand_SReg_32(Val); 985 } 986 987 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 988 unsigned Val) const { 989 // SReg_32_XM0 is SReg_32 without EXEC_HI 990 return decodeOperand_SReg_32(Val); 991 } 992 993 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 994 // table-gen generated disassembler doesn't care about operand types 995 // leaving only registry class so SSrc_32 operand turns into SReg_32 996 // and therefore we accept immediates and literals here as well 997 return decodeSrcOp(OPW32, Val); 998 } 999 1000 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1001 return decodeSrcOp(OPW64, Val); 1002 } 1003 1004 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1005 return decodeSrcOp(OPW64, Val); 1006 } 1007 1008 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1009 return decodeSrcOp(OPW128, Val); 1010 } 1011 1012 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1013 return decodeDstOp(OPW256, Val); 1014 } 1015 1016 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1017 return decodeDstOp(OPW512, Val); 1018 } 1019 1020 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1021 // For now all literal constants are supposed to be unsigned integer 1022 // ToDo: deal with signed/unsigned 64-bit integer constants 1023 // ToDo: deal with float/double constants 1024 if (!HasLiteral) { 1025 if (Bytes.size() < 4) { 1026 return errOperand(0, "cannot read literal, inst bytes left " + 1027 Twine(Bytes.size())); 1028 } 1029 HasLiteral = true; 1030 Literal = eatBytes<uint32_t>(Bytes); 1031 } 1032 return MCOperand::createImm(Literal); 1033 } 1034 1035 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1036 using namespace AMDGPU::EncValues; 1037 1038 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1039 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1040 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1041 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1042 // Cast prevents negative overflow. 1043 } 1044 1045 static int64_t getInlineImmVal32(unsigned Imm) { 1046 switch (Imm) { 1047 case 240: 1048 return FloatToBits(0.5f); 1049 case 241: 1050 return FloatToBits(-0.5f); 1051 case 242: 1052 return FloatToBits(1.0f); 1053 case 243: 1054 return FloatToBits(-1.0f); 1055 case 244: 1056 return FloatToBits(2.0f); 1057 case 245: 1058 return FloatToBits(-2.0f); 1059 case 246: 1060 return FloatToBits(4.0f); 1061 case 247: 1062 return FloatToBits(-4.0f); 1063 case 248: // 1 / (2 * PI) 1064 return 0x3e22f983; 1065 default: 1066 llvm_unreachable("invalid fp inline imm"); 1067 } 1068 } 1069 1070 static int64_t getInlineImmVal64(unsigned Imm) { 1071 switch (Imm) { 1072 case 240: 1073 return DoubleToBits(0.5); 1074 case 241: 1075 return DoubleToBits(-0.5); 1076 case 242: 1077 return DoubleToBits(1.0); 1078 case 243: 1079 return DoubleToBits(-1.0); 1080 case 244: 1081 return DoubleToBits(2.0); 1082 case 245: 1083 return DoubleToBits(-2.0); 1084 case 246: 1085 return DoubleToBits(4.0); 1086 case 247: 1087 return DoubleToBits(-4.0); 1088 case 248: // 1 / (2 * PI) 1089 return 0x3fc45f306dc9c882; 1090 default: 1091 llvm_unreachable("invalid fp inline imm"); 1092 } 1093 } 1094 1095 static int64_t getInlineImmVal16(unsigned Imm) { 1096 switch (Imm) { 1097 case 240: 1098 return 0x3800; 1099 case 241: 1100 return 0xB800; 1101 case 242: 1102 return 0x3C00; 1103 case 243: 1104 return 0xBC00; 1105 case 244: 1106 return 0x4000; 1107 case 245: 1108 return 0xC000; 1109 case 246: 1110 return 0x4400; 1111 case 247: 1112 return 0xC400; 1113 case 248: // 1 / (2 * PI) 1114 return 0x3118; 1115 default: 1116 llvm_unreachable("invalid fp inline imm"); 1117 } 1118 } 1119 1120 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1121 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1122 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1123 1124 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1125 switch (Width) { 1126 case OPW32: 1127 case OPW128: // splat constants 1128 case OPW512: 1129 case OPW1024: 1130 case OPWV232: 1131 return MCOperand::createImm(getInlineImmVal32(Imm)); 1132 case OPW64: 1133 case OPW256: 1134 return MCOperand::createImm(getInlineImmVal64(Imm)); 1135 case OPW16: 1136 case OPWV216: 1137 return MCOperand::createImm(getInlineImmVal16(Imm)); 1138 default: 1139 llvm_unreachable("implement me"); 1140 } 1141 } 1142 1143 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1144 using namespace AMDGPU; 1145 1146 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1147 switch (Width) { 1148 default: // fall 1149 case OPW32: 1150 case OPW16: 1151 case OPWV216: 1152 return VGPR_32RegClassID; 1153 case OPW64: 1154 case OPWV232: return VReg_64RegClassID; 1155 case OPW96: return VReg_96RegClassID; 1156 case OPW128: return VReg_128RegClassID; 1157 case OPW160: return VReg_160RegClassID; 1158 case OPW256: return VReg_256RegClassID; 1159 case OPW512: return VReg_512RegClassID; 1160 case OPW1024: return VReg_1024RegClassID; 1161 } 1162 } 1163 1164 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1165 using namespace AMDGPU; 1166 1167 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1168 switch (Width) { 1169 default: // fall 1170 case OPW32: 1171 case OPW16: 1172 case OPWV216: 1173 return AGPR_32RegClassID; 1174 case OPW64: 1175 case OPWV232: return AReg_64RegClassID; 1176 case OPW96: return AReg_96RegClassID; 1177 case OPW128: return AReg_128RegClassID; 1178 case OPW160: return AReg_160RegClassID; 1179 case OPW256: return AReg_256RegClassID; 1180 case OPW512: return AReg_512RegClassID; 1181 case OPW1024: return AReg_1024RegClassID; 1182 } 1183 } 1184 1185 1186 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1187 using namespace AMDGPU; 1188 1189 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1190 switch (Width) { 1191 default: // fall 1192 case OPW32: 1193 case OPW16: 1194 case OPWV216: 1195 return SGPR_32RegClassID; 1196 case OPW64: 1197 case OPWV232: return SGPR_64RegClassID; 1198 case OPW96: return SGPR_96RegClassID; 1199 case OPW128: return SGPR_128RegClassID; 1200 case OPW160: return SGPR_160RegClassID; 1201 case OPW256: return SGPR_256RegClassID; 1202 case OPW512: return SGPR_512RegClassID; 1203 } 1204 } 1205 1206 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1207 using namespace AMDGPU; 1208 1209 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1210 switch (Width) { 1211 default: // fall 1212 case OPW32: 1213 case OPW16: 1214 case OPWV216: 1215 return TTMP_32RegClassID; 1216 case OPW64: 1217 case OPWV232: return TTMP_64RegClassID; 1218 case OPW128: return TTMP_128RegClassID; 1219 case OPW256: return TTMP_256RegClassID; 1220 case OPW512: return TTMP_512RegClassID; 1221 } 1222 } 1223 1224 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1225 using namespace AMDGPU::EncValues; 1226 1227 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1228 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1229 1230 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1231 } 1232 1233 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 1234 using namespace AMDGPU::EncValues; 1235 1236 assert(Val < 1024); // enum10 1237 1238 bool IsAGPR = Val & 512; 1239 Val &= 511; 1240 1241 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1242 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1243 : getVgprClassId(Width), Val - VGPR_MIN); 1244 } 1245 if (Val <= SGPR_MAX) { 1246 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1247 static_assert(SGPR_MIN == 0, ""); 1248 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1249 } 1250 1251 int TTmpIdx = getTTmpIdx(Val); 1252 if (TTmpIdx >= 0) { 1253 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1254 } 1255 1256 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1257 return decodeIntImmed(Val); 1258 1259 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1260 return decodeFPImmed(Width, Val); 1261 1262 if (Val == LITERAL_CONST) 1263 return decodeLiteralConstant(); 1264 1265 switch (Width) { 1266 case OPW32: 1267 case OPW16: 1268 case OPWV216: 1269 return decodeSpecialReg32(Val); 1270 case OPW64: 1271 case OPWV232: 1272 return decodeSpecialReg64(Val); 1273 default: 1274 llvm_unreachable("unexpected immediate type"); 1275 } 1276 } 1277 1278 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1279 using namespace AMDGPU::EncValues; 1280 1281 assert(Val < 128); 1282 assert(Width == OPW256 || Width == OPW512); 1283 1284 if (Val <= SGPR_MAX) { 1285 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1286 static_assert(SGPR_MIN == 0, ""); 1287 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1288 } 1289 1290 int TTmpIdx = getTTmpIdx(Val); 1291 if (TTmpIdx >= 0) { 1292 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1293 } 1294 1295 llvm_unreachable("unknown dst register"); 1296 } 1297 1298 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1299 using namespace AMDGPU; 1300 1301 switch (Val) { 1302 case 102: return createRegOperand(FLAT_SCR_LO); 1303 case 103: return createRegOperand(FLAT_SCR_HI); 1304 case 104: return createRegOperand(XNACK_MASK_LO); 1305 case 105: return createRegOperand(XNACK_MASK_HI); 1306 case 106: return createRegOperand(VCC_LO); 1307 case 107: return createRegOperand(VCC_HI); 1308 case 108: return createRegOperand(TBA_LO); 1309 case 109: return createRegOperand(TBA_HI); 1310 case 110: return createRegOperand(TMA_LO); 1311 case 111: return createRegOperand(TMA_HI); 1312 case 124: return createRegOperand(M0); 1313 case 125: return createRegOperand(SGPR_NULL); 1314 case 126: return createRegOperand(EXEC_LO); 1315 case 127: return createRegOperand(EXEC_HI); 1316 case 235: return createRegOperand(SRC_SHARED_BASE); 1317 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1318 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1319 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1320 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1321 case 251: return createRegOperand(SRC_VCCZ); 1322 case 252: return createRegOperand(SRC_EXECZ); 1323 case 253: return createRegOperand(SRC_SCC); 1324 case 254: return createRegOperand(LDS_DIRECT); 1325 default: break; 1326 } 1327 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1328 } 1329 1330 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1331 using namespace AMDGPU; 1332 1333 switch (Val) { 1334 case 102: return createRegOperand(FLAT_SCR); 1335 case 104: return createRegOperand(XNACK_MASK); 1336 case 106: return createRegOperand(VCC); 1337 case 108: return createRegOperand(TBA); 1338 case 110: return createRegOperand(TMA); 1339 case 125: return createRegOperand(SGPR_NULL); 1340 case 126: return createRegOperand(EXEC); 1341 case 235: return createRegOperand(SRC_SHARED_BASE); 1342 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1343 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1344 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1345 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1346 case 251: return createRegOperand(SRC_VCCZ); 1347 case 252: return createRegOperand(SRC_EXECZ); 1348 case 253: return createRegOperand(SRC_SCC); 1349 default: break; 1350 } 1351 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1352 } 1353 1354 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1355 const unsigned Val) const { 1356 using namespace AMDGPU::SDWA; 1357 using namespace AMDGPU::EncValues; 1358 1359 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1360 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1361 // XXX: cast to int is needed to avoid stupid warning: 1362 // compare with unsigned is always true 1363 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1364 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1365 return createRegOperand(getVgprClassId(Width), 1366 Val - SDWA9EncValues::SRC_VGPR_MIN); 1367 } 1368 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1369 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1370 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1371 return createSRegOperand(getSgprClassId(Width), 1372 Val - SDWA9EncValues::SRC_SGPR_MIN); 1373 } 1374 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1375 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1376 return createSRegOperand(getTtmpClassId(Width), 1377 Val - SDWA9EncValues::SRC_TTMP_MIN); 1378 } 1379 1380 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1381 1382 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1383 return decodeIntImmed(SVal); 1384 1385 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1386 return decodeFPImmed(Width, SVal); 1387 1388 return decodeSpecialReg32(SVal); 1389 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1390 return createRegOperand(getVgprClassId(Width), Val); 1391 } 1392 llvm_unreachable("unsupported target"); 1393 } 1394 1395 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1396 return decodeSDWASrc(OPW16, Val); 1397 } 1398 1399 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1400 return decodeSDWASrc(OPW32, Val); 1401 } 1402 1403 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1404 using namespace AMDGPU::SDWA; 1405 1406 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1407 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1408 "SDWAVopcDst should be present only on GFX9+"); 1409 1410 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1411 1412 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1413 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1414 1415 int TTmpIdx = getTTmpIdx(Val); 1416 if (TTmpIdx >= 0) { 1417 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1418 return createSRegOperand(TTmpClsId, TTmpIdx); 1419 } else if (Val > SGPR_MAX) { 1420 return IsWave64 ? decodeSpecialReg64(Val) 1421 : decodeSpecialReg32(Val); 1422 } else { 1423 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1424 } 1425 } else { 1426 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1427 } 1428 } 1429 1430 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1431 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1432 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1433 } 1434 1435 bool AMDGPUDisassembler::isVI() const { 1436 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1437 } 1438 1439 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1440 1441 bool AMDGPUDisassembler::isGFX90A() const { 1442 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1443 } 1444 1445 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1446 1447 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1448 1449 bool AMDGPUDisassembler::isGFX10Plus() const { 1450 return AMDGPU::isGFX10Plus(STI); 1451 } 1452 1453 //===----------------------------------------------------------------------===// 1454 // AMDGPU specific symbol handling 1455 //===----------------------------------------------------------------------===// 1456 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1457 do { \ 1458 KdStream << Indent << DIRECTIVE " " \ 1459 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1460 } while (0) 1461 1462 // NOLINTNEXTLINE(readability-identifier-naming) 1463 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1464 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1465 using namespace amdhsa; 1466 StringRef Indent = "\t"; 1467 1468 // We cannot accurately backward compute #VGPRs used from 1469 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1470 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1471 // simply calculate the inverse of what the assembler does. 1472 1473 uint32_t GranulatedWorkitemVGPRCount = 1474 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1475 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1476 1477 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1478 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1479 1480 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1481 1482 // We cannot backward compute values used to calculate 1483 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1484 // directives can't be computed: 1485 // .amdhsa_reserve_vcc 1486 // .amdhsa_reserve_flat_scratch 1487 // .amdhsa_reserve_xnack_mask 1488 // They take their respective default values if not specified in the assembly. 1489 // 1490 // GRANULATED_WAVEFRONT_SGPR_COUNT 1491 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1492 // 1493 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1494 // are set to 0. So while disassembling we consider that: 1495 // 1496 // GRANULATED_WAVEFRONT_SGPR_COUNT 1497 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1498 // 1499 // The disassembler cannot recover the original values of those 3 directives. 1500 1501 uint32_t GranulatedWavefrontSGPRCount = 1502 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1503 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1504 1505 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1506 return MCDisassembler::Fail; 1507 1508 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1509 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1510 1511 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1512 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1513 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1514 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1515 1516 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1517 return MCDisassembler::Fail; 1518 1519 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1520 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1521 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1522 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1523 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1524 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1525 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1526 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1527 1528 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1529 return MCDisassembler::Fail; 1530 1531 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1532 1533 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1534 return MCDisassembler::Fail; 1535 1536 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1537 1538 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1539 return MCDisassembler::Fail; 1540 1541 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1542 return MCDisassembler::Fail; 1543 1544 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1545 1546 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1547 return MCDisassembler::Fail; 1548 1549 if (isGFX10Plus()) { 1550 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1551 COMPUTE_PGM_RSRC1_WGP_MODE); 1552 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1553 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1554 } 1555 return MCDisassembler::Success; 1556 } 1557 1558 // NOLINTNEXTLINE(readability-identifier-naming) 1559 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1560 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1561 using namespace amdhsa; 1562 StringRef Indent = "\t"; 1563 PRINT_DIRECTIVE( 1564 ".amdhsa_system_sgpr_private_segment_wavefront_offset", 1565 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1566 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1567 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1568 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1569 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1570 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1571 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1572 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1573 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1574 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1575 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1576 1577 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1578 return MCDisassembler::Fail; 1579 1580 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1581 return MCDisassembler::Fail; 1582 1583 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1584 return MCDisassembler::Fail; 1585 1586 PRINT_DIRECTIVE( 1587 ".amdhsa_exception_fp_ieee_invalid_op", 1588 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1589 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1590 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1591 PRINT_DIRECTIVE( 1592 ".amdhsa_exception_fp_ieee_div_zero", 1593 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1594 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1595 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1596 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1597 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1598 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1599 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1600 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1601 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1602 1603 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1604 return MCDisassembler::Fail; 1605 1606 return MCDisassembler::Success; 1607 } 1608 1609 #undef PRINT_DIRECTIVE 1610 1611 MCDisassembler::DecodeStatus 1612 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1613 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1614 raw_string_ostream &KdStream) const { 1615 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1616 do { \ 1617 KdStream << Indent << DIRECTIVE " " \ 1618 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1619 } while (0) 1620 1621 uint16_t TwoByteBuffer = 0; 1622 uint32_t FourByteBuffer = 0; 1623 uint64_t EightByteBuffer = 0; 1624 1625 StringRef ReservedBytes; 1626 StringRef Indent = "\t"; 1627 1628 assert(Bytes.size() == 64); 1629 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1630 1631 switch (Cursor.tell()) { 1632 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1633 FourByteBuffer = DE.getU32(Cursor); 1634 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1635 << '\n'; 1636 return MCDisassembler::Success; 1637 1638 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1639 FourByteBuffer = DE.getU32(Cursor); 1640 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1641 << FourByteBuffer << '\n'; 1642 return MCDisassembler::Success; 1643 1644 case amdhsa::RESERVED0_OFFSET: 1645 // 8 reserved bytes, must be 0. 1646 EightByteBuffer = DE.getU64(Cursor); 1647 if (EightByteBuffer) { 1648 return MCDisassembler::Fail; 1649 } 1650 return MCDisassembler::Success; 1651 1652 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1653 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1654 // So far no directive controls this for Code Object V3, so simply skip for 1655 // disassembly. 1656 DE.skip(Cursor, 8); 1657 return MCDisassembler::Success; 1658 1659 case amdhsa::RESERVED1_OFFSET: 1660 // 20 reserved bytes, must be 0. 1661 ReservedBytes = DE.getBytes(Cursor, 20); 1662 for (int I = 0; I < 20; ++I) { 1663 if (ReservedBytes[I] != 0) { 1664 return MCDisassembler::Fail; 1665 } 1666 } 1667 return MCDisassembler::Success; 1668 1669 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1670 // COMPUTE_PGM_RSRC3 1671 // - Only set for GFX10, GFX6-9 have this to be 0. 1672 // - Currently no directives directly control this. 1673 FourByteBuffer = DE.getU32(Cursor); 1674 if (!isGFX10Plus() && FourByteBuffer) { 1675 return MCDisassembler::Fail; 1676 } 1677 return MCDisassembler::Success; 1678 1679 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1680 FourByteBuffer = DE.getU32(Cursor); 1681 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1682 MCDisassembler::Fail) { 1683 return MCDisassembler::Fail; 1684 } 1685 return MCDisassembler::Success; 1686 1687 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1688 FourByteBuffer = DE.getU32(Cursor); 1689 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1690 MCDisassembler::Fail) { 1691 return MCDisassembler::Fail; 1692 } 1693 return MCDisassembler::Success; 1694 1695 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1696 using namespace amdhsa; 1697 TwoByteBuffer = DE.getU16(Cursor); 1698 1699 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1700 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1701 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1702 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1703 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1704 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1705 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1706 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1707 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1708 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1709 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1710 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1711 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1712 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1713 1714 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1715 return MCDisassembler::Fail; 1716 1717 // Reserved for GFX9 1718 if (isGFX9() && 1719 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1720 return MCDisassembler::Fail; 1721 } else if (isGFX10Plus()) { 1722 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1723 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1724 } 1725 1726 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1727 return MCDisassembler::Fail; 1728 1729 return MCDisassembler::Success; 1730 1731 case amdhsa::RESERVED2_OFFSET: 1732 // 6 bytes from here are reserved, must be 0. 1733 ReservedBytes = DE.getBytes(Cursor, 6); 1734 for (int I = 0; I < 6; ++I) { 1735 if (ReservedBytes[I] != 0) 1736 return MCDisassembler::Fail; 1737 } 1738 return MCDisassembler::Success; 1739 1740 default: 1741 llvm_unreachable("Unhandled index. Case statements cover everything."); 1742 return MCDisassembler::Fail; 1743 } 1744 #undef PRINT_DIRECTIVE 1745 } 1746 1747 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1748 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1749 // CP microcode requires the kernel descriptor to be 64 aligned. 1750 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1751 return MCDisassembler::Fail; 1752 1753 std::string Kd; 1754 raw_string_ostream KdStream(Kd); 1755 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1756 1757 DataExtractor::Cursor C(0); 1758 while (C && C.tell() < Bytes.size()) { 1759 MCDisassembler::DecodeStatus Status = 1760 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1761 1762 cantFail(C.takeError()); 1763 1764 if (Status == MCDisassembler::Fail) 1765 return MCDisassembler::Fail; 1766 } 1767 KdStream << ".end_amdhsa_kernel\n"; 1768 outs() << KdStream.str(); 1769 return MCDisassembler::Success; 1770 } 1771 1772 Optional<MCDisassembler::DecodeStatus> 1773 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1774 ArrayRef<uint8_t> Bytes, uint64_t Address, 1775 raw_ostream &CStream) const { 1776 // Right now only kernel descriptor needs to be handled. 1777 // We ignore all other symbols for target specific handling. 1778 // TODO: 1779 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1780 // Object V2 and V3 when symbols are marked protected. 1781 1782 // amd_kernel_code_t for Code Object V2. 1783 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1784 Size = 256; 1785 return MCDisassembler::Fail; 1786 } 1787 1788 // Code Object V3 kernel descriptors. 1789 StringRef Name = Symbol.Name; 1790 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1791 Size = 64; // Size = 64 regardless of success or failure. 1792 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1793 } 1794 return None; 1795 } 1796 1797 //===----------------------------------------------------------------------===// 1798 // AMDGPUSymbolizer 1799 //===----------------------------------------------------------------------===// 1800 1801 // Try to find symbol name for specified label 1802 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1803 raw_ostream &/*cStream*/, int64_t Value, 1804 uint64_t /*Address*/, bool IsBranch, 1805 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1806 1807 if (!IsBranch) { 1808 return false; 1809 } 1810 1811 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1812 if (!Symbols) 1813 return false; 1814 1815 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1816 return Val.Addr == static_cast<uint64_t>(Value) && 1817 Val.Type == ELF::STT_NOTYPE; 1818 }); 1819 if (Result != Symbols->end()) { 1820 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1821 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1822 Inst.addOperand(MCOperand::createExpr(Add)); 1823 return true; 1824 } 1825 return false; 1826 } 1827 1828 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1829 int64_t Value, 1830 uint64_t Address) { 1831 llvm_unreachable("unimplemented"); 1832 } 1833 1834 //===----------------------------------------------------------------------===// 1835 // Initialization 1836 //===----------------------------------------------------------------------===// 1837 1838 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1839 LLVMOpInfoCallback /*GetOpInfo*/, 1840 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1841 void *DisInfo, 1842 MCContext *Ctx, 1843 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1844 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1845 } 1846 1847 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1848 const MCSubtargetInfo &STI, 1849 MCContext &Ctx) { 1850 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1851 } 1852 1853 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1854 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1855 createAMDGPUDisassembler); 1856 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1857 createAMDGPUSymbolizer); 1858 } 1859