1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/BinaryFormat/ELF.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCDecoderOps.h" 28 #include "llvm/MC/MCExpr.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/AMDHSAKernelDescriptor.h" 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 #define SGPR_MAX \ 40 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 41 : AMDGPU::EncValues::SGPR_MAX_SI) 42 43 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 44 45 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 46 MCContext &Ctx, 47 MCInstrInfo const *MCII) : 48 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 49 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 50 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 95 Offset = Imm & 0xFFFFF; 96 } else { // GFX9+ supports 21-bit signed offsets. 97 Offset = SignExtend64<21>(Imm); 98 } 99 return addOperand(Inst, MCOperand::createImm(Offset)); 100 } 101 102 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 103 const MCDisassembler *Decoder) { 104 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 105 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 106 } 107 108 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 109 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const MCDisassembler *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 #define DECODE_OPERAND_REG(RegClass) \ 117 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 118 119 DECODE_OPERAND_REG(VGPR_32) 120 DECODE_OPERAND_REG(VRegOrLds_32) 121 DECODE_OPERAND_REG(VS_32) 122 DECODE_OPERAND_REG(VS_64) 123 DECODE_OPERAND_REG(VS_128) 124 125 DECODE_OPERAND_REG(VReg_64) 126 DECODE_OPERAND_REG(VReg_96) 127 DECODE_OPERAND_REG(VReg_128) 128 DECODE_OPERAND_REG(VReg_256) 129 DECODE_OPERAND_REG(VReg_512) 130 DECODE_OPERAND_REG(VReg_1024) 131 132 DECODE_OPERAND_REG(SReg_32) 133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 135 DECODE_OPERAND_REG(SRegOrLds_32) 136 DECODE_OPERAND_REG(SReg_64) 137 DECODE_OPERAND_REG(SReg_64_XEXEC) 138 DECODE_OPERAND_REG(SReg_128) 139 DECODE_OPERAND_REG(SReg_256) 140 DECODE_OPERAND_REG(SReg_512) 141 142 DECODE_OPERAND_REG(AGPR_32) 143 DECODE_OPERAND_REG(AReg_64) 144 DECODE_OPERAND_REG(AReg_128) 145 DECODE_OPERAND_REG(AReg_256) 146 DECODE_OPERAND_REG(AReg_512) 147 DECODE_OPERAND_REG(AReg_1024) 148 DECODE_OPERAND_REG(AV_32) 149 DECODE_OPERAND_REG(AV_64) 150 DECODE_OPERAND_REG(AV_128) 151 DECODE_OPERAND_REG(AVDst_128) 152 DECODE_OPERAND_REG(AVDst_512) 153 154 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 155 uint64_t Addr, 156 const MCDisassembler *Decoder) { 157 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 158 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 159 } 160 161 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 162 uint64_t Addr, 163 const MCDisassembler *Decoder) { 164 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 165 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 166 } 167 168 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 169 uint64_t Addr, 170 const MCDisassembler *Decoder) { 171 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 172 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 173 } 174 175 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 176 uint64_t Addr, 177 const MCDisassembler *Decoder) { 178 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 179 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 180 } 181 182 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 183 uint64_t Addr, 184 const MCDisassembler *Decoder) { 185 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 186 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 187 } 188 189 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 190 uint64_t Addr, 191 const MCDisassembler *Decoder) { 192 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 193 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 194 } 195 196 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 197 uint64_t Addr, 198 const MCDisassembler *Decoder) { 199 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 200 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 201 } 202 203 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 204 uint64_t Addr, 205 const MCDisassembler *Decoder) { 206 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 207 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 208 } 209 210 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, 212 const MCDisassembler *Decoder) { 213 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 214 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 215 } 216 217 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 218 uint64_t Addr, 219 const MCDisassembler *Decoder) { 220 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 221 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 222 } 223 224 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 225 uint64_t Addr, 226 const MCDisassembler *Decoder) { 227 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 228 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 229 } 230 231 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 232 uint64_t Addr, 233 const MCDisassembler *Decoder) { 234 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 235 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 236 } 237 238 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 239 uint64_t Addr, 240 const MCDisassembler *Decoder) { 241 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 242 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 243 } 244 245 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 246 uint64_t Addr, 247 const MCDisassembler *Decoder) { 248 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 249 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 250 } 251 252 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 253 uint64_t Addr, 254 const MCDisassembler *Decoder) { 255 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 256 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 257 } 258 259 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 260 uint64_t Addr, 261 const MCDisassembler *Decoder) { 262 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 263 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 264 } 265 266 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 267 uint64_t Addr, 268 const MCDisassembler *Decoder) { 269 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 270 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 271 } 272 273 static DecodeStatus 274 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 275 const MCDisassembler *Decoder) { 276 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 277 return addOperand( 278 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 279 } 280 281 static DecodeStatus 282 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 283 const MCDisassembler *Decoder) { 284 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 285 return addOperand( 286 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 287 } 288 289 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 290 const MCRegisterInfo *MRI) { 291 if (OpIdx < 0) 292 return false; 293 294 const MCOperand &Op = Inst.getOperand(OpIdx); 295 if (!Op.isReg()) 296 return false; 297 298 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 299 auto Reg = Sub ? Sub : Op.getReg(); 300 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 301 } 302 303 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 304 AMDGPUDisassembler::OpWidthTy Opw, 305 const MCDisassembler *Decoder) { 306 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 307 if (!DAsm->isGFX90A()) { 308 Imm &= 511; 309 } else { 310 // If atomic has both vdata and vdst their register classes are tied. 311 // The bit is decoded along with the vdst, first operand. We need to 312 // change register class to AGPR if vdst was AGPR. 313 // If a DS instruction has both data0 and data1 their register classes 314 // are also tied. 315 unsigned Opc = Inst.getOpcode(); 316 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 317 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 318 : AMDGPU::OpName::vdata; 319 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 320 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 321 if ((int)Inst.getNumOperands() == DataIdx) { 322 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 323 if (IsAGPROperand(Inst, DstIdx, MRI)) 324 Imm |= 512; 325 } 326 327 if (TSFlags & SIInstrFlags::DS) { 328 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 329 if ((int)Inst.getNumOperands() == Data2Idx && 330 IsAGPROperand(Inst, DataIdx, MRI)) 331 Imm |= 512; 332 } 333 } 334 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 335 } 336 337 static DecodeStatus 338 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 339 const MCDisassembler *Decoder) { 340 return decodeOperand_AVLdSt_Any(Inst, Imm, 341 AMDGPUDisassembler::OPW32, Decoder); 342 } 343 344 static DecodeStatus 345 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 346 const MCDisassembler *Decoder) { 347 return decodeOperand_AVLdSt_Any(Inst, Imm, 348 AMDGPUDisassembler::OPW64, Decoder); 349 } 350 351 static DecodeStatus 352 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 353 const MCDisassembler *Decoder) { 354 return decodeOperand_AVLdSt_Any(Inst, Imm, 355 AMDGPUDisassembler::OPW96, Decoder); 356 } 357 358 static DecodeStatus 359 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 360 const MCDisassembler *Decoder) { 361 return decodeOperand_AVLdSt_Any(Inst, Imm, 362 AMDGPUDisassembler::OPW128, Decoder); 363 } 364 365 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 366 uint64_t Addr, 367 const MCDisassembler *Decoder) { 368 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 369 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 370 } 371 372 #define DECODE_SDWA(DecName) \ 373 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 374 375 DECODE_SDWA(Src32) 376 DECODE_SDWA(Src16) 377 DECODE_SDWA(VopcDst) 378 379 #include "AMDGPUGenDisassemblerTables.inc" 380 381 //===----------------------------------------------------------------------===// 382 // 383 //===----------------------------------------------------------------------===// 384 385 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 386 assert(Bytes.size() >= sizeof(T)); 387 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 388 Bytes = Bytes.slice(sizeof(T)); 389 return Res; 390 } 391 392 // The disassembler is greedy, so we need to check FI operand value to 393 // not parse a dpp if the correct literal is not set. For dpp16 the 394 // autogenerated decoder checks the dpp literal 395 static bool isValidDPP8(const MCInst &MI) { 396 using namespace llvm::AMDGPU::DPP; 397 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 398 assert(FiIdx != -1); 399 if ((unsigned)FiIdx >= MI.getNumOperands()) 400 return false; 401 unsigned Fi = MI.getOperand(FiIdx).getImm(); 402 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 403 } 404 405 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 406 ArrayRef<uint8_t> Bytes_, 407 uint64_t Address, 408 raw_ostream &CS) const { 409 CommentStream = &CS; 410 bool IsSDWA = false; 411 412 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 413 Bytes = Bytes_.slice(0, MaxInstBytesNum); 414 415 DecodeStatus Res = MCDisassembler::Fail; 416 do { 417 // ToDo: better to switch encoding length using some bit predicate 418 // but it is unknown yet, so try all we can 419 420 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 421 // encodings 422 if (Bytes.size() >= 8) { 423 const uint64_t QW = eatBytes<uint64_t>(Bytes); 424 425 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 426 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 427 if (Res) { 428 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 429 == -1) 430 break; 431 if (convertDPP8Inst(MI) == MCDisassembler::Success) 432 break; 433 MI = MCInst(); // clear 434 } 435 } 436 437 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 438 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 439 break; 440 441 MI = MCInst(); // clear 442 443 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 444 if (Res) break; 445 446 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 447 if (Res) { IsSDWA = true; break; } 448 449 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 450 if (Res) { IsSDWA = true; break; } 451 452 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 453 if (Res) { IsSDWA = true; break; } 454 455 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 456 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 457 if (Res) 458 break; 459 } 460 461 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 462 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 463 // table first so we print the correct name. 464 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 465 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 466 if (Res) 467 break; 468 } 469 } 470 471 // Reinitialize Bytes as DPP64 could have eaten too much 472 Bytes = Bytes_.slice(0, MaxInstBytesNum); 473 474 // Try decode 32-bit instruction 475 if (Bytes.size() < 4) break; 476 const uint32_t DW = eatBytes<uint32_t>(Bytes); 477 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 478 if (Res) break; 479 480 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 481 if (Res) break; 482 483 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 484 if (Res) break; 485 486 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 487 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 488 if (Res) 489 break; 490 } 491 492 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 493 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 494 if (Res) break; 495 } 496 497 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 498 if (Res) break; 499 500 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 501 if (Res) break; 502 503 if (Bytes.size() < 4) break; 504 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 505 506 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 507 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 508 if (Res) 509 break; 510 } 511 512 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 513 if (Res) break; 514 515 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 516 if (Res) break; 517 518 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 519 if (Res) break; 520 521 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 522 if (Res) break; 523 524 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 525 } while (false); 526 527 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 528 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 529 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 530 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 531 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 532 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 533 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 534 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 535 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 536 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 537 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 538 // Insert dummy unused src2_modifiers. 539 insertNamedMCOperand(MI, MCOperand::createImm(0), 540 AMDGPU::OpName::src2_modifiers); 541 } 542 543 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 544 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 545 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 546 AMDGPU::OpName::cpol); 547 if (CPolPos != -1) { 548 unsigned CPol = 549 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 550 AMDGPU::CPol::GLC : 0; 551 if (MI.getNumOperands() <= (unsigned)CPolPos) { 552 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 553 AMDGPU::OpName::cpol); 554 } else if (CPol) { 555 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 556 } 557 } 558 } 559 560 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 561 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 562 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 563 // GFX90A lost TFE, its place is occupied by ACC. 564 int TFEOpIdx = 565 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 566 if (TFEOpIdx != -1) { 567 auto TFEIter = MI.begin(); 568 std::advance(TFEIter, TFEOpIdx); 569 MI.insert(TFEIter, MCOperand::createImm(0)); 570 } 571 } 572 573 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 574 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 575 int SWZOpIdx = 576 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 577 if (SWZOpIdx != -1) { 578 auto SWZIter = MI.begin(); 579 std::advance(SWZIter, SWZOpIdx); 580 MI.insert(SWZIter, MCOperand::createImm(0)); 581 } 582 } 583 584 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 585 int VAddr0Idx = 586 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 587 int RsrcIdx = 588 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 589 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 590 if (VAddr0Idx >= 0 && NSAArgs > 0) { 591 unsigned NSAWords = (NSAArgs + 3) / 4; 592 if (Bytes.size() < 4 * NSAWords) { 593 Res = MCDisassembler::Fail; 594 } else { 595 for (unsigned i = 0; i < NSAArgs; ++i) { 596 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 597 decodeOperand_VGPR_32(Bytes[i])); 598 } 599 Bytes = Bytes.slice(4 * NSAWords); 600 } 601 } 602 603 if (Res) 604 Res = convertMIMGInst(MI); 605 } 606 607 if (Res && IsSDWA) 608 Res = convertSDWAInst(MI); 609 610 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 611 AMDGPU::OpName::vdst_in); 612 if (VDstIn_Idx != -1) { 613 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 614 MCOI::OperandConstraint::TIED_TO); 615 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 616 !MI.getOperand(VDstIn_Idx).isReg() || 617 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 618 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 619 MI.erase(&MI.getOperand(VDstIn_Idx)); 620 insertNamedMCOperand(MI, 621 MCOperand::createReg(MI.getOperand(Tied).getReg()), 622 AMDGPU::OpName::vdst_in); 623 } 624 } 625 626 int ImmLitIdx = 627 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 628 if (Res && ImmLitIdx != -1) 629 Res = convertFMAanyK(MI, ImmLitIdx); 630 631 // if the opcode was not recognized we'll assume a Size of 4 bytes 632 // (unless there are fewer bytes left) 633 Size = Res ? (MaxInstBytesNum - Bytes.size()) 634 : std::min((size_t)4, Bytes_.size()); 635 return Res; 636 } 637 638 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 639 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 640 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 641 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 642 // VOPC - insert clamp 643 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 644 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 645 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 646 if (SDst != -1) { 647 // VOPC - insert VCC register as sdst 648 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 649 AMDGPU::OpName::sdst); 650 } else { 651 // VOP1/2 - insert omod if present in instruction 652 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 653 } 654 } 655 return MCDisassembler::Success; 656 } 657 658 // We must check FI == literal to reject not genuine dpp8 insts, and we must 659 // first add optional MI operands to check FI 660 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 661 unsigned Opc = MI.getOpcode(); 662 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 663 664 // Insert dummy unused src modifiers. 665 if (MI.getNumOperands() < DescNumOps && 666 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 667 insertNamedMCOperand(MI, MCOperand::createImm(0), 668 AMDGPU::OpName::src0_modifiers); 669 670 if (MI.getNumOperands() < DescNumOps && 671 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 672 insertNamedMCOperand(MI, MCOperand::createImm(0), 673 AMDGPU::OpName::src1_modifiers); 674 675 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 676 } 677 678 // Note that before gfx10, the MIMG encoding provided no information about 679 // VADDR size. Consequently, decoded instructions always show address as if it 680 // has 1 dword, which could be not really so. 681 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 682 683 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 684 AMDGPU::OpName::vdst); 685 686 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 687 AMDGPU::OpName::vdata); 688 int VAddr0Idx = 689 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 690 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 691 AMDGPU::OpName::dmask); 692 693 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 694 AMDGPU::OpName::tfe); 695 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 696 AMDGPU::OpName::d16); 697 698 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 699 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 700 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 701 702 assert(VDataIdx != -1); 703 if (BaseOpcode->BVH) { 704 // Add A16 operand for intersect_ray instructions 705 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 706 addOperand(MI, MCOperand::createImm(1)); 707 } 708 return MCDisassembler::Success; 709 } 710 711 bool IsAtomic = (VDstIdx != -1); 712 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 713 bool IsNSA = false; 714 unsigned AddrSize = Info->VAddrDwords; 715 716 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 717 unsigned DimIdx = 718 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 719 int A16Idx = 720 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 721 const AMDGPU::MIMGDimInfo *Dim = 722 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 723 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 724 725 AddrSize = 726 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 727 728 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 729 if (!IsNSA) { 730 if (AddrSize > 8) 731 AddrSize = 16; 732 } else { 733 if (AddrSize > Info->VAddrDwords) { 734 // The NSA encoding does not contain enough operands for the combination 735 // of base opcode / dimension. Should this be an error? 736 return MCDisassembler::Success; 737 } 738 } 739 } 740 741 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 742 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 743 744 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 745 if (D16 && AMDGPU::hasPackedD16(STI)) { 746 DstSize = (DstSize + 1) / 2; 747 } 748 749 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 750 DstSize += 1; 751 752 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 753 return MCDisassembler::Success; 754 755 int NewOpcode = 756 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 757 if (NewOpcode == -1) 758 return MCDisassembler::Success; 759 760 // Widen the register to the correct number of enabled channels. 761 unsigned NewVdata = AMDGPU::NoRegister; 762 if (DstSize != Info->VDataDwords) { 763 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 764 765 // Get first subregister of VData 766 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 767 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 768 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 769 770 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 771 &MRI.getRegClass(DataRCID)); 772 if (NewVdata == AMDGPU::NoRegister) { 773 // It's possible to encode this such that the low register + enabled 774 // components exceeds the register count. 775 return MCDisassembler::Success; 776 } 777 } 778 779 unsigned NewVAddr0 = AMDGPU::NoRegister; 780 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 781 AddrSize != Info->VAddrDwords) { 782 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 783 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 784 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 785 786 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 787 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 788 &MRI.getRegClass(AddrRCID)); 789 if (NewVAddr0 == AMDGPU::NoRegister) 790 return MCDisassembler::Success; 791 } 792 793 MI.setOpcode(NewOpcode); 794 795 if (NewVdata != AMDGPU::NoRegister) { 796 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 797 798 if (IsAtomic) { 799 // Atomic operations have an additional operand (a copy of data) 800 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 801 } 802 } 803 804 if (NewVAddr0 != AMDGPU::NoRegister) { 805 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 806 } else if (IsNSA) { 807 assert(AddrSize <= Info->VAddrDwords); 808 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 809 MI.begin() + VAddr0Idx + Info->VAddrDwords); 810 } 811 812 return MCDisassembler::Success; 813 } 814 815 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 816 int ImmLitIdx) const { 817 assert(HasLiteral && "Should have decoded a literal"); 818 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 819 unsigned DescNumOps = Desc.getNumOperands(); 820 assert(DescNumOps == MI.getNumOperands()); 821 for (unsigned I = 0; I < DescNumOps; ++I) { 822 auto &Op = MI.getOperand(I); 823 auto OpType = Desc.OpInfo[I].OperandType; 824 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 825 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 826 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 827 IsDeferredOp) 828 Op.setImm(Literal); 829 } 830 return MCDisassembler::Success; 831 } 832 833 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 834 return getContext().getRegisterInfo()-> 835 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 836 } 837 838 inline 839 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 840 const Twine& ErrMsg) const { 841 *CommentStream << "Error: " + ErrMsg; 842 843 // ToDo: add support for error operands to MCInst.h 844 // return MCOperand::createError(V); 845 return MCOperand(); 846 } 847 848 inline 849 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 850 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 851 } 852 853 inline 854 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 855 unsigned Val) const { 856 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 857 if (Val >= RegCl.getNumRegs()) 858 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 859 ": unknown register " + Twine(Val)); 860 return createRegOperand(RegCl.getRegister(Val)); 861 } 862 863 inline 864 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 865 unsigned Val) const { 866 // ToDo: SI/CI have 104 SGPRs, VI - 102 867 // Valery: here we accepting as much as we can, let assembler sort it out 868 int shift = 0; 869 switch (SRegClassID) { 870 case AMDGPU::SGPR_32RegClassID: 871 case AMDGPU::TTMP_32RegClassID: 872 break; 873 case AMDGPU::SGPR_64RegClassID: 874 case AMDGPU::TTMP_64RegClassID: 875 shift = 1; 876 break; 877 case AMDGPU::SGPR_128RegClassID: 878 case AMDGPU::TTMP_128RegClassID: 879 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 880 // this bundle? 881 case AMDGPU::SGPR_256RegClassID: 882 case AMDGPU::TTMP_256RegClassID: 883 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 884 // this bundle? 885 case AMDGPU::SGPR_512RegClassID: 886 case AMDGPU::TTMP_512RegClassID: 887 shift = 2; 888 break; 889 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 890 // this bundle? 891 default: 892 llvm_unreachable("unhandled register class"); 893 } 894 895 if (Val % (1 << shift)) { 896 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 897 << ": scalar reg isn't aligned " << Val; 898 } 899 900 return createRegOperand(SRegClassID, Val >> shift); 901 } 902 903 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 904 return decodeSrcOp(OPW32, Val); 905 } 906 907 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 908 return decodeSrcOp(OPW64, Val); 909 } 910 911 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 912 return decodeSrcOp(OPW128, Val); 913 } 914 915 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 916 return decodeSrcOp(OPW16, Val); 917 } 918 919 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 920 return decodeSrcOp(OPWV216, Val); 921 } 922 923 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 924 return decodeSrcOp(OPWV232, Val); 925 } 926 927 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 928 // Some instructions have operand restrictions beyond what the encoding 929 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 930 // high bit. 931 Val &= 255; 932 933 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 934 } 935 936 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 937 return decodeSrcOp(OPW32, Val); 938 } 939 940 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 941 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 942 } 943 944 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 945 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 946 } 947 948 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 949 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 950 } 951 952 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 953 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 954 } 955 956 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 957 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 958 } 959 960 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 961 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 962 } 963 964 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 965 return decodeSrcOp(OPW32, Val); 966 } 967 968 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 969 return decodeSrcOp(OPW64, Val); 970 } 971 972 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 973 return decodeSrcOp(OPW128, Val); 974 } 975 976 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 977 using namespace AMDGPU::EncValues; 978 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 979 return decodeSrcOp(OPW128, Val | IS_VGPR); 980 } 981 982 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 983 using namespace AMDGPU::EncValues; 984 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 985 return decodeSrcOp(OPW512, Val | IS_VGPR); 986 } 987 988 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 989 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 990 } 991 992 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 993 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 994 } 995 996 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 997 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 998 } 999 1000 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1001 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1002 } 1003 1004 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1005 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1006 } 1007 1008 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1009 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1010 } 1011 1012 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1013 // table-gen generated disassembler doesn't care about operand types 1014 // leaving only registry class so SSrc_32 operand turns into SReg_32 1015 // and therefore we accept immediates and literals here as well 1016 return decodeSrcOp(OPW32, Val); 1017 } 1018 1019 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1020 unsigned Val) const { 1021 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1022 return decodeOperand_SReg_32(Val); 1023 } 1024 1025 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1026 unsigned Val) const { 1027 // SReg_32_XM0 is SReg_32 without EXEC_HI 1028 return decodeOperand_SReg_32(Val); 1029 } 1030 1031 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1032 // table-gen generated disassembler doesn't care about operand types 1033 // leaving only registry class so SSrc_32 operand turns into SReg_32 1034 // and therefore we accept immediates and literals here as well 1035 return decodeSrcOp(OPW32, Val); 1036 } 1037 1038 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1039 return decodeSrcOp(OPW64, Val); 1040 } 1041 1042 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1043 return decodeSrcOp(OPW64, Val); 1044 } 1045 1046 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1047 return decodeSrcOp(OPW128, Val); 1048 } 1049 1050 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1051 return decodeDstOp(OPW256, Val); 1052 } 1053 1054 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1055 return decodeDstOp(OPW512, Val); 1056 } 1057 1058 // Decode Literals for insts which always have a literal in the encoding 1059 MCOperand 1060 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1061 if (HasLiteral) { 1062 if (Literal != Val) 1063 return errOperand(Val, "More than one unique literal is illegal"); 1064 } 1065 HasLiteral = true; 1066 Literal = Val; 1067 return MCOperand::createImm(Literal); 1068 } 1069 1070 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1071 // For now all literal constants are supposed to be unsigned integer 1072 // ToDo: deal with signed/unsigned 64-bit integer constants 1073 // ToDo: deal with float/double constants 1074 if (!HasLiteral) { 1075 if (Bytes.size() < 4) { 1076 return errOperand(0, "cannot read literal, inst bytes left " + 1077 Twine(Bytes.size())); 1078 } 1079 HasLiteral = true; 1080 Literal = eatBytes<uint32_t>(Bytes); 1081 } 1082 return MCOperand::createImm(Literal); 1083 } 1084 1085 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1086 using namespace AMDGPU::EncValues; 1087 1088 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1089 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1090 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1091 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1092 // Cast prevents negative overflow. 1093 } 1094 1095 static int64_t getInlineImmVal32(unsigned Imm) { 1096 switch (Imm) { 1097 case 240: 1098 return FloatToBits(0.5f); 1099 case 241: 1100 return FloatToBits(-0.5f); 1101 case 242: 1102 return FloatToBits(1.0f); 1103 case 243: 1104 return FloatToBits(-1.0f); 1105 case 244: 1106 return FloatToBits(2.0f); 1107 case 245: 1108 return FloatToBits(-2.0f); 1109 case 246: 1110 return FloatToBits(4.0f); 1111 case 247: 1112 return FloatToBits(-4.0f); 1113 case 248: // 1 / (2 * PI) 1114 return 0x3e22f983; 1115 default: 1116 llvm_unreachable("invalid fp inline imm"); 1117 } 1118 } 1119 1120 static int64_t getInlineImmVal64(unsigned Imm) { 1121 switch (Imm) { 1122 case 240: 1123 return DoubleToBits(0.5); 1124 case 241: 1125 return DoubleToBits(-0.5); 1126 case 242: 1127 return DoubleToBits(1.0); 1128 case 243: 1129 return DoubleToBits(-1.0); 1130 case 244: 1131 return DoubleToBits(2.0); 1132 case 245: 1133 return DoubleToBits(-2.0); 1134 case 246: 1135 return DoubleToBits(4.0); 1136 case 247: 1137 return DoubleToBits(-4.0); 1138 case 248: // 1 / (2 * PI) 1139 return 0x3fc45f306dc9c882; 1140 default: 1141 llvm_unreachable("invalid fp inline imm"); 1142 } 1143 } 1144 1145 static int64_t getInlineImmVal16(unsigned Imm) { 1146 switch (Imm) { 1147 case 240: 1148 return 0x3800; 1149 case 241: 1150 return 0xB800; 1151 case 242: 1152 return 0x3C00; 1153 case 243: 1154 return 0xBC00; 1155 case 244: 1156 return 0x4000; 1157 case 245: 1158 return 0xC000; 1159 case 246: 1160 return 0x4400; 1161 case 247: 1162 return 0xC400; 1163 case 248: // 1 / (2 * PI) 1164 return 0x3118; 1165 default: 1166 llvm_unreachable("invalid fp inline imm"); 1167 } 1168 } 1169 1170 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1171 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1172 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1173 1174 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1175 switch (Width) { 1176 case OPW32: 1177 case OPW128: // splat constants 1178 case OPW512: 1179 case OPW1024: 1180 case OPWV232: 1181 return MCOperand::createImm(getInlineImmVal32(Imm)); 1182 case OPW64: 1183 case OPW256: 1184 return MCOperand::createImm(getInlineImmVal64(Imm)); 1185 case OPW16: 1186 case OPWV216: 1187 return MCOperand::createImm(getInlineImmVal16(Imm)); 1188 default: 1189 llvm_unreachable("implement me"); 1190 } 1191 } 1192 1193 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1194 using namespace AMDGPU; 1195 1196 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1197 switch (Width) { 1198 default: // fall 1199 case OPW32: 1200 case OPW16: 1201 case OPWV216: 1202 return VGPR_32RegClassID; 1203 case OPW64: 1204 case OPWV232: return VReg_64RegClassID; 1205 case OPW96: return VReg_96RegClassID; 1206 case OPW128: return VReg_128RegClassID; 1207 case OPW160: return VReg_160RegClassID; 1208 case OPW256: return VReg_256RegClassID; 1209 case OPW512: return VReg_512RegClassID; 1210 case OPW1024: return VReg_1024RegClassID; 1211 } 1212 } 1213 1214 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1215 using namespace AMDGPU; 1216 1217 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1218 switch (Width) { 1219 default: // fall 1220 case OPW32: 1221 case OPW16: 1222 case OPWV216: 1223 return AGPR_32RegClassID; 1224 case OPW64: 1225 case OPWV232: return AReg_64RegClassID; 1226 case OPW96: return AReg_96RegClassID; 1227 case OPW128: return AReg_128RegClassID; 1228 case OPW160: return AReg_160RegClassID; 1229 case OPW256: return AReg_256RegClassID; 1230 case OPW512: return AReg_512RegClassID; 1231 case OPW1024: return AReg_1024RegClassID; 1232 } 1233 } 1234 1235 1236 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1237 using namespace AMDGPU; 1238 1239 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1240 switch (Width) { 1241 default: // fall 1242 case OPW32: 1243 case OPW16: 1244 case OPWV216: 1245 return SGPR_32RegClassID; 1246 case OPW64: 1247 case OPWV232: return SGPR_64RegClassID; 1248 case OPW96: return SGPR_96RegClassID; 1249 case OPW128: return SGPR_128RegClassID; 1250 case OPW160: return SGPR_160RegClassID; 1251 case OPW256: return SGPR_256RegClassID; 1252 case OPW512: return SGPR_512RegClassID; 1253 } 1254 } 1255 1256 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1257 using namespace AMDGPU; 1258 1259 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1260 switch (Width) { 1261 default: // fall 1262 case OPW32: 1263 case OPW16: 1264 case OPWV216: 1265 return TTMP_32RegClassID; 1266 case OPW64: 1267 case OPWV232: return TTMP_64RegClassID; 1268 case OPW128: return TTMP_128RegClassID; 1269 case OPW256: return TTMP_256RegClassID; 1270 case OPW512: return TTMP_512RegClassID; 1271 } 1272 } 1273 1274 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1275 using namespace AMDGPU::EncValues; 1276 1277 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1278 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1279 1280 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1281 } 1282 1283 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1284 bool MandatoryLiteral) const { 1285 using namespace AMDGPU::EncValues; 1286 1287 assert(Val < 1024); // enum10 1288 1289 bool IsAGPR = Val & 512; 1290 Val &= 511; 1291 1292 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1293 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1294 : getVgprClassId(Width), Val - VGPR_MIN); 1295 } 1296 if (Val <= SGPR_MAX) { 1297 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1298 static_assert(SGPR_MIN == 0, ""); 1299 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1300 } 1301 1302 int TTmpIdx = getTTmpIdx(Val); 1303 if (TTmpIdx >= 0) { 1304 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1305 } 1306 1307 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1308 return decodeIntImmed(Val); 1309 1310 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1311 return decodeFPImmed(Width, Val); 1312 1313 if (Val == LITERAL_CONST) { 1314 if (MandatoryLiteral) 1315 // Keep a sentinel value for deferred setting 1316 return MCOperand::createImm(LITERAL_CONST); 1317 else 1318 return decodeLiteralConstant(); 1319 } 1320 1321 switch (Width) { 1322 case OPW32: 1323 case OPW16: 1324 case OPWV216: 1325 return decodeSpecialReg32(Val); 1326 case OPW64: 1327 case OPWV232: 1328 return decodeSpecialReg64(Val); 1329 default: 1330 llvm_unreachable("unexpected immediate type"); 1331 } 1332 } 1333 1334 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1335 using namespace AMDGPU::EncValues; 1336 1337 assert(Val < 128); 1338 assert(Width == OPW256 || Width == OPW512); 1339 1340 if (Val <= SGPR_MAX) { 1341 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1342 static_assert(SGPR_MIN == 0, ""); 1343 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1344 } 1345 1346 int TTmpIdx = getTTmpIdx(Val); 1347 if (TTmpIdx >= 0) { 1348 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1349 } 1350 1351 llvm_unreachable("unknown dst register"); 1352 } 1353 1354 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1355 using namespace AMDGPU; 1356 1357 switch (Val) { 1358 case 102: return createRegOperand(FLAT_SCR_LO); 1359 case 103: return createRegOperand(FLAT_SCR_HI); 1360 case 104: return createRegOperand(XNACK_MASK_LO); 1361 case 105: return createRegOperand(XNACK_MASK_HI); 1362 case 106: return createRegOperand(VCC_LO); 1363 case 107: return createRegOperand(VCC_HI); 1364 case 108: return createRegOperand(TBA_LO); 1365 case 109: return createRegOperand(TBA_HI); 1366 case 110: return createRegOperand(TMA_LO); 1367 case 111: return createRegOperand(TMA_HI); 1368 case 124: 1369 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1370 case 125: 1371 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1372 case 126: return createRegOperand(EXEC_LO); 1373 case 127: return createRegOperand(EXEC_HI); 1374 case 235: return createRegOperand(SRC_SHARED_BASE); 1375 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1376 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1377 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1378 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1379 case 251: return createRegOperand(SRC_VCCZ); 1380 case 252: return createRegOperand(SRC_EXECZ); 1381 case 253: return createRegOperand(SRC_SCC); 1382 case 254: return createRegOperand(LDS_DIRECT); 1383 default: break; 1384 } 1385 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1386 } 1387 1388 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1389 using namespace AMDGPU; 1390 1391 switch (Val) { 1392 case 102: return createRegOperand(FLAT_SCR); 1393 case 104: return createRegOperand(XNACK_MASK); 1394 case 106: return createRegOperand(VCC); 1395 case 108: return createRegOperand(TBA); 1396 case 110: return createRegOperand(TMA); 1397 case 124: 1398 if (isGFX11Plus()) 1399 return createRegOperand(SGPR_NULL); 1400 break; 1401 case 125: 1402 if (!isGFX11Plus()) 1403 return createRegOperand(SGPR_NULL); 1404 break; 1405 case 126: return createRegOperand(EXEC); 1406 case 235: return createRegOperand(SRC_SHARED_BASE); 1407 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1408 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1409 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1410 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1411 case 251: return createRegOperand(SRC_VCCZ); 1412 case 252: return createRegOperand(SRC_EXECZ); 1413 case 253: return createRegOperand(SRC_SCC); 1414 default: break; 1415 } 1416 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1417 } 1418 1419 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1420 const unsigned Val) const { 1421 using namespace AMDGPU::SDWA; 1422 using namespace AMDGPU::EncValues; 1423 1424 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1425 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1426 // XXX: cast to int is needed to avoid stupid warning: 1427 // compare with unsigned is always true 1428 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1429 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1430 return createRegOperand(getVgprClassId(Width), 1431 Val - SDWA9EncValues::SRC_VGPR_MIN); 1432 } 1433 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1434 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1435 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1436 return createSRegOperand(getSgprClassId(Width), 1437 Val - SDWA9EncValues::SRC_SGPR_MIN); 1438 } 1439 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1440 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1441 return createSRegOperand(getTtmpClassId(Width), 1442 Val - SDWA9EncValues::SRC_TTMP_MIN); 1443 } 1444 1445 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1446 1447 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1448 return decodeIntImmed(SVal); 1449 1450 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1451 return decodeFPImmed(Width, SVal); 1452 1453 return decodeSpecialReg32(SVal); 1454 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1455 return createRegOperand(getVgprClassId(Width), Val); 1456 } 1457 llvm_unreachable("unsupported target"); 1458 } 1459 1460 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1461 return decodeSDWASrc(OPW16, Val); 1462 } 1463 1464 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1465 return decodeSDWASrc(OPW32, Val); 1466 } 1467 1468 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1469 using namespace AMDGPU::SDWA; 1470 1471 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1472 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1473 "SDWAVopcDst should be present only on GFX9+"); 1474 1475 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1476 1477 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1478 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1479 1480 int TTmpIdx = getTTmpIdx(Val); 1481 if (TTmpIdx >= 0) { 1482 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1483 return createSRegOperand(TTmpClsId, TTmpIdx); 1484 } else if (Val > SGPR_MAX) { 1485 return IsWave64 ? decodeSpecialReg64(Val) 1486 : decodeSpecialReg32(Val); 1487 } else { 1488 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1489 } 1490 } else { 1491 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1492 } 1493 } 1494 1495 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1496 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1497 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1498 } 1499 1500 bool AMDGPUDisassembler::isVI() const { 1501 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1502 } 1503 1504 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1505 1506 bool AMDGPUDisassembler::isGFX90A() const { 1507 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1508 } 1509 1510 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1511 1512 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1513 1514 bool AMDGPUDisassembler::isGFX10Plus() const { 1515 return AMDGPU::isGFX10Plus(STI); 1516 } 1517 1518 bool AMDGPUDisassembler::isGFX11() const { 1519 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1520 } 1521 1522 bool AMDGPUDisassembler::isGFX11Plus() const { 1523 return AMDGPU::isGFX11Plus(STI); 1524 } 1525 1526 1527 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1528 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1529 } 1530 1531 //===----------------------------------------------------------------------===// 1532 // AMDGPU specific symbol handling 1533 //===----------------------------------------------------------------------===// 1534 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1535 do { \ 1536 KdStream << Indent << DIRECTIVE " " \ 1537 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1538 } while (0) 1539 1540 // NOLINTNEXTLINE(readability-identifier-naming) 1541 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1542 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1543 using namespace amdhsa; 1544 StringRef Indent = "\t"; 1545 1546 // We cannot accurately backward compute #VGPRs used from 1547 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1548 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1549 // simply calculate the inverse of what the assembler does. 1550 1551 uint32_t GranulatedWorkitemVGPRCount = 1552 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1553 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1554 1555 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1556 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1557 1558 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1559 1560 // We cannot backward compute values used to calculate 1561 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1562 // directives can't be computed: 1563 // .amdhsa_reserve_vcc 1564 // .amdhsa_reserve_flat_scratch 1565 // .amdhsa_reserve_xnack_mask 1566 // They take their respective default values if not specified in the assembly. 1567 // 1568 // GRANULATED_WAVEFRONT_SGPR_COUNT 1569 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1570 // 1571 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1572 // are set to 0. So while disassembling we consider that: 1573 // 1574 // GRANULATED_WAVEFRONT_SGPR_COUNT 1575 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1576 // 1577 // The disassembler cannot recover the original values of those 3 directives. 1578 1579 uint32_t GranulatedWavefrontSGPRCount = 1580 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1581 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1582 1583 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1584 return MCDisassembler::Fail; 1585 1586 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1587 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1588 1589 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1590 if (!hasArchitectedFlatScratch()) 1591 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1592 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1593 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1594 1595 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1596 return MCDisassembler::Fail; 1597 1598 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1599 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1600 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1601 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1602 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1603 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1604 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1605 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1606 1607 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1608 return MCDisassembler::Fail; 1609 1610 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1611 1612 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1613 return MCDisassembler::Fail; 1614 1615 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1616 1617 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1618 return MCDisassembler::Fail; 1619 1620 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1621 return MCDisassembler::Fail; 1622 1623 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1624 1625 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1626 return MCDisassembler::Fail; 1627 1628 if (isGFX10Plus()) { 1629 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1630 COMPUTE_PGM_RSRC1_WGP_MODE); 1631 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1632 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1633 } 1634 return MCDisassembler::Success; 1635 } 1636 1637 // NOLINTNEXTLINE(readability-identifier-naming) 1638 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1639 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1640 using namespace amdhsa; 1641 StringRef Indent = "\t"; 1642 if (hasArchitectedFlatScratch()) 1643 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1644 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1645 else 1646 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1647 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1648 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1649 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1650 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1651 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1652 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1653 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1654 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1655 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1656 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1657 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1658 1659 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1660 return MCDisassembler::Fail; 1661 1662 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1663 return MCDisassembler::Fail; 1664 1665 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1666 return MCDisassembler::Fail; 1667 1668 PRINT_DIRECTIVE( 1669 ".amdhsa_exception_fp_ieee_invalid_op", 1670 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1671 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1672 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1673 PRINT_DIRECTIVE( 1674 ".amdhsa_exception_fp_ieee_div_zero", 1675 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1676 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1677 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1678 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1679 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1680 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1681 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1682 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1683 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1684 1685 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1686 return MCDisassembler::Fail; 1687 1688 return MCDisassembler::Success; 1689 } 1690 1691 #undef PRINT_DIRECTIVE 1692 1693 MCDisassembler::DecodeStatus 1694 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1695 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1696 raw_string_ostream &KdStream) const { 1697 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1698 do { \ 1699 KdStream << Indent << DIRECTIVE " " \ 1700 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1701 } while (0) 1702 1703 uint16_t TwoByteBuffer = 0; 1704 uint32_t FourByteBuffer = 0; 1705 1706 StringRef ReservedBytes; 1707 StringRef Indent = "\t"; 1708 1709 assert(Bytes.size() == 64); 1710 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1711 1712 switch (Cursor.tell()) { 1713 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1714 FourByteBuffer = DE.getU32(Cursor); 1715 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1716 << '\n'; 1717 return MCDisassembler::Success; 1718 1719 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1720 FourByteBuffer = DE.getU32(Cursor); 1721 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1722 << FourByteBuffer << '\n'; 1723 return MCDisassembler::Success; 1724 1725 case amdhsa::KERNARG_SIZE_OFFSET: 1726 FourByteBuffer = DE.getU32(Cursor); 1727 KdStream << Indent << ".amdhsa_kernarg_size " 1728 << FourByteBuffer << '\n'; 1729 return MCDisassembler::Success; 1730 1731 case amdhsa::RESERVED0_OFFSET: 1732 // 4 reserved bytes, must be 0. 1733 ReservedBytes = DE.getBytes(Cursor, 4); 1734 for (int I = 0; I < 4; ++I) { 1735 if (ReservedBytes[I] != 0) { 1736 return MCDisassembler::Fail; 1737 } 1738 } 1739 return MCDisassembler::Success; 1740 1741 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1742 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1743 // So far no directive controls this for Code Object V3, so simply skip for 1744 // disassembly. 1745 DE.skip(Cursor, 8); 1746 return MCDisassembler::Success; 1747 1748 case amdhsa::RESERVED1_OFFSET: 1749 // 20 reserved bytes, must be 0. 1750 ReservedBytes = DE.getBytes(Cursor, 20); 1751 for (int I = 0; I < 20; ++I) { 1752 if (ReservedBytes[I] != 0) { 1753 return MCDisassembler::Fail; 1754 } 1755 } 1756 return MCDisassembler::Success; 1757 1758 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1759 // COMPUTE_PGM_RSRC3 1760 // - Only set for GFX10, GFX6-9 have this to be 0. 1761 // - Currently no directives directly control this. 1762 FourByteBuffer = DE.getU32(Cursor); 1763 if (!isGFX10Plus() && FourByteBuffer) { 1764 return MCDisassembler::Fail; 1765 } 1766 return MCDisassembler::Success; 1767 1768 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1769 FourByteBuffer = DE.getU32(Cursor); 1770 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1771 MCDisassembler::Fail) { 1772 return MCDisassembler::Fail; 1773 } 1774 return MCDisassembler::Success; 1775 1776 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1777 FourByteBuffer = DE.getU32(Cursor); 1778 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1779 MCDisassembler::Fail) { 1780 return MCDisassembler::Fail; 1781 } 1782 return MCDisassembler::Success; 1783 1784 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1785 using namespace amdhsa; 1786 TwoByteBuffer = DE.getU16(Cursor); 1787 1788 if (!hasArchitectedFlatScratch()) 1789 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1790 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1791 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1792 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1793 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1794 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1795 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1796 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1797 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1798 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1799 if (!hasArchitectedFlatScratch()) 1800 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1801 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1802 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1803 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1804 1805 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1806 return MCDisassembler::Fail; 1807 1808 // Reserved for GFX9 1809 if (isGFX9() && 1810 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1811 return MCDisassembler::Fail; 1812 } else if (isGFX10Plus()) { 1813 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1814 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1815 } 1816 1817 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1818 return MCDisassembler::Fail; 1819 1820 return MCDisassembler::Success; 1821 1822 case amdhsa::RESERVED2_OFFSET: 1823 // 6 bytes from here are reserved, must be 0. 1824 ReservedBytes = DE.getBytes(Cursor, 6); 1825 for (int I = 0; I < 6; ++I) { 1826 if (ReservedBytes[I] != 0) 1827 return MCDisassembler::Fail; 1828 } 1829 return MCDisassembler::Success; 1830 1831 default: 1832 llvm_unreachable("Unhandled index. Case statements cover everything."); 1833 return MCDisassembler::Fail; 1834 } 1835 #undef PRINT_DIRECTIVE 1836 } 1837 1838 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1839 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1840 // CP microcode requires the kernel descriptor to be 64 aligned. 1841 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1842 return MCDisassembler::Fail; 1843 1844 std::string Kd; 1845 raw_string_ostream KdStream(Kd); 1846 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1847 1848 DataExtractor::Cursor C(0); 1849 while (C && C.tell() < Bytes.size()) { 1850 MCDisassembler::DecodeStatus Status = 1851 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1852 1853 cantFail(C.takeError()); 1854 1855 if (Status == MCDisassembler::Fail) 1856 return MCDisassembler::Fail; 1857 } 1858 KdStream << ".end_amdhsa_kernel\n"; 1859 outs() << KdStream.str(); 1860 return MCDisassembler::Success; 1861 } 1862 1863 Optional<MCDisassembler::DecodeStatus> 1864 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1865 ArrayRef<uint8_t> Bytes, uint64_t Address, 1866 raw_ostream &CStream) const { 1867 // Right now only kernel descriptor needs to be handled. 1868 // We ignore all other symbols for target specific handling. 1869 // TODO: 1870 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1871 // Object V2 and V3 when symbols are marked protected. 1872 1873 // amd_kernel_code_t for Code Object V2. 1874 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1875 Size = 256; 1876 return MCDisassembler::Fail; 1877 } 1878 1879 // Code Object V3 kernel descriptors. 1880 StringRef Name = Symbol.Name; 1881 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1882 Size = 64; // Size = 64 regardless of success or failure. 1883 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1884 } 1885 return None; 1886 } 1887 1888 //===----------------------------------------------------------------------===// 1889 // AMDGPUSymbolizer 1890 //===----------------------------------------------------------------------===// 1891 1892 // Try to find symbol name for specified label 1893 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1894 raw_ostream &/*cStream*/, int64_t Value, 1895 uint64_t /*Address*/, bool IsBranch, 1896 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1897 1898 if (!IsBranch) { 1899 return false; 1900 } 1901 1902 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1903 if (!Symbols) 1904 return false; 1905 1906 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1907 return Val.Addr == static_cast<uint64_t>(Value) && 1908 Val.Type == ELF::STT_NOTYPE; 1909 }); 1910 if (Result != Symbols->end()) { 1911 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1912 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1913 Inst.addOperand(MCOperand::createExpr(Add)); 1914 return true; 1915 } 1916 // Add to list of referenced addresses, so caller can synthesize a label. 1917 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1918 return false; 1919 } 1920 1921 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1922 int64_t Value, 1923 uint64_t Address) { 1924 llvm_unreachable("unimplemented"); 1925 } 1926 1927 //===----------------------------------------------------------------------===// 1928 // Initialization 1929 //===----------------------------------------------------------------------===// 1930 1931 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1932 LLVMOpInfoCallback /*GetOpInfo*/, 1933 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1934 void *DisInfo, 1935 MCContext *Ctx, 1936 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1937 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1938 } 1939 1940 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1941 const MCSubtargetInfo &STI, 1942 MCContext &Ctx) { 1943 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1944 } 1945 1946 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1947 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1948 createAMDGPUDisassembler); 1949 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1950 createAMDGPUSymbolizer); 1951 } 1952