1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VRegOrLds_32) 123 DECODE_OPERAND_REG(VS_32) 124 DECODE_OPERAND_REG(VS_64) 125 DECODE_OPERAND_REG(VS_128) 126 127 DECODE_OPERAND_REG(VReg_64) 128 DECODE_OPERAND_REG(VReg_96) 129 DECODE_OPERAND_REG(VReg_128) 130 DECODE_OPERAND_REG(VReg_256) 131 DECODE_OPERAND_REG(VReg_512) 132 DECODE_OPERAND_REG(VReg_1024) 133 134 DECODE_OPERAND_REG(SReg_32) 135 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 136 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 137 DECODE_OPERAND_REG(SRegOrLds_32) 138 DECODE_OPERAND_REG(SReg_64) 139 DECODE_OPERAND_REG(SReg_64_XEXEC) 140 DECODE_OPERAND_REG(SReg_128) 141 DECODE_OPERAND_REG(SReg_256) 142 DECODE_OPERAND_REG(SReg_512) 143 144 DECODE_OPERAND_REG(AGPR_32) 145 DECODE_OPERAND_REG(AReg_64) 146 DECODE_OPERAND_REG(AReg_128) 147 DECODE_OPERAND_REG(AReg_256) 148 DECODE_OPERAND_REG(AReg_512) 149 DECODE_OPERAND_REG(AReg_1024) 150 DECODE_OPERAND_REG(AV_32) 151 DECODE_OPERAND_REG(AV_64) 152 DECODE_OPERAND_REG(AV_128) 153 DECODE_OPERAND_REG(AVDst_128) 154 DECODE_OPERAND_REG(AVDst_512) 155 156 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 157 uint64_t Addr, 158 const MCDisassembler *Decoder) { 159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 160 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 161 } 162 163 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 164 uint64_t Addr, 165 const MCDisassembler *Decoder) { 166 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 167 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 168 } 169 170 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, 172 const MCDisassembler *Decoder) { 173 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 174 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 175 } 176 177 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, 179 const MCDisassembler *Decoder) { 180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 181 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 182 } 183 184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, 186 const MCDisassembler *Decoder) { 187 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 188 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 189 } 190 191 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, 193 const MCDisassembler *Decoder) { 194 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 195 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 196 } 197 198 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const MCDisassembler *Decoder) { 201 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 202 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 203 } 204 205 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, 207 const MCDisassembler *Decoder) { 208 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 209 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 210 } 211 212 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, 214 const MCDisassembler *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 220 uint64_t Addr, 221 const MCDisassembler *Decoder) { 222 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 223 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 224 } 225 226 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 227 uint64_t Addr, 228 const MCDisassembler *Decoder) { 229 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 230 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 231 } 232 233 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 234 uint64_t Addr, 235 const MCDisassembler *Decoder) { 236 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 237 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 238 } 239 240 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 241 uint64_t Addr, 242 const MCDisassembler *Decoder) { 243 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 244 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 245 } 246 247 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 248 uint64_t Addr, 249 const MCDisassembler *Decoder) { 250 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 251 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 252 } 253 254 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 255 uint64_t Addr, 256 const MCDisassembler *Decoder) { 257 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 258 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 259 } 260 261 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 262 uint64_t Addr, 263 const MCDisassembler *Decoder) { 264 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 265 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 266 } 267 268 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 269 uint64_t Addr, 270 const MCDisassembler *Decoder) { 271 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 272 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 273 } 274 275 static DecodeStatus 276 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 277 const MCDisassembler *Decoder) { 278 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 279 return addOperand( 280 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 281 } 282 283 static DecodeStatus 284 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 285 const MCDisassembler *Decoder) { 286 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand( 288 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 289 } 290 291 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 292 uint64_t Addr, const void *Decoder) { 293 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 294 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 295 } 296 297 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 298 const MCRegisterInfo *MRI) { 299 if (OpIdx < 0) 300 return false; 301 302 const MCOperand &Op = Inst.getOperand(OpIdx); 303 if (!Op.isReg()) 304 return false; 305 306 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 307 auto Reg = Sub ? Sub : Op.getReg(); 308 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 309 } 310 311 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 312 AMDGPUDisassembler::OpWidthTy Opw, 313 const MCDisassembler *Decoder) { 314 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 315 if (!DAsm->isGFX90A()) { 316 Imm &= 511; 317 } else { 318 // If atomic has both vdata and vdst their register classes are tied. 319 // The bit is decoded along with the vdst, first operand. We need to 320 // change register class to AGPR if vdst was AGPR. 321 // If a DS instruction has both data0 and data1 their register classes 322 // are also tied. 323 unsigned Opc = Inst.getOpcode(); 324 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 325 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 326 : AMDGPU::OpName::vdata; 327 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 328 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 329 if ((int)Inst.getNumOperands() == DataIdx) { 330 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 331 if (IsAGPROperand(Inst, DstIdx, MRI)) 332 Imm |= 512; 333 } 334 335 if (TSFlags & SIInstrFlags::DS) { 336 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 337 if ((int)Inst.getNumOperands() == Data2Idx && 338 IsAGPROperand(Inst, DataIdx, MRI)) 339 Imm |= 512; 340 } 341 } 342 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 343 } 344 345 static DecodeStatus 346 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 347 const MCDisassembler *Decoder) { 348 return decodeOperand_AVLdSt_Any(Inst, Imm, 349 AMDGPUDisassembler::OPW32, Decoder); 350 } 351 352 static DecodeStatus 353 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 354 const MCDisassembler *Decoder) { 355 return decodeOperand_AVLdSt_Any(Inst, Imm, 356 AMDGPUDisassembler::OPW64, Decoder); 357 } 358 359 static DecodeStatus 360 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 361 const MCDisassembler *Decoder) { 362 return decodeOperand_AVLdSt_Any(Inst, Imm, 363 AMDGPUDisassembler::OPW96, Decoder); 364 } 365 366 static DecodeStatus 367 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 368 const MCDisassembler *Decoder) { 369 return decodeOperand_AVLdSt_Any(Inst, Imm, 370 AMDGPUDisassembler::OPW128, Decoder); 371 } 372 373 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 374 uint64_t Addr, 375 const MCDisassembler *Decoder) { 376 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 377 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 378 } 379 380 #define DECODE_SDWA(DecName) \ 381 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 382 383 DECODE_SDWA(Src32) 384 DECODE_SDWA(Src16) 385 DECODE_SDWA(VopcDst) 386 387 #include "AMDGPUGenDisassemblerTables.inc" 388 389 //===----------------------------------------------------------------------===// 390 // 391 //===----------------------------------------------------------------------===// 392 393 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 394 assert(Bytes.size() >= sizeof(T)); 395 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 396 Bytes = Bytes.slice(sizeof(T)); 397 return Res; 398 } 399 400 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 401 assert(Bytes.size() >= 12); 402 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 403 Bytes.data()); 404 Bytes = Bytes.slice(8); 405 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 406 Bytes.data()); 407 Bytes = Bytes.slice(4); 408 return DecoderUInt128(Lo, Hi); 409 } 410 411 // The disassembler is greedy, so we need to check FI operand value to 412 // not parse a dpp if the correct literal is not set. For dpp16 the 413 // autogenerated decoder checks the dpp literal 414 static bool isValidDPP8(const MCInst &MI) { 415 using namespace llvm::AMDGPU::DPP; 416 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 417 assert(FiIdx != -1); 418 if ((unsigned)FiIdx >= MI.getNumOperands()) 419 return false; 420 unsigned Fi = MI.getOperand(FiIdx).getImm(); 421 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 422 } 423 424 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 425 ArrayRef<uint8_t> Bytes_, 426 uint64_t Address, 427 raw_ostream &CS) const { 428 CommentStream = &CS; 429 bool IsSDWA = false; 430 431 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 432 Bytes = Bytes_.slice(0, MaxInstBytesNum); 433 434 DecodeStatus Res = MCDisassembler::Fail; 435 do { 436 // ToDo: better to switch encoding length using some bit predicate 437 // but it is unknown yet, so try all we can 438 439 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 440 // encodings 441 if (isGFX11Plus() && Bytes.size() >= 12 ) { 442 DecoderUInt128 DecW = eat12Bytes(Bytes); 443 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 444 Address); 445 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 446 break; 447 MI = MCInst(); // clear 448 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 449 Address); 450 if (Res) { 451 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 452 convertVOP3PDPPInst(MI); 453 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 454 convertVOPCDPPInst(MI); // Special VOP3 case 455 else { 456 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 457 convertVOP3DPPInst(MI); // Regular VOP3 case 458 } 459 break; 460 } 461 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address); 462 if (Res) 463 break; 464 } 465 // Reinitialize Bytes 466 Bytes = Bytes_.slice(0, MaxInstBytesNum); 467 468 if (Bytes.size() >= 8) { 469 const uint64_t QW = eatBytes<uint64_t>(Bytes); 470 471 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 472 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 473 if (Res) { 474 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 475 == -1) 476 break; 477 if (convertDPP8Inst(MI) == MCDisassembler::Success) 478 break; 479 MI = MCInst(); // clear 480 } 481 } 482 483 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 484 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 485 break; 486 MI = MCInst(); // clear 487 488 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 489 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 490 break; 491 MI = MCInst(); // clear 492 493 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 494 if (Res) break; 495 496 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 497 if (Res) { 498 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 499 convertVOPCDPPInst(MI); 500 break; 501 } 502 503 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 504 if (Res) { IsSDWA = true; break; } 505 506 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 507 if (Res) { IsSDWA = true; break; } 508 509 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 510 if (Res) { IsSDWA = true; break; } 511 512 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 513 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 514 if (Res) 515 break; 516 } 517 518 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 519 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 520 // table first so we print the correct name. 521 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 522 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 523 if (Res) 524 break; 525 } 526 } 527 528 // Reinitialize Bytes as DPP64 could have eaten too much 529 Bytes = Bytes_.slice(0, MaxInstBytesNum); 530 531 // Try decode 32-bit instruction 532 if (Bytes.size() < 4) break; 533 const uint32_t DW = eatBytes<uint32_t>(Bytes); 534 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 535 if (Res) break; 536 537 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 538 if (Res) break; 539 540 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 541 if (Res) break; 542 543 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 544 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 545 if (Res) 546 break; 547 } 548 549 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 550 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 551 if (Res) break; 552 } 553 554 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 555 if (Res) break; 556 557 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 558 if (Res) break; 559 560 if (Bytes.size() < 4) break; 561 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 562 563 if (STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts]) { 564 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address); 565 if (Res) 566 break; 567 } 568 569 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 570 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 571 if (Res) 572 break; 573 } 574 575 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 576 if (Res) break; 577 578 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 579 if (Res) break; 580 581 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 582 if (Res) break; 583 584 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 585 if (Res) break; 586 587 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 588 if (Res) 589 break; 590 591 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address); 592 } while (false); 593 594 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 595 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 596 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 597 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 598 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 599 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 600 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 601 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 602 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 603 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 || 604 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 605 MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || 606 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 || 607 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx11)) { 608 // Insert dummy unused src2_modifiers. 609 insertNamedMCOperand(MI, MCOperand::createImm(0), 610 AMDGPU::OpName::src2_modifiers); 611 } 612 613 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 614 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 615 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 616 AMDGPU::OpName::cpol); 617 if (CPolPos != -1) { 618 unsigned CPol = 619 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 620 AMDGPU::CPol::GLC : 0; 621 if (MI.getNumOperands() <= (unsigned)CPolPos) { 622 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 623 AMDGPU::OpName::cpol); 624 } else if (CPol) { 625 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 626 } 627 } 628 } 629 630 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 631 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 632 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 633 // GFX90A lost TFE, its place is occupied by ACC. 634 int TFEOpIdx = 635 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 636 if (TFEOpIdx != -1) { 637 auto TFEIter = MI.begin(); 638 std::advance(TFEIter, TFEOpIdx); 639 MI.insert(TFEIter, MCOperand::createImm(0)); 640 } 641 } 642 643 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 644 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 645 int SWZOpIdx = 646 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 647 if (SWZOpIdx != -1) { 648 auto SWZIter = MI.begin(); 649 std::advance(SWZIter, SWZOpIdx); 650 MI.insert(SWZIter, MCOperand::createImm(0)); 651 } 652 } 653 654 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 655 int VAddr0Idx = 656 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 657 int RsrcIdx = 658 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 659 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 660 if (VAddr0Idx >= 0 && NSAArgs > 0) { 661 unsigned NSAWords = (NSAArgs + 3) / 4; 662 if (Bytes.size() < 4 * NSAWords) { 663 Res = MCDisassembler::Fail; 664 } else { 665 for (unsigned i = 0; i < NSAArgs; ++i) { 666 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 667 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 668 MI.insert(MI.begin() + VAddrIdx, 669 createRegOperand(VAddrRCID, Bytes[i])); 670 } 671 Bytes = Bytes.slice(4 * NSAWords); 672 } 673 } 674 675 if (Res) 676 Res = convertMIMGInst(MI); 677 } 678 679 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 680 Res = convertEXPInst(MI); 681 682 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 683 Res = convertVINTERPInst(MI); 684 685 if (Res && IsSDWA) 686 Res = convertSDWAInst(MI); 687 688 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 689 AMDGPU::OpName::vdst_in); 690 if (VDstIn_Idx != -1) { 691 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 692 MCOI::OperandConstraint::TIED_TO); 693 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 694 !MI.getOperand(VDstIn_Idx).isReg() || 695 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 696 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 697 MI.erase(&MI.getOperand(VDstIn_Idx)); 698 insertNamedMCOperand(MI, 699 MCOperand::createReg(MI.getOperand(Tied).getReg()), 700 AMDGPU::OpName::vdst_in); 701 } 702 } 703 704 int ImmLitIdx = 705 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 706 if (Res && ImmLitIdx != -1) 707 Res = convertFMAanyK(MI, ImmLitIdx); 708 709 // if the opcode was not recognized we'll assume a Size of 4 bytes 710 // (unless there are fewer bytes left) 711 Size = Res ? (MaxInstBytesNum - Bytes.size()) 712 : std::min((size_t)4, Bytes_.size()); 713 return Res; 714 } 715 716 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 717 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 718 // The MCInst still has these fields even though they are no longer encoded 719 // in the GFX11 instruction. 720 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 721 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 722 } 723 return MCDisassembler::Success; 724 } 725 726 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 727 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 728 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 729 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 730 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 731 // The MCInst has this field that is not directly encoded in the 732 // instruction. 733 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 734 } 735 return MCDisassembler::Success; 736 } 737 738 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 739 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 740 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 741 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 742 // VOPC - insert clamp 743 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 744 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 745 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 746 if (SDst != -1) { 747 // VOPC - insert VCC register as sdst 748 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 749 AMDGPU::OpName::sdst); 750 } else { 751 // VOP1/2 - insert omod if present in instruction 752 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 753 } 754 } 755 return MCDisassembler::Success; 756 } 757 758 struct VOPModifiers { 759 unsigned OpSel = 0; 760 unsigned OpSelHi = 0; 761 unsigned NegLo = 0; 762 unsigned NegHi = 0; 763 }; 764 765 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 766 // Note that these values do not affect disassembler output, 767 // so this is only necessary for consistency with src_modifiers. 768 static VOPModifiers collectVOPModifiers(const MCInst &MI, 769 bool IsVOP3P = false) { 770 VOPModifiers Modifiers; 771 unsigned Opc = MI.getOpcode(); 772 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 773 AMDGPU::OpName::src1_modifiers, 774 AMDGPU::OpName::src2_modifiers}; 775 for (int J = 0; J < 3; ++J) { 776 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 777 if (OpIdx == -1) 778 continue; 779 780 unsigned Val = MI.getOperand(OpIdx).getImm(); 781 782 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 783 if (IsVOP3P) { 784 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 785 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 786 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 787 } else if (J == 0) { 788 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 789 } 790 } 791 792 return Modifiers; 793 } 794 795 // We must check FI == literal to reject not genuine dpp8 insts, and we must 796 // first add optional MI operands to check FI 797 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 798 unsigned Opc = MI.getOpcode(); 799 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 800 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 801 convertVOP3PDPPInst(MI); 802 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 803 AMDGPU::isVOPC64DPP(Opc)) { 804 convertVOPCDPPInst(MI); 805 } else if (MI.getNumOperands() < DescNumOps && 806 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { 807 auto Mods = collectVOPModifiers(MI); 808 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 809 AMDGPU::OpName::op_sel); 810 } else { 811 // Insert dummy unused src modifiers. 812 if (MI.getNumOperands() < DescNumOps && 813 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 814 insertNamedMCOperand(MI, MCOperand::createImm(0), 815 AMDGPU::OpName::src0_modifiers); 816 817 if (MI.getNumOperands() < DescNumOps && 818 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 819 insertNamedMCOperand(MI, MCOperand::createImm(0), 820 AMDGPU::OpName::src1_modifiers); 821 } 822 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 823 } 824 825 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 826 unsigned Opc = MI.getOpcode(); 827 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 828 if (MI.getNumOperands() < DescNumOps && 829 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) { 830 auto Mods = collectVOPModifiers(MI); 831 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 832 AMDGPU::OpName::op_sel); 833 } 834 return MCDisassembler::Success; 835 } 836 837 // Note that before gfx10, the MIMG encoding provided no information about 838 // VADDR size. Consequently, decoded instructions always show address as if it 839 // has 1 dword, which could be not really so. 840 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 841 842 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 843 AMDGPU::OpName::vdst); 844 845 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 846 AMDGPU::OpName::vdata); 847 int VAddr0Idx = 848 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 849 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 850 AMDGPU::OpName::dmask); 851 852 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 853 AMDGPU::OpName::tfe); 854 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 855 AMDGPU::OpName::d16); 856 857 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 858 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 859 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 860 861 assert(VDataIdx != -1); 862 if (BaseOpcode->BVH) { 863 // Add A16 operand for intersect_ray instructions 864 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 865 addOperand(MI, MCOperand::createImm(1)); 866 } 867 return MCDisassembler::Success; 868 } 869 870 bool IsAtomic = (VDstIdx != -1); 871 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 872 bool IsNSA = false; 873 unsigned AddrSize = Info->VAddrDwords; 874 875 if (isGFX10Plus()) { 876 unsigned DimIdx = 877 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 878 int A16Idx = 879 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 880 const AMDGPU::MIMGDimInfo *Dim = 881 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 882 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 883 884 AddrSize = 885 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 886 887 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 888 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 889 if (!IsNSA) { 890 if (AddrSize > 8) 891 AddrSize = 16; 892 } else { 893 if (AddrSize > Info->VAddrDwords) { 894 // The NSA encoding does not contain enough operands for the combination 895 // of base opcode / dimension. Should this be an error? 896 return MCDisassembler::Success; 897 } 898 } 899 } 900 901 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 902 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 903 904 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 905 if (D16 && AMDGPU::hasPackedD16(STI)) { 906 DstSize = (DstSize + 1) / 2; 907 } 908 909 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 910 DstSize += 1; 911 912 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 913 return MCDisassembler::Success; 914 915 int NewOpcode = 916 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 917 if (NewOpcode == -1) 918 return MCDisassembler::Success; 919 920 // Widen the register to the correct number of enabled channels. 921 unsigned NewVdata = AMDGPU::NoRegister; 922 if (DstSize != Info->VDataDwords) { 923 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 924 925 // Get first subregister of VData 926 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 927 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 928 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 929 930 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 931 &MRI.getRegClass(DataRCID)); 932 if (NewVdata == AMDGPU::NoRegister) { 933 // It's possible to encode this such that the low register + enabled 934 // components exceeds the register count. 935 return MCDisassembler::Success; 936 } 937 } 938 939 // If not using NSA on GFX10+, widen address register to correct size. 940 unsigned NewVAddr0 = AMDGPU::NoRegister; 941 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 942 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 943 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 944 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 945 946 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 947 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 948 &MRI.getRegClass(AddrRCID)); 949 if (NewVAddr0 == AMDGPU::NoRegister) 950 return MCDisassembler::Success; 951 } 952 953 MI.setOpcode(NewOpcode); 954 955 if (NewVdata != AMDGPU::NoRegister) { 956 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 957 958 if (IsAtomic) { 959 // Atomic operations have an additional operand (a copy of data) 960 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 961 } 962 } 963 964 if (NewVAddr0 != AMDGPU::NoRegister) { 965 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 966 } else if (IsNSA) { 967 assert(AddrSize <= Info->VAddrDwords); 968 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 969 MI.begin() + VAddr0Idx + Info->VAddrDwords); 970 } 971 972 return MCDisassembler::Success; 973 } 974 975 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 976 // decoder only adds to src_modifiers, so manually add the bits to the other 977 // operands. 978 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 979 unsigned Opc = MI.getOpcode(); 980 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 981 auto Mods = collectVOPModifiers(MI, true); 982 983 if (MI.getNumOperands() < DescNumOps && 984 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) 985 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 986 987 if (MI.getNumOperands() < DescNumOps && 988 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) 989 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 990 AMDGPU::OpName::op_sel); 991 if (MI.getNumOperands() < DescNumOps && 992 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi) != -1) 993 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 994 AMDGPU::OpName::op_sel_hi); 995 if (MI.getNumOperands() < DescNumOps && 996 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1) 997 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 998 AMDGPU::OpName::neg_lo); 999 if (MI.getNumOperands() < DescNumOps && 1000 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1) 1001 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1002 AMDGPU::OpName::neg_hi); 1003 1004 return MCDisassembler::Success; 1005 } 1006 1007 // Create dummy old operand and insert optional operands 1008 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1009 unsigned Opc = MI.getOpcode(); 1010 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1011 1012 if (MI.getNumOperands() < DescNumOps && 1013 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1) 1014 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1015 1016 if (MI.getNumOperands() < DescNumOps && 1017 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 1018 insertNamedMCOperand(MI, MCOperand::createImm(0), 1019 AMDGPU::OpName::src0_modifiers); 1020 1021 if (MI.getNumOperands() < DescNumOps && 1022 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 1023 insertNamedMCOperand(MI, MCOperand::createImm(0), 1024 AMDGPU::OpName::src1_modifiers); 1025 return MCDisassembler::Success; 1026 } 1027 1028 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1029 int ImmLitIdx) const { 1030 assert(HasLiteral && "Should have decoded a literal"); 1031 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1032 unsigned DescNumOps = Desc.getNumOperands(); 1033 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1034 AMDGPU::OpName::immDeferred); 1035 assert(DescNumOps == MI.getNumOperands()); 1036 for (unsigned I = 0; I < DescNumOps; ++I) { 1037 auto &Op = MI.getOperand(I); 1038 auto OpType = Desc.OpInfo[I].OperandType; 1039 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1040 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1041 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1042 IsDeferredOp) 1043 Op.setImm(Literal); 1044 } 1045 return MCDisassembler::Success; 1046 } 1047 1048 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1049 return getContext().getRegisterInfo()-> 1050 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1051 } 1052 1053 inline 1054 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1055 const Twine& ErrMsg) const { 1056 *CommentStream << "Error: " + ErrMsg; 1057 1058 // ToDo: add support for error operands to MCInst.h 1059 // return MCOperand::createError(V); 1060 return MCOperand(); 1061 } 1062 1063 inline 1064 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1065 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1066 } 1067 1068 inline 1069 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1070 unsigned Val) const { 1071 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1072 if (Val >= RegCl.getNumRegs()) 1073 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1074 ": unknown register " + Twine(Val)); 1075 return createRegOperand(RegCl.getRegister(Val)); 1076 } 1077 1078 inline 1079 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1080 unsigned Val) const { 1081 // ToDo: SI/CI have 104 SGPRs, VI - 102 1082 // Valery: here we accepting as much as we can, let assembler sort it out 1083 int shift = 0; 1084 switch (SRegClassID) { 1085 case AMDGPU::SGPR_32RegClassID: 1086 case AMDGPU::TTMP_32RegClassID: 1087 break; 1088 case AMDGPU::SGPR_64RegClassID: 1089 case AMDGPU::TTMP_64RegClassID: 1090 shift = 1; 1091 break; 1092 case AMDGPU::SGPR_128RegClassID: 1093 case AMDGPU::TTMP_128RegClassID: 1094 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1095 // this bundle? 1096 case AMDGPU::SGPR_256RegClassID: 1097 case AMDGPU::TTMP_256RegClassID: 1098 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1099 // this bundle? 1100 case AMDGPU::SGPR_512RegClassID: 1101 case AMDGPU::TTMP_512RegClassID: 1102 shift = 2; 1103 break; 1104 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1105 // this bundle? 1106 default: 1107 llvm_unreachable("unhandled register class"); 1108 } 1109 1110 if (Val % (1 << shift)) { 1111 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1112 << ": scalar reg isn't aligned " << Val; 1113 } 1114 1115 return createRegOperand(SRegClassID, Val >> shift); 1116 } 1117 1118 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 1119 return decodeSrcOp(OPW32, Val); 1120 } 1121 1122 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 1123 return decodeSrcOp(OPW64, Val); 1124 } 1125 1126 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 1127 return decodeSrcOp(OPW128, Val); 1128 } 1129 1130 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 1131 return decodeSrcOp(OPW16, Val); 1132 } 1133 1134 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 1135 return decodeSrcOp(OPWV216, Val); 1136 } 1137 1138 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 1139 return decodeSrcOp(OPWV232, Val); 1140 } 1141 1142 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 1143 // Some instructions have operand restrictions beyond what the encoding 1144 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1145 // high bit. 1146 Val &= 255; 1147 1148 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1149 } 1150 1151 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1152 return decodeSrcOp(OPW32, Val); 1153 } 1154 1155 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1156 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1157 } 1158 1159 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1160 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1161 } 1162 1163 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1164 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1165 } 1166 1167 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1168 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1169 } 1170 1171 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1172 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1173 } 1174 1175 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1176 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1177 } 1178 1179 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1180 return decodeSrcOp(OPW32, Val); 1181 } 1182 1183 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1184 return decodeSrcOp(OPW64, Val); 1185 } 1186 1187 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1188 return decodeSrcOp(OPW128, Val); 1189 } 1190 1191 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1192 using namespace AMDGPU::EncValues; 1193 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1194 return decodeSrcOp(OPW128, Val | IS_VGPR); 1195 } 1196 1197 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1198 using namespace AMDGPU::EncValues; 1199 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1200 return decodeSrcOp(OPW512, Val | IS_VGPR); 1201 } 1202 1203 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1204 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1205 } 1206 1207 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1208 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1209 } 1210 1211 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1212 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1213 } 1214 1215 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1216 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1217 } 1218 1219 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1220 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1221 } 1222 1223 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1224 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1225 } 1226 1227 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1228 // table-gen generated disassembler doesn't care about operand types 1229 // leaving only registry class so SSrc_32 operand turns into SReg_32 1230 // and therefore we accept immediates and literals here as well 1231 return decodeSrcOp(OPW32, Val); 1232 } 1233 1234 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1235 unsigned Val) const { 1236 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1237 return decodeOperand_SReg_32(Val); 1238 } 1239 1240 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1241 unsigned Val) const { 1242 // SReg_32_XM0 is SReg_32 without EXEC_HI 1243 return decodeOperand_SReg_32(Val); 1244 } 1245 1246 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1247 // table-gen generated disassembler doesn't care about operand types 1248 // leaving only registry class so SSrc_32 operand turns into SReg_32 1249 // and therefore we accept immediates and literals here as well 1250 return decodeSrcOp(OPW32, Val); 1251 } 1252 1253 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1254 return decodeSrcOp(OPW64, Val); 1255 } 1256 1257 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1258 return decodeSrcOp(OPW64, Val); 1259 } 1260 1261 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1262 return decodeSrcOp(OPW128, Val); 1263 } 1264 1265 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1266 return decodeDstOp(OPW256, Val); 1267 } 1268 1269 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1270 return decodeDstOp(OPW512, Val); 1271 } 1272 1273 // Decode Literals for insts which always have a literal in the encoding 1274 MCOperand 1275 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1276 if (HasLiteral) { 1277 assert( 1278 AMDGPU::hasVOPD(STI) && 1279 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1280 if (Literal != Val) 1281 return errOperand(Val, "More than one unique literal is illegal"); 1282 } 1283 HasLiteral = true; 1284 Literal = Val; 1285 return MCOperand::createImm(Literal); 1286 } 1287 1288 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1289 // For now all literal constants are supposed to be unsigned integer 1290 // ToDo: deal with signed/unsigned 64-bit integer constants 1291 // ToDo: deal with float/double constants 1292 if (!HasLiteral) { 1293 if (Bytes.size() < 4) { 1294 return errOperand(0, "cannot read literal, inst bytes left " + 1295 Twine(Bytes.size())); 1296 } 1297 HasLiteral = true; 1298 Literal = eatBytes<uint32_t>(Bytes); 1299 } 1300 return MCOperand::createImm(Literal); 1301 } 1302 1303 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1304 using namespace AMDGPU::EncValues; 1305 1306 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1307 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1308 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1309 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1310 // Cast prevents negative overflow. 1311 } 1312 1313 static int64_t getInlineImmVal32(unsigned Imm) { 1314 switch (Imm) { 1315 case 240: 1316 return FloatToBits(0.5f); 1317 case 241: 1318 return FloatToBits(-0.5f); 1319 case 242: 1320 return FloatToBits(1.0f); 1321 case 243: 1322 return FloatToBits(-1.0f); 1323 case 244: 1324 return FloatToBits(2.0f); 1325 case 245: 1326 return FloatToBits(-2.0f); 1327 case 246: 1328 return FloatToBits(4.0f); 1329 case 247: 1330 return FloatToBits(-4.0f); 1331 case 248: // 1 / (2 * PI) 1332 return 0x3e22f983; 1333 default: 1334 llvm_unreachable("invalid fp inline imm"); 1335 } 1336 } 1337 1338 static int64_t getInlineImmVal64(unsigned Imm) { 1339 switch (Imm) { 1340 case 240: 1341 return DoubleToBits(0.5); 1342 case 241: 1343 return DoubleToBits(-0.5); 1344 case 242: 1345 return DoubleToBits(1.0); 1346 case 243: 1347 return DoubleToBits(-1.0); 1348 case 244: 1349 return DoubleToBits(2.0); 1350 case 245: 1351 return DoubleToBits(-2.0); 1352 case 246: 1353 return DoubleToBits(4.0); 1354 case 247: 1355 return DoubleToBits(-4.0); 1356 case 248: // 1 / (2 * PI) 1357 return 0x3fc45f306dc9c882; 1358 default: 1359 llvm_unreachable("invalid fp inline imm"); 1360 } 1361 } 1362 1363 static int64_t getInlineImmVal16(unsigned Imm) { 1364 switch (Imm) { 1365 case 240: 1366 return 0x3800; 1367 case 241: 1368 return 0xB800; 1369 case 242: 1370 return 0x3C00; 1371 case 243: 1372 return 0xBC00; 1373 case 244: 1374 return 0x4000; 1375 case 245: 1376 return 0xC000; 1377 case 246: 1378 return 0x4400; 1379 case 247: 1380 return 0xC400; 1381 case 248: // 1 / (2 * PI) 1382 return 0x3118; 1383 default: 1384 llvm_unreachable("invalid fp inline imm"); 1385 } 1386 } 1387 1388 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1389 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1390 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1391 1392 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1393 switch (Width) { 1394 case OPW32: 1395 case OPW128: // splat constants 1396 case OPW512: 1397 case OPW1024: 1398 case OPWV232: 1399 return MCOperand::createImm(getInlineImmVal32(Imm)); 1400 case OPW64: 1401 case OPW256: 1402 return MCOperand::createImm(getInlineImmVal64(Imm)); 1403 case OPW16: 1404 case OPWV216: 1405 return MCOperand::createImm(getInlineImmVal16(Imm)); 1406 default: 1407 llvm_unreachable("implement me"); 1408 } 1409 } 1410 1411 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1412 using namespace AMDGPU; 1413 1414 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1415 switch (Width) { 1416 default: // fall 1417 case OPW32: 1418 case OPW16: 1419 case OPWV216: 1420 return VGPR_32RegClassID; 1421 case OPW64: 1422 case OPWV232: return VReg_64RegClassID; 1423 case OPW96: return VReg_96RegClassID; 1424 case OPW128: return VReg_128RegClassID; 1425 case OPW160: return VReg_160RegClassID; 1426 case OPW256: return VReg_256RegClassID; 1427 case OPW512: return VReg_512RegClassID; 1428 case OPW1024: return VReg_1024RegClassID; 1429 } 1430 } 1431 1432 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1433 using namespace AMDGPU; 1434 1435 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1436 switch (Width) { 1437 default: // fall 1438 case OPW32: 1439 case OPW16: 1440 case OPWV216: 1441 return AGPR_32RegClassID; 1442 case OPW64: 1443 case OPWV232: return AReg_64RegClassID; 1444 case OPW96: return AReg_96RegClassID; 1445 case OPW128: return AReg_128RegClassID; 1446 case OPW160: return AReg_160RegClassID; 1447 case OPW256: return AReg_256RegClassID; 1448 case OPW512: return AReg_512RegClassID; 1449 case OPW1024: return AReg_1024RegClassID; 1450 } 1451 } 1452 1453 1454 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1455 using namespace AMDGPU; 1456 1457 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1458 switch (Width) { 1459 default: // fall 1460 case OPW32: 1461 case OPW16: 1462 case OPWV216: 1463 return SGPR_32RegClassID; 1464 case OPW64: 1465 case OPWV232: return SGPR_64RegClassID; 1466 case OPW96: return SGPR_96RegClassID; 1467 case OPW128: return SGPR_128RegClassID; 1468 case OPW160: return SGPR_160RegClassID; 1469 case OPW256: return SGPR_256RegClassID; 1470 case OPW512: return SGPR_512RegClassID; 1471 } 1472 } 1473 1474 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1475 using namespace AMDGPU; 1476 1477 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1478 switch (Width) { 1479 default: // fall 1480 case OPW32: 1481 case OPW16: 1482 case OPWV216: 1483 return TTMP_32RegClassID; 1484 case OPW64: 1485 case OPWV232: return TTMP_64RegClassID; 1486 case OPW128: return TTMP_128RegClassID; 1487 case OPW256: return TTMP_256RegClassID; 1488 case OPW512: return TTMP_512RegClassID; 1489 } 1490 } 1491 1492 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1493 using namespace AMDGPU::EncValues; 1494 1495 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1496 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1497 1498 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1499 } 1500 1501 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1502 bool MandatoryLiteral) const { 1503 using namespace AMDGPU::EncValues; 1504 1505 assert(Val < 1024); // enum10 1506 1507 bool IsAGPR = Val & 512; 1508 Val &= 511; 1509 1510 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1511 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1512 : getVgprClassId(Width), Val - VGPR_MIN); 1513 } 1514 if (Val <= SGPR_MAX) { 1515 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1516 static_assert(SGPR_MIN == 0); 1517 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1518 } 1519 1520 int TTmpIdx = getTTmpIdx(Val); 1521 if (TTmpIdx >= 0) { 1522 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1523 } 1524 1525 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1526 return decodeIntImmed(Val); 1527 1528 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1529 return decodeFPImmed(Width, Val); 1530 1531 if (Val == LITERAL_CONST) { 1532 if (MandatoryLiteral) 1533 // Keep a sentinel value for deferred setting 1534 return MCOperand::createImm(LITERAL_CONST); 1535 else 1536 return decodeLiteralConstant(); 1537 } 1538 1539 switch (Width) { 1540 case OPW32: 1541 case OPW16: 1542 case OPWV216: 1543 return decodeSpecialReg32(Val); 1544 case OPW64: 1545 case OPWV232: 1546 return decodeSpecialReg64(Val); 1547 default: 1548 llvm_unreachable("unexpected immediate type"); 1549 } 1550 } 1551 1552 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1553 using namespace AMDGPU::EncValues; 1554 1555 assert(Val < 128); 1556 assert(Width == OPW256 || Width == OPW512); 1557 1558 if (Val <= SGPR_MAX) { 1559 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1560 static_assert(SGPR_MIN == 0); 1561 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1562 } 1563 1564 int TTmpIdx = getTTmpIdx(Val); 1565 if (TTmpIdx >= 0) { 1566 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1567 } 1568 1569 llvm_unreachable("unknown dst register"); 1570 } 1571 1572 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1573 // opposite of bit 0 of DstX. 1574 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1575 unsigned Val) const { 1576 int VDstXInd = 1577 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1578 assert(VDstXInd != -1); 1579 assert(Inst.getOperand(VDstXInd).isReg()); 1580 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1581 Val |= ~XDstReg & 1; 1582 auto Width = llvm::AMDGPUDisassembler::OPW32; 1583 return createRegOperand(getVgprClassId(Width), Val); 1584 } 1585 1586 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1587 using namespace AMDGPU; 1588 1589 switch (Val) { 1590 case 102: return createRegOperand(FLAT_SCR_LO); 1591 case 103: return createRegOperand(FLAT_SCR_HI); 1592 case 104: return createRegOperand(XNACK_MASK_LO); 1593 case 105: return createRegOperand(XNACK_MASK_HI); 1594 case 106: return createRegOperand(VCC_LO); 1595 case 107: return createRegOperand(VCC_HI); 1596 case 108: return createRegOperand(TBA_LO); 1597 case 109: return createRegOperand(TBA_HI); 1598 case 110: return createRegOperand(TMA_LO); 1599 case 111: return createRegOperand(TMA_HI); 1600 case 124: 1601 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1602 case 125: 1603 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1604 case 126: return createRegOperand(EXEC_LO); 1605 case 127: return createRegOperand(EXEC_HI); 1606 case 235: return createRegOperand(SRC_SHARED_BASE); 1607 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1608 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1609 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1610 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1611 case 251: return createRegOperand(SRC_VCCZ); 1612 case 252: return createRegOperand(SRC_EXECZ); 1613 case 253: return createRegOperand(SRC_SCC); 1614 case 254: return createRegOperand(LDS_DIRECT); 1615 default: break; 1616 } 1617 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1618 } 1619 1620 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1621 using namespace AMDGPU; 1622 1623 switch (Val) { 1624 case 102: return createRegOperand(FLAT_SCR); 1625 case 104: return createRegOperand(XNACK_MASK); 1626 case 106: return createRegOperand(VCC); 1627 case 108: return createRegOperand(TBA); 1628 case 110: return createRegOperand(TMA); 1629 case 124: 1630 if (isGFX11Plus()) 1631 return createRegOperand(SGPR_NULL); 1632 break; 1633 case 125: 1634 if (!isGFX11Plus()) 1635 return createRegOperand(SGPR_NULL); 1636 break; 1637 case 126: return createRegOperand(EXEC); 1638 case 235: return createRegOperand(SRC_SHARED_BASE); 1639 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1640 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1641 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1642 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1643 case 251: return createRegOperand(SRC_VCCZ); 1644 case 252: return createRegOperand(SRC_EXECZ); 1645 case 253: return createRegOperand(SRC_SCC); 1646 default: break; 1647 } 1648 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1649 } 1650 1651 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1652 const unsigned Val) const { 1653 using namespace AMDGPU::SDWA; 1654 using namespace AMDGPU::EncValues; 1655 1656 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1657 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1658 // XXX: cast to int is needed to avoid stupid warning: 1659 // compare with unsigned is always true 1660 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1661 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1662 return createRegOperand(getVgprClassId(Width), 1663 Val - SDWA9EncValues::SRC_VGPR_MIN); 1664 } 1665 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1666 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1667 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1668 return createSRegOperand(getSgprClassId(Width), 1669 Val - SDWA9EncValues::SRC_SGPR_MIN); 1670 } 1671 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1672 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1673 return createSRegOperand(getTtmpClassId(Width), 1674 Val - SDWA9EncValues::SRC_TTMP_MIN); 1675 } 1676 1677 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1678 1679 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1680 return decodeIntImmed(SVal); 1681 1682 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1683 return decodeFPImmed(Width, SVal); 1684 1685 return decodeSpecialReg32(SVal); 1686 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1687 return createRegOperand(getVgprClassId(Width), Val); 1688 } 1689 llvm_unreachable("unsupported target"); 1690 } 1691 1692 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1693 return decodeSDWASrc(OPW16, Val); 1694 } 1695 1696 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1697 return decodeSDWASrc(OPW32, Val); 1698 } 1699 1700 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1701 using namespace AMDGPU::SDWA; 1702 1703 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1704 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1705 "SDWAVopcDst should be present only on GFX9+"); 1706 1707 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1708 1709 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1710 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1711 1712 int TTmpIdx = getTTmpIdx(Val); 1713 if (TTmpIdx >= 0) { 1714 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1715 return createSRegOperand(TTmpClsId, TTmpIdx); 1716 } else if (Val > SGPR_MAX) { 1717 return IsWave64 ? decodeSpecialReg64(Val) 1718 : decodeSpecialReg32(Val); 1719 } else { 1720 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1721 } 1722 } else { 1723 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1724 } 1725 } 1726 1727 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1728 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1729 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1730 } 1731 1732 bool AMDGPUDisassembler::isVI() const { 1733 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1734 } 1735 1736 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1737 1738 bool AMDGPUDisassembler::isGFX90A() const { 1739 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1740 } 1741 1742 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1743 1744 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1745 1746 bool AMDGPUDisassembler::isGFX10Plus() const { 1747 return AMDGPU::isGFX10Plus(STI); 1748 } 1749 1750 bool AMDGPUDisassembler::isGFX11() const { 1751 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1752 } 1753 1754 bool AMDGPUDisassembler::isGFX11Plus() const { 1755 return AMDGPU::isGFX11Plus(STI); 1756 } 1757 1758 1759 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1760 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1761 } 1762 1763 //===----------------------------------------------------------------------===// 1764 // AMDGPU specific symbol handling 1765 //===----------------------------------------------------------------------===// 1766 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1767 do { \ 1768 KdStream << Indent << DIRECTIVE " " \ 1769 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1770 } while (0) 1771 1772 // NOLINTNEXTLINE(readability-identifier-naming) 1773 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1774 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1775 using namespace amdhsa; 1776 StringRef Indent = "\t"; 1777 1778 // We cannot accurately backward compute #VGPRs used from 1779 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1780 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1781 // simply calculate the inverse of what the assembler does. 1782 1783 uint32_t GranulatedWorkitemVGPRCount = 1784 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1785 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1786 1787 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1788 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1789 1790 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1791 1792 // We cannot backward compute values used to calculate 1793 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1794 // directives can't be computed: 1795 // .amdhsa_reserve_vcc 1796 // .amdhsa_reserve_flat_scratch 1797 // .amdhsa_reserve_xnack_mask 1798 // They take their respective default values if not specified in the assembly. 1799 // 1800 // GRANULATED_WAVEFRONT_SGPR_COUNT 1801 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1802 // 1803 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1804 // are set to 0. So while disassembling we consider that: 1805 // 1806 // GRANULATED_WAVEFRONT_SGPR_COUNT 1807 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1808 // 1809 // The disassembler cannot recover the original values of those 3 directives. 1810 1811 uint32_t GranulatedWavefrontSGPRCount = 1812 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1813 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1814 1815 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1816 return MCDisassembler::Fail; 1817 1818 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1819 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1820 1821 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1822 if (!hasArchitectedFlatScratch()) 1823 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1824 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1825 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1826 1827 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1828 return MCDisassembler::Fail; 1829 1830 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1831 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1832 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1833 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1834 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1835 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1836 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1837 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1838 1839 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1840 return MCDisassembler::Fail; 1841 1842 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1843 1844 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1845 return MCDisassembler::Fail; 1846 1847 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1848 1849 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1850 return MCDisassembler::Fail; 1851 1852 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1853 return MCDisassembler::Fail; 1854 1855 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1856 1857 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1858 return MCDisassembler::Fail; 1859 1860 if (isGFX10Plus()) { 1861 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1862 COMPUTE_PGM_RSRC1_WGP_MODE); 1863 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1864 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1865 } 1866 return MCDisassembler::Success; 1867 } 1868 1869 // NOLINTNEXTLINE(readability-identifier-naming) 1870 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1871 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1872 using namespace amdhsa; 1873 StringRef Indent = "\t"; 1874 if (hasArchitectedFlatScratch()) 1875 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1876 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1877 else 1878 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1879 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1880 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1881 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1882 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1883 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1884 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1885 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1886 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1887 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1888 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1889 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1890 1891 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1892 return MCDisassembler::Fail; 1893 1894 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1895 return MCDisassembler::Fail; 1896 1897 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1898 return MCDisassembler::Fail; 1899 1900 PRINT_DIRECTIVE( 1901 ".amdhsa_exception_fp_ieee_invalid_op", 1902 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1903 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1904 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1905 PRINT_DIRECTIVE( 1906 ".amdhsa_exception_fp_ieee_div_zero", 1907 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1908 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1909 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1910 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1911 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1912 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1913 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1914 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1915 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1916 1917 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1918 return MCDisassembler::Fail; 1919 1920 return MCDisassembler::Success; 1921 } 1922 1923 #undef PRINT_DIRECTIVE 1924 1925 MCDisassembler::DecodeStatus 1926 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1927 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1928 raw_string_ostream &KdStream) const { 1929 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1930 do { \ 1931 KdStream << Indent << DIRECTIVE " " \ 1932 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1933 } while (0) 1934 1935 uint16_t TwoByteBuffer = 0; 1936 uint32_t FourByteBuffer = 0; 1937 1938 StringRef ReservedBytes; 1939 StringRef Indent = "\t"; 1940 1941 assert(Bytes.size() == 64); 1942 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1943 1944 switch (Cursor.tell()) { 1945 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1946 FourByteBuffer = DE.getU32(Cursor); 1947 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1948 << '\n'; 1949 return MCDisassembler::Success; 1950 1951 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1952 FourByteBuffer = DE.getU32(Cursor); 1953 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1954 << FourByteBuffer << '\n'; 1955 return MCDisassembler::Success; 1956 1957 case amdhsa::KERNARG_SIZE_OFFSET: 1958 FourByteBuffer = DE.getU32(Cursor); 1959 KdStream << Indent << ".amdhsa_kernarg_size " 1960 << FourByteBuffer << '\n'; 1961 return MCDisassembler::Success; 1962 1963 case amdhsa::RESERVED0_OFFSET: 1964 // 4 reserved bytes, must be 0. 1965 ReservedBytes = DE.getBytes(Cursor, 4); 1966 for (int I = 0; I < 4; ++I) { 1967 if (ReservedBytes[I] != 0) { 1968 return MCDisassembler::Fail; 1969 } 1970 } 1971 return MCDisassembler::Success; 1972 1973 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1974 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1975 // So far no directive controls this for Code Object V3, so simply skip for 1976 // disassembly. 1977 DE.skip(Cursor, 8); 1978 return MCDisassembler::Success; 1979 1980 case amdhsa::RESERVED1_OFFSET: 1981 // 20 reserved bytes, must be 0. 1982 ReservedBytes = DE.getBytes(Cursor, 20); 1983 for (int I = 0; I < 20; ++I) { 1984 if (ReservedBytes[I] != 0) { 1985 return MCDisassembler::Fail; 1986 } 1987 } 1988 return MCDisassembler::Success; 1989 1990 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1991 // COMPUTE_PGM_RSRC3 1992 // - Only set for GFX10, GFX6-9 have this to be 0. 1993 // - Currently no directives directly control this. 1994 FourByteBuffer = DE.getU32(Cursor); 1995 if (!isGFX10Plus() && FourByteBuffer) { 1996 return MCDisassembler::Fail; 1997 } 1998 return MCDisassembler::Success; 1999 2000 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2001 FourByteBuffer = DE.getU32(Cursor); 2002 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 2003 MCDisassembler::Fail) { 2004 return MCDisassembler::Fail; 2005 } 2006 return MCDisassembler::Success; 2007 2008 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2009 FourByteBuffer = DE.getU32(Cursor); 2010 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 2011 MCDisassembler::Fail) { 2012 return MCDisassembler::Fail; 2013 } 2014 return MCDisassembler::Success; 2015 2016 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2017 using namespace amdhsa; 2018 TwoByteBuffer = DE.getU16(Cursor); 2019 2020 if (!hasArchitectedFlatScratch()) 2021 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2022 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2023 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2024 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2025 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2026 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2027 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2028 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2029 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2030 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2031 if (!hasArchitectedFlatScratch()) 2032 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2033 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2034 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2035 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2036 2037 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2038 return MCDisassembler::Fail; 2039 2040 // Reserved for GFX9 2041 if (isGFX9() && 2042 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2043 return MCDisassembler::Fail; 2044 } else if (isGFX10Plus()) { 2045 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2046 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2047 } 2048 2049 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2050 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2051 2052 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2053 return MCDisassembler::Fail; 2054 2055 return MCDisassembler::Success; 2056 2057 case amdhsa::RESERVED2_OFFSET: 2058 // 6 bytes from here are reserved, must be 0. 2059 ReservedBytes = DE.getBytes(Cursor, 6); 2060 for (int I = 0; I < 6; ++I) { 2061 if (ReservedBytes[I] != 0) 2062 return MCDisassembler::Fail; 2063 } 2064 return MCDisassembler::Success; 2065 2066 default: 2067 llvm_unreachable("Unhandled index. Case statements cover everything."); 2068 return MCDisassembler::Fail; 2069 } 2070 #undef PRINT_DIRECTIVE 2071 } 2072 2073 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2074 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2075 // CP microcode requires the kernel descriptor to be 64 aligned. 2076 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2077 return MCDisassembler::Fail; 2078 2079 std::string Kd; 2080 raw_string_ostream KdStream(Kd); 2081 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2082 2083 DataExtractor::Cursor C(0); 2084 while (C && C.tell() < Bytes.size()) { 2085 MCDisassembler::DecodeStatus Status = 2086 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2087 2088 cantFail(C.takeError()); 2089 2090 if (Status == MCDisassembler::Fail) 2091 return MCDisassembler::Fail; 2092 } 2093 KdStream << ".end_amdhsa_kernel\n"; 2094 outs() << KdStream.str(); 2095 return MCDisassembler::Success; 2096 } 2097 2098 Optional<MCDisassembler::DecodeStatus> 2099 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2100 ArrayRef<uint8_t> Bytes, uint64_t Address, 2101 raw_ostream &CStream) const { 2102 // Right now only kernel descriptor needs to be handled. 2103 // We ignore all other symbols for target specific handling. 2104 // TODO: 2105 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2106 // Object V2 and V3 when symbols are marked protected. 2107 2108 // amd_kernel_code_t for Code Object V2. 2109 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2110 Size = 256; 2111 return MCDisassembler::Fail; 2112 } 2113 2114 // Code Object V3 kernel descriptors. 2115 StringRef Name = Symbol.Name; 2116 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2117 Size = 64; // Size = 64 regardless of success or failure. 2118 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2119 } 2120 return None; 2121 } 2122 2123 //===----------------------------------------------------------------------===// 2124 // AMDGPUSymbolizer 2125 //===----------------------------------------------------------------------===// 2126 2127 // Try to find symbol name for specified label 2128 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2129 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2130 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2131 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2132 2133 if (!IsBranch) { 2134 return false; 2135 } 2136 2137 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2138 if (!Symbols) 2139 return false; 2140 2141 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2142 return Val.Addr == static_cast<uint64_t>(Value) && 2143 Val.Type == ELF::STT_NOTYPE; 2144 }); 2145 if (Result != Symbols->end()) { 2146 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2147 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2148 Inst.addOperand(MCOperand::createExpr(Add)); 2149 return true; 2150 } 2151 // Add to list of referenced addresses, so caller can synthesize a label. 2152 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2153 return false; 2154 } 2155 2156 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2157 int64_t Value, 2158 uint64_t Address) { 2159 llvm_unreachable("unimplemented"); 2160 } 2161 2162 //===----------------------------------------------------------------------===// 2163 // Initialization 2164 //===----------------------------------------------------------------------===// 2165 2166 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2167 LLVMOpInfoCallback /*GetOpInfo*/, 2168 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2169 void *DisInfo, 2170 MCContext *Ctx, 2171 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2172 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2173 } 2174 2175 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2176 const MCSubtargetInfo &STI, 2177 MCContext &Ctx) { 2178 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2179 } 2180 2181 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2182 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2183 createAMDGPUDisassembler); 2184 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2185 createAMDGPUSymbolizer); 2186 } 2187