1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) { 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 95 Offset = SignExtend64<24>(Imm); 96 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 static DecodeStatus decodeSplitBarrier(MCInst &Inst, unsigned Val, 111 uint64_t Addr, 112 const MCDisassembler *Decoder) { 113 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 114 return addOperand(Inst, DAsm->decodeSplitBarrier(Val)); 115 } 116 117 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 118 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 119 uint64_t /*Addr*/, \ 120 const MCDisassembler *Decoder) { \ 121 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 122 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 123 } 124 125 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 126 // number of register. Used by VGPR only and AGPR only operands. 127 #define DECODE_OPERAND_REG_8(RegClass) \ 128 static DecodeStatus Decode##RegClass##RegisterClass( \ 129 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 130 const MCDisassembler *Decoder) { \ 131 assert(Imm < (1 << 8) && "8-bit encoding"); \ 132 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 133 return addOperand( \ 134 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 135 } 136 137 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 138 ImmWidth) \ 139 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 140 const MCDisassembler *Decoder) { \ 141 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 142 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 143 return addOperand(Inst, \ 144 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 145 MandatoryLiteral, ImmWidth)); \ 146 } 147 148 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 149 // get register class. Used by SGPR only operands. 150 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 152 153 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 154 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 155 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 156 // Used by AV_ register classes (AGPR or VGPR only register operands). 157 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ 158 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ 159 Imm | AMDGPU::EncValues::IS_VGPR, false, 0) 160 161 // Decoder for Src(9-bit encoding) registers only. 162 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ 163 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 164 165 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 166 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 167 // only. 168 #define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \ 169 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) 170 171 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 172 // Imm{9} is acc, registers only. 173 #define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \ 174 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) 175 176 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 177 // register from RegClass or immediate. Registers that don't belong to RegClass 178 // will be decoded and InstPrinter will report warning. Immediate will be 179 // decoded into constant of size ImmWidth, should match width of immediate used 180 // by OperandType (important for floating point types). 181 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ 182 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ 183 false, ImmWidth) 184 185 #define DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(Name, OpWidth, ImmWidth) \ 186 DECODE_SrcOp(decodeOperand_##Name, 9, OpWidth, Imm, false, ImmWidth) 187 188 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 189 // and decode using 'enum10' from decodeSrcOp. 190 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ 191 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ 192 Imm | 512, false, ImmWidth) 193 194 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ 195 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ 196 OpWidth, Imm, true, ImmWidth) 197 198 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 199 // when RegisterClass is used as an operand. Most often used for destination 200 // operands. 201 202 DECODE_OPERAND_REG_8(VGPR_32) 203 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 204 DECODE_OPERAND_REG_8(VReg_64) 205 DECODE_OPERAND_REG_8(VReg_96) 206 DECODE_OPERAND_REG_8(VReg_128) 207 DECODE_OPERAND_REG_8(VReg_256) 208 DECODE_OPERAND_REG_8(VReg_288) 209 DECODE_OPERAND_REG_8(VReg_352) 210 DECODE_OPERAND_REG_8(VReg_384) 211 DECODE_OPERAND_REG_8(VReg_512) 212 DECODE_OPERAND_REG_8(VReg_1024) 213 214 DECODE_OPERAND_REG_7(SReg_32, OPW32) 215 DECODE_OPERAND_REG_7(SReg_32_XEXEC, OPW32) 216 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 217 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 218 DECODE_OPERAND_REG_7(SReg_64, OPW64) 219 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 220 DECODE_OPERAND_REG_7(SReg_96, OPW96) 221 DECODE_OPERAND_REG_7(SReg_128, OPW128) 222 DECODE_OPERAND_REG_7(SReg_256, OPW256) 223 DECODE_OPERAND_REG_7(SReg_512, OPW512) 224 225 DECODE_OPERAND_REG_8(AGPR_32) 226 DECODE_OPERAND_REG_8(AReg_64) 227 DECODE_OPERAND_REG_8(AReg_128) 228 DECODE_OPERAND_REG_8(AReg_256) 229 DECODE_OPERAND_REG_8(AReg_512) 230 DECODE_OPERAND_REG_8(AReg_1024) 231 232 DECODE_OPERAND_REG_AV10(AVDst_128, OPW128) 233 DECODE_OPERAND_REG_AV10(AVDst_512, OPW512) 234 235 // Decoders for register only source RegisterOperands that use use 9-bit Src 236 // encoding: 'decodeOperand_<RegClass>'. 237 238 DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) 239 DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) 240 DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) 241 DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) 242 DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) 243 244 DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32) 245 246 DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32) 247 DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64) 248 DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128) 249 250 // Decoders for register or immediate RegisterOperands that use 9-bit Src 251 // encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'. 252 253 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) 254 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) 255 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 16) 256 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) 257 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) 258 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) 259 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) 260 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) 261 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32) 262 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) 263 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 32) 264 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 16) 265 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) 266 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 16) 267 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) 268 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 32) 269 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) 270 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) 271 272 DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(VS_32_ImmV2I16, OPW32, 32) 273 DECODE_OPERAND_SRC_REG_OR_IMM_9_TYPED(VS_32_ImmV2F16, OPW32, 16) 274 275 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) 276 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) 277 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) 278 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) 279 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) 280 281 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) 282 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) 283 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) 284 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32) 285 286 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 287 uint64_t /*Addr*/, 288 const MCDisassembler *Decoder) { 289 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 290 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 291 292 bool IsHi = Imm & (1 << 9); 293 unsigned RegIdx = Imm & 0xff; 294 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 295 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 296 } 297 298 static DecodeStatus 299 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 300 const MCDisassembler *Decoder) { 301 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 302 303 bool IsHi = Imm & (1 << 7); 304 unsigned RegIdx = Imm & 0x7f; 305 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 306 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 307 } 308 309 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 310 uint64_t /*Addr*/, 311 const MCDisassembler *Decoder) { 312 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 313 314 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 315 bool IsVGPR = Imm & (1 << 8); 316 if (IsVGPR) { 317 bool IsHi = Imm & (1 << 7); 318 unsigned RegIdx = Imm & 0x7f; 319 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 320 } 321 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 322 Imm & 0xFF, false, 16)); 323 } 324 325 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 326 uint64_t /*Addr*/, 327 const MCDisassembler *Decoder) { 328 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 329 330 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 331 bool IsVGPR = Imm & (1 << 8); 332 if (IsVGPR) { 333 bool IsHi = Imm & (1 << 9); 334 unsigned RegIdx = Imm & 0xff; 335 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 336 } 337 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 338 Imm & 0xFF, false, 16)); 339 } 340 341 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 342 uint64_t Addr, 343 const MCDisassembler *Decoder) { 344 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 345 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 346 } 347 348 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 349 uint64_t Addr, const void *Decoder) { 350 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 351 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 352 } 353 354 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 355 const MCRegisterInfo *MRI) { 356 if (OpIdx < 0) 357 return false; 358 359 const MCOperand &Op = Inst.getOperand(OpIdx); 360 if (!Op.isReg()) 361 return false; 362 363 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 364 auto Reg = Sub ? Sub : Op.getReg(); 365 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 366 } 367 368 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 369 AMDGPUDisassembler::OpWidthTy Opw, 370 const MCDisassembler *Decoder) { 371 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 372 if (!DAsm->isGFX90A()) { 373 Imm &= 511; 374 } else { 375 // If atomic has both vdata and vdst their register classes are tied. 376 // The bit is decoded along with the vdst, first operand. We need to 377 // change register class to AGPR if vdst was AGPR. 378 // If a DS instruction has both data0 and data1 their register classes 379 // are also tied. 380 unsigned Opc = Inst.getOpcode(); 381 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 382 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 383 : AMDGPU::OpName::vdata; 384 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 385 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 386 if ((int)Inst.getNumOperands() == DataIdx) { 387 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 388 if (IsAGPROperand(Inst, DstIdx, MRI)) 389 Imm |= 512; 390 } 391 392 if (TSFlags & SIInstrFlags::DS) { 393 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 394 if ((int)Inst.getNumOperands() == Data2Idx && 395 IsAGPROperand(Inst, DataIdx, MRI)) 396 Imm |= 512; 397 } 398 } 399 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 400 } 401 402 template <AMDGPUDisassembler::OpWidthTy Opw> 403 static DecodeStatus decodeAVLdSt(MCInst &Inst, unsigned Imm, 404 uint64_t /* Addr */, 405 const MCDisassembler *Decoder) { 406 return decodeAVLdSt(Inst, Imm, Opw, Decoder); 407 } 408 409 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 410 uint64_t Addr, 411 const MCDisassembler *Decoder) { 412 assert(Imm < (1 << 9) && "9-bit encoding"); 413 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 414 return addOperand( 415 Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true)); 416 } 417 418 #define DECODE_SDWA(DecName) \ 419 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 420 421 DECODE_SDWA(Src32) 422 DECODE_SDWA(Src16) 423 DECODE_SDWA(VopcDst) 424 425 #include "AMDGPUGenDisassemblerTables.inc" 426 427 //===----------------------------------------------------------------------===// 428 // 429 //===----------------------------------------------------------------------===// 430 431 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 432 assert(Bytes.size() >= sizeof(T)); 433 const auto Res = 434 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 435 Bytes = Bytes.slice(sizeof(T)); 436 return Res; 437 } 438 439 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 440 assert(Bytes.size() >= 12); 441 uint64_t Lo = 442 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 443 Bytes = Bytes.slice(8); 444 uint64_t Hi = 445 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 446 Bytes = Bytes.slice(4); 447 return DecoderUInt128(Lo, Hi); 448 } 449 450 // The disassembler is greedy, so we need to check FI operand value to 451 // not parse a dpp if the correct literal is not set. For dpp16 the 452 // autogenerated decoder checks the dpp literal 453 static bool isValidDPP8(const MCInst &MI) { 454 using namespace llvm::AMDGPU::DPP; 455 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 456 assert(FiIdx != -1); 457 if ((unsigned)FiIdx >= MI.getNumOperands()) 458 return false; 459 unsigned Fi = MI.getOperand(FiIdx).getImm(); 460 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 461 } 462 463 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 464 ArrayRef<uint8_t> Bytes_, 465 uint64_t Address, 466 raw_ostream &CS) const { 467 bool IsSDWA = false; 468 469 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 470 Bytes = Bytes_.slice(0, MaxInstBytesNum); 471 472 DecodeStatus Res = MCDisassembler::Fail; 473 do { 474 // ToDo: better to switch encoding length using some bit predicate 475 // but it is unknown yet, so try all we can 476 477 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 478 // encodings 479 if (isGFX11Plus() && Bytes.size() >= 12 ) { 480 DecoderUInt128 DecW = eat12Bytes(Bytes); 481 Res = 482 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 483 MI, DecW, Address, CS); 484 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 485 break; 486 MI = MCInst(); // clear 487 Res = 488 tryDecodeInst(DecoderTableDPP8GFX1296, DecoderTableDPP8GFX12_FAKE1696, 489 MI, DecW, Address, CS); 490 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 491 break; 492 MI = MCInst(); // clear 493 494 const auto convertVOPDPP = [&]() { 495 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) { 496 convertVOP3PDPPInst(MI); 497 } else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) { 498 convertVOPCDPPInst(MI); // Special VOP3 case 499 } else { 500 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 501 convertVOP3DPPInst(MI); // Regular VOP3 case 502 } 503 }; 504 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 505 MI, DecW, Address, CS); 506 if (Res) { 507 convertVOPDPP(); 508 break; 509 } 510 Res = tryDecodeInst(DecoderTableDPPGFX1296, DecoderTableDPPGFX12_FAKE1696, 511 MI, DecW, Address, CS); 512 if (Res) { 513 convertVOPDPP(); 514 break; 515 } 516 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 517 if (Res) 518 break; 519 520 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 521 if (Res) 522 break; 523 524 Res = tryDecodeInst(DecoderTableGFX12W6496, MI, DecW, Address, CS); 525 if (Res) 526 break; 527 } 528 // Reinitialize Bytes 529 Bytes = Bytes_.slice(0, MaxInstBytesNum); 530 531 if (Bytes.size() >= 8) { 532 const uint64_t QW = eatBytes<uint64_t>(Bytes); 533 534 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 535 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 536 if (Res) { 537 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 538 == -1) 539 break; 540 if (convertDPP8Inst(MI) == MCDisassembler::Success) 541 break; 542 MI = MCInst(); // clear 543 } 544 } 545 546 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 547 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 548 break; 549 MI = MCInst(); // clear 550 551 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 552 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 553 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 554 break; 555 MI = MCInst(); // clear 556 557 Res = tryDecodeInst(DecoderTableDPP8GFX1264, 558 DecoderTableDPP8GFX12_FAKE1664, MI, QW, Address, CS); 559 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 560 break; 561 MI = MCInst(); // clear 562 563 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 564 if (Res) break; 565 566 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 567 MI, QW, Address, CS); 568 if (Res) { 569 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 570 convertVOPCDPPInst(MI); 571 break; 572 } 573 574 Res = tryDecodeInst(DecoderTableDPPGFX1264, DecoderTableDPPGFX12_FAKE1664, 575 MI, QW, Address, CS); 576 if (Res) { 577 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 578 convertVOPCDPPInst(MI); 579 break; 580 } 581 582 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 583 if (Res) { IsSDWA = true; break; } 584 585 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 586 if (Res) { IsSDWA = true; break; } 587 588 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 589 if (Res) { IsSDWA = true; break; } 590 591 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 592 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 593 if (Res) 594 break; 595 } 596 597 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 598 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 599 // table first so we print the correct name. 600 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 601 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 602 if (Res) 603 break; 604 } 605 } 606 607 // Reinitialize Bytes as DPP64 could have eaten too much 608 Bytes = Bytes_.slice(0, MaxInstBytesNum); 609 610 // Try decode 32-bit instruction 611 if (Bytes.size() < 4) break; 612 const uint32_t DW = eatBytes<uint32_t>(Bytes); 613 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 614 if (Res) break; 615 616 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 617 if (Res) break; 618 619 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 620 if (Res) break; 621 622 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 623 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 624 if (Res) 625 break; 626 } 627 628 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 629 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 630 if (Res) break; 631 } 632 633 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 634 if (Res) break; 635 636 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 637 Address, CS); 638 if (Res) break; 639 640 Res = tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW, 641 Address, CS); 642 if (Res) 643 break; 644 645 if (Bytes.size() < 4) break; 646 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 647 648 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 649 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 650 if (Res) 651 break; 652 } 653 654 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 655 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 656 if (Res) 657 break; 658 } 659 660 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 661 if (Res) break; 662 663 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS); 664 if (Res) break; 665 666 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 667 if (Res) break; 668 669 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 670 if (Res) break; 671 672 Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW, 673 Address, CS); 674 if (Res) 675 break; 676 677 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 678 Address, CS); 679 if (Res) 680 break; 681 682 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS); 683 if (Res) 684 break; 685 686 Res = tryDecodeInst(DecoderTableWMMAGFX1264, MI, QW, Address, CS); 687 } while (false); 688 689 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 690 // Insert dummy unused src2_modifiers. 691 insertNamedMCOperand(MI, MCOperand::createImm(0), 692 AMDGPU::OpName::src2_modifiers); 693 } 694 695 if (Res && (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp || 696 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp)) { 697 // Insert dummy unused src2_modifiers. 698 insertNamedMCOperand(MI, MCOperand::createImm(0), 699 AMDGPU::OpName::src2_modifiers); 700 } 701 702 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) && 703 !AMDGPU::hasGDS(STI)) { 704 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds); 705 } 706 707 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 708 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 709 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 710 AMDGPU::OpName::cpol); 711 if (CPolPos != -1) { 712 unsigned CPol = 713 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 714 AMDGPU::CPol::GLC : 0; 715 if (MI.getNumOperands() <= (unsigned)CPolPos) { 716 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 717 AMDGPU::OpName::cpol); 718 } else if (CPol) { 719 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 720 } 721 } 722 } 723 724 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 725 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 726 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 727 // GFX90A lost TFE, its place is occupied by ACC. 728 int TFEOpIdx = 729 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 730 if (TFEOpIdx != -1) { 731 auto TFEIter = MI.begin(); 732 std::advance(TFEIter, TFEOpIdx); 733 MI.insert(TFEIter, MCOperand::createImm(0)); 734 } 735 } 736 737 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 738 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 739 int SWZOpIdx = 740 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 741 if (SWZOpIdx != -1) { 742 auto SWZIter = MI.begin(); 743 std::advance(SWZIter, SWZOpIdx); 744 MI.insert(SWZIter, MCOperand::createImm(0)); 745 } 746 } 747 748 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 749 int VAddr0Idx = 750 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 751 int RsrcIdx = 752 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 753 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 754 if (VAddr0Idx >= 0 && NSAArgs > 0) { 755 unsigned NSAWords = (NSAArgs + 3) / 4; 756 if (Bytes.size() < 4 * NSAWords) { 757 Res = MCDisassembler::Fail; 758 } else { 759 for (unsigned i = 0; i < NSAArgs; ++i) { 760 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 761 auto VAddrRCID = 762 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 763 MI.insert(MI.begin() + VAddrIdx, 764 createRegOperand(VAddrRCID, Bytes[i])); 765 } 766 Bytes = Bytes.slice(4 * NSAWords); 767 } 768 } 769 770 if (Res) 771 Res = convertMIMGInst(MI); 772 } 773 774 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 775 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 776 Res = convertMIMGInst(MI); 777 778 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 779 Res = convertEXPInst(MI); 780 781 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 782 Res = convertVINTERPInst(MI); 783 784 if (Res && IsSDWA) 785 Res = convertSDWAInst(MI); 786 787 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 788 AMDGPU::OpName::vdst_in); 789 if (VDstIn_Idx != -1) { 790 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 791 MCOI::OperandConstraint::TIED_TO); 792 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 793 !MI.getOperand(VDstIn_Idx).isReg() || 794 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 795 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 796 MI.erase(&MI.getOperand(VDstIn_Idx)); 797 insertNamedMCOperand(MI, 798 MCOperand::createReg(MI.getOperand(Tied).getReg()), 799 AMDGPU::OpName::vdst_in); 800 } 801 } 802 803 int ImmLitIdx = 804 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 805 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 806 if (Res && ImmLitIdx != -1 && !IsSOPK) 807 Res = convertFMAanyK(MI, ImmLitIdx); 808 809 // if the opcode was not recognized we'll assume a Size of 4 bytes 810 // (unless there are fewer bytes left) 811 Size = Res ? (MaxInstBytesNum - Bytes.size()) 812 : std::min((size_t)4, Bytes_.size()); 813 return Res; 814 } 815 816 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 817 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 818 // The MCInst still has these fields even though they are no longer encoded 819 // in the GFX11 instruction. 820 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 821 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 822 } 823 return MCDisassembler::Success; 824 } 825 826 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 827 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 828 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 829 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 830 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 831 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 832 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 833 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 834 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 835 // The MCInst has this field that is not directly encoded in the 836 // instruction. 837 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 838 } 839 return MCDisassembler::Success; 840 } 841 842 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 843 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 844 STI.hasFeature(AMDGPU::FeatureGFX10)) { 845 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 846 // VOPC - insert clamp 847 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 848 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 849 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 850 if (SDst != -1) { 851 // VOPC - insert VCC register as sdst 852 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 853 AMDGPU::OpName::sdst); 854 } else { 855 // VOP1/2 - insert omod if present in instruction 856 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 857 } 858 } 859 return MCDisassembler::Success; 860 } 861 862 struct VOPModifiers { 863 unsigned OpSel = 0; 864 unsigned OpSelHi = 0; 865 unsigned NegLo = 0; 866 unsigned NegHi = 0; 867 }; 868 869 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 870 // Note that these values do not affect disassembler output, 871 // so this is only necessary for consistency with src_modifiers. 872 static VOPModifiers collectVOPModifiers(const MCInst &MI, 873 bool IsVOP3P = false) { 874 VOPModifiers Modifiers; 875 unsigned Opc = MI.getOpcode(); 876 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 877 AMDGPU::OpName::src1_modifiers, 878 AMDGPU::OpName::src2_modifiers}; 879 for (int J = 0; J < 3; ++J) { 880 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 881 if (OpIdx == -1) 882 continue; 883 884 unsigned Val = MI.getOperand(OpIdx).getImm(); 885 886 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 887 if (IsVOP3P) { 888 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 889 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 890 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 891 } else if (J == 0) { 892 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 893 } 894 } 895 896 return Modifiers; 897 } 898 899 // MAC opcodes have special old and src2 operands. 900 // src2 is tied to dst, while old is not tied (but assumed to be). 901 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 902 constexpr int DST_IDX = 0; 903 auto Opcode = MI.getOpcode(); 904 const auto &Desc = MCII->get(Opcode); 905 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 906 907 if (OldIdx != -1 && Desc.getOperandConstraint( 908 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 909 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 910 assert(Desc.getOperandConstraint( 911 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 912 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 913 (void)DST_IDX; 914 return true; 915 } 916 917 return false; 918 } 919 920 // Create dummy old operand and insert dummy unused src2_modifiers 921 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 922 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 923 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 924 insertNamedMCOperand(MI, MCOperand::createImm(0), 925 AMDGPU::OpName::src2_modifiers); 926 } 927 928 // We must check FI == literal to reject not genuine dpp8 insts, and we must 929 // first add optional MI operands to check FI 930 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 931 unsigned Opc = MI.getOpcode(); 932 933 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 934 convertVOP3PDPPInst(MI); 935 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 936 AMDGPU::isVOPC64DPP(Opc)) { 937 convertVOPCDPPInst(MI); 938 } else { 939 if (isMacDPP(MI)) 940 convertMacDPPInst(MI); 941 942 int VDstInIdx = 943 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 944 if (VDstInIdx != -1) 945 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 946 947 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 || 948 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12) 949 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 950 951 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 952 if (MI.getNumOperands() < DescNumOps && 953 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 954 auto Mods = collectVOPModifiers(MI); 955 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 956 AMDGPU::OpName::op_sel); 957 } else { 958 // Insert dummy unused src modifiers. 959 if (MI.getNumOperands() < DescNumOps && 960 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 961 insertNamedMCOperand(MI, MCOperand::createImm(0), 962 AMDGPU::OpName::src0_modifiers); 963 964 if (MI.getNumOperands() < DescNumOps && 965 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 966 insertNamedMCOperand(MI, MCOperand::createImm(0), 967 AMDGPU::OpName::src1_modifiers); 968 } 969 } 970 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 971 } 972 973 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 974 if (isMacDPP(MI)) 975 convertMacDPPInst(MI); 976 977 int VDstInIdx = 978 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in); 979 if (VDstInIdx != -1) 980 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); 981 982 if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 || 983 MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12) 984 insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); 985 986 unsigned Opc = MI.getOpcode(); 987 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 988 if (MI.getNumOperands() < DescNumOps && 989 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 990 auto Mods = collectVOPModifiers(MI); 991 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 992 AMDGPU::OpName::op_sel); 993 } 994 return MCDisassembler::Success; 995 } 996 997 // Note that before gfx10, the MIMG encoding provided no information about 998 // VADDR size. Consequently, decoded instructions always show address as if it 999 // has 1 dword, which could be not really so. 1000 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 1001 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 1002 1003 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1004 AMDGPU::OpName::vdst); 1005 1006 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1007 AMDGPU::OpName::vdata); 1008 int VAddr0Idx = 1009 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 1010 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 1011 : AMDGPU::OpName::rsrc; 1012 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 1013 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1014 AMDGPU::OpName::dmask); 1015 1016 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1017 AMDGPU::OpName::tfe); 1018 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 1019 AMDGPU::OpName::d16); 1020 1021 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 1022 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 1023 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 1024 1025 assert(VDataIdx != -1); 1026 if (BaseOpcode->BVH) { 1027 // Add A16 operand for intersect_ray instructions 1028 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 1029 return MCDisassembler::Success; 1030 } 1031 1032 bool IsAtomic = (VDstIdx != -1); 1033 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 1034 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 1035 bool IsNSA = false; 1036 bool IsPartialNSA = false; 1037 unsigned AddrSize = Info->VAddrDwords; 1038 1039 if (isGFX10Plus()) { 1040 unsigned DimIdx = 1041 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 1042 int A16Idx = 1043 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 1044 const AMDGPU::MIMGDimInfo *Dim = 1045 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 1046 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 1047 1048 AddrSize = 1049 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 1050 1051 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 1052 // VIMAGE insts other than BVH never use vaddr4. 1053 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 1054 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 1055 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 1056 if (!IsNSA) { 1057 if (!IsVSample && AddrSize > 12) 1058 AddrSize = 16; 1059 } else { 1060 if (AddrSize > Info->VAddrDwords) { 1061 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1062 // The NSA encoding does not contain enough operands for the 1063 // combination of base opcode / dimension. Should this be an error? 1064 return MCDisassembler::Success; 1065 } 1066 IsPartialNSA = true; 1067 } 1068 } 1069 } 1070 1071 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1072 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1073 1074 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1075 if (D16 && AMDGPU::hasPackedD16(STI)) { 1076 DstSize = (DstSize + 1) / 2; 1077 } 1078 1079 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1080 DstSize += 1; 1081 1082 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1083 return MCDisassembler::Success; 1084 1085 int NewOpcode = 1086 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1087 if (NewOpcode == -1) 1088 return MCDisassembler::Success; 1089 1090 // Widen the register to the correct number of enabled channels. 1091 unsigned NewVdata = AMDGPU::NoRegister; 1092 if (DstSize != Info->VDataDwords) { 1093 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1094 1095 // Get first subregister of VData 1096 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1097 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1098 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1099 1100 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1101 &MRI.getRegClass(DataRCID)); 1102 if (NewVdata == AMDGPU::NoRegister) { 1103 // It's possible to encode this such that the low register + enabled 1104 // components exceeds the register count. 1105 return MCDisassembler::Success; 1106 } 1107 } 1108 1109 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1110 // If using partial NSA on GFX11+ widen last address register. 1111 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1112 unsigned NewVAddrSA = AMDGPU::NoRegister; 1113 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1114 AddrSize != Info->VAddrDwords) { 1115 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1116 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1117 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1118 1119 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1120 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1121 &MRI.getRegClass(AddrRCID)); 1122 if (!NewVAddrSA) 1123 return MCDisassembler::Success; 1124 } 1125 1126 MI.setOpcode(NewOpcode); 1127 1128 if (NewVdata != AMDGPU::NoRegister) { 1129 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1130 1131 if (IsAtomic) { 1132 // Atomic operations have an additional operand (a copy of data) 1133 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1134 } 1135 } 1136 1137 if (NewVAddrSA) { 1138 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1139 } else if (IsNSA) { 1140 assert(AddrSize <= Info->VAddrDwords); 1141 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1142 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1143 } 1144 1145 return MCDisassembler::Success; 1146 } 1147 1148 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1149 // decoder only adds to src_modifiers, so manually add the bits to the other 1150 // operands. 1151 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1152 unsigned Opc = MI.getOpcode(); 1153 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1154 auto Mods = collectVOPModifiers(MI, true); 1155 1156 if (MI.getNumOperands() < DescNumOps && 1157 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1158 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1159 1160 if (MI.getNumOperands() < DescNumOps && 1161 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1162 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1163 AMDGPU::OpName::op_sel); 1164 if (MI.getNumOperands() < DescNumOps && 1165 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1166 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1167 AMDGPU::OpName::op_sel_hi); 1168 if (MI.getNumOperands() < DescNumOps && 1169 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1170 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1171 AMDGPU::OpName::neg_lo); 1172 if (MI.getNumOperands() < DescNumOps && 1173 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1174 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1175 AMDGPU::OpName::neg_hi); 1176 1177 return MCDisassembler::Success; 1178 } 1179 1180 // Create dummy old operand and insert optional operands 1181 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1182 unsigned Opc = MI.getOpcode(); 1183 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1184 1185 if (MI.getNumOperands() < DescNumOps && 1186 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1187 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1188 1189 if (MI.getNumOperands() < DescNumOps && 1190 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1191 insertNamedMCOperand(MI, MCOperand::createImm(0), 1192 AMDGPU::OpName::src0_modifiers); 1193 1194 if (MI.getNumOperands() < DescNumOps && 1195 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1196 insertNamedMCOperand(MI, MCOperand::createImm(0), 1197 AMDGPU::OpName::src1_modifiers); 1198 return MCDisassembler::Success; 1199 } 1200 1201 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1202 int ImmLitIdx) const { 1203 assert(HasLiteral && "Should have decoded a literal"); 1204 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1205 unsigned DescNumOps = Desc.getNumOperands(); 1206 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1207 AMDGPU::OpName::immDeferred); 1208 assert(DescNumOps == MI.getNumOperands()); 1209 for (unsigned I = 0; I < DescNumOps; ++I) { 1210 auto &Op = MI.getOperand(I); 1211 auto OpType = Desc.operands()[I].OperandType; 1212 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1213 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1214 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1215 IsDeferredOp) 1216 Op.setImm(Literal); 1217 } 1218 return MCDisassembler::Success; 1219 } 1220 1221 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1222 return getContext().getRegisterInfo()-> 1223 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1224 } 1225 1226 inline 1227 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1228 const Twine& ErrMsg) const { 1229 *CommentStream << "Error: " + ErrMsg; 1230 1231 // ToDo: add support for error operands to MCInst.h 1232 // return MCOperand::createError(V); 1233 return MCOperand(); 1234 } 1235 1236 inline 1237 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1238 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1239 } 1240 1241 inline 1242 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1243 unsigned Val) const { 1244 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1245 if (Val >= RegCl.getNumRegs()) 1246 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1247 ": unknown register " + Twine(Val)); 1248 return createRegOperand(RegCl.getRegister(Val)); 1249 } 1250 1251 inline 1252 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1253 unsigned Val) const { 1254 // ToDo: SI/CI have 104 SGPRs, VI - 102 1255 // Valery: here we accepting as much as we can, let assembler sort it out 1256 int shift = 0; 1257 switch (SRegClassID) { 1258 case AMDGPU::SGPR_32RegClassID: 1259 case AMDGPU::TTMP_32RegClassID: 1260 break; 1261 case AMDGPU::SGPR_64RegClassID: 1262 case AMDGPU::TTMP_64RegClassID: 1263 shift = 1; 1264 break; 1265 case AMDGPU::SGPR_96RegClassID: 1266 case AMDGPU::TTMP_96RegClassID: 1267 case AMDGPU::SGPR_128RegClassID: 1268 case AMDGPU::TTMP_128RegClassID: 1269 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1270 // this bundle? 1271 case AMDGPU::SGPR_256RegClassID: 1272 case AMDGPU::TTMP_256RegClassID: 1273 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1274 // this bundle? 1275 case AMDGPU::SGPR_288RegClassID: 1276 case AMDGPU::TTMP_288RegClassID: 1277 case AMDGPU::SGPR_320RegClassID: 1278 case AMDGPU::TTMP_320RegClassID: 1279 case AMDGPU::SGPR_352RegClassID: 1280 case AMDGPU::TTMP_352RegClassID: 1281 case AMDGPU::SGPR_384RegClassID: 1282 case AMDGPU::TTMP_384RegClassID: 1283 case AMDGPU::SGPR_512RegClassID: 1284 case AMDGPU::TTMP_512RegClassID: 1285 shift = 2; 1286 break; 1287 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1288 // this bundle? 1289 default: 1290 llvm_unreachable("unhandled register class"); 1291 } 1292 1293 if (Val % (1 << shift)) { 1294 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1295 << ": scalar reg isn't aligned " << Val; 1296 } 1297 1298 return createRegOperand(SRegClassID, Val >> shift); 1299 } 1300 1301 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1302 bool IsHi) const { 1303 unsigned RegIdxInVGPR16 = RegIdx * 2 + (IsHi ? 1 : 0); 1304 return createRegOperand(AMDGPU::VGPR_16RegClassID, RegIdxInVGPR16); 1305 } 1306 1307 // Decode Literals for insts which always have a literal in the encoding 1308 MCOperand 1309 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1310 if (HasLiteral) { 1311 assert( 1312 AMDGPU::hasVOPD(STI) && 1313 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1314 if (Literal != Val) 1315 return errOperand(Val, "More than one unique literal is illegal"); 1316 } 1317 HasLiteral = true; 1318 Literal = Val; 1319 return MCOperand::createImm(Literal); 1320 } 1321 1322 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1323 // For now all literal constants are supposed to be unsigned integer 1324 // ToDo: deal with signed/unsigned 64-bit integer constants 1325 // ToDo: deal with float/double constants 1326 if (!HasLiteral) { 1327 if (Bytes.size() < 4) { 1328 return errOperand(0, "cannot read literal, inst bytes left " + 1329 Twine(Bytes.size())); 1330 } 1331 HasLiteral = true; 1332 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1333 if (ExtendFP64) 1334 Literal64 <<= 32; 1335 } 1336 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1337 } 1338 1339 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1340 using namespace AMDGPU::EncValues; 1341 1342 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1343 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1344 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1345 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1346 // Cast prevents negative overflow. 1347 } 1348 1349 static int64_t getInlineImmVal32(unsigned Imm) { 1350 switch (Imm) { 1351 case 240: 1352 return llvm::bit_cast<uint32_t>(0.5f); 1353 case 241: 1354 return llvm::bit_cast<uint32_t>(-0.5f); 1355 case 242: 1356 return llvm::bit_cast<uint32_t>(1.0f); 1357 case 243: 1358 return llvm::bit_cast<uint32_t>(-1.0f); 1359 case 244: 1360 return llvm::bit_cast<uint32_t>(2.0f); 1361 case 245: 1362 return llvm::bit_cast<uint32_t>(-2.0f); 1363 case 246: 1364 return llvm::bit_cast<uint32_t>(4.0f); 1365 case 247: 1366 return llvm::bit_cast<uint32_t>(-4.0f); 1367 case 248: // 1 / (2 * PI) 1368 return 0x3e22f983; 1369 default: 1370 llvm_unreachable("invalid fp inline imm"); 1371 } 1372 } 1373 1374 static int64_t getInlineImmVal64(unsigned Imm) { 1375 switch (Imm) { 1376 case 240: 1377 return llvm::bit_cast<uint64_t>(0.5); 1378 case 241: 1379 return llvm::bit_cast<uint64_t>(-0.5); 1380 case 242: 1381 return llvm::bit_cast<uint64_t>(1.0); 1382 case 243: 1383 return llvm::bit_cast<uint64_t>(-1.0); 1384 case 244: 1385 return llvm::bit_cast<uint64_t>(2.0); 1386 case 245: 1387 return llvm::bit_cast<uint64_t>(-2.0); 1388 case 246: 1389 return llvm::bit_cast<uint64_t>(4.0); 1390 case 247: 1391 return llvm::bit_cast<uint64_t>(-4.0); 1392 case 248: // 1 / (2 * PI) 1393 return 0x3fc45f306dc9c882; 1394 default: 1395 llvm_unreachable("invalid fp inline imm"); 1396 } 1397 } 1398 1399 static int64_t getInlineImmVal16(unsigned Imm) { 1400 switch (Imm) { 1401 case 240: 1402 return 0x3800; 1403 case 241: 1404 return 0xB800; 1405 case 242: 1406 return 0x3C00; 1407 case 243: 1408 return 0xBC00; 1409 case 244: 1410 return 0x4000; 1411 case 245: 1412 return 0xC000; 1413 case 246: 1414 return 0x4400; 1415 case 247: 1416 return 0xC400; 1417 case 248: // 1 / (2 * PI) 1418 return 0x3118; 1419 default: 1420 llvm_unreachable("invalid fp inline imm"); 1421 } 1422 } 1423 1424 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1425 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1426 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1427 1428 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1429 // ImmWidth 0 is a default case where operand should not allow immediates. 1430 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1431 // use it to print verbose error message. 1432 switch (ImmWidth) { 1433 case 0: 1434 case 32: 1435 return MCOperand::createImm(getInlineImmVal32(Imm)); 1436 case 64: 1437 return MCOperand::createImm(getInlineImmVal64(Imm)); 1438 case 16: 1439 return MCOperand::createImm(getInlineImmVal16(Imm)); 1440 default: 1441 llvm_unreachable("implement me"); 1442 } 1443 } 1444 1445 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1446 using namespace AMDGPU; 1447 1448 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1449 switch (Width) { 1450 default: // fall 1451 case OPW32: 1452 case OPW16: 1453 case OPWV216: 1454 return VGPR_32RegClassID; 1455 case OPW64: 1456 case OPWV232: return VReg_64RegClassID; 1457 case OPW96: return VReg_96RegClassID; 1458 case OPW128: return VReg_128RegClassID; 1459 case OPW160: return VReg_160RegClassID; 1460 case OPW256: return VReg_256RegClassID; 1461 case OPW288: return VReg_288RegClassID; 1462 case OPW320: return VReg_320RegClassID; 1463 case OPW352: return VReg_352RegClassID; 1464 case OPW384: return VReg_384RegClassID; 1465 case OPW512: return VReg_512RegClassID; 1466 case OPW1024: return VReg_1024RegClassID; 1467 } 1468 } 1469 1470 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1471 using namespace AMDGPU; 1472 1473 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1474 switch (Width) { 1475 default: // fall 1476 case OPW32: 1477 case OPW16: 1478 case OPWV216: 1479 return AGPR_32RegClassID; 1480 case OPW64: 1481 case OPWV232: return AReg_64RegClassID; 1482 case OPW96: return AReg_96RegClassID; 1483 case OPW128: return AReg_128RegClassID; 1484 case OPW160: return AReg_160RegClassID; 1485 case OPW256: return AReg_256RegClassID; 1486 case OPW288: return AReg_288RegClassID; 1487 case OPW320: return AReg_320RegClassID; 1488 case OPW352: return AReg_352RegClassID; 1489 case OPW384: return AReg_384RegClassID; 1490 case OPW512: return AReg_512RegClassID; 1491 case OPW1024: return AReg_1024RegClassID; 1492 } 1493 } 1494 1495 1496 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1497 using namespace AMDGPU; 1498 1499 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1500 switch (Width) { 1501 default: // fall 1502 case OPW32: 1503 case OPW16: 1504 case OPWV216: 1505 return SGPR_32RegClassID; 1506 case OPW64: 1507 case OPWV232: return SGPR_64RegClassID; 1508 case OPW96: return SGPR_96RegClassID; 1509 case OPW128: return SGPR_128RegClassID; 1510 case OPW160: return SGPR_160RegClassID; 1511 case OPW256: return SGPR_256RegClassID; 1512 case OPW288: return SGPR_288RegClassID; 1513 case OPW320: return SGPR_320RegClassID; 1514 case OPW352: return SGPR_352RegClassID; 1515 case OPW384: return SGPR_384RegClassID; 1516 case OPW512: return SGPR_512RegClassID; 1517 } 1518 } 1519 1520 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1521 using namespace AMDGPU; 1522 1523 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1524 switch (Width) { 1525 default: // fall 1526 case OPW32: 1527 case OPW16: 1528 case OPWV216: 1529 return TTMP_32RegClassID; 1530 case OPW64: 1531 case OPWV232: return TTMP_64RegClassID; 1532 case OPW128: return TTMP_128RegClassID; 1533 case OPW256: return TTMP_256RegClassID; 1534 case OPW288: return TTMP_288RegClassID; 1535 case OPW320: return TTMP_320RegClassID; 1536 case OPW352: return TTMP_352RegClassID; 1537 case OPW384: return TTMP_384RegClassID; 1538 case OPW512: return TTMP_512RegClassID; 1539 } 1540 } 1541 1542 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1543 using namespace AMDGPU::EncValues; 1544 1545 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1546 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1547 1548 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1549 } 1550 1551 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1552 bool MandatoryLiteral, 1553 unsigned ImmWidth, bool IsFP) const { 1554 using namespace AMDGPU::EncValues; 1555 1556 assert(Val < 1024); // enum10 1557 1558 bool IsAGPR = Val & 512; 1559 Val &= 511; 1560 1561 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1562 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1563 : getVgprClassId(Width), Val - VGPR_MIN); 1564 } 1565 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1566 IsFP); 1567 } 1568 1569 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, 1570 unsigned Val, 1571 bool MandatoryLiteral, 1572 unsigned ImmWidth, 1573 bool IsFP) const { 1574 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1575 // decoded earlier. 1576 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1577 using namespace AMDGPU::EncValues; 1578 1579 if (Val <= SGPR_MAX) { 1580 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1581 static_assert(SGPR_MIN == 0); 1582 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1583 } 1584 1585 int TTmpIdx = getTTmpIdx(Val); 1586 if (TTmpIdx >= 0) { 1587 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1588 } 1589 1590 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1591 return decodeIntImmed(Val); 1592 1593 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1594 return decodeFPImmed(ImmWidth, Val); 1595 1596 if (Val == LITERAL_CONST) { 1597 if (MandatoryLiteral) 1598 // Keep a sentinel value for deferred setting 1599 return MCOperand::createImm(LITERAL_CONST); 1600 else 1601 return decodeLiteralConstant(IsFP && ImmWidth == 64); 1602 } 1603 1604 switch (Width) { 1605 case OPW32: 1606 case OPW16: 1607 case OPWV216: 1608 return decodeSpecialReg32(Val); 1609 case OPW64: 1610 case OPWV232: 1611 return decodeSpecialReg64(Val); 1612 default: 1613 llvm_unreachable("unexpected immediate type"); 1614 } 1615 } 1616 1617 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1618 // opposite of bit 0 of DstX. 1619 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1620 unsigned Val) const { 1621 int VDstXInd = 1622 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1623 assert(VDstXInd != -1); 1624 assert(Inst.getOperand(VDstXInd).isReg()); 1625 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1626 Val |= ~XDstReg & 1; 1627 auto Width = llvm::AMDGPUDisassembler::OPW32; 1628 return createRegOperand(getVgprClassId(Width), Val); 1629 } 1630 1631 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1632 using namespace AMDGPU; 1633 1634 switch (Val) { 1635 // clang-format off 1636 case 102: return createRegOperand(FLAT_SCR_LO); 1637 case 103: return createRegOperand(FLAT_SCR_HI); 1638 case 104: return createRegOperand(XNACK_MASK_LO); 1639 case 105: return createRegOperand(XNACK_MASK_HI); 1640 case 106: return createRegOperand(VCC_LO); 1641 case 107: return createRegOperand(VCC_HI); 1642 case 108: return createRegOperand(TBA_LO); 1643 case 109: return createRegOperand(TBA_HI); 1644 case 110: return createRegOperand(TMA_LO); 1645 case 111: return createRegOperand(TMA_HI); 1646 case 124: 1647 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1648 case 125: 1649 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1650 case 126: return createRegOperand(EXEC_LO); 1651 case 127: return createRegOperand(EXEC_HI); 1652 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1653 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1654 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1655 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1656 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1657 case 251: return createRegOperand(SRC_VCCZ); 1658 case 252: return createRegOperand(SRC_EXECZ); 1659 case 253: return createRegOperand(SRC_SCC); 1660 case 254: return createRegOperand(LDS_DIRECT); 1661 default: break; 1662 // clang-format on 1663 } 1664 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1665 } 1666 1667 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1668 using namespace AMDGPU; 1669 1670 switch (Val) { 1671 case 102: return createRegOperand(FLAT_SCR); 1672 case 104: return createRegOperand(XNACK_MASK); 1673 case 106: return createRegOperand(VCC); 1674 case 108: return createRegOperand(TBA); 1675 case 110: return createRegOperand(TMA); 1676 case 124: 1677 if (isGFX11Plus()) 1678 return createRegOperand(SGPR_NULL); 1679 break; 1680 case 125: 1681 if (!isGFX11Plus()) 1682 return createRegOperand(SGPR_NULL); 1683 break; 1684 case 126: return createRegOperand(EXEC); 1685 case 235: return createRegOperand(SRC_SHARED_BASE); 1686 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1687 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1688 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1689 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1690 case 251: return createRegOperand(SRC_VCCZ); 1691 case 252: return createRegOperand(SRC_EXECZ); 1692 case 253: return createRegOperand(SRC_SCC); 1693 default: break; 1694 } 1695 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1696 } 1697 1698 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1699 const unsigned Val, 1700 unsigned ImmWidth) const { 1701 using namespace AMDGPU::SDWA; 1702 using namespace AMDGPU::EncValues; 1703 1704 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1705 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1706 // XXX: cast to int is needed to avoid stupid warning: 1707 // compare with unsigned is always true 1708 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1709 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1710 return createRegOperand(getVgprClassId(Width), 1711 Val - SDWA9EncValues::SRC_VGPR_MIN); 1712 } 1713 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1714 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1715 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1716 return createSRegOperand(getSgprClassId(Width), 1717 Val - SDWA9EncValues::SRC_SGPR_MIN); 1718 } 1719 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1720 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1721 return createSRegOperand(getTtmpClassId(Width), 1722 Val - SDWA9EncValues::SRC_TTMP_MIN); 1723 } 1724 1725 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1726 1727 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1728 return decodeIntImmed(SVal); 1729 1730 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1731 return decodeFPImmed(ImmWidth, SVal); 1732 1733 return decodeSpecialReg32(SVal); 1734 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1735 return createRegOperand(getVgprClassId(Width), Val); 1736 } 1737 llvm_unreachable("unsupported target"); 1738 } 1739 1740 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1741 return decodeSDWASrc(OPW16, Val, 16); 1742 } 1743 1744 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1745 return decodeSDWASrc(OPW32, Val, 32); 1746 } 1747 1748 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1749 using namespace AMDGPU::SDWA; 1750 1751 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1752 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1753 "SDWAVopcDst should be present only on GFX9+"); 1754 1755 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1756 1757 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1758 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1759 1760 int TTmpIdx = getTTmpIdx(Val); 1761 if (TTmpIdx >= 0) { 1762 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1763 return createSRegOperand(TTmpClsId, TTmpIdx); 1764 } else if (Val > SGPR_MAX) { 1765 return IsWave64 ? decodeSpecialReg64(Val) 1766 : decodeSpecialReg32(Val); 1767 } else { 1768 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1769 } 1770 } else { 1771 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1772 } 1773 } 1774 1775 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1776 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1777 ? decodeSrcOp(OPW64, Val) 1778 : decodeSrcOp(OPW32, Val); 1779 } 1780 1781 MCOperand AMDGPUDisassembler::decodeSplitBarrier(unsigned Val) const { 1782 return decodeSrcOp(OPW32, Val); 1783 } 1784 1785 bool AMDGPUDisassembler::isVI() const { 1786 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1787 } 1788 1789 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1790 1791 bool AMDGPUDisassembler::isGFX90A() const { 1792 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1793 } 1794 1795 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1796 1797 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1798 1799 bool AMDGPUDisassembler::isGFX10Plus() const { 1800 return AMDGPU::isGFX10Plus(STI); 1801 } 1802 1803 bool AMDGPUDisassembler::isGFX11() const { 1804 return STI.hasFeature(AMDGPU::FeatureGFX11); 1805 } 1806 1807 bool AMDGPUDisassembler::isGFX11Plus() const { 1808 return AMDGPU::isGFX11Plus(STI); 1809 } 1810 1811 bool AMDGPUDisassembler::isGFX12Plus() const { 1812 return AMDGPU::isGFX12Plus(STI); 1813 } 1814 1815 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1816 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1817 } 1818 1819 bool AMDGPUDisassembler::hasKernargPreload() const { 1820 return AMDGPU::hasKernargPreload(STI); 1821 } 1822 1823 //===----------------------------------------------------------------------===// 1824 // AMDGPU specific symbol handling 1825 //===----------------------------------------------------------------------===// 1826 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1827 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1828 do { \ 1829 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1830 } while (0) 1831 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1832 do { \ 1833 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1834 << GET_FIELD(MASK) << '\n'; \ 1835 } while (0) 1836 1837 // NOLINTNEXTLINE(readability-identifier-naming) 1838 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1839 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1840 using namespace amdhsa; 1841 StringRef Indent = "\t"; 1842 1843 // We cannot accurately backward compute #VGPRs used from 1844 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1845 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1846 // simply calculate the inverse of what the assembler does. 1847 1848 uint32_t GranulatedWorkitemVGPRCount = 1849 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1850 1851 uint32_t NextFreeVGPR = 1852 (GranulatedWorkitemVGPRCount + 1) * 1853 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1854 1855 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1856 1857 // We cannot backward compute values used to calculate 1858 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1859 // directives can't be computed: 1860 // .amdhsa_reserve_vcc 1861 // .amdhsa_reserve_flat_scratch 1862 // .amdhsa_reserve_xnack_mask 1863 // They take their respective default values if not specified in the assembly. 1864 // 1865 // GRANULATED_WAVEFRONT_SGPR_COUNT 1866 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1867 // 1868 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1869 // are set to 0. So while disassembling we consider that: 1870 // 1871 // GRANULATED_WAVEFRONT_SGPR_COUNT 1872 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1873 // 1874 // The disassembler cannot recover the original values of those 3 directives. 1875 1876 uint32_t GranulatedWavefrontSGPRCount = 1877 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1878 1879 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1880 return MCDisassembler::Fail; 1881 1882 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1883 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1884 1885 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1886 if (!hasArchitectedFlatScratch()) 1887 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1888 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1889 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1890 1891 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1892 return MCDisassembler::Fail; 1893 1894 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1895 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1896 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1897 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1898 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1899 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1900 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1901 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1902 1903 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1904 return MCDisassembler::Fail; 1905 1906 if (!isGFX12Plus()) 1907 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", 1908 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP); 1909 1910 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1911 return MCDisassembler::Fail; 1912 1913 if (!isGFX12Plus()) 1914 PRINT_DIRECTIVE(".amdhsa_ieee_mode", 1915 COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE); 1916 1917 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1918 return MCDisassembler::Fail; 1919 1920 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1921 return MCDisassembler::Fail; 1922 1923 if (isGFX9Plus()) 1924 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1925 1926 if (!isGFX9Plus()) 1927 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1928 return MCDisassembler::Fail; 1929 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1930 return MCDisassembler::Fail; 1931 if (!isGFX10Plus()) 1932 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1933 return MCDisassembler::Fail; 1934 1935 if (isGFX10Plus()) { 1936 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1937 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1938 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1939 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1940 } 1941 1942 if (isGFX12Plus()) 1943 PRINT_DIRECTIVE(".amdhsa_round_robin_scheduling", 1944 COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN); 1945 1946 return MCDisassembler::Success; 1947 } 1948 1949 // NOLINTNEXTLINE(readability-identifier-naming) 1950 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1951 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1952 using namespace amdhsa; 1953 StringRef Indent = "\t"; 1954 if (hasArchitectedFlatScratch()) 1955 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1956 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1957 else 1958 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1959 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1960 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1961 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1962 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1963 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1964 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1965 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1966 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1967 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1968 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1969 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1970 1971 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1972 return MCDisassembler::Fail; 1973 1974 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1975 return MCDisassembler::Fail; 1976 1977 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1978 return MCDisassembler::Fail; 1979 1980 PRINT_DIRECTIVE( 1981 ".amdhsa_exception_fp_ieee_invalid_op", 1982 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1983 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1984 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1985 PRINT_DIRECTIVE( 1986 ".amdhsa_exception_fp_ieee_div_zero", 1987 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1988 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1989 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1990 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1991 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1992 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1993 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1994 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1995 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1996 1997 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1998 return MCDisassembler::Fail; 1999 2000 return MCDisassembler::Success; 2001 } 2002 2003 // NOLINTNEXTLINE(readability-identifier-naming) 2004 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 2005 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 2006 using namespace amdhsa; 2007 StringRef Indent = "\t"; 2008 if (isGFX90A()) { 2009 KdStream << Indent << ".amdhsa_accum_offset " 2010 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 2011 << '\n'; 2012 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 2013 return MCDisassembler::Fail; 2014 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 2015 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 2016 return MCDisassembler::Fail; 2017 } else if (isGFX10Plus()) { 2018 // Bits [0-3]. 2019 if (!isGFX12Plus()) { 2020 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 2021 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 2022 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2023 } else { 2024 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2025 "SHARED_VGPR_COUNT", 2026 COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT); 2027 } 2028 } else { 2029 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX12_PLUS_RESERVED0) 2030 return MCDisassembler::Fail; 2031 } 2032 2033 // Bits [4-11]. 2034 if (isGFX11()) { 2035 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 2036 COMPUTE_PGM_RSRC3_GFX11_INST_PREF_SIZE); 2037 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 2038 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_START); 2039 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 2040 COMPUTE_PGM_RSRC3_GFX11_TRAP_ON_END); 2041 } else if (isGFX12Plus()) { 2042 PRINT_PSEUDO_DIRECTIVE_COMMENT( 2043 "INST_PREF_SIZE", COMPUTE_PGM_RSRC3_GFX12_PLUS_INST_PREF_SIZE); 2044 } else { 2045 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED1) 2046 return MCDisassembler::Fail; 2047 } 2048 2049 // Bits [12]. 2050 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED2) 2051 return MCDisassembler::Fail; 2052 2053 // Bits [13]. 2054 if (isGFX12Plus()) { 2055 PRINT_PSEUDO_DIRECTIVE_COMMENT("GLG_EN", 2056 COMPUTE_PGM_RSRC3_GFX12_PLUS_GLG_EN); 2057 } else { 2058 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_GFX11_RESERVED3) 2059 return MCDisassembler::Fail; 2060 } 2061 2062 // Bits [14-30]. 2063 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED4) 2064 return MCDisassembler::Fail; 2065 2066 // Bits [31]. 2067 if (isGFX11Plus()) { 2068 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 2069 COMPUTE_PGM_RSRC3_GFX11_PLUS_IMAGE_OP); 2070 } else { 2071 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED5) 2072 return MCDisassembler::Fail; 2073 } 2074 } else if (FourByteBuffer) { 2075 return MCDisassembler::Fail; 2076 } 2077 return MCDisassembler::Success; 2078 } 2079 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 2080 #undef PRINT_DIRECTIVE 2081 #undef GET_FIELD 2082 2083 MCDisassembler::DecodeStatus 2084 AMDGPUDisassembler::decodeKernelDescriptorDirective( 2085 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 2086 raw_string_ostream &KdStream) const { 2087 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 2088 do { \ 2089 KdStream << Indent << DIRECTIVE " " \ 2090 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 2091 } while (0) 2092 2093 uint16_t TwoByteBuffer = 0; 2094 uint32_t FourByteBuffer = 0; 2095 2096 StringRef ReservedBytes; 2097 StringRef Indent = "\t"; 2098 2099 assert(Bytes.size() == 64); 2100 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 2101 2102 switch (Cursor.tell()) { 2103 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2104 FourByteBuffer = DE.getU32(Cursor); 2105 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2106 << '\n'; 2107 return MCDisassembler::Success; 2108 2109 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2110 FourByteBuffer = DE.getU32(Cursor); 2111 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2112 << FourByteBuffer << '\n'; 2113 return MCDisassembler::Success; 2114 2115 case amdhsa::KERNARG_SIZE_OFFSET: 2116 FourByteBuffer = DE.getU32(Cursor); 2117 KdStream << Indent << ".amdhsa_kernarg_size " 2118 << FourByteBuffer << '\n'; 2119 return MCDisassembler::Success; 2120 2121 case amdhsa::RESERVED0_OFFSET: 2122 // 4 reserved bytes, must be 0. 2123 ReservedBytes = DE.getBytes(Cursor, 4); 2124 for (int I = 0; I < 4; ++I) { 2125 if (ReservedBytes[I] != 0) { 2126 return MCDisassembler::Fail; 2127 } 2128 } 2129 return MCDisassembler::Success; 2130 2131 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2132 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2133 // So far no directive controls this for Code Object V3, so simply skip for 2134 // disassembly. 2135 DE.skip(Cursor, 8); 2136 return MCDisassembler::Success; 2137 2138 case amdhsa::RESERVED1_OFFSET: 2139 // 20 reserved bytes, must be 0. 2140 ReservedBytes = DE.getBytes(Cursor, 20); 2141 for (int I = 0; I < 20; ++I) { 2142 if (ReservedBytes[I] != 0) { 2143 return MCDisassembler::Fail; 2144 } 2145 } 2146 return MCDisassembler::Success; 2147 2148 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2149 FourByteBuffer = DE.getU32(Cursor); 2150 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2151 2152 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2153 FourByteBuffer = DE.getU32(Cursor); 2154 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2155 2156 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2157 FourByteBuffer = DE.getU32(Cursor); 2158 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2159 2160 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2161 using namespace amdhsa; 2162 TwoByteBuffer = DE.getU16(Cursor); 2163 2164 if (!hasArchitectedFlatScratch()) 2165 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2166 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2167 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2168 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2169 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2170 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2171 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2172 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2173 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2174 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2175 if (!hasArchitectedFlatScratch()) 2176 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2177 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2178 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2179 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2180 2181 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2182 return MCDisassembler::Fail; 2183 2184 // Reserved for GFX9 2185 if (isGFX9() && 2186 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2187 return MCDisassembler::Fail; 2188 } else if (isGFX10Plus()) { 2189 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2190 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2191 } 2192 2193 // FIXME: We should be looking at the ELF header ABI version for this. 2194 if (AMDGPU::getDefaultAMDHSACodeObjectVersion() >= AMDGPU::AMDHSA_COV5) 2195 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2196 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2197 2198 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2199 return MCDisassembler::Fail; 2200 2201 return MCDisassembler::Success; 2202 2203 case amdhsa::KERNARG_PRELOAD_OFFSET: 2204 using namespace amdhsa; 2205 TwoByteBuffer = DE.getU16(Cursor); 2206 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2207 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2208 KERNARG_PRELOAD_SPEC_LENGTH); 2209 } 2210 2211 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2212 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2213 KERNARG_PRELOAD_SPEC_OFFSET); 2214 } 2215 return MCDisassembler::Success; 2216 2217 case amdhsa::RESERVED3_OFFSET: 2218 // 4 bytes from here are reserved, must be 0. 2219 ReservedBytes = DE.getBytes(Cursor, 4); 2220 for (int I = 0; I < 4; ++I) { 2221 if (ReservedBytes[I] != 0) 2222 return MCDisassembler::Fail; 2223 } 2224 return MCDisassembler::Success; 2225 2226 default: 2227 llvm_unreachable("Unhandled index. Case statements cover everything."); 2228 return MCDisassembler::Fail; 2229 } 2230 #undef PRINT_DIRECTIVE 2231 } 2232 2233 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2234 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2235 // CP microcode requires the kernel descriptor to be 64 aligned. 2236 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2237 return MCDisassembler::Fail; 2238 2239 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2240 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2241 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2242 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2243 // when required. 2244 if (isGFX10Plus()) { 2245 uint16_t KernelCodeProperties = 2246 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2247 llvm::endianness::little); 2248 EnableWavefrontSize32 = 2249 AMDHSA_BITS_GET(KernelCodeProperties, 2250 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2251 } 2252 2253 std::string Kd; 2254 raw_string_ostream KdStream(Kd); 2255 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2256 2257 DataExtractor::Cursor C(0); 2258 while (C && C.tell() < Bytes.size()) { 2259 MCDisassembler::DecodeStatus Status = 2260 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2261 2262 cantFail(C.takeError()); 2263 2264 if (Status == MCDisassembler::Fail) 2265 return MCDisassembler::Fail; 2266 } 2267 KdStream << ".end_amdhsa_kernel\n"; 2268 outs() << KdStream.str(); 2269 return MCDisassembler::Success; 2270 } 2271 2272 std::optional<MCDisassembler::DecodeStatus> 2273 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2274 ArrayRef<uint8_t> Bytes, uint64_t Address, 2275 raw_ostream &CStream) const { 2276 // Right now only kernel descriptor needs to be handled. 2277 // We ignore all other symbols for target specific handling. 2278 // TODO: 2279 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2280 // Object V2 and V3 when symbols are marked protected. 2281 2282 // amd_kernel_code_t for Code Object V2. 2283 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2284 Size = 256; 2285 return MCDisassembler::Fail; 2286 } 2287 2288 // Code Object V3 kernel descriptors. 2289 StringRef Name = Symbol.Name; 2290 if (Symbol.Type == ELF::STT_OBJECT && Name.ends_with(StringRef(".kd"))) { 2291 Size = 64; // Size = 64 regardless of success or failure. 2292 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2293 } 2294 return std::nullopt; 2295 } 2296 2297 //===----------------------------------------------------------------------===// 2298 // AMDGPUSymbolizer 2299 //===----------------------------------------------------------------------===// 2300 2301 // Try to find symbol name for specified label 2302 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2303 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2304 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2305 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2306 2307 if (!IsBranch) { 2308 return false; 2309 } 2310 2311 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2312 if (!Symbols) 2313 return false; 2314 2315 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2316 return Val.Addr == static_cast<uint64_t>(Value) && 2317 Val.Type == ELF::STT_NOTYPE; 2318 }); 2319 if (Result != Symbols->end()) { 2320 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2321 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2322 Inst.addOperand(MCOperand::createExpr(Add)); 2323 return true; 2324 } 2325 // Add to list of referenced addresses, so caller can synthesize a label. 2326 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2327 return false; 2328 } 2329 2330 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2331 int64_t Value, 2332 uint64_t Address) { 2333 llvm_unreachable("unimplemented"); 2334 } 2335 2336 //===----------------------------------------------------------------------===// 2337 // Initialization 2338 //===----------------------------------------------------------------------===// 2339 2340 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2341 LLVMOpInfoCallback /*GetOpInfo*/, 2342 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2343 void *DisInfo, 2344 MCContext *Ctx, 2345 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2346 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2347 } 2348 2349 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2350 const MCSubtargetInfo &STI, 2351 MCContext &Ctx) { 2352 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2353 } 2354 2355 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2356 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2357 createAMDGPUDisassembler); 2358 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2359 createAMDGPUSymbolizer); 2360 } 2361