1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VGPR_32_Lo128) 123 DECODE_OPERAND_REG(VRegOrLds_32) 124 DECODE_OPERAND_REG(VS_32) 125 DECODE_OPERAND_REG(VS_64) 126 DECODE_OPERAND_REG(VS_128) 127 128 DECODE_OPERAND_REG(VReg_64) 129 DECODE_OPERAND_REG(VReg_96) 130 DECODE_OPERAND_REG(VReg_128) 131 DECODE_OPERAND_REG(VReg_256) 132 DECODE_OPERAND_REG(VReg_512) 133 DECODE_OPERAND_REG(VReg_1024) 134 135 DECODE_OPERAND_REG(SReg_32) 136 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 137 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 138 DECODE_OPERAND_REG(SRegOrLds_32) 139 DECODE_OPERAND_REG(SReg_64) 140 DECODE_OPERAND_REG(SReg_64_XEXEC) 141 DECODE_OPERAND_REG(SReg_128) 142 DECODE_OPERAND_REG(SReg_256) 143 DECODE_OPERAND_REG(SReg_512) 144 145 DECODE_OPERAND_REG(AGPR_32) 146 DECODE_OPERAND_REG(AReg_64) 147 DECODE_OPERAND_REG(AReg_128) 148 DECODE_OPERAND_REG(AReg_256) 149 DECODE_OPERAND_REG(AReg_512) 150 DECODE_OPERAND_REG(AReg_1024) 151 DECODE_OPERAND_REG(AV_32) 152 DECODE_OPERAND_REG(AV_64) 153 DECODE_OPERAND_REG(AV_128) 154 DECODE_OPERAND_REG(AVDst_128) 155 DECODE_OPERAND_REG(AVDst_512) 156 157 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 158 uint64_t Addr, 159 const MCDisassembler *Decoder) { 160 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 161 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 162 } 163 164 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 165 uint64_t Addr, 166 const MCDisassembler *Decoder) { 167 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 168 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 169 } 170 171 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 172 uint64_t Addr, 173 const MCDisassembler *Decoder) { 174 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 175 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 176 } 177 178 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 179 uint64_t Addr, 180 const MCDisassembler *Decoder) { 181 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 182 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 183 } 184 185 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 186 uint64_t Addr, 187 const MCDisassembler *Decoder) { 188 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 189 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 190 } 191 192 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 193 uint64_t Addr, 194 const MCDisassembler *Decoder) { 195 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 196 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 197 } 198 199 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 200 uint64_t Addr, 201 const MCDisassembler *Decoder) { 202 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 203 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 204 } 205 206 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 207 uint64_t Addr, 208 const MCDisassembler *Decoder) { 209 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 210 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 211 } 212 213 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 214 uint64_t Addr, 215 const MCDisassembler *Decoder) { 216 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 217 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 218 } 219 220 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 221 uint64_t Addr, 222 const MCDisassembler *Decoder) { 223 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 224 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 225 } 226 227 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 228 uint64_t Addr, 229 const MCDisassembler *Decoder) { 230 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 231 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 232 } 233 234 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 235 uint64_t Addr, 236 const MCDisassembler *Decoder) { 237 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 238 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 239 } 240 241 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 242 uint64_t Addr, 243 const MCDisassembler *Decoder) { 244 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 245 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 246 } 247 248 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 249 uint64_t Addr, 250 const MCDisassembler *Decoder) { 251 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 252 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 253 } 254 255 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 256 uint64_t Addr, 257 const MCDisassembler *Decoder) { 258 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 259 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 260 } 261 262 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 263 uint64_t Addr, 264 const MCDisassembler *Decoder) { 265 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 266 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 267 } 268 269 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 270 uint64_t Addr, 271 const MCDisassembler *Decoder) { 272 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 273 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 274 } 275 276 static DecodeStatus 277 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 278 const MCDisassembler *Decoder) { 279 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 280 return addOperand( 281 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 282 } 283 284 static DecodeStatus 285 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 286 const MCDisassembler *Decoder) { 287 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 288 return addOperand( 289 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 290 } 291 292 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 293 uint64_t Addr, const void *Decoder) { 294 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 295 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 296 } 297 298 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 299 const MCRegisterInfo *MRI) { 300 if (OpIdx < 0) 301 return false; 302 303 const MCOperand &Op = Inst.getOperand(OpIdx); 304 if (!Op.isReg()) 305 return false; 306 307 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 308 auto Reg = Sub ? Sub : Op.getReg(); 309 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 310 } 311 312 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 313 AMDGPUDisassembler::OpWidthTy Opw, 314 const MCDisassembler *Decoder) { 315 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 316 if (!DAsm->isGFX90A()) { 317 Imm &= 511; 318 } else { 319 // If atomic has both vdata and vdst their register classes are tied. 320 // The bit is decoded along with the vdst, first operand. We need to 321 // change register class to AGPR if vdst was AGPR. 322 // If a DS instruction has both data0 and data1 their register classes 323 // are also tied. 324 unsigned Opc = Inst.getOpcode(); 325 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 326 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 327 : AMDGPU::OpName::vdata; 328 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 329 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 330 if ((int)Inst.getNumOperands() == DataIdx) { 331 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 332 if (IsAGPROperand(Inst, DstIdx, MRI)) 333 Imm |= 512; 334 } 335 336 if (TSFlags & SIInstrFlags::DS) { 337 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 338 if ((int)Inst.getNumOperands() == Data2Idx && 339 IsAGPROperand(Inst, DataIdx, MRI)) 340 Imm |= 512; 341 } 342 } 343 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 344 } 345 346 static DecodeStatus 347 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 348 const MCDisassembler *Decoder) { 349 return decodeOperand_AVLdSt_Any(Inst, Imm, 350 AMDGPUDisassembler::OPW32, Decoder); 351 } 352 353 static DecodeStatus 354 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 355 const MCDisassembler *Decoder) { 356 return decodeOperand_AVLdSt_Any(Inst, Imm, 357 AMDGPUDisassembler::OPW64, Decoder); 358 } 359 360 static DecodeStatus 361 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 362 const MCDisassembler *Decoder) { 363 return decodeOperand_AVLdSt_Any(Inst, Imm, 364 AMDGPUDisassembler::OPW96, Decoder); 365 } 366 367 static DecodeStatus 368 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 369 const MCDisassembler *Decoder) { 370 return decodeOperand_AVLdSt_Any(Inst, Imm, 371 AMDGPUDisassembler::OPW128, Decoder); 372 } 373 374 static DecodeStatus 375 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 376 const MCDisassembler *Decoder) { 377 return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160, 378 Decoder); 379 } 380 381 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 382 uint64_t Addr, 383 const MCDisassembler *Decoder) { 384 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 385 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 386 } 387 388 #define DECODE_SDWA(DecName) \ 389 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 390 391 DECODE_SDWA(Src32) 392 DECODE_SDWA(Src16) 393 DECODE_SDWA(VopcDst) 394 395 #include "AMDGPUGenDisassemblerTables.inc" 396 397 //===----------------------------------------------------------------------===// 398 // 399 //===----------------------------------------------------------------------===// 400 401 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 402 assert(Bytes.size() >= sizeof(T)); 403 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 404 Bytes = Bytes.slice(sizeof(T)); 405 return Res; 406 } 407 408 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 409 assert(Bytes.size() >= 12); 410 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 411 Bytes.data()); 412 Bytes = Bytes.slice(8); 413 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 414 Bytes.data()); 415 Bytes = Bytes.slice(4); 416 return DecoderUInt128(Lo, Hi); 417 } 418 419 // The disassembler is greedy, so we need to check FI operand value to 420 // not parse a dpp if the correct literal is not set. For dpp16 the 421 // autogenerated decoder checks the dpp literal 422 static bool isValidDPP8(const MCInst &MI) { 423 using namespace llvm::AMDGPU::DPP; 424 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 425 assert(FiIdx != -1); 426 if ((unsigned)FiIdx >= MI.getNumOperands()) 427 return false; 428 unsigned Fi = MI.getOperand(FiIdx).getImm(); 429 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 430 } 431 432 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 433 ArrayRef<uint8_t> Bytes_, 434 uint64_t Address, 435 raw_ostream &CS) const { 436 CommentStream = &CS; 437 bool IsSDWA = false; 438 439 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 440 Bytes = Bytes_.slice(0, MaxInstBytesNum); 441 442 DecodeStatus Res = MCDisassembler::Fail; 443 do { 444 // ToDo: better to switch encoding length using some bit predicate 445 // but it is unknown yet, so try all we can 446 447 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 448 // encodings 449 if (isGFX11Plus() && Bytes.size() >= 12 ) { 450 DecoderUInt128 DecW = eat12Bytes(Bytes); 451 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 452 Address); 453 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 454 break; 455 MI = MCInst(); // clear 456 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 457 Address); 458 if (Res) { 459 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 460 convertVOP3PDPPInst(MI); 461 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 462 convertVOPCDPPInst(MI); // Special VOP3 case 463 else { 464 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 465 convertVOP3DPPInst(MI); // Regular VOP3 case 466 } 467 break; 468 } 469 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address); 470 if (Res) 471 break; 472 } 473 // Reinitialize Bytes 474 Bytes = Bytes_.slice(0, MaxInstBytesNum); 475 476 if (Bytes.size() >= 8) { 477 const uint64_t QW = eatBytes<uint64_t>(Bytes); 478 479 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 480 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 481 if (Res) { 482 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 483 == -1) 484 break; 485 if (convertDPP8Inst(MI) == MCDisassembler::Success) 486 break; 487 MI = MCInst(); // clear 488 } 489 } 490 491 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 492 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 493 break; 494 MI = MCInst(); // clear 495 496 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 497 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 498 break; 499 MI = MCInst(); // clear 500 501 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 502 if (Res) break; 503 504 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 505 if (Res) { 506 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 507 convertVOPCDPPInst(MI); 508 break; 509 } 510 511 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 512 if (Res) { IsSDWA = true; break; } 513 514 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 515 if (Res) { IsSDWA = true; break; } 516 517 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 518 if (Res) { IsSDWA = true; break; } 519 520 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 521 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 522 if (Res) 523 break; 524 } 525 526 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 527 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 528 // table first so we print the correct name. 529 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 530 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 531 if (Res) 532 break; 533 } 534 } 535 536 // Reinitialize Bytes as DPP64 could have eaten too much 537 Bytes = Bytes_.slice(0, MaxInstBytesNum); 538 539 // Try decode 32-bit instruction 540 if (Bytes.size() < 4) break; 541 const uint32_t DW = eatBytes<uint32_t>(Bytes); 542 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 543 if (Res) break; 544 545 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 546 if (Res) break; 547 548 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 549 if (Res) break; 550 551 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 552 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 553 if (Res) 554 break; 555 } 556 557 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 558 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 559 if (Res) break; 560 } 561 562 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 563 if (Res) break; 564 565 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 566 if (Res) break; 567 568 if (Bytes.size() < 4) break; 569 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 570 571 if (STI.getFeatureBits()[AMDGPU::FeatureGFX940Insts]) { 572 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address); 573 if (Res) 574 break; 575 } 576 577 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 578 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 579 if (Res) 580 break; 581 } 582 583 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 584 if (Res) break; 585 586 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 587 if (Res) break; 588 589 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 590 if (Res) break; 591 592 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 593 if (Res) break; 594 595 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 596 if (Res) 597 break; 598 599 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address); 600 } while (false); 601 602 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 603 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 604 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 605 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 606 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 607 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 608 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 609 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 610 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 611 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 || 612 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 613 MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || 614 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 || 615 MI.getOpcode() == AMDGPU::V_FMAC_F16_t16_e64_gfx11)) { 616 // Insert dummy unused src2_modifiers. 617 insertNamedMCOperand(MI, MCOperand::createImm(0), 618 AMDGPU::OpName::src2_modifiers); 619 } 620 621 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 622 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 623 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 624 AMDGPU::OpName::cpol); 625 if (CPolPos != -1) { 626 unsigned CPol = 627 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 628 AMDGPU::CPol::GLC : 0; 629 if (MI.getNumOperands() <= (unsigned)CPolPos) { 630 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 631 AMDGPU::OpName::cpol); 632 } else if (CPol) { 633 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 634 } 635 } 636 } 637 638 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 639 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 640 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 641 // GFX90A lost TFE, its place is occupied by ACC. 642 int TFEOpIdx = 643 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 644 if (TFEOpIdx != -1) { 645 auto TFEIter = MI.begin(); 646 std::advance(TFEIter, TFEOpIdx); 647 MI.insert(TFEIter, MCOperand::createImm(0)); 648 } 649 } 650 651 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 652 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 653 int SWZOpIdx = 654 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 655 if (SWZOpIdx != -1) { 656 auto SWZIter = MI.begin(); 657 std::advance(SWZIter, SWZOpIdx); 658 MI.insert(SWZIter, MCOperand::createImm(0)); 659 } 660 } 661 662 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 663 int VAddr0Idx = 664 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 665 int RsrcIdx = 666 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 667 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 668 if (VAddr0Idx >= 0 && NSAArgs > 0) { 669 unsigned NSAWords = (NSAArgs + 3) / 4; 670 if (Bytes.size() < 4 * NSAWords) { 671 Res = MCDisassembler::Fail; 672 } else { 673 for (unsigned i = 0; i < NSAArgs; ++i) { 674 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 675 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 676 MI.insert(MI.begin() + VAddrIdx, 677 createRegOperand(VAddrRCID, Bytes[i])); 678 } 679 Bytes = Bytes.slice(4 * NSAWords); 680 } 681 } 682 683 if (Res) 684 Res = convertMIMGInst(MI); 685 } 686 687 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 688 Res = convertEXPInst(MI); 689 690 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 691 Res = convertVINTERPInst(MI); 692 693 if (Res && IsSDWA) 694 Res = convertSDWAInst(MI); 695 696 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 697 AMDGPU::OpName::vdst_in); 698 if (VDstIn_Idx != -1) { 699 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 700 MCOI::OperandConstraint::TIED_TO); 701 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 702 !MI.getOperand(VDstIn_Idx).isReg() || 703 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 704 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 705 MI.erase(&MI.getOperand(VDstIn_Idx)); 706 insertNamedMCOperand(MI, 707 MCOperand::createReg(MI.getOperand(Tied).getReg()), 708 AMDGPU::OpName::vdst_in); 709 } 710 } 711 712 int ImmLitIdx = 713 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 714 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 715 if (Res && ImmLitIdx != -1 && !IsSOPK) 716 Res = convertFMAanyK(MI, ImmLitIdx); 717 718 // if the opcode was not recognized we'll assume a Size of 4 bytes 719 // (unless there are fewer bytes left) 720 Size = Res ? (MaxInstBytesNum - Bytes.size()) 721 : std::min((size_t)4, Bytes_.size()); 722 return Res; 723 } 724 725 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 726 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 727 // The MCInst still has these fields even though they are no longer encoded 728 // in the GFX11 instruction. 729 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 730 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 731 } 732 return MCDisassembler::Success; 733 } 734 735 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 736 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 737 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 738 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 739 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 740 // The MCInst has this field that is not directly encoded in the 741 // instruction. 742 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 743 } 744 return MCDisassembler::Success; 745 } 746 747 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 748 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 749 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 750 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 751 // VOPC - insert clamp 752 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 753 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 754 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 755 if (SDst != -1) { 756 // VOPC - insert VCC register as sdst 757 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 758 AMDGPU::OpName::sdst); 759 } else { 760 // VOP1/2 - insert omod if present in instruction 761 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 762 } 763 } 764 return MCDisassembler::Success; 765 } 766 767 struct VOPModifiers { 768 unsigned OpSel = 0; 769 unsigned OpSelHi = 0; 770 unsigned NegLo = 0; 771 unsigned NegHi = 0; 772 }; 773 774 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 775 // Note that these values do not affect disassembler output, 776 // so this is only necessary for consistency with src_modifiers. 777 static VOPModifiers collectVOPModifiers(const MCInst &MI, 778 bool IsVOP3P = false) { 779 VOPModifiers Modifiers; 780 unsigned Opc = MI.getOpcode(); 781 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 782 AMDGPU::OpName::src1_modifiers, 783 AMDGPU::OpName::src2_modifiers}; 784 for (int J = 0; J < 3; ++J) { 785 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 786 if (OpIdx == -1) 787 continue; 788 789 unsigned Val = MI.getOperand(OpIdx).getImm(); 790 791 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 792 if (IsVOP3P) { 793 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 794 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 795 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 796 } else if (J == 0) { 797 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 798 } 799 } 800 801 return Modifiers; 802 } 803 804 // MAC opcodes have special old and src2 operands. 805 // src2 is tied to dst, while old is not tied (but assumed to be). 806 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 807 constexpr int DST_IDX = 0; 808 auto Opcode = MI.getOpcode(); 809 const auto &Desc = MCII->get(Opcode); 810 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 811 812 if (OldIdx != -1 && Desc.getOperandConstraint( 813 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 814 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 815 assert(Desc.getOperandConstraint( 816 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 817 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 818 (void)DST_IDX; 819 return true; 820 } 821 822 return false; 823 } 824 825 // Create dummy old operand and insert dummy unused src2_modifiers 826 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 827 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 828 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 829 insertNamedMCOperand(MI, MCOperand::createImm(0), 830 AMDGPU::OpName::src2_modifiers); 831 } 832 833 // We must check FI == literal to reject not genuine dpp8 insts, and we must 834 // first add optional MI operands to check FI 835 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 836 unsigned Opc = MI.getOpcode(); 837 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 838 convertVOP3PDPPInst(MI); 839 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 840 AMDGPU::isVOPC64DPP(Opc)) { 841 convertVOPCDPPInst(MI); 842 } else { 843 if (isMacDPP(MI)) 844 convertMacDPPInst(MI); 845 846 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 847 if (MI.getNumOperands() < DescNumOps && 848 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 849 auto Mods = collectVOPModifiers(MI); 850 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 851 AMDGPU::OpName::op_sel); 852 } else { 853 // Insert dummy unused src modifiers. 854 if (MI.getNumOperands() < DescNumOps && 855 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 856 insertNamedMCOperand(MI, MCOperand::createImm(0), 857 AMDGPU::OpName::src0_modifiers); 858 859 if (MI.getNumOperands() < DescNumOps && 860 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 861 insertNamedMCOperand(MI, MCOperand::createImm(0), 862 AMDGPU::OpName::src1_modifiers); 863 } 864 } 865 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 866 } 867 868 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 869 if (isMacDPP(MI)) 870 convertMacDPPInst(MI); 871 872 unsigned Opc = MI.getOpcode(); 873 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 874 if (MI.getNumOperands() < DescNumOps && 875 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 876 auto Mods = collectVOPModifiers(MI); 877 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 878 AMDGPU::OpName::op_sel); 879 } 880 return MCDisassembler::Success; 881 } 882 883 // Note that before gfx10, the MIMG encoding provided no information about 884 // VADDR size. Consequently, decoded instructions always show address as if it 885 // has 1 dword, which could be not really so. 886 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 887 888 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 889 AMDGPU::OpName::vdst); 890 891 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 892 AMDGPU::OpName::vdata); 893 int VAddr0Idx = 894 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 895 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 896 AMDGPU::OpName::dmask); 897 898 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 899 AMDGPU::OpName::tfe); 900 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 901 AMDGPU::OpName::d16); 902 903 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 904 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 905 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 906 907 assert(VDataIdx != -1); 908 if (BaseOpcode->BVH) { 909 // Add A16 operand for intersect_ray instructions 910 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::a16)) 911 addOperand(MI, MCOperand::createImm(1)); 912 return MCDisassembler::Success; 913 } 914 915 bool IsAtomic = (VDstIdx != -1); 916 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 917 bool IsNSA = false; 918 unsigned AddrSize = Info->VAddrDwords; 919 920 if (isGFX10Plus()) { 921 unsigned DimIdx = 922 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 923 int A16Idx = 924 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 925 const AMDGPU::MIMGDimInfo *Dim = 926 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 927 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 928 929 AddrSize = 930 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 931 932 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 933 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 934 if (!IsNSA) { 935 if (AddrSize > 8) 936 AddrSize = 16; 937 } else { 938 if (AddrSize > Info->VAddrDwords) { 939 // The NSA encoding does not contain enough operands for the combination 940 // of base opcode / dimension. Should this be an error? 941 return MCDisassembler::Success; 942 } 943 } 944 } 945 946 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 947 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 948 949 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 950 if (D16 && AMDGPU::hasPackedD16(STI)) { 951 DstSize = (DstSize + 1) / 2; 952 } 953 954 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 955 DstSize += 1; 956 957 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 958 return MCDisassembler::Success; 959 960 int NewOpcode = 961 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 962 if (NewOpcode == -1) 963 return MCDisassembler::Success; 964 965 // Widen the register to the correct number of enabled channels. 966 unsigned NewVdata = AMDGPU::NoRegister; 967 if (DstSize != Info->VDataDwords) { 968 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 969 970 // Get first subregister of VData 971 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 972 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 973 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 974 975 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 976 &MRI.getRegClass(DataRCID)); 977 if (NewVdata == AMDGPU::NoRegister) { 978 // It's possible to encode this such that the low register + enabled 979 // components exceeds the register count. 980 return MCDisassembler::Success; 981 } 982 } 983 984 // If not using NSA on GFX10+, widen address register to correct size. 985 unsigned NewVAddr0 = AMDGPU::NoRegister; 986 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 987 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 988 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 989 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 990 991 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 992 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 993 &MRI.getRegClass(AddrRCID)); 994 if (NewVAddr0 == AMDGPU::NoRegister) 995 return MCDisassembler::Success; 996 } 997 998 MI.setOpcode(NewOpcode); 999 1000 if (NewVdata != AMDGPU::NoRegister) { 1001 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1002 1003 if (IsAtomic) { 1004 // Atomic operations have an additional operand (a copy of data) 1005 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1006 } 1007 } 1008 1009 if (NewVAddr0 != AMDGPU::NoRegister) { 1010 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 1011 } else if (IsNSA) { 1012 assert(AddrSize <= Info->VAddrDwords); 1013 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1014 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1015 } 1016 1017 return MCDisassembler::Success; 1018 } 1019 1020 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1021 // decoder only adds to src_modifiers, so manually add the bits to the other 1022 // operands. 1023 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1024 unsigned Opc = MI.getOpcode(); 1025 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1026 auto Mods = collectVOPModifiers(MI, true); 1027 1028 if (MI.getNumOperands() < DescNumOps && 1029 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1030 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1031 1032 if (MI.getNumOperands() < DescNumOps && 1033 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1034 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1035 AMDGPU::OpName::op_sel); 1036 if (MI.getNumOperands() < DescNumOps && 1037 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1038 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1039 AMDGPU::OpName::op_sel_hi); 1040 if (MI.getNumOperands() < DescNumOps && 1041 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1042 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1043 AMDGPU::OpName::neg_lo); 1044 if (MI.getNumOperands() < DescNumOps && 1045 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1046 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1047 AMDGPU::OpName::neg_hi); 1048 1049 return MCDisassembler::Success; 1050 } 1051 1052 // Create dummy old operand and insert optional operands 1053 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1054 unsigned Opc = MI.getOpcode(); 1055 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1056 1057 if (MI.getNumOperands() < DescNumOps && 1058 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1059 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1060 1061 if (MI.getNumOperands() < DescNumOps && 1062 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1063 insertNamedMCOperand(MI, MCOperand::createImm(0), 1064 AMDGPU::OpName::src0_modifiers); 1065 1066 if (MI.getNumOperands() < DescNumOps && 1067 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1068 insertNamedMCOperand(MI, MCOperand::createImm(0), 1069 AMDGPU::OpName::src1_modifiers); 1070 return MCDisassembler::Success; 1071 } 1072 1073 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1074 int ImmLitIdx) const { 1075 assert(HasLiteral && "Should have decoded a literal"); 1076 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1077 unsigned DescNumOps = Desc.getNumOperands(); 1078 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1079 AMDGPU::OpName::immDeferred); 1080 assert(DescNumOps == MI.getNumOperands()); 1081 for (unsigned I = 0; I < DescNumOps; ++I) { 1082 auto &Op = MI.getOperand(I); 1083 auto OpType = Desc.OpInfo[I].OperandType; 1084 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1085 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1086 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1087 IsDeferredOp) 1088 Op.setImm(Literal); 1089 } 1090 return MCDisassembler::Success; 1091 } 1092 1093 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1094 return getContext().getRegisterInfo()-> 1095 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1096 } 1097 1098 inline 1099 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1100 const Twine& ErrMsg) const { 1101 *CommentStream << "Error: " + ErrMsg; 1102 1103 // ToDo: add support for error operands to MCInst.h 1104 // return MCOperand::createError(V); 1105 return MCOperand(); 1106 } 1107 1108 inline 1109 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1110 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1111 } 1112 1113 inline 1114 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1115 unsigned Val) const { 1116 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1117 if (Val >= RegCl.getNumRegs()) 1118 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1119 ": unknown register " + Twine(Val)); 1120 return createRegOperand(RegCl.getRegister(Val)); 1121 } 1122 1123 inline 1124 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1125 unsigned Val) const { 1126 // ToDo: SI/CI have 104 SGPRs, VI - 102 1127 // Valery: here we accepting as much as we can, let assembler sort it out 1128 int shift = 0; 1129 switch (SRegClassID) { 1130 case AMDGPU::SGPR_32RegClassID: 1131 case AMDGPU::TTMP_32RegClassID: 1132 break; 1133 case AMDGPU::SGPR_64RegClassID: 1134 case AMDGPU::TTMP_64RegClassID: 1135 shift = 1; 1136 break; 1137 case AMDGPU::SGPR_128RegClassID: 1138 case AMDGPU::TTMP_128RegClassID: 1139 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1140 // this bundle? 1141 case AMDGPU::SGPR_256RegClassID: 1142 case AMDGPU::TTMP_256RegClassID: 1143 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1144 // this bundle? 1145 case AMDGPU::SGPR_512RegClassID: 1146 case AMDGPU::TTMP_512RegClassID: 1147 shift = 2; 1148 break; 1149 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1150 // this bundle? 1151 default: 1152 llvm_unreachable("unhandled register class"); 1153 } 1154 1155 if (Val % (1 << shift)) { 1156 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1157 << ": scalar reg isn't aligned " << Val; 1158 } 1159 1160 return createRegOperand(SRegClassID, Val >> shift); 1161 } 1162 1163 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 1164 return decodeSrcOp(OPW32, Val); 1165 } 1166 1167 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 1168 return decodeSrcOp(OPW64, Val); 1169 } 1170 1171 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 1172 return decodeSrcOp(OPW128, Val); 1173 } 1174 1175 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 1176 return decodeSrcOp(OPW16, Val); 1177 } 1178 1179 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 1180 return decodeSrcOp(OPWV216, Val); 1181 } 1182 1183 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 1184 return decodeSrcOp(OPWV232, Val); 1185 } 1186 1187 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32_Lo128(unsigned Val) const { 1188 return createRegOperand(AMDGPU::VGPR_32_Lo128RegClassID, Val); 1189 } 1190 1191 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 1192 // Some instructions have operand restrictions beyond what the encoding 1193 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1194 // high bit. 1195 Val &= 255; 1196 1197 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1198 } 1199 1200 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1201 return decodeSrcOp(OPW32, Val); 1202 } 1203 1204 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1205 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1206 } 1207 1208 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1209 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1210 } 1211 1212 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1213 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1214 } 1215 1216 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1217 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1218 } 1219 1220 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1221 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1222 } 1223 1224 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1225 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1226 } 1227 1228 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1229 return decodeSrcOp(OPW32, Val); 1230 } 1231 1232 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1233 return decodeSrcOp(OPW64, Val); 1234 } 1235 1236 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1237 return decodeSrcOp(OPW128, Val); 1238 } 1239 1240 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1241 using namespace AMDGPU::EncValues; 1242 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1243 return decodeSrcOp(OPW128, Val | IS_VGPR); 1244 } 1245 1246 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1247 using namespace AMDGPU::EncValues; 1248 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1249 return decodeSrcOp(OPW512, Val | IS_VGPR); 1250 } 1251 1252 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1253 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1254 } 1255 1256 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1257 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1258 } 1259 1260 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1261 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1262 } 1263 1264 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1265 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1266 } 1267 1268 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1269 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1270 } 1271 1272 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1273 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1274 } 1275 1276 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1277 // table-gen generated disassembler doesn't care about operand types 1278 // leaving only registry class so SSrc_32 operand turns into SReg_32 1279 // and therefore we accept immediates and literals here as well 1280 return decodeSrcOp(OPW32, Val); 1281 } 1282 1283 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1284 unsigned Val) const { 1285 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1286 return decodeOperand_SReg_32(Val); 1287 } 1288 1289 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1290 unsigned Val) const { 1291 // SReg_32_XM0 is SReg_32 without EXEC_HI 1292 return decodeOperand_SReg_32(Val); 1293 } 1294 1295 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1296 // table-gen generated disassembler doesn't care about operand types 1297 // leaving only registry class so SSrc_32 operand turns into SReg_32 1298 // and therefore we accept immediates and literals here as well 1299 return decodeSrcOp(OPW32, Val); 1300 } 1301 1302 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1303 return decodeSrcOp(OPW64, Val); 1304 } 1305 1306 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1307 return decodeSrcOp(OPW64, Val); 1308 } 1309 1310 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1311 return decodeSrcOp(OPW128, Val); 1312 } 1313 1314 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1315 return decodeDstOp(OPW256, Val); 1316 } 1317 1318 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1319 return decodeDstOp(OPW512, Val); 1320 } 1321 1322 // Decode Literals for insts which always have a literal in the encoding 1323 MCOperand 1324 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1325 if (HasLiteral) { 1326 assert( 1327 AMDGPU::hasVOPD(STI) && 1328 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1329 if (Literal != Val) 1330 return errOperand(Val, "More than one unique literal is illegal"); 1331 } 1332 HasLiteral = true; 1333 Literal = Val; 1334 return MCOperand::createImm(Literal); 1335 } 1336 1337 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1338 // For now all literal constants are supposed to be unsigned integer 1339 // ToDo: deal with signed/unsigned 64-bit integer constants 1340 // ToDo: deal with float/double constants 1341 if (!HasLiteral) { 1342 if (Bytes.size() < 4) { 1343 return errOperand(0, "cannot read literal, inst bytes left " + 1344 Twine(Bytes.size())); 1345 } 1346 HasLiteral = true; 1347 Literal = eatBytes<uint32_t>(Bytes); 1348 } 1349 return MCOperand::createImm(Literal); 1350 } 1351 1352 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1353 using namespace AMDGPU::EncValues; 1354 1355 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1356 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1357 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1358 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1359 // Cast prevents negative overflow. 1360 } 1361 1362 static int64_t getInlineImmVal32(unsigned Imm) { 1363 switch (Imm) { 1364 case 240: 1365 return FloatToBits(0.5f); 1366 case 241: 1367 return FloatToBits(-0.5f); 1368 case 242: 1369 return FloatToBits(1.0f); 1370 case 243: 1371 return FloatToBits(-1.0f); 1372 case 244: 1373 return FloatToBits(2.0f); 1374 case 245: 1375 return FloatToBits(-2.0f); 1376 case 246: 1377 return FloatToBits(4.0f); 1378 case 247: 1379 return FloatToBits(-4.0f); 1380 case 248: // 1 / (2 * PI) 1381 return 0x3e22f983; 1382 default: 1383 llvm_unreachable("invalid fp inline imm"); 1384 } 1385 } 1386 1387 static int64_t getInlineImmVal64(unsigned Imm) { 1388 switch (Imm) { 1389 case 240: 1390 return DoubleToBits(0.5); 1391 case 241: 1392 return DoubleToBits(-0.5); 1393 case 242: 1394 return DoubleToBits(1.0); 1395 case 243: 1396 return DoubleToBits(-1.0); 1397 case 244: 1398 return DoubleToBits(2.0); 1399 case 245: 1400 return DoubleToBits(-2.0); 1401 case 246: 1402 return DoubleToBits(4.0); 1403 case 247: 1404 return DoubleToBits(-4.0); 1405 case 248: // 1 / (2 * PI) 1406 return 0x3fc45f306dc9c882; 1407 default: 1408 llvm_unreachable("invalid fp inline imm"); 1409 } 1410 } 1411 1412 static int64_t getInlineImmVal16(unsigned Imm) { 1413 switch (Imm) { 1414 case 240: 1415 return 0x3800; 1416 case 241: 1417 return 0xB800; 1418 case 242: 1419 return 0x3C00; 1420 case 243: 1421 return 0xBC00; 1422 case 244: 1423 return 0x4000; 1424 case 245: 1425 return 0xC000; 1426 case 246: 1427 return 0x4400; 1428 case 247: 1429 return 0xC400; 1430 case 248: // 1 / (2 * PI) 1431 return 0x3118; 1432 default: 1433 llvm_unreachable("invalid fp inline imm"); 1434 } 1435 } 1436 1437 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1438 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1439 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1440 1441 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1442 switch (Width) { 1443 case OPW32: 1444 case OPW128: // splat constants 1445 case OPW512: 1446 case OPW1024: 1447 case OPWV232: 1448 return MCOperand::createImm(getInlineImmVal32(Imm)); 1449 case OPW64: 1450 case OPW256: 1451 return MCOperand::createImm(getInlineImmVal64(Imm)); 1452 case OPW16: 1453 case OPWV216: 1454 return MCOperand::createImm(getInlineImmVal16(Imm)); 1455 default: 1456 llvm_unreachable("implement me"); 1457 } 1458 } 1459 1460 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1461 using namespace AMDGPU; 1462 1463 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1464 switch (Width) { 1465 default: // fall 1466 case OPW32: 1467 case OPW16: 1468 case OPWV216: 1469 return VGPR_32RegClassID; 1470 case OPW64: 1471 case OPWV232: return VReg_64RegClassID; 1472 case OPW96: return VReg_96RegClassID; 1473 case OPW128: return VReg_128RegClassID; 1474 case OPW160: return VReg_160RegClassID; 1475 case OPW256: return VReg_256RegClassID; 1476 case OPW512: return VReg_512RegClassID; 1477 case OPW1024: return VReg_1024RegClassID; 1478 } 1479 } 1480 1481 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1482 using namespace AMDGPU; 1483 1484 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1485 switch (Width) { 1486 default: // fall 1487 case OPW32: 1488 case OPW16: 1489 case OPWV216: 1490 return AGPR_32RegClassID; 1491 case OPW64: 1492 case OPWV232: return AReg_64RegClassID; 1493 case OPW96: return AReg_96RegClassID; 1494 case OPW128: return AReg_128RegClassID; 1495 case OPW160: return AReg_160RegClassID; 1496 case OPW256: return AReg_256RegClassID; 1497 case OPW512: return AReg_512RegClassID; 1498 case OPW1024: return AReg_1024RegClassID; 1499 } 1500 } 1501 1502 1503 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1504 using namespace AMDGPU; 1505 1506 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1507 switch (Width) { 1508 default: // fall 1509 case OPW32: 1510 case OPW16: 1511 case OPWV216: 1512 return SGPR_32RegClassID; 1513 case OPW64: 1514 case OPWV232: return SGPR_64RegClassID; 1515 case OPW96: return SGPR_96RegClassID; 1516 case OPW128: return SGPR_128RegClassID; 1517 case OPW160: return SGPR_160RegClassID; 1518 case OPW256: return SGPR_256RegClassID; 1519 case OPW512: return SGPR_512RegClassID; 1520 } 1521 } 1522 1523 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1524 using namespace AMDGPU; 1525 1526 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1527 switch (Width) { 1528 default: // fall 1529 case OPW32: 1530 case OPW16: 1531 case OPWV216: 1532 return TTMP_32RegClassID; 1533 case OPW64: 1534 case OPWV232: return TTMP_64RegClassID; 1535 case OPW128: return TTMP_128RegClassID; 1536 case OPW256: return TTMP_256RegClassID; 1537 case OPW512: return TTMP_512RegClassID; 1538 } 1539 } 1540 1541 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1542 using namespace AMDGPU::EncValues; 1543 1544 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1545 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1546 1547 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1548 } 1549 1550 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1551 bool MandatoryLiteral) const { 1552 using namespace AMDGPU::EncValues; 1553 1554 assert(Val < 1024); // enum10 1555 1556 bool IsAGPR = Val & 512; 1557 Val &= 511; 1558 1559 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1560 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1561 : getVgprClassId(Width), Val - VGPR_MIN); 1562 } 1563 if (Val <= SGPR_MAX) { 1564 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1565 static_assert(SGPR_MIN == 0); 1566 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1567 } 1568 1569 int TTmpIdx = getTTmpIdx(Val); 1570 if (TTmpIdx >= 0) { 1571 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1572 } 1573 1574 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1575 return decodeIntImmed(Val); 1576 1577 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1578 return decodeFPImmed(Width, Val); 1579 1580 if (Val == LITERAL_CONST) { 1581 if (MandatoryLiteral) 1582 // Keep a sentinel value for deferred setting 1583 return MCOperand::createImm(LITERAL_CONST); 1584 else 1585 return decodeLiteralConstant(); 1586 } 1587 1588 switch (Width) { 1589 case OPW32: 1590 case OPW16: 1591 case OPWV216: 1592 return decodeSpecialReg32(Val); 1593 case OPW64: 1594 case OPWV232: 1595 return decodeSpecialReg64(Val); 1596 default: 1597 llvm_unreachable("unexpected immediate type"); 1598 } 1599 } 1600 1601 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1602 using namespace AMDGPU::EncValues; 1603 1604 assert(Val < 128); 1605 assert(Width == OPW256 || Width == OPW512); 1606 1607 if (Val <= SGPR_MAX) { 1608 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1609 static_assert(SGPR_MIN == 0); 1610 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1611 } 1612 1613 int TTmpIdx = getTTmpIdx(Val); 1614 if (TTmpIdx >= 0) { 1615 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1616 } 1617 1618 llvm_unreachable("unknown dst register"); 1619 } 1620 1621 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1622 // opposite of bit 0 of DstX. 1623 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1624 unsigned Val) const { 1625 int VDstXInd = 1626 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1627 assert(VDstXInd != -1); 1628 assert(Inst.getOperand(VDstXInd).isReg()); 1629 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1630 Val |= ~XDstReg & 1; 1631 auto Width = llvm::AMDGPUDisassembler::OPW32; 1632 return createRegOperand(getVgprClassId(Width), Val); 1633 } 1634 1635 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1636 using namespace AMDGPU; 1637 1638 switch (Val) { 1639 // clang-format off 1640 case 102: return createRegOperand(FLAT_SCR_LO); 1641 case 103: return createRegOperand(FLAT_SCR_HI); 1642 case 104: return createRegOperand(XNACK_MASK_LO); 1643 case 105: return createRegOperand(XNACK_MASK_HI); 1644 case 106: return createRegOperand(VCC_LO); 1645 case 107: return createRegOperand(VCC_HI); 1646 case 108: return createRegOperand(TBA_LO); 1647 case 109: return createRegOperand(TBA_HI); 1648 case 110: return createRegOperand(TMA_LO); 1649 case 111: return createRegOperand(TMA_HI); 1650 case 124: 1651 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1652 case 125: 1653 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1654 case 126: return createRegOperand(EXEC_LO); 1655 case 127: return createRegOperand(EXEC_HI); 1656 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1657 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1658 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1659 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1660 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1661 case 251: return createRegOperand(SRC_VCCZ); 1662 case 252: return createRegOperand(SRC_EXECZ); 1663 case 253: return createRegOperand(SRC_SCC); 1664 case 254: return createRegOperand(LDS_DIRECT); 1665 default: break; 1666 // clang-format on 1667 } 1668 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1669 } 1670 1671 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1672 using namespace AMDGPU; 1673 1674 switch (Val) { 1675 case 102: return createRegOperand(FLAT_SCR); 1676 case 104: return createRegOperand(XNACK_MASK); 1677 case 106: return createRegOperand(VCC); 1678 case 108: return createRegOperand(TBA); 1679 case 110: return createRegOperand(TMA); 1680 case 124: 1681 if (isGFX11Plus()) 1682 return createRegOperand(SGPR_NULL); 1683 break; 1684 case 125: 1685 if (!isGFX11Plus()) 1686 return createRegOperand(SGPR_NULL); 1687 break; 1688 case 126: return createRegOperand(EXEC); 1689 case 235: return createRegOperand(SRC_SHARED_BASE); 1690 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1691 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1692 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1693 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1694 case 251: return createRegOperand(SRC_VCCZ); 1695 case 252: return createRegOperand(SRC_EXECZ); 1696 case 253: return createRegOperand(SRC_SCC); 1697 default: break; 1698 } 1699 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1700 } 1701 1702 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1703 const unsigned Val) const { 1704 using namespace AMDGPU::SDWA; 1705 using namespace AMDGPU::EncValues; 1706 1707 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1708 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1709 // XXX: cast to int is needed to avoid stupid warning: 1710 // compare with unsigned is always true 1711 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1712 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1713 return createRegOperand(getVgprClassId(Width), 1714 Val - SDWA9EncValues::SRC_VGPR_MIN); 1715 } 1716 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1717 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1718 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1719 return createSRegOperand(getSgprClassId(Width), 1720 Val - SDWA9EncValues::SRC_SGPR_MIN); 1721 } 1722 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1723 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1724 return createSRegOperand(getTtmpClassId(Width), 1725 Val - SDWA9EncValues::SRC_TTMP_MIN); 1726 } 1727 1728 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1729 1730 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1731 return decodeIntImmed(SVal); 1732 1733 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1734 return decodeFPImmed(Width, SVal); 1735 1736 return decodeSpecialReg32(SVal); 1737 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1738 return createRegOperand(getVgprClassId(Width), Val); 1739 } 1740 llvm_unreachable("unsupported target"); 1741 } 1742 1743 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1744 return decodeSDWASrc(OPW16, Val); 1745 } 1746 1747 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1748 return decodeSDWASrc(OPW32, Val); 1749 } 1750 1751 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1752 using namespace AMDGPU::SDWA; 1753 1754 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1755 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1756 "SDWAVopcDst should be present only on GFX9+"); 1757 1758 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1759 1760 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1761 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1762 1763 int TTmpIdx = getTTmpIdx(Val); 1764 if (TTmpIdx >= 0) { 1765 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1766 return createSRegOperand(TTmpClsId, TTmpIdx); 1767 } else if (Val > SGPR_MAX) { 1768 return IsWave64 ? decodeSpecialReg64(Val) 1769 : decodeSpecialReg32(Val); 1770 } else { 1771 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1772 } 1773 } else { 1774 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1775 } 1776 } 1777 1778 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1779 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1780 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1781 } 1782 1783 bool AMDGPUDisassembler::isVI() const { 1784 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1785 } 1786 1787 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1788 1789 bool AMDGPUDisassembler::isGFX90A() const { 1790 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1791 } 1792 1793 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1794 1795 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1796 1797 bool AMDGPUDisassembler::isGFX10Plus() const { 1798 return AMDGPU::isGFX10Plus(STI); 1799 } 1800 1801 bool AMDGPUDisassembler::isGFX11() const { 1802 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1803 } 1804 1805 bool AMDGPUDisassembler::isGFX11Plus() const { 1806 return AMDGPU::isGFX11Plus(STI); 1807 } 1808 1809 1810 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1811 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1812 } 1813 1814 //===----------------------------------------------------------------------===// 1815 // AMDGPU specific symbol handling 1816 //===----------------------------------------------------------------------===// 1817 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1818 do { \ 1819 KdStream << Indent << DIRECTIVE " " \ 1820 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1821 } while (0) 1822 1823 // NOLINTNEXTLINE(readability-identifier-naming) 1824 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1825 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1826 using namespace amdhsa; 1827 StringRef Indent = "\t"; 1828 1829 // We cannot accurately backward compute #VGPRs used from 1830 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1831 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1832 // simply calculate the inverse of what the assembler does. 1833 1834 uint32_t GranulatedWorkitemVGPRCount = 1835 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1836 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1837 1838 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1839 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1840 1841 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1842 1843 // We cannot backward compute values used to calculate 1844 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1845 // directives can't be computed: 1846 // .amdhsa_reserve_vcc 1847 // .amdhsa_reserve_flat_scratch 1848 // .amdhsa_reserve_xnack_mask 1849 // They take their respective default values if not specified in the assembly. 1850 // 1851 // GRANULATED_WAVEFRONT_SGPR_COUNT 1852 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1853 // 1854 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1855 // are set to 0. So while disassembling we consider that: 1856 // 1857 // GRANULATED_WAVEFRONT_SGPR_COUNT 1858 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1859 // 1860 // The disassembler cannot recover the original values of those 3 directives. 1861 1862 uint32_t GranulatedWavefrontSGPRCount = 1863 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1864 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1865 1866 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1867 return MCDisassembler::Fail; 1868 1869 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1870 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1871 1872 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1873 if (!hasArchitectedFlatScratch()) 1874 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1875 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1876 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1877 1878 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1879 return MCDisassembler::Fail; 1880 1881 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1882 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1883 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1884 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1885 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1886 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1887 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1888 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1889 1890 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1891 return MCDisassembler::Fail; 1892 1893 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1894 1895 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1896 return MCDisassembler::Fail; 1897 1898 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1899 1900 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1901 return MCDisassembler::Fail; 1902 1903 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1904 return MCDisassembler::Fail; 1905 1906 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1907 1908 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1909 return MCDisassembler::Fail; 1910 1911 if (isGFX10Plus()) { 1912 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1913 COMPUTE_PGM_RSRC1_WGP_MODE); 1914 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1915 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1916 } 1917 return MCDisassembler::Success; 1918 } 1919 1920 // NOLINTNEXTLINE(readability-identifier-naming) 1921 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1922 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1923 using namespace amdhsa; 1924 StringRef Indent = "\t"; 1925 if (hasArchitectedFlatScratch()) 1926 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1927 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1928 else 1929 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1930 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1931 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1932 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1933 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1934 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1935 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1936 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1937 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1938 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1939 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1940 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1941 1942 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1943 return MCDisassembler::Fail; 1944 1945 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1946 return MCDisassembler::Fail; 1947 1948 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1949 return MCDisassembler::Fail; 1950 1951 PRINT_DIRECTIVE( 1952 ".amdhsa_exception_fp_ieee_invalid_op", 1953 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1954 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1955 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1956 PRINT_DIRECTIVE( 1957 ".amdhsa_exception_fp_ieee_div_zero", 1958 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1959 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1960 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1961 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1962 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1963 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1964 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1965 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1966 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1967 1968 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1969 return MCDisassembler::Fail; 1970 1971 return MCDisassembler::Success; 1972 } 1973 1974 #undef PRINT_DIRECTIVE 1975 1976 MCDisassembler::DecodeStatus 1977 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1978 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1979 raw_string_ostream &KdStream) const { 1980 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1981 do { \ 1982 KdStream << Indent << DIRECTIVE " " \ 1983 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1984 } while (0) 1985 1986 uint16_t TwoByteBuffer = 0; 1987 uint32_t FourByteBuffer = 0; 1988 1989 StringRef ReservedBytes; 1990 StringRef Indent = "\t"; 1991 1992 assert(Bytes.size() == 64); 1993 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1994 1995 switch (Cursor.tell()) { 1996 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1997 FourByteBuffer = DE.getU32(Cursor); 1998 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1999 << '\n'; 2000 return MCDisassembler::Success; 2001 2002 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2003 FourByteBuffer = DE.getU32(Cursor); 2004 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2005 << FourByteBuffer << '\n'; 2006 return MCDisassembler::Success; 2007 2008 case amdhsa::KERNARG_SIZE_OFFSET: 2009 FourByteBuffer = DE.getU32(Cursor); 2010 KdStream << Indent << ".amdhsa_kernarg_size " 2011 << FourByteBuffer << '\n'; 2012 return MCDisassembler::Success; 2013 2014 case amdhsa::RESERVED0_OFFSET: 2015 // 4 reserved bytes, must be 0. 2016 ReservedBytes = DE.getBytes(Cursor, 4); 2017 for (int I = 0; I < 4; ++I) { 2018 if (ReservedBytes[I] != 0) { 2019 return MCDisassembler::Fail; 2020 } 2021 } 2022 return MCDisassembler::Success; 2023 2024 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2025 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2026 // So far no directive controls this for Code Object V3, so simply skip for 2027 // disassembly. 2028 DE.skip(Cursor, 8); 2029 return MCDisassembler::Success; 2030 2031 case amdhsa::RESERVED1_OFFSET: 2032 // 20 reserved bytes, must be 0. 2033 ReservedBytes = DE.getBytes(Cursor, 20); 2034 for (int I = 0; I < 20; ++I) { 2035 if (ReservedBytes[I] != 0) { 2036 return MCDisassembler::Fail; 2037 } 2038 } 2039 return MCDisassembler::Success; 2040 2041 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2042 // COMPUTE_PGM_RSRC3 2043 // - Only set for GFX10, GFX6-9 have this to be 0. 2044 // - Currently no directives directly control this. 2045 FourByteBuffer = DE.getU32(Cursor); 2046 if (!isGFX10Plus() && FourByteBuffer) { 2047 return MCDisassembler::Fail; 2048 } 2049 return MCDisassembler::Success; 2050 2051 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2052 FourByteBuffer = DE.getU32(Cursor); 2053 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 2054 MCDisassembler::Fail) { 2055 return MCDisassembler::Fail; 2056 } 2057 return MCDisassembler::Success; 2058 2059 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2060 FourByteBuffer = DE.getU32(Cursor); 2061 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 2062 MCDisassembler::Fail) { 2063 return MCDisassembler::Fail; 2064 } 2065 return MCDisassembler::Success; 2066 2067 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2068 using namespace amdhsa; 2069 TwoByteBuffer = DE.getU16(Cursor); 2070 2071 if (!hasArchitectedFlatScratch()) 2072 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2073 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2074 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2075 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2076 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2077 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2078 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2079 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2080 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2081 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2082 if (!hasArchitectedFlatScratch()) 2083 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2084 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2085 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2086 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2087 2088 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2089 return MCDisassembler::Fail; 2090 2091 // Reserved for GFX9 2092 if (isGFX9() && 2093 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2094 return MCDisassembler::Fail; 2095 } else if (isGFX10Plus()) { 2096 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2097 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2098 } 2099 2100 if (AMDGPU::getAmdhsaCodeObjectVersion() >= 5) 2101 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2102 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2103 2104 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2105 return MCDisassembler::Fail; 2106 2107 return MCDisassembler::Success; 2108 2109 case amdhsa::RESERVED2_OFFSET: 2110 // 6 bytes from here are reserved, must be 0. 2111 ReservedBytes = DE.getBytes(Cursor, 6); 2112 for (int I = 0; I < 6; ++I) { 2113 if (ReservedBytes[I] != 0) 2114 return MCDisassembler::Fail; 2115 } 2116 return MCDisassembler::Success; 2117 2118 default: 2119 llvm_unreachable("Unhandled index. Case statements cover everything."); 2120 return MCDisassembler::Fail; 2121 } 2122 #undef PRINT_DIRECTIVE 2123 } 2124 2125 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2126 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2127 // CP microcode requires the kernel descriptor to be 64 aligned. 2128 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2129 return MCDisassembler::Fail; 2130 2131 std::string Kd; 2132 raw_string_ostream KdStream(Kd); 2133 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2134 2135 DataExtractor::Cursor C(0); 2136 while (C && C.tell() < Bytes.size()) { 2137 MCDisassembler::DecodeStatus Status = 2138 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2139 2140 cantFail(C.takeError()); 2141 2142 if (Status == MCDisassembler::Fail) 2143 return MCDisassembler::Fail; 2144 } 2145 KdStream << ".end_amdhsa_kernel\n"; 2146 outs() << KdStream.str(); 2147 return MCDisassembler::Success; 2148 } 2149 2150 Optional<MCDisassembler::DecodeStatus> 2151 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2152 ArrayRef<uint8_t> Bytes, uint64_t Address, 2153 raw_ostream &CStream) const { 2154 // Right now only kernel descriptor needs to be handled. 2155 // We ignore all other symbols for target specific handling. 2156 // TODO: 2157 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2158 // Object V2 and V3 when symbols are marked protected. 2159 2160 // amd_kernel_code_t for Code Object V2. 2161 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2162 Size = 256; 2163 return MCDisassembler::Fail; 2164 } 2165 2166 // Code Object V3 kernel descriptors. 2167 StringRef Name = Symbol.Name; 2168 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2169 Size = 64; // Size = 64 regardless of success or failure. 2170 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2171 } 2172 return None; 2173 } 2174 2175 //===----------------------------------------------------------------------===// 2176 // AMDGPUSymbolizer 2177 //===----------------------------------------------------------------------===// 2178 2179 // Try to find symbol name for specified label 2180 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2181 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2182 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2183 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2184 2185 if (!IsBranch) { 2186 return false; 2187 } 2188 2189 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2190 if (!Symbols) 2191 return false; 2192 2193 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2194 return Val.Addr == static_cast<uint64_t>(Value) && 2195 Val.Type == ELF::STT_NOTYPE; 2196 }); 2197 if (Result != Symbols->end()) { 2198 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2199 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2200 Inst.addOperand(MCOperand::createExpr(Add)); 2201 return true; 2202 } 2203 // Add to list of referenced addresses, so caller can synthesize a label. 2204 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2205 return false; 2206 } 2207 2208 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2209 int64_t Value, 2210 uint64_t Address) { 2211 llvm_unreachable("unimplemented"); 2212 } 2213 2214 //===----------------------------------------------------------------------===// 2215 // Initialization 2216 //===----------------------------------------------------------------------===// 2217 2218 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2219 LLVMOpInfoCallback /*GetOpInfo*/, 2220 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2221 void *DisInfo, 2222 MCContext *Ctx, 2223 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2224 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2225 } 2226 2227 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2228 const MCSubtargetInfo &STI, 2229 MCContext &Ctx) { 2230 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2231 } 2232 2233 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2234 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2235 createAMDGPUDisassembler); 2236 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2237 createAMDGPUSymbolizer); 2238 } 2239