1 //===-- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "SIDefines.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCFixedLenDisassembler.h" 28 #include "llvm/MC/MCInst.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCSubtargetInfo.h" 31 #include "llvm/Support/Endian.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/TargetRegistry.h" 34 35 36 using namespace llvm; 37 38 #define DEBUG_TYPE "amdgpu-disassembler" 39 40 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus; 41 42 43 inline static MCDisassembler::DecodeStatus 44 addOperand(MCInst &Inst, const MCOperand& Opnd) { 45 Inst.addOperand(Opnd); 46 return Opnd.isValid() ? 47 MCDisassembler::Success : 48 MCDisassembler::SoftFail; 49 } 50 51 #define DECODE_OPERAND2(RegClass, DecName) \ 52 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \ 53 unsigned Imm, \ 54 uint64_t /*Addr*/, \ 55 const void *Decoder) { \ 56 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 57 return addOperand(Inst, DAsm->decodeOperand_##DecName(Imm)); \ 58 } 59 60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) 61 62 DECODE_OPERAND(VGPR_32) 63 DECODE_OPERAND(VS_32) 64 DECODE_OPERAND(VS_64) 65 66 DECODE_OPERAND(VReg_64) 67 DECODE_OPERAND(VReg_96) 68 DECODE_OPERAND(VReg_128) 69 70 DECODE_OPERAND(SReg_32) 71 DECODE_OPERAND(SReg_32_XM0) 72 DECODE_OPERAND(SReg_64) 73 DECODE_OPERAND(SReg_128) 74 DECODE_OPERAND(SReg_256) 75 DECODE_OPERAND(SReg_512) 76 77 #define GET_SUBTARGETINFO_ENUM 78 #include "AMDGPUGenSubtargetInfo.inc" 79 #undef GET_SUBTARGETINFO_ENUM 80 81 #include "AMDGPUGenDisassemblerTables.inc" 82 83 //===----------------------------------------------------------------------===// 84 // 85 //===----------------------------------------------------------------------===// 86 87 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 88 assert(Bytes.size() >= sizeof(T)); 89 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 90 Bytes = Bytes.slice(sizeof(T)); 91 return Res; 92 } 93 94 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 95 MCInst &MI, 96 uint64_t Inst, 97 uint64_t Address) const { 98 assert(MI.getOpcode() == 0); 99 assert(MI.getNumOperands() == 0); 100 MCInst TmpInst; 101 const auto SavedBytes = Bytes; 102 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 103 MI = TmpInst; 104 return MCDisassembler::Success; 105 } 106 Bytes = SavedBytes; 107 return MCDisassembler::Fail; 108 } 109 110 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 111 ArrayRef<uint8_t> Bytes_, 112 uint64_t Address, 113 raw_ostream &WS, 114 raw_ostream &CS) const { 115 CommentStream = &CS; 116 117 // ToDo: AMDGPUDisassembler supports only VI ISA. 118 assert(AMDGPU::isVI(STI) && "Can disassemble only VI ISA."); 119 120 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 121 Bytes = Bytes_.slice(0, MaxInstBytesNum); 122 123 DecodeStatus Res = MCDisassembler::Fail; 124 do { 125 // ToDo: better to switch encoding length using some bit predicate 126 // but it is unknown yet, so try all we can 127 128 // Try to decode DPP first to solve conflict with VOP1 and VOP2 encodings 129 if (Bytes.size() >= 8) { 130 const uint64_t QW = eatBytes<uint64_t>(Bytes); 131 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 132 if (Res) break; 133 } 134 135 // Reinitialize Bytes as DPP64 could have eaten too much 136 Bytes = Bytes_.slice(0, MaxInstBytesNum); 137 138 // Try decode 32-bit instruction 139 if (Bytes.size() < 4) break; 140 const uint32_t DW = eatBytes<uint32_t>(Bytes); 141 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 142 if (Res) break; 143 144 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 145 if (Res) break; 146 147 if (Bytes.size() < 4) break; 148 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 149 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 150 if (Res) break; 151 152 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 153 } while (false); 154 155 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 156 return Res; 157 } 158 159 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 160 return getContext().getRegisterInfo()-> 161 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 162 } 163 164 inline 165 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 166 const Twine& ErrMsg) const { 167 *CommentStream << "Error: " + ErrMsg; 168 169 // ToDo: add support for error operands to MCInst.h 170 // return MCOperand::createError(V); 171 return MCOperand(); 172 } 173 174 inline 175 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 176 return MCOperand::createReg(RegId); 177 } 178 179 inline 180 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 181 unsigned Val) const { 182 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 183 if (Val >= RegCl.getNumRegs()) 184 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 185 ": unknown register " + Twine(Val)); 186 return createRegOperand(RegCl.getRegister(Val)); 187 } 188 189 inline 190 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 191 unsigned Val) const { 192 // ToDo: SI/CI have 104 SGPRs, VI - 102 193 // Valery: here we accepting as much as we can, let assembler sort it out 194 int shift = 0; 195 switch (SRegClassID) { 196 case AMDGPU::SGPR_32RegClassID: 197 case AMDGPU::TTMP_32RegClassID: 198 break; 199 case AMDGPU::SGPR_64RegClassID: 200 case AMDGPU::TTMP_64RegClassID: 201 shift = 1; 202 break; 203 case AMDGPU::SGPR_128RegClassID: 204 case AMDGPU::TTMP_128RegClassID: 205 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 206 // this bundle? 207 case AMDGPU::SReg_256RegClassID: 208 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 209 // this bundle? 210 case AMDGPU::SReg_512RegClassID: 211 shift = 2; 212 break; 213 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 214 // this bundle? 215 default: 216 assert(false); 217 break; 218 } 219 if (Val % (1 << shift)) 220 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 221 << ": scalar reg isn't aligned " << Val; 222 return createRegOperand(SRegClassID, Val >> shift); 223 } 224 225 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 226 return decodeSrcOp(OPW32, Val); 227 } 228 229 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 230 return decodeSrcOp(OPW64, Val); 231 } 232 233 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 234 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 235 } 236 237 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 238 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 239 } 240 241 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 242 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 243 } 244 245 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 246 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 247 } 248 249 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 250 // table-gen generated disassembler doesn't care about operand types 251 // leaving only registry class so SSrc_32 operand turns into SReg_32 252 // and therefore we accept immediates and literals here as well 253 return decodeSrcOp(OPW32, Val); 254 } 255 256 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0(unsigned Val) const { 257 // SReg_32_XM0 is SReg_32 without M0 258 return decodeOperand_SReg_32(Val); 259 } 260 261 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 262 // see decodeOperand_SReg_32 comment 263 return decodeSrcOp(OPW64, Val); 264 } 265 266 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 267 return decodeSrcOp(OPW128, Val); 268 } 269 270 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 271 return createSRegOperand(AMDGPU::SReg_256RegClassID, Val); 272 } 273 274 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 275 return createSRegOperand(AMDGPU::SReg_512RegClassID, Val); 276 } 277 278 279 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 280 // For now all literal constants are supposed to be unsigned integer 281 // ToDo: deal with signed/unsigned 64-bit integer constants 282 // ToDo: deal with float/double constants 283 if (Bytes.size() < 4) 284 return errOperand(0, "cannot read literal, inst bytes left " + 285 Twine(Bytes.size())); 286 return MCOperand::createImm(eatBytes<uint32_t>(Bytes)); 287 } 288 289 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 290 using namespace AMDGPU::EncValues; 291 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 292 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 293 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 294 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 295 // Cast prevents negative overflow. 296 } 297 298 MCOperand AMDGPUDisassembler::decodeFPImmed(bool Is32, unsigned Imm) { 299 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 300 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 301 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 302 // ToDo: AMDGPUInstPrinter does not support 1/(2*PI). It consider 1/(2*PI) as 303 // literal constant. 304 float V = 0.0f; 305 switch (Imm) { 306 case 240: V = 0.5f; break; 307 case 241: V = -0.5f; break; 308 case 242: V = 1.0f; break; 309 case 243: V = -1.0f; break; 310 case 244: V = 2.0f; break; 311 case 245: V = -2.0f; break; 312 case 246: V = 4.0f; break; 313 case 247: V = -4.0f; break; 314 case 248: return MCOperand::createImm(Is32 ? // 1/(2*PI) 315 0x3e22f983 : 316 0x3fc45f306dc9c882); 317 default: break; 318 } 319 return MCOperand::createImm(Is32? FloatToBits(V) : DoubleToBits(V)); 320 } 321 322 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 323 using namespace AMDGPU; 324 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 325 switch (Width) { 326 default: // fall 327 case OPW32: return VGPR_32RegClassID; 328 case OPW64: return VReg_64RegClassID; 329 case OPW128: return VReg_128RegClassID; 330 } 331 } 332 333 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 334 using namespace AMDGPU; 335 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 336 switch (Width) { 337 default: // fall 338 case OPW32: return SGPR_32RegClassID; 339 case OPW64: return SGPR_64RegClassID; 340 case OPW128: return SGPR_128RegClassID; 341 } 342 } 343 344 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 345 using namespace AMDGPU; 346 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 347 switch (Width) { 348 default: // fall 349 case OPW32: return TTMP_32RegClassID; 350 case OPW64: return TTMP_64RegClassID; 351 case OPW128: return TTMP_128RegClassID; 352 } 353 } 354 355 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 356 using namespace AMDGPU::EncValues; 357 assert(Val < 512); // enum9 358 359 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 360 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); 361 } 362 if (SGPR_MIN <= Val && Val <= SGPR_MAX) { 363 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 364 } 365 if (TTMP_MIN <= Val && Val <= TTMP_MAX) { 366 return createSRegOperand(getTtmpClassId(Width), Val - TTMP_MIN); 367 } 368 369 assert(Width == OPW32 || Width == OPW64); 370 const bool Is32 = (Width == OPW32); 371 372 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 373 return decodeIntImmed(Val); 374 375 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 376 return decodeFPImmed(Is32, Val); 377 378 if (Val == LITERAL_CONST) 379 return decodeLiteralConstant(); 380 381 return Is32 ? decodeSpecialReg32(Val) : decodeSpecialReg64(Val); 382 } 383 384 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 385 using namespace AMDGPU; 386 switch (Val) { 387 case 102: return createRegOperand(getMCReg(FLAT_SCR_LO, STI)); 388 case 103: return createRegOperand(getMCReg(FLAT_SCR_HI, STI)); 389 // ToDo: no support for xnack_mask_lo/_hi register 390 case 104: 391 case 105: break; 392 case 106: return createRegOperand(VCC_LO); 393 case 107: return createRegOperand(VCC_HI); 394 case 108: return createRegOperand(TBA_LO); 395 case 109: return createRegOperand(TBA_HI); 396 case 110: return createRegOperand(TMA_LO); 397 case 111: return createRegOperand(TMA_HI); 398 case 124: return createRegOperand(M0); 399 case 126: return createRegOperand(EXEC_LO); 400 case 127: return createRegOperand(EXEC_HI); 401 // ToDo: no support for vccz register 402 case 251: break; 403 // ToDo: no support for execz register 404 case 252: break; 405 case 253: return createRegOperand(SCC); 406 default: break; 407 } 408 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 409 } 410 411 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 412 using namespace AMDGPU; 413 switch (Val) { 414 case 102: return createRegOperand(getMCReg(FLAT_SCR, STI)); 415 case 106: return createRegOperand(VCC); 416 case 108: return createRegOperand(TBA); 417 case 110: return createRegOperand(TMA); 418 case 126: return createRegOperand(EXEC); 419 default: break; 420 } 421 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 422 } 423 424 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 425 const MCSubtargetInfo &STI, 426 MCContext &Ctx) { 427 return new AMDGPUDisassembler(STI, Ctx); 428 } 429 430 extern "C" void LLVMInitializeAMDGPUDisassembler() { 431 TargetRegistry::RegisterMCDisassembler(TheGCNTarget, createAMDGPUDisassembler); 432 } 433