1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) { 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 95 Offset = Imm & 0xFFFFF; 96 } else { // GFX9+ supports 21-bit signed offsets. 97 Offset = SignExtend64<21>(Imm); 98 } 99 return addOperand(Inst, MCOperand::createImm(Offset)); 100 } 101 102 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 103 const MCDisassembler *Decoder) { 104 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 105 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 106 } 107 108 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 109 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const MCDisassembler *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 117 // number of register. Used by VGPR only and AGPR only operands. 118 #define DECODE_OPERAND_REG_8(RegClass) \ 119 static DecodeStatus Decode##RegClass##RegisterClass( \ 120 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 121 const MCDisassembler *Decoder) { \ 122 assert(Imm < (1 << 8) && "8-bit encoding"); \ 123 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 124 return addOperand( \ 125 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 126 } 127 128 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 129 ImmWidth) \ 130 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 131 const MCDisassembler *Decoder) { \ 132 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 133 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 134 return addOperand(Inst, \ 135 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 136 MandatoryLiteral, ImmWidth)); \ 137 } 138 139 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 140 // get register class. Used by SGPR only operands. 141 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 142 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 143 144 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 145 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 146 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 147 // Used by AV_ register classes (AGPR or VGPR only register operands). 148 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ 149 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ 150 Imm | AMDGPU::EncValues::IS_VGPR, false, 0) 151 152 // Decoder for Src(9-bit encoding) registers only. 153 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ 154 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 155 156 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 157 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 158 // only. 159 #define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \ 160 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) 161 162 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 163 // Imm{9} is acc, registers only. 164 #define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \ 165 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) 166 167 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 168 // register from RegClass or immediate. Registers that don't belong to RegClass 169 // will be decoded and InstPrinter will report warning. Immediate will be 170 // decoded into constant of size ImmWidth, should match width of immediate used 171 // by OperandType (important for floating point types). 172 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ 173 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ 174 false, ImmWidth) 175 176 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 177 // and decode using 'enum10' from decodeSrcOp. 178 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ 179 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ 180 Imm | 512, false, ImmWidth) 181 182 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ 183 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ 184 OpWidth, Imm, true, ImmWidth) 185 186 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 187 // when RegisterClass is used as an operand. Most often used for destination 188 // operands. 189 190 DECODE_OPERAND_REG_8(VGPR_32) 191 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 192 DECODE_OPERAND_REG_8(VReg_64) 193 DECODE_OPERAND_REG_8(VReg_96) 194 DECODE_OPERAND_REG_8(VReg_128) 195 DECODE_OPERAND_REG_8(VReg_256) 196 DECODE_OPERAND_REG_8(VReg_288) 197 DECODE_OPERAND_REG_8(VReg_352) 198 DECODE_OPERAND_REG_8(VReg_384) 199 DECODE_OPERAND_REG_8(VReg_512) 200 DECODE_OPERAND_REG_8(VReg_1024) 201 202 DECODE_OPERAND_REG_7(SReg_32, OPW32) 203 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 204 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 205 DECODE_OPERAND_REG_7(SReg_64, OPW64) 206 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 207 DECODE_OPERAND_REG_7(SReg_128, OPW128) 208 DECODE_OPERAND_REG_7(SReg_256, OPW256) 209 DECODE_OPERAND_REG_7(SReg_512, OPW512) 210 211 DECODE_OPERAND_REG_8(AGPR_32) 212 DECODE_OPERAND_REG_8(AReg_64) 213 DECODE_OPERAND_REG_8(AReg_128) 214 DECODE_OPERAND_REG_8(AReg_256) 215 DECODE_OPERAND_REG_8(AReg_512) 216 DECODE_OPERAND_REG_8(AReg_1024) 217 218 DECODE_OPERAND_REG_AV10(AVDst_128, OPW128) 219 DECODE_OPERAND_REG_AV10(AVDst_512, OPW512) 220 221 // Decoders for register only source RegisterOperands that use use 9-bit Src 222 // encoding: 'decodeOperand_<RegClass>'. 223 224 DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) 225 DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) 226 DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) 227 DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) 228 DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) 229 230 DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32) 231 232 DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32) 233 DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64) 234 DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128) 235 236 // Decoders for register or immediate RegisterOperands that use 9-bit Src 237 // encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'. 238 239 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) 240 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) 241 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 16) 242 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) 243 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) 244 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) 245 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) 246 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) 247 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32) 248 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) 249 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) 250 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) 251 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) 252 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) 253 254 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) 255 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) 256 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) 257 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) 258 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) 259 260 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) 261 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) 262 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) 263 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32) 264 265 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 266 uint64_t /*Addr*/, 267 const MCDisassembler *Decoder) { 268 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 269 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 270 271 bool IsHi = Imm & (1 << 9); 272 unsigned RegIdx = Imm & 0xff; 273 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 274 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 275 } 276 277 static DecodeStatus 278 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 279 const MCDisassembler *Decoder) { 280 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 281 282 bool IsHi = Imm & (1 << 7); 283 unsigned RegIdx = Imm & 0x7f; 284 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 285 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 286 } 287 288 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 289 uint64_t /*Addr*/, 290 const MCDisassembler *Decoder) { 291 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 292 293 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 294 bool IsVGPR = Imm & (1 << 8); 295 if (IsVGPR) { 296 bool IsHi = Imm & (1 << 7); 297 unsigned RegIdx = Imm & 0x7f; 298 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 299 } 300 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 301 Imm & 0xFF, false, 16)); 302 } 303 304 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 305 uint64_t /*Addr*/, 306 const MCDisassembler *Decoder) { 307 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 308 309 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 310 bool IsVGPR = Imm & (1 << 8); 311 if (IsVGPR) { 312 bool IsHi = Imm & (1 << 9); 313 unsigned RegIdx = Imm & 0xff; 314 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 315 } 316 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 317 Imm & 0xFF, false, 16)); 318 } 319 320 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 321 uint64_t Addr, 322 const MCDisassembler *Decoder) { 323 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 324 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 325 } 326 327 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 328 uint64_t Addr, const void *Decoder) { 329 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 330 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 331 } 332 333 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 334 const MCRegisterInfo *MRI) { 335 if (OpIdx < 0) 336 return false; 337 338 const MCOperand &Op = Inst.getOperand(OpIdx); 339 if (!Op.isReg()) 340 return false; 341 342 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 343 auto Reg = Sub ? Sub : Op.getReg(); 344 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 345 } 346 347 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 348 AMDGPUDisassembler::OpWidthTy Opw, 349 const MCDisassembler *Decoder) { 350 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 351 if (!DAsm->isGFX90A()) { 352 Imm &= 511; 353 } else { 354 // If atomic has both vdata and vdst their register classes are tied. 355 // The bit is decoded along with the vdst, first operand. We need to 356 // change register class to AGPR if vdst was AGPR. 357 // If a DS instruction has both data0 and data1 their register classes 358 // are also tied. 359 unsigned Opc = Inst.getOpcode(); 360 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 361 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 362 : AMDGPU::OpName::vdata; 363 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 364 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 365 if ((int)Inst.getNumOperands() == DataIdx) { 366 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 367 if (IsAGPROperand(Inst, DstIdx, MRI)) 368 Imm |= 512; 369 } 370 371 if (TSFlags & SIInstrFlags::DS) { 372 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 373 if ((int)Inst.getNumOperands() == Data2Idx && 374 IsAGPROperand(Inst, DataIdx, MRI)) 375 Imm |= 512; 376 } 377 } 378 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 379 } 380 381 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 382 uint64_t Addr, 383 const MCDisassembler *Decoder) { 384 assert(Imm < (1 << 9) && "9-bit encoding"); 385 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 386 return addOperand( 387 Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true)); 388 } 389 390 static DecodeStatus 391 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 392 const MCDisassembler *Decoder) { 393 return decodeOperand_AVLdSt_Any(Inst, Imm, 394 AMDGPUDisassembler::OPW32, Decoder); 395 } 396 397 static DecodeStatus 398 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 399 const MCDisassembler *Decoder) { 400 return decodeOperand_AVLdSt_Any(Inst, Imm, 401 AMDGPUDisassembler::OPW64, Decoder); 402 } 403 404 static DecodeStatus 405 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 406 const MCDisassembler *Decoder) { 407 return decodeOperand_AVLdSt_Any(Inst, Imm, 408 AMDGPUDisassembler::OPW96, Decoder); 409 } 410 411 static DecodeStatus 412 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 413 const MCDisassembler *Decoder) { 414 return decodeOperand_AVLdSt_Any(Inst, Imm, 415 AMDGPUDisassembler::OPW128, Decoder); 416 } 417 418 static DecodeStatus 419 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 420 const MCDisassembler *Decoder) { 421 return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160, 422 Decoder); 423 } 424 425 #define DECODE_SDWA(DecName) \ 426 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 427 428 DECODE_SDWA(Src32) 429 DECODE_SDWA(Src16) 430 DECODE_SDWA(VopcDst) 431 432 #include "AMDGPUGenDisassemblerTables.inc" 433 434 //===----------------------------------------------------------------------===// 435 // 436 //===----------------------------------------------------------------------===// 437 438 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 439 assert(Bytes.size() >= sizeof(T)); 440 const auto Res = 441 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 442 Bytes = Bytes.slice(sizeof(T)); 443 return Res; 444 } 445 446 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 447 assert(Bytes.size() >= 12); 448 uint64_t Lo = 449 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 450 Bytes = Bytes.slice(8); 451 uint64_t Hi = 452 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 453 Bytes = Bytes.slice(4); 454 return DecoderUInt128(Lo, Hi); 455 } 456 457 // The disassembler is greedy, so we need to check FI operand value to 458 // not parse a dpp if the correct literal is not set. For dpp16 the 459 // autogenerated decoder checks the dpp literal 460 static bool isValidDPP8(const MCInst &MI) { 461 using namespace llvm::AMDGPU::DPP; 462 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 463 assert(FiIdx != -1); 464 if ((unsigned)FiIdx >= MI.getNumOperands()) 465 return false; 466 unsigned Fi = MI.getOperand(FiIdx).getImm(); 467 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 468 } 469 470 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 471 ArrayRef<uint8_t> Bytes_, 472 uint64_t Address, 473 raw_ostream &CS) const { 474 bool IsSDWA = false; 475 476 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 477 Bytes = Bytes_.slice(0, MaxInstBytesNum); 478 479 DecodeStatus Res = MCDisassembler::Fail; 480 do { 481 // ToDo: better to switch encoding length using some bit predicate 482 // but it is unknown yet, so try all we can 483 484 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 485 // encodings 486 if (isGFX11Plus() && Bytes.size() >= 12 ) { 487 DecoderUInt128 DecW = eat12Bytes(Bytes); 488 Res = 489 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 490 MI, DecW, Address, CS); 491 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 492 break; 493 MI = MCInst(); // clear 494 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 495 MI, DecW, Address, CS); 496 if (Res) { 497 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 498 convertVOP3PDPPInst(MI); 499 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 500 convertVOPCDPPInst(MI); // Special VOP3 case 501 else { 502 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 503 convertVOP3DPPInst(MI); // Regular VOP3 case 504 } 505 break; 506 } 507 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 508 if (Res) 509 break; 510 511 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 512 if (Res) 513 break; 514 } 515 // Reinitialize Bytes 516 Bytes = Bytes_.slice(0, MaxInstBytesNum); 517 518 if (Bytes.size() >= 8) { 519 const uint64_t QW = eatBytes<uint64_t>(Bytes); 520 521 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 522 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 523 if (Res) { 524 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 525 == -1) 526 break; 527 if (convertDPP8Inst(MI) == MCDisassembler::Success) 528 break; 529 MI = MCInst(); // clear 530 } 531 } 532 533 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 534 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 535 break; 536 MI = MCInst(); // clear 537 538 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 539 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 540 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 541 break; 542 MI = MCInst(); // clear 543 544 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 545 if (Res) break; 546 547 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 548 MI, QW, Address, CS); 549 if (Res) { 550 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 551 convertVOPCDPPInst(MI); 552 break; 553 } 554 555 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 556 if (Res) { IsSDWA = true; break; } 557 558 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 559 if (Res) { IsSDWA = true; break; } 560 561 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 562 if (Res) { IsSDWA = true; break; } 563 564 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 565 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 566 if (Res) 567 break; 568 } 569 570 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 571 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 572 // table first so we print the correct name. 573 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 574 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 575 if (Res) 576 break; 577 } 578 } 579 580 // Reinitialize Bytes as DPP64 could have eaten too much 581 Bytes = Bytes_.slice(0, MaxInstBytesNum); 582 583 // Try decode 32-bit instruction 584 if (Bytes.size() < 4) break; 585 const uint32_t DW = eatBytes<uint32_t>(Bytes); 586 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 587 if (Res) break; 588 589 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 590 if (Res) break; 591 592 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 593 if (Res) break; 594 595 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 596 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 597 if (Res) 598 break; 599 } 600 601 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 602 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 603 if (Res) break; 604 } 605 606 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 607 if (Res) break; 608 609 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 610 Address, CS); 611 if (Res) break; 612 613 Res = tryDecodeInst(DecoderTableGFX1232, MI, DW, Address, CS); 614 if (Res) 615 break; 616 617 if (Bytes.size() < 4) break; 618 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 619 620 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 621 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 622 if (Res) 623 break; 624 } 625 626 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 627 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 628 if (Res) 629 break; 630 } 631 632 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 633 if (Res) break; 634 635 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS); 636 if (Res) break; 637 638 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 639 if (Res) break; 640 641 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 642 if (Res) break; 643 644 Res = tryDecodeInst(DecoderTableGFX1264, MI, QW, Address, CS); 645 if (Res) 646 break; 647 648 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 649 Address, CS); 650 if (Res) 651 break; 652 653 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS); 654 } while (false); 655 656 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 657 // Insert dummy unused src2_modifiers. 658 insertNamedMCOperand(MI, MCOperand::createImm(0), 659 AMDGPU::OpName::src2_modifiers); 660 } 661 662 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 663 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 664 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 665 AMDGPU::OpName::cpol); 666 if (CPolPos != -1) { 667 unsigned CPol = 668 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 669 AMDGPU::CPol::GLC : 0; 670 if (MI.getNumOperands() <= (unsigned)CPolPos) { 671 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 672 AMDGPU::OpName::cpol); 673 } else if (CPol) { 674 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 675 } 676 } 677 } 678 679 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 680 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 681 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 682 // GFX90A lost TFE, its place is occupied by ACC. 683 int TFEOpIdx = 684 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 685 if (TFEOpIdx != -1) { 686 auto TFEIter = MI.begin(); 687 std::advance(TFEIter, TFEOpIdx); 688 MI.insert(TFEIter, MCOperand::createImm(0)); 689 } 690 } 691 692 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 693 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 694 int SWZOpIdx = 695 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 696 if (SWZOpIdx != -1) { 697 auto SWZIter = MI.begin(); 698 std::advance(SWZIter, SWZOpIdx); 699 MI.insert(SWZIter, MCOperand::createImm(0)); 700 } 701 } 702 703 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 704 int VAddr0Idx = 705 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 706 int RsrcIdx = 707 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 708 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 709 if (VAddr0Idx >= 0 && NSAArgs > 0) { 710 unsigned NSAWords = (NSAArgs + 3) / 4; 711 if (Bytes.size() < 4 * NSAWords) { 712 Res = MCDisassembler::Fail; 713 } else { 714 for (unsigned i = 0; i < NSAArgs; ++i) { 715 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 716 auto VAddrRCID = 717 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 718 MI.insert(MI.begin() + VAddrIdx, 719 createRegOperand(VAddrRCID, Bytes[i])); 720 } 721 Bytes = Bytes.slice(4 * NSAWords); 722 } 723 } 724 725 if (Res) 726 Res = convertMIMGInst(MI); 727 } 728 729 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 730 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 731 Res = convertMIMGInst(MI); 732 733 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 734 Res = convertEXPInst(MI); 735 736 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 737 Res = convertVINTERPInst(MI); 738 739 if (Res && IsSDWA) 740 Res = convertSDWAInst(MI); 741 742 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 743 AMDGPU::OpName::vdst_in); 744 if (VDstIn_Idx != -1) { 745 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 746 MCOI::OperandConstraint::TIED_TO); 747 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 748 !MI.getOperand(VDstIn_Idx).isReg() || 749 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 750 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 751 MI.erase(&MI.getOperand(VDstIn_Idx)); 752 insertNamedMCOperand(MI, 753 MCOperand::createReg(MI.getOperand(Tied).getReg()), 754 AMDGPU::OpName::vdst_in); 755 } 756 } 757 758 int ImmLitIdx = 759 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 760 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 761 if (Res && ImmLitIdx != -1 && !IsSOPK) 762 Res = convertFMAanyK(MI, ImmLitIdx); 763 764 // if the opcode was not recognized we'll assume a Size of 4 bytes 765 // (unless there are fewer bytes left) 766 Size = Res ? (MaxInstBytesNum - Bytes.size()) 767 : std::min((size_t)4, Bytes_.size()); 768 return Res; 769 } 770 771 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 772 if (STI.hasFeature(AMDGPU::FeatureGFX11)) { 773 // The MCInst still has these fields even though they are no longer encoded 774 // in the GFX11 instruction. 775 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 776 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 777 } 778 return MCDisassembler::Success; 779 } 780 781 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 782 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 783 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 784 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 785 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 786 // The MCInst has this field that is not directly encoded in the 787 // instruction. 788 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 789 } 790 return MCDisassembler::Success; 791 } 792 793 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 794 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 795 STI.hasFeature(AMDGPU::FeatureGFX10)) { 796 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 797 // VOPC - insert clamp 798 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 799 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 800 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 801 if (SDst != -1) { 802 // VOPC - insert VCC register as sdst 803 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 804 AMDGPU::OpName::sdst); 805 } else { 806 // VOP1/2 - insert omod if present in instruction 807 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 808 } 809 } 810 return MCDisassembler::Success; 811 } 812 813 struct VOPModifiers { 814 unsigned OpSel = 0; 815 unsigned OpSelHi = 0; 816 unsigned NegLo = 0; 817 unsigned NegHi = 0; 818 }; 819 820 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 821 // Note that these values do not affect disassembler output, 822 // so this is only necessary for consistency with src_modifiers. 823 static VOPModifiers collectVOPModifiers(const MCInst &MI, 824 bool IsVOP3P = false) { 825 VOPModifiers Modifiers; 826 unsigned Opc = MI.getOpcode(); 827 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 828 AMDGPU::OpName::src1_modifiers, 829 AMDGPU::OpName::src2_modifiers}; 830 for (int J = 0; J < 3; ++J) { 831 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 832 if (OpIdx == -1) 833 continue; 834 835 unsigned Val = MI.getOperand(OpIdx).getImm(); 836 837 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 838 if (IsVOP3P) { 839 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 840 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 841 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 842 } else if (J == 0) { 843 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 844 } 845 } 846 847 return Modifiers; 848 } 849 850 // MAC opcodes have special old and src2 operands. 851 // src2 is tied to dst, while old is not tied (but assumed to be). 852 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 853 constexpr int DST_IDX = 0; 854 auto Opcode = MI.getOpcode(); 855 const auto &Desc = MCII->get(Opcode); 856 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 857 858 if (OldIdx != -1 && Desc.getOperandConstraint( 859 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 860 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 861 assert(Desc.getOperandConstraint( 862 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 863 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 864 (void)DST_IDX; 865 return true; 866 } 867 868 return false; 869 } 870 871 // Create dummy old operand and insert dummy unused src2_modifiers 872 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 873 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 874 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 875 insertNamedMCOperand(MI, MCOperand::createImm(0), 876 AMDGPU::OpName::src2_modifiers); 877 } 878 879 // We must check FI == literal to reject not genuine dpp8 insts, and we must 880 // first add optional MI operands to check FI 881 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 882 unsigned Opc = MI.getOpcode(); 883 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 884 convertVOP3PDPPInst(MI); 885 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 886 AMDGPU::isVOPC64DPP(Opc)) { 887 convertVOPCDPPInst(MI); 888 } else { 889 if (isMacDPP(MI)) 890 convertMacDPPInst(MI); 891 892 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 893 if (MI.getNumOperands() < DescNumOps && 894 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 895 auto Mods = collectVOPModifiers(MI); 896 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 897 AMDGPU::OpName::op_sel); 898 } else { 899 // Insert dummy unused src modifiers. 900 if (MI.getNumOperands() < DescNumOps && 901 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 902 insertNamedMCOperand(MI, MCOperand::createImm(0), 903 AMDGPU::OpName::src0_modifiers); 904 905 if (MI.getNumOperands() < DescNumOps && 906 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 907 insertNamedMCOperand(MI, MCOperand::createImm(0), 908 AMDGPU::OpName::src1_modifiers); 909 } 910 } 911 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 912 } 913 914 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 915 if (isMacDPP(MI)) 916 convertMacDPPInst(MI); 917 918 unsigned Opc = MI.getOpcode(); 919 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 920 if (MI.getNumOperands() < DescNumOps && 921 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 922 auto Mods = collectVOPModifiers(MI); 923 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 924 AMDGPU::OpName::op_sel); 925 } 926 return MCDisassembler::Success; 927 } 928 929 // Note that before gfx10, the MIMG encoding provided no information about 930 // VADDR size. Consequently, decoded instructions always show address as if it 931 // has 1 dword, which could be not really so. 932 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 933 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 934 935 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 936 AMDGPU::OpName::vdst); 937 938 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 939 AMDGPU::OpName::vdata); 940 int VAddr0Idx = 941 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 942 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 943 : AMDGPU::OpName::rsrc; 944 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 945 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 946 AMDGPU::OpName::dmask); 947 948 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 949 AMDGPU::OpName::tfe); 950 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 951 AMDGPU::OpName::d16); 952 953 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 954 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 955 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 956 957 assert(VDataIdx != -1); 958 if (BaseOpcode->BVH) { 959 // Add A16 operand for intersect_ray instructions 960 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 961 return MCDisassembler::Success; 962 } 963 964 bool IsAtomic = (VDstIdx != -1); 965 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 966 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 967 bool IsNSA = false; 968 bool IsPartialNSA = false; 969 unsigned AddrSize = Info->VAddrDwords; 970 971 if (isGFX10Plus()) { 972 unsigned DimIdx = 973 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 974 int A16Idx = 975 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 976 const AMDGPU::MIMGDimInfo *Dim = 977 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 978 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 979 980 AddrSize = 981 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 982 983 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 984 // VIMAGE insts other than BVH never use vaddr4. 985 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 986 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 987 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 988 if (!IsNSA) { 989 if (!IsVSample && AddrSize > 12) 990 AddrSize = 16; 991 } else { 992 if (AddrSize > Info->VAddrDwords) { 993 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 994 // The NSA encoding does not contain enough operands for the 995 // combination of base opcode / dimension. Should this be an error? 996 return MCDisassembler::Success; 997 } 998 IsPartialNSA = true; 999 } 1000 } 1001 } 1002 1003 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1004 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1005 1006 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1007 if (D16 && AMDGPU::hasPackedD16(STI)) { 1008 DstSize = (DstSize + 1) / 2; 1009 } 1010 1011 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1012 DstSize += 1; 1013 1014 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1015 return MCDisassembler::Success; 1016 1017 int NewOpcode = 1018 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1019 if (NewOpcode == -1) 1020 return MCDisassembler::Success; 1021 1022 // Widen the register to the correct number of enabled channels. 1023 unsigned NewVdata = AMDGPU::NoRegister; 1024 if (DstSize != Info->VDataDwords) { 1025 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1026 1027 // Get first subregister of VData 1028 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1029 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1030 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1031 1032 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1033 &MRI.getRegClass(DataRCID)); 1034 if (NewVdata == AMDGPU::NoRegister) { 1035 // It's possible to encode this such that the low register + enabled 1036 // components exceeds the register count. 1037 return MCDisassembler::Success; 1038 } 1039 } 1040 1041 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1042 // If using partial NSA on GFX11+ widen last address register. 1043 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1044 unsigned NewVAddrSA = AMDGPU::NoRegister; 1045 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1046 AddrSize != Info->VAddrDwords) { 1047 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1048 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1049 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1050 1051 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1052 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1053 &MRI.getRegClass(AddrRCID)); 1054 if (!NewVAddrSA) 1055 return MCDisassembler::Success; 1056 } 1057 1058 MI.setOpcode(NewOpcode); 1059 1060 if (NewVdata != AMDGPU::NoRegister) { 1061 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1062 1063 if (IsAtomic) { 1064 // Atomic operations have an additional operand (a copy of data) 1065 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1066 } 1067 } 1068 1069 if (NewVAddrSA) { 1070 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1071 } else if (IsNSA) { 1072 assert(AddrSize <= Info->VAddrDwords); 1073 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1074 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1075 } 1076 1077 return MCDisassembler::Success; 1078 } 1079 1080 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1081 // decoder only adds to src_modifiers, so manually add the bits to the other 1082 // operands. 1083 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1084 unsigned Opc = MI.getOpcode(); 1085 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1086 auto Mods = collectVOPModifiers(MI, true); 1087 1088 if (MI.getNumOperands() < DescNumOps && 1089 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1090 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1091 1092 if (MI.getNumOperands() < DescNumOps && 1093 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1094 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1095 AMDGPU::OpName::op_sel); 1096 if (MI.getNumOperands() < DescNumOps && 1097 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1098 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1099 AMDGPU::OpName::op_sel_hi); 1100 if (MI.getNumOperands() < DescNumOps && 1101 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1102 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1103 AMDGPU::OpName::neg_lo); 1104 if (MI.getNumOperands() < DescNumOps && 1105 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1106 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1107 AMDGPU::OpName::neg_hi); 1108 1109 return MCDisassembler::Success; 1110 } 1111 1112 // Create dummy old operand and insert optional operands 1113 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1114 unsigned Opc = MI.getOpcode(); 1115 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1116 1117 if (MI.getNumOperands() < DescNumOps && 1118 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1119 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1120 1121 if (MI.getNumOperands() < DescNumOps && 1122 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1123 insertNamedMCOperand(MI, MCOperand::createImm(0), 1124 AMDGPU::OpName::src0_modifiers); 1125 1126 if (MI.getNumOperands() < DescNumOps && 1127 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1128 insertNamedMCOperand(MI, MCOperand::createImm(0), 1129 AMDGPU::OpName::src1_modifiers); 1130 return MCDisassembler::Success; 1131 } 1132 1133 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1134 int ImmLitIdx) const { 1135 assert(HasLiteral && "Should have decoded a literal"); 1136 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1137 unsigned DescNumOps = Desc.getNumOperands(); 1138 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1139 AMDGPU::OpName::immDeferred); 1140 assert(DescNumOps == MI.getNumOperands()); 1141 for (unsigned I = 0; I < DescNumOps; ++I) { 1142 auto &Op = MI.getOperand(I); 1143 auto OpType = Desc.operands()[I].OperandType; 1144 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1145 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1146 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1147 IsDeferredOp) 1148 Op.setImm(Literal); 1149 } 1150 return MCDisassembler::Success; 1151 } 1152 1153 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1154 return getContext().getRegisterInfo()-> 1155 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1156 } 1157 1158 inline 1159 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1160 const Twine& ErrMsg) const { 1161 *CommentStream << "Error: " + ErrMsg; 1162 1163 // ToDo: add support for error operands to MCInst.h 1164 // return MCOperand::createError(V); 1165 return MCOperand(); 1166 } 1167 1168 inline 1169 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1170 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1171 } 1172 1173 inline 1174 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1175 unsigned Val) const { 1176 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1177 if (Val >= RegCl.getNumRegs()) 1178 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1179 ": unknown register " + Twine(Val)); 1180 return createRegOperand(RegCl.getRegister(Val)); 1181 } 1182 1183 inline 1184 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1185 unsigned Val) const { 1186 // ToDo: SI/CI have 104 SGPRs, VI - 102 1187 // Valery: here we accepting as much as we can, let assembler sort it out 1188 int shift = 0; 1189 switch (SRegClassID) { 1190 case AMDGPU::SGPR_32RegClassID: 1191 case AMDGPU::TTMP_32RegClassID: 1192 break; 1193 case AMDGPU::SGPR_64RegClassID: 1194 case AMDGPU::TTMP_64RegClassID: 1195 shift = 1; 1196 break; 1197 case AMDGPU::SGPR_128RegClassID: 1198 case AMDGPU::TTMP_128RegClassID: 1199 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1200 // this bundle? 1201 case AMDGPU::SGPR_256RegClassID: 1202 case AMDGPU::TTMP_256RegClassID: 1203 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1204 // this bundle? 1205 case AMDGPU::SGPR_288RegClassID: 1206 case AMDGPU::TTMP_288RegClassID: 1207 case AMDGPU::SGPR_320RegClassID: 1208 case AMDGPU::TTMP_320RegClassID: 1209 case AMDGPU::SGPR_352RegClassID: 1210 case AMDGPU::TTMP_352RegClassID: 1211 case AMDGPU::SGPR_384RegClassID: 1212 case AMDGPU::TTMP_384RegClassID: 1213 case AMDGPU::SGPR_512RegClassID: 1214 case AMDGPU::TTMP_512RegClassID: 1215 shift = 2; 1216 break; 1217 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1218 // this bundle? 1219 default: 1220 llvm_unreachable("unhandled register class"); 1221 } 1222 1223 if (Val % (1 << shift)) { 1224 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1225 << ": scalar reg isn't aligned " << Val; 1226 } 1227 1228 return createRegOperand(SRegClassID, Val >> shift); 1229 } 1230 1231 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1232 bool IsHi) const { 1233 unsigned RCID = 1234 IsHi ? AMDGPU::VGPR_HI16RegClassID : AMDGPU::VGPR_LO16RegClassID; 1235 return createRegOperand(RCID, RegIdx); 1236 } 1237 1238 // Decode Literals for insts which always have a literal in the encoding 1239 MCOperand 1240 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1241 if (HasLiteral) { 1242 assert( 1243 AMDGPU::hasVOPD(STI) && 1244 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1245 if (Literal != Val) 1246 return errOperand(Val, "More than one unique literal is illegal"); 1247 } 1248 HasLiteral = true; 1249 Literal = Val; 1250 return MCOperand::createImm(Literal); 1251 } 1252 1253 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1254 // For now all literal constants are supposed to be unsigned integer 1255 // ToDo: deal with signed/unsigned 64-bit integer constants 1256 // ToDo: deal with float/double constants 1257 if (!HasLiteral) { 1258 if (Bytes.size() < 4) { 1259 return errOperand(0, "cannot read literal, inst bytes left " + 1260 Twine(Bytes.size())); 1261 } 1262 HasLiteral = true; 1263 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1264 if (ExtendFP64) 1265 Literal64 <<= 32; 1266 } 1267 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1268 } 1269 1270 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1271 using namespace AMDGPU::EncValues; 1272 1273 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1274 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1275 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1276 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1277 // Cast prevents negative overflow. 1278 } 1279 1280 static int64_t getInlineImmVal32(unsigned Imm) { 1281 switch (Imm) { 1282 case 240: 1283 return llvm::bit_cast<uint32_t>(0.5f); 1284 case 241: 1285 return llvm::bit_cast<uint32_t>(-0.5f); 1286 case 242: 1287 return llvm::bit_cast<uint32_t>(1.0f); 1288 case 243: 1289 return llvm::bit_cast<uint32_t>(-1.0f); 1290 case 244: 1291 return llvm::bit_cast<uint32_t>(2.0f); 1292 case 245: 1293 return llvm::bit_cast<uint32_t>(-2.0f); 1294 case 246: 1295 return llvm::bit_cast<uint32_t>(4.0f); 1296 case 247: 1297 return llvm::bit_cast<uint32_t>(-4.0f); 1298 case 248: // 1 / (2 * PI) 1299 return 0x3e22f983; 1300 default: 1301 llvm_unreachable("invalid fp inline imm"); 1302 } 1303 } 1304 1305 static int64_t getInlineImmVal64(unsigned Imm) { 1306 switch (Imm) { 1307 case 240: 1308 return llvm::bit_cast<uint64_t>(0.5); 1309 case 241: 1310 return llvm::bit_cast<uint64_t>(-0.5); 1311 case 242: 1312 return llvm::bit_cast<uint64_t>(1.0); 1313 case 243: 1314 return llvm::bit_cast<uint64_t>(-1.0); 1315 case 244: 1316 return llvm::bit_cast<uint64_t>(2.0); 1317 case 245: 1318 return llvm::bit_cast<uint64_t>(-2.0); 1319 case 246: 1320 return llvm::bit_cast<uint64_t>(4.0); 1321 case 247: 1322 return llvm::bit_cast<uint64_t>(-4.0); 1323 case 248: // 1 / (2 * PI) 1324 return 0x3fc45f306dc9c882; 1325 default: 1326 llvm_unreachable("invalid fp inline imm"); 1327 } 1328 } 1329 1330 static int64_t getInlineImmVal16(unsigned Imm) { 1331 switch (Imm) { 1332 case 240: 1333 return 0x3800; 1334 case 241: 1335 return 0xB800; 1336 case 242: 1337 return 0x3C00; 1338 case 243: 1339 return 0xBC00; 1340 case 244: 1341 return 0x4000; 1342 case 245: 1343 return 0xC000; 1344 case 246: 1345 return 0x4400; 1346 case 247: 1347 return 0xC400; 1348 case 248: // 1 / (2 * PI) 1349 return 0x3118; 1350 default: 1351 llvm_unreachable("invalid fp inline imm"); 1352 } 1353 } 1354 1355 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1356 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1357 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1358 1359 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1360 // ImmWidth 0 is a default case where operand should not allow immediates. 1361 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1362 // use it to print verbose error message. 1363 switch (ImmWidth) { 1364 case 0: 1365 case 32: 1366 return MCOperand::createImm(getInlineImmVal32(Imm)); 1367 case 64: 1368 return MCOperand::createImm(getInlineImmVal64(Imm)); 1369 case 16: 1370 return MCOperand::createImm(getInlineImmVal16(Imm)); 1371 default: 1372 llvm_unreachable("implement me"); 1373 } 1374 } 1375 1376 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1377 using namespace AMDGPU; 1378 1379 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1380 switch (Width) { 1381 default: // fall 1382 case OPW32: 1383 case OPW16: 1384 case OPWV216: 1385 return VGPR_32RegClassID; 1386 case OPW64: 1387 case OPWV232: return VReg_64RegClassID; 1388 case OPW96: return VReg_96RegClassID; 1389 case OPW128: return VReg_128RegClassID; 1390 case OPW160: return VReg_160RegClassID; 1391 case OPW256: return VReg_256RegClassID; 1392 case OPW288: return VReg_288RegClassID; 1393 case OPW320: return VReg_320RegClassID; 1394 case OPW352: return VReg_352RegClassID; 1395 case OPW384: return VReg_384RegClassID; 1396 case OPW512: return VReg_512RegClassID; 1397 case OPW1024: return VReg_1024RegClassID; 1398 } 1399 } 1400 1401 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1402 using namespace AMDGPU; 1403 1404 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1405 switch (Width) { 1406 default: // fall 1407 case OPW32: 1408 case OPW16: 1409 case OPWV216: 1410 return AGPR_32RegClassID; 1411 case OPW64: 1412 case OPWV232: return AReg_64RegClassID; 1413 case OPW96: return AReg_96RegClassID; 1414 case OPW128: return AReg_128RegClassID; 1415 case OPW160: return AReg_160RegClassID; 1416 case OPW256: return AReg_256RegClassID; 1417 case OPW288: return AReg_288RegClassID; 1418 case OPW320: return AReg_320RegClassID; 1419 case OPW352: return AReg_352RegClassID; 1420 case OPW384: return AReg_384RegClassID; 1421 case OPW512: return AReg_512RegClassID; 1422 case OPW1024: return AReg_1024RegClassID; 1423 } 1424 } 1425 1426 1427 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1428 using namespace AMDGPU; 1429 1430 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1431 switch (Width) { 1432 default: // fall 1433 case OPW32: 1434 case OPW16: 1435 case OPWV216: 1436 return SGPR_32RegClassID; 1437 case OPW64: 1438 case OPWV232: return SGPR_64RegClassID; 1439 case OPW96: return SGPR_96RegClassID; 1440 case OPW128: return SGPR_128RegClassID; 1441 case OPW160: return SGPR_160RegClassID; 1442 case OPW256: return SGPR_256RegClassID; 1443 case OPW288: return SGPR_288RegClassID; 1444 case OPW320: return SGPR_320RegClassID; 1445 case OPW352: return SGPR_352RegClassID; 1446 case OPW384: return SGPR_384RegClassID; 1447 case OPW512: return SGPR_512RegClassID; 1448 } 1449 } 1450 1451 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1452 using namespace AMDGPU; 1453 1454 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1455 switch (Width) { 1456 default: // fall 1457 case OPW32: 1458 case OPW16: 1459 case OPWV216: 1460 return TTMP_32RegClassID; 1461 case OPW64: 1462 case OPWV232: return TTMP_64RegClassID; 1463 case OPW128: return TTMP_128RegClassID; 1464 case OPW256: return TTMP_256RegClassID; 1465 case OPW288: return TTMP_288RegClassID; 1466 case OPW320: return TTMP_320RegClassID; 1467 case OPW352: return TTMP_352RegClassID; 1468 case OPW384: return TTMP_384RegClassID; 1469 case OPW512: return TTMP_512RegClassID; 1470 } 1471 } 1472 1473 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1474 using namespace AMDGPU::EncValues; 1475 1476 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1477 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1478 1479 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1480 } 1481 1482 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1483 bool MandatoryLiteral, 1484 unsigned ImmWidth, bool IsFP) const { 1485 using namespace AMDGPU::EncValues; 1486 1487 assert(Val < 1024); // enum10 1488 1489 bool IsAGPR = Val & 512; 1490 Val &= 511; 1491 1492 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1493 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1494 : getVgprClassId(Width), Val - VGPR_MIN); 1495 } 1496 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1497 IsFP); 1498 } 1499 1500 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, 1501 unsigned Val, 1502 bool MandatoryLiteral, 1503 unsigned ImmWidth, 1504 bool IsFP) const { 1505 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1506 // decoded earlier. 1507 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1508 using namespace AMDGPU::EncValues; 1509 1510 if (Val <= SGPR_MAX) { 1511 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1512 static_assert(SGPR_MIN == 0); 1513 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1514 } 1515 1516 int TTmpIdx = getTTmpIdx(Val); 1517 if (TTmpIdx >= 0) { 1518 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1519 } 1520 1521 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1522 return decodeIntImmed(Val); 1523 1524 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1525 return decodeFPImmed(ImmWidth, Val); 1526 1527 if (Val == LITERAL_CONST) { 1528 if (MandatoryLiteral) 1529 // Keep a sentinel value for deferred setting 1530 return MCOperand::createImm(LITERAL_CONST); 1531 else 1532 return decodeLiteralConstant(IsFP && ImmWidth == 64); 1533 } 1534 1535 switch (Width) { 1536 case OPW32: 1537 case OPW16: 1538 case OPWV216: 1539 return decodeSpecialReg32(Val); 1540 case OPW64: 1541 case OPWV232: 1542 return decodeSpecialReg64(Val); 1543 default: 1544 llvm_unreachable("unexpected immediate type"); 1545 } 1546 } 1547 1548 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1549 // opposite of bit 0 of DstX. 1550 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1551 unsigned Val) const { 1552 int VDstXInd = 1553 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1554 assert(VDstXInd != -1); 1555 assert(Inst.getOperand(VDstXInd).isReg()); 1556 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1557 Val |= ~XDstReg & 1; 1558 auto Width = llvm::AMDGPUDisassembler::OPW32; 1559 return createRegOperand(getVgprClassId(Width), Val); 1560 } 1561 1562 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1563 using namespace AMDGPU; 1564 1565 switch (Val) { 1566 // clang-format off 1567 case 102: return createRegOperand(FLAT_SCR_LO); 1568 case 103: return createRegOperand(FLAT_SCR_HI); 1569 case 104: return createRegOperand(XNACK_MASK_LO); 1570 case 105: return createRegOperand(XNACK_MASK_HI); 1571 case 106: return createRegOperand(VCC_LO); 1572 case 107: return createRegOperand(VCC_HI); 1573 case 108: return createRegOperand(TBA_LO); 1574 case 109: return createRegOperand(TBA_HI); 1575 case 110: return createRegOperand(TMA_LO); 1576 case 111: return createRegOperand(TMA_HI); 1577 case 124: 1578 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1579 case 125: 1580 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1581 case 126: return createRegOperand(EXEC_LO); 1582 case 127: return createRegOperand(EXEC_HI); 1583 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1584 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1585 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1586 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1587 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1588 case 251: return createRegOperand(SRC_VCCZ); 1589 case 252: return createRegOperand(SRC_EXECZ); 1590 case 253: return createRegOperand(SRC_SCC); 1591 case 254: return createRegOperand(LDS_DIRECT); 1592 default: break; 1593 // clang-format on 1594 } 1595 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1596 } 1597 1598 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1599 using namespace AMDGPU; 1600 1601 switch (Val) { 1602 case 102: return createRegOperand(FLAT_SCR); 1603 case 104: return createRegOperand(XNACK_MASK); 1604 case 106: return createRegOperand(VCC); 1605 case 108: return createRegOperand(TBA); 1606 case 110: return createRegOperand(TMA); 1607 case 124: 1608 if (isGFX11Plus()) 1609 return createRegOperand(SGPR_NULL); 1610 break; 1611 case 125: 1612 if (!isGFX11Plus()) 1613 return createRegOperand(SGPR_NULL); 1614 break; 1615 case 126: return createRegOperand(EXEC); 1616 case 235: return createRegOperand(SRC_SHARED_BASE); 1617 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1618 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1619 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1620 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1621 case 251: return createRegOperand(SRC_VCCZ); 1622 case 252: return createRegOperand(SRC_EXECZ); 1623 case 253: return createRegOperand(SRC_SCC); 1624 default: break; 1625 } 1626 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1627 } 1628 1629 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1630 const unsigned Val, 1631 unsigned ImmWidth) const { 1632 using namespace AMDGPU::SDWA; 1633 using namespace AMDGPU::EncValues; 1634 1635 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1636 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1637 // XXX: cast to int is needed to avoid stupid warning: 1638 // compare with unsigned is always true 1639 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1640 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1641 return createRegOperand(getVgprClassId(Width), 1642 Val - SDWA9EncValues::SRC_VGPR_MIN); 1643 } 1644 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1645 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1646 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1647 return createSRegOperand(getSgprClassId(Width), 1648 Val - SDWA9EncValues::SRC_SGPR_MIN); 1649 } 1650 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1651 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1652 return createSRegOperand(getTtmpClassId(Width), 1653 Val - SDWA9EncValues::SRC_TTMP_MIN); 1654 } 1655 1656 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1657 1658 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1659 return decodeIntImmed(SVal); 1660 1661 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1662 return decodeFPImmed(ImmWidth, SVal); 1663 1664 return decodeSpecialReg32(SVal); 1665 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1666 return createRegOperand(getVgprClassId(Width), Val); 1667 } 1668 llvm_unreachable("unsupported target"); 1669 } 1670 1671 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1672 return decodeSDWASrc(OPW16, Val, 16); 1673 } 1674 1675 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1676 return decodeSDWASrc(OPW32, Val, 32); 1677 } 1678 1679 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1680 using namespace AMDGPU::SDWA; 1681 1682 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1683 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1684 "SDWAVopcDst should be present only on GFX9+"); 1685 1686 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1687 1688 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1689 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1690 1691 int TTmpIdx = getTTmpIdx(Val); 1692 if (TTmpIdx >= 0) { 1693 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1694 return createSRegOperand(TTmpClsId, TTmpIdx); 1695 } else if (Val > SGPR_MAX) { 1696 return IsWave64 ? decodeSpecialReg64(Val) 1697 : decodeSpecialReg32(Val); 1698 } else { 1699 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1700 } 1701 } else { 1702 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1703 } 1704 } 1705 1706 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1707 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1708 ? decodeSrcOp(OPW64, Val) 1709 : decodeSrcOp(OPW32, Val); 1710 } 1711 1712 bool AMDGPUDisassembler::isVI() const { 1713 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1714 } 1715 1716 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1717 1718 bool AMDGPUDisassembler::isGFX90A() const { 1719 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1720 } 1721 1722 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1723 1724 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1725 1726 bool AMDGPUDisassembler::isGFX10Plus() const { 1727 return AMDGPU::isGFX10Plus(STI); 1728 } 1729 1730 bool AMDGPUDisassembler::isGFX11() const { 1731 return STI.hasFeature(AMDGPU::FeatureGFX11); 1732 } 1733 1734 bool AMDGPUDisassembler::isGFX11Plus() const { 1735 return AMDGPU::isGFX11Plus(STI); 1736 } 1737 1738 bool AMDGPUDisassembler::isGFX12Plus() const { 1739 return AMDGPU::isGFX12Plus(STI); 1740 } 1741 1742 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1743 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1744 } 1745 1746 bool AMDGPUDisassembler::hasKernargPreload() const { 1747 return AMDGPU::hasKernargPreload(STI); 1748 } 1749 1750 //===----------------------------------------------------------------------===// 1751 // AMDGPU specific symbol handling 1752 //===----------------------------------------------------------------------===// 1753 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1754 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1755 do { \ 1756 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1757 } while (0) 1758 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1759 do { \ 1760 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1761 << GET_FIELD(MASK) << '\n'; \ 1762 } while (0) 1763 1764 // NOLINTNEXTLINE(readability-identifier-naming) 1765 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1766 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1767 using namespace amdhsa; 1768 StringRef Indent = "\t"; 1769 1770 // We cannot accurately backward compute #VGPRs used from 1771 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1772 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1773 // simply calculate the inverse of what the assembler does. 1774 1775 uint32_t GranulatedWorkitemVGPRCount = 1776 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1777 1778 uint32_t NextFreeVGPR = 1779 (GranulatedWorkitemVGPRCount + 1) * 1780 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1781 1782 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1783 1784 // We cannot backward compute values used to calculate 1785 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1786 // directives can't be computed: 1787 // .amdhsa_reserve_vcc 1788 // .amdhsa_reserve_flat_scratch 1789 // .amdhsa_reserve_xnack_mask 1790 // They take their respective default values if not specified in the assembly. 1791 // 1792 // GRANULATED_WAVEFRONT_SGPR_COUNT 1793 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1794 // 1795 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1796 // are set to 0. So while disassembling we consider that: 1797 // 1798 // GRANULATED_WAVEFRONT_SGPR_COUNT 1799 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1800 // 1801 // The disassembler cannot recover the original values of those 3 directives. 1802 1803 uint32_t GranulatedWavefrontSGPRCount = 1804 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1805 1806 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1807 return MCDisassembler::Fail; 1808 1809 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1810 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1811 1812 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1813 if (!hasArchitectedFlatScratch()) 1814 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1815 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1816 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1817 1818 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1819 return MCDisassembler::Fail; 1820 1821 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1822 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1823 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1824 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1825 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1826 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1827 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1828 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1829 1830 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1831 return MCDisassembler::Fail; 1832 1833 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1834 1835 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1836 return MCDisassembler::Fail; 1837 1838 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1839 1840 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1841 return MCDisassembler::Fail; 1842 1843 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1844 return MCDisassembler::Fail; 1845 1846 if (isGFX9Plus()) 1847 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1848 1849 if (!isGFX9Plus()) 1850 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1851 return MCDisassembler::Fail; 1852 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1853 return MCDisassembler::Fail; 1854 if (!isGFX10Plus()) 1855 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1856 return MCDisassembler::Fail; 1857 1858 if (isGFX10Plus()) { 1859 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1860 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1861 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1862 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1863 } 1864 return MCDisassembler::Success; 1865 } 1866 1867 // NOLINTNEXTLINE(readability-identifier-naming) 1868 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1869 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1870 using namespace amdhsa; 1871 StringRef Indent = "\t"; 1872 if (hasArchitectedFlatScratch()) 1873 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1874 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1875 else 1876 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1877 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1878 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1879 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1880 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1881 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1882 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1883 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1884 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1885 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1886 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1887 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1888 1889 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1890 return MCDisassembler::Fail; 1891 1892 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1893 return MCDisassembler::Fail; 1894 1895 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1896 return MCDisassembler::Fail; 1897 1898 PRINT_DIRECTIVE( 1899 ".amdhsa_exception_fp_ieee_invalid_op", 1900 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1901 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1902 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1903 PRINT_DIRECTIVE( 1904 ".amdhsa_exception_fp_ieee_div_zero", 1905 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1906 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1907 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1908 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1909 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1910 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1911 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1912 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1913 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1914 1915 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1916 return MCDisassembler::Fail; 1917 1918 return MCDisassembler::Success; 1919 } 1920 1921 // NOLINTNEXTLINE(readability-identifier-naming) 1922 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 1923 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1924 using namespace amdhsa; 1925 StringRef Indent = "\t"; 1926 if (isGFX90A()) { 1927 KdStream << Indent << ".amdhsa_accum_offset " 1928 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 1929 << '\n'; 1930 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 1931 return MCDisassembler::Fail; 1932 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 1933 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 1934 return MCDisassembler::Fail; 1935 } else if (isGFX10Plus()) { 1936 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 1937 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 1938 COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1939 } else { 1940 PRINT_PSEUDO_DIRECTIVE_COMMENT( 1941 "SHARED_VGPR_COUNT", COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1942 } 1943 1944 if (isGFX11Plus()) { 1945 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 1946 COMPUTE_PGM_RSRC3_GFX11_PLUS_INST_PREF_SIZE); 1947 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 1948 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 1949 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 1950 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_END); 1951 } else { 1952 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED0) 1953 return MCDisassembler::Fail; 1954 } 1955 1956 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED1) 1957 return MCDisassembler::Fail; 1958 1959 if (isGFX11Plus()) { 1960 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 1961 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 1962 } else { 1963 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED2) 1964 return MCDisassembler::Fail; 1965 } 1966 } else if (FourByteBuffer) { 1967 return MCDisassembler::Fail; 1968 } 1969 return MCDisassembler::Success; 1970 } 1971 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 1972 #undef PRINT_DIRECTIVE 1973 #undef GET_FIELD 1974 1975 MCDisassembler::DecodeStatus 1976 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1977 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1978 raw_string_ostream &KdStream) const { 1979 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1980 do { \ 1981 KdStream << Indent << DIRECTIVE " " \ 1982 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1983 } while (0) 1984 1985 uint16_t TwoByteBuffer = 0; 1986 uint32_t FourByteBuffer = 0; 1987 1988 StringRef ReservedBytes; 1989 StringRef Indent = "\t"; 1990 1991 assert(Bytes.size() == 64); 1992 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1993 1994 switch (Cursor.tell()) { 1995 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1996 FourByteBuffer = DE.getU32(Cursor); 1997 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1998 << '\n'; 1999 return MCDisassembler::Success; 2000 2001 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2002 FourByteBuffer = DE.getU32(Cursor); 2003 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2004 << FourByteBuffer << '\n'; 2005 return MCDisassembler::Success; 2006 2007 case amdhsa::KERNARG_SIZE_OFFSET: 2008 FourByteBuffer = DE.getU32(Cursor); 2009 KdStream << Indent << ".amdhsa_kernarg_size " 2010 << FourByteBuffer << '\n'; 2011 return MCDisassembler::Success; 2012 2013 case amdhsa::RESERVED0_OFFSET: 2014 // 4 reserved bytes, must be 0. 2015 ReservedBytes = DE.getBytes(Cursor, 4); 2016 for (int I = 0; I < 4; ++I) { 2017 if (ReservedBytes[I] != 0) { 2018 return MCDisassembler::Fail; 2019 } 2020 } 2021 return MCDisassembler::Success; 2022 2023 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2024 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2025 // So far no directive controls this for Code Object V3, so simply skip for 2026 // disassembly. 2027 DE.skip(Cursor, 8); 2028 return MCDisassembler::Success; 2029 2030 case amdhsa::RESERVED1_OFFSET: 2031 // 20 reserved bytes, must be 0. 2032 ReservedBytes = DE.getBytes(Cursor, 20); 2033 for (int I = 0; I < 20; ++I) { 2034 if (ReservedBytes[I] != 0) { 2035 return MCDisassembler::Fail; 2036 } 2037 } 2038 return MCDisassembler::Success; 2039 2040 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2041 FourByteBuffer = DE.getU32(Cursor); 2042 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2043 2044 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2045 FourByteBuffer = DE.getU32(Cursor); 2046 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2047 2048 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2049 FourByteBuffer = DE.getU32(Cursor); 2050 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2051 2052 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2053 using namespace amdhsa; 2054 TwoByteBuffer = DE.getU16(Cursor); 2055 2056 if (!hasArchitectedFlatScratch()) 2057 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2058 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2059 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2060 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2061 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2062 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2063 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2064 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2065 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2066 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2067 if (!hasArchitectedFlatScratch()) 2068 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2069 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2070 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2071 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2072 2073 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2074 return MCDisassembler::Fail; 2075 2076 // Reserved for GFX9 2077 if (isGFX9() && 2078 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2079 return MCDisassembler::Fail; 2080 } else if (isGFX10Plus()) { 2081 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2082 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2083 } 2084 2085 if (AMDGPU::getAmdhsaCodeObjectVersion() >= AMDGPU::AMDHSA_COV5) 2086 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2087 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2088 2089 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2090 return MCDisassembler::Fail; 2091 2092 return MCDisassembler::Success; 2093 2094 case amdhsa::KERNARG_PRELOAD_OFFSET: 2095 using namespace amdhsa; 2096 TwoByteBuffer = DE.getU16(Cursor); 2097 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2098 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2099 KERNARG_PRELOAD_SPEC_LENGTH); 2100 } 2101 2102 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2103 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2104 KERNARG_PRELOAD_SPEC_OFFSET); 2105 } 2106 return MCDisassembler::Success; 2107 2108 case amdhsa::RESERVED3_OFFSET: 2109 // 4 bytes from here are reserved, must be 0. 2110 ReservedBytes = DE.getBytes(Cursor, 4); 2111 for (int I = 0; I < 4; ++I) { 2112 if (ReservedBytes[I] != 0) 2113 return MCDisassembler::Fail; 2114 } 2115 return MCDisassembler::Success; 2116 2117 default: 2118 llvm_unreachable("Unhandled index. Case statements cover everything."); 2119 return MCDisassembler::Fail; 2120 } 2121 #undef PRINT_DIRECTIVE 2122 } 2123 2124 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2125 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2126 // CP microcode requires the kernel descriptor to be 64 aligned. 2127 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2128 return MCDisassembler::Fail; 2129 2130 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2131 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2132 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2133 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2134 // when required. 2135 if (isGFX10Plus()) { 2136 uint16_t KernelCodeProperties = 2137 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2138 llvm::endianness::little); 2139 EnableWavefrontSize32 = 2140 AMDHSA_BITS_GET(KernelCodeProperties, 2141 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2142 } 2143 2144 std::string Kd; 2145 raw_string_ostream KdStream(Kd); 2146 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2147 2148 DataExtractor::Cursor C(0); 2149 while (C && C.tell() < Bytes.size()) { 2150 MCDisassembler::DecodeStatus Status = 2151 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2152 2153 cantFail(C.takeError()); 2154 2155 if (Status == MCDisassembler::Fail) 2156 return MCDisassembler::Fail; 2157 } 2158 KdStream << ".end_amdhsa_kernel\n"; 2159 outs() << KdStream.str(); 2160 return MCDisassembler::Success; 2161 } 2162 2163 std::optional<MCDisassembler::DecodeStatus> 2164 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2165 ArrayRef<uint8_t> Bytes, uint64_t Address, 2166 raw_ostream &CStream) const { 2167 // Right now only kernel descriptor needs to be handled. 2168 // We ignore all other symbols for target specific handling. 2169 // TODO: 2170 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2171 // Object V2 and V3 when symbols are marked protected. 2172 2173 // amd_kernel_code_t for Code Object V2. 2174 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2175 Size = 256; 2176 return MCDisassembler::Fail; 2177 } 2178 2179 // Code Object V3 kernel descriptors. 2180 StringRef Name = Symbol.Name; 2181 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2182 Size = 64; // Size = 64 regardless of success or failure. 2183 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2184 } 2185 return std::nullopt; 2186 } 2187 2188 //===----------------------------------------------------------------------===// 2189 // AMDGPUSymbolizer 2190 //===----------------------------------------------------------------------===// 2191 2192 // Try to find symbol name for specified label 2193 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2194 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2195 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2196 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2197 2198 if (!IsBranch) { 2199 return false; 2200 } 2201 2202 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2203 if (!Symbols) 2204 return false; 2205 2206 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2207 return Val.Addr == static_cast<uint64_t>(Value) && 2208 Val.Type == ELF::STT_NOTYPE; 2209 }); 2210 if (Result != Symbols->end()) { 2211 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2212 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2213 Inst.addOperand(MCOperand::createExpr(Add)); 2214 return true; 2215 } 2216 // Add to list of referenced addresses, so caller can synthesize a label. 2217 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2218 return false; 2219 } 2220 2221 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2222 int64_t Value, 2223 uint64_t Address) { 2224 llvm_unreachable("unimplemented"); 2225 } 2226 2227 //===----------------------------------------------------------------------===// 2228 // Initialization 2229 //===----------------------------------------------------------------------===// 2230 2231 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2232 LLVMOpInfoCallback /*GetOpInfo*/, 2233 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2234 void *DisInfo, 2235 MCContext *Ctx, 2236 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2237 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2238 } 2239 2240 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2241 const MCSubtargetInfo &STI, 2242 MCContext &Ctx) { 2243 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2244 } 2245 2246 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2247 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2248 createAMDGPUDisassembler); 2249 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2250 createAMDGPUSymbolizer); 2251 } 2252