1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "TargetInfo/AMDGPUTargetInfo.h" 22 #include "Utils/AMDGPUBaseInfo.h" 23 #include "llvm-c/DisassemblerTypes.h" 24 #include "llvm/BinaryFormat/ELF.h" 25 #include "llvm/MC/MCAsmInfo.h" 26 #include "llvm/MC/MCContext.h" 27 #include "llvm/MC/MCDecoderOps.h" 28 #include "llvm/MC/MCExpr.h" 29 #include "llvm/MC/MCInstrDesc.h" 30 #include "llvm/MC/MCRegisterInfo.h" 31 #include "llvm/MC/MCSubtargetInfo.h" 32 #include "llvm/MC/TargetRegistry.h" 33 #include "llvm/Support/AMDHSAKernelDescriptor.h" 34 35 using namespace llvm; 36 37 #define DEBUG_TYPE "amdgpu-disassembler" 38 39 #define SGPR_MAX \ 40 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 41 : AMDGPU::EncValues::SGPR_MAX_SI) 42 43 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 44 45 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 46 MCContext &Ctx, 47 MCInstrInfo const *MCII) : 48 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 49 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 50 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 95 Offset = Imm & 0xFFFFF; 96 } else { // GFX9+ supports 21-bit signed offsets. 97 Offset = SignExtend64<21>(Imm); 98 } 99 return addOperand(Inst, MCOperand::createImm(Offset)); 100 } 101 102 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 103 const MCDisassembler *Decoder) { 104 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 105 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 106 } 107 108 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 109 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 110 uint64_t /*Addr*/, \ 111 const MCDisassembler *Decoder) { \ 112 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 113 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 114 } 115 116 #define DECODE_OPERAND_REG(RegClass) \ 117 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 118 119 DECODE_OPERAND_REG(VGPR_32) 120 DECODE_OPERAND_REG(VRegOrLds_32) 121 DECODE_OPERAND_REG(VS_32) 122 DECODE_OPERAND_REG(VS_64) 123 DECODE_OPERAND_REG(VS_128) 124 125 DECODE_OPERAND_REG(VReg_64) 126 DECODE_OPERAND_REG(VReg_96) 127 DECODE_OPERAND_REG(VReg_128) 128 DECODE_OPERAND_REG(VReg_256) 129 DECODE_OPERAND_REG(VReg_512) 130 DECODE_OPERAND_REG(VReg_1024) 131 132 DECODE_OPERAND_REG(SReg_32) 133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 135 DECODE_OPERAND_REG(SRegOrLds_32) 136 DECODE_OPERAND_REG(SReg_64) 137 DECODE_OPERAND_REG(SReg_64_XEXEC) 138 DECODE_OPERAND_REG(SReg_128) 139 DECODE_OPERAND_REG(SReg_256) 140 DECODE_OPERAND_REG(SReg_512) 141 142 DECODE_OPERAND_REG(AGPR_32) 143 DECODE_OPERAND_REG(AReg_64) 144 DECODE_OPERAND_REG(AReg_128) 145 DECODE_OPERAND_REG(AReg_256) 146 DECODE_OPERAND_REG(AReg_512) 147 DECODE_OPERAND_REG(AReg_1024) 148 DECODE_OPERAND_REG(AV_32) 149 DECODE_OPERAND_REG(AV_64) 150 DECODE_OPERAND_REG(AV_128) 151 DECODE_OPERAND_REG(AVDst_128) 152 DECODE_OPERAND_REG(AVDst_512) 153 154 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 155 uint64_t Addr, 156 const MCDisassembler *Decoder) { 157 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 158 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 159 } 160 161 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 162 uint64_t Addr, 163 const MCDisassembler *Decoder) { 164 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 165 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 166 } 167 168 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 169 uint64_t Addr, 170 const MCDisassembler *Decoder) { 171 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 172 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 173 } 174 175 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 176 uint64_t Addr, 177 const MCDisassembler *Decoder) { 178 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 179 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 180 } 181 182 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 183 uint64_t Addr, 184 const MCDisassembler *Decoder) { 185 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 186 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 187 } 188 189 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 190 uint64_t Addr, 191 const MCDisassembler *Decoder) { 192 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 193 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 194 } 195 196 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 197 uint64_t Addr, 198 const MCDisassembler *Decoder) { 199 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 200 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 201 } 202 203 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 204 uint64_t Addr, 205 const MCDisassembler *Decoder) { 206 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 207 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 208 } 209 210 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 211 uint64_t Addr, 212 const MCDisassembler *Decoder) { 213 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 214 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 215 } 216 217 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 218 uint64_t Addr, 219 const MCDisassembler *Decoder) { 220 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 221 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 222 } 223 224 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 225 uint64_t Addr, 226 const MCDisassembler *Decoder) { 227 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 228 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 229 } 230 231 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 232 uint64_t Addr, 233 const MCDisassembler *Decoder) { 234 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 235 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 236 } 237 238 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 239 uint64_t Addr, 240 const MCDisassembler *Decoder) { 241 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 242 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 243 } 244 245 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 246 uint64_t Addr, 247 const MCDisassembler *Decoder) { 248 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 249 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 250 } 251 252 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 253 uint64_t Addr, 254 const MCDisassembler *Decoder) { 255 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 256 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 257 } 258 259 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 260 uint64_t Addr, 261 const MCDisassembler *Decoder) { 262 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 263 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 264 } 265 266 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 267 uint64_t Addr, 268 const MCDisassembler *Decoder) { 269 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 270 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 271 } 272 273 static DecodeStatus 274 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 275 const MCDisassembler *Decoder) { 276 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 277 return addOperand( 278 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 279 } 280 281 static DecodeStatus 282 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 283 const MCDisassembler *Decoder) { 284 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 285 return addOperand( 286 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 287 } 288 289 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 290 const MCRegisterInfo *MRI) { 291 if (OpIdx < 0) 292 return false; 293 294 const MCOperand &Op = Inst.getOperand(OpIdx); 295 if (!Op.isReg()) 296 return false; 297 298 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 299 auto Reg = Sub ? Sub : Op.getReg(); 300 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 301 } 302 303 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 304 AMDGPUDisassembler::OpWidthTy Opw, 305 const MCDisassembler *Decoder) { 306 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 307 if (!DAsm->isGFX90A()) { 308 Imm &= 511; 309 } else { 310 // If atomic has both vdata and vdst their register classes are tied. 311 // The bit is decoded along with the vdst, first operand. We need to 312 // change register class to AGPR if vdst was AGPR. 313 // If a DS instruction has both data0 and data1 their register classes 314 // are also tied. 315 unsigned Opc = Inst.getOpcode(); 316 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 317 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 318 : AMDGPU::OpName::vdata; 319 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 320 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 321 if ((int)Inst.getNumOperands() == DataIdx) { 322 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 323 if (IsAGPROperand(Inst, DstIdx, MRI)) 324 Imm |= 512; 325 } 326 327 if (TSFlags & SIInstrFlags::DS) { 328 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 329 if ((int)Inst.getNumOperands() == Data2Idx && 330 IsAGPROperand(Inst, DataIdx, MRI)) 331 Imm |= 512; 332 } 333 } 334 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 335 } 336 337 static DecodeStatus 338 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 339 const MCDisassembler *Decoder) { 340 return decodeOperand_AVLdSt_Any(Inst, Imm, 341 AMDGPUDisassembler::OPW32, Decoder); 342 } 343 344 static DecodeStatus 345 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 346 const MCDisassembler *Decoder) { 347 return decodeOperand_AVLdSt_Any(Inst, Imm, 348 AMDGPUDisassembler::OPW64, Decoder); 349 } 350 351 static DecodeStatus 352 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 353 const MCDisassembler *Decoder) { 354 return decodeOperand_AVLdSt_Any(Inst, Imm, 355 AMDGPUDisassembler::OPW96, Decoder); 356 } 357 358 static DecodeStatus 359 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 360 const MCDisassembler *Decoder) { 361 return decodeOperand_AVLdSt_Any(Inst, Imm, 362 AMDGPUDisassembler::OPW128, Decoder); 363 } 364 365 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 366 uint64_t Addr, 367 const MCDisassembler *Decoder) { 368 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 369 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 370 } 371 372 #define DECODE_SDWA(DecName) \ 373 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 374 375 DECODE_SDWA(Src32) 376 DECODE_SDWA(Src16) 377 DECODE_SDWA(VopcDst) 378 379 #include "AMDGPUGenDisassemblerTables.inc" 380 381 //===----------------------------------------------------------------------===// 382 // 383 //===----------------------------------------------------------------------===// 384 385 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 386 assert(Bytes.size() >= sizeof(T)); 387 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 388 Bytes = Bytes.slice(sizeof(T)); 389 return Res; 390 } 391 392 // The disassembler is greedy, so we need to check FI operand value to 393 // not parse a dpp if the correct literal is not set. For dpp16 the 394 // autogenerated decoder checks the dpp literal 395 static bool isValidDPP8(const MCInst &MI) { 396 using namespace llvm::AMDGPU::DPP; 397 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 398 assert(FiIdx != -1); 399 if ((unsigned)FiIdx >= MI.getNumOperands()) 400 return false; 401 unsigned Fi = MI.getOperand(FiIdx).getImm(); 402 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 403 } 404 405 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 406 ArrayRef<uint8_t> Bytes_, 407 uint64_t Address, 408 raw_ostream &CS) const { 409 CommentStream = &CS; 410 bool IsSDWA = false; 411 412 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 413 Bytes = Bytes_.slice(0, MaxInstBytesNum); 414 415 DecodeStatus Res = MCDisassembler::Fail; 416 do { 417 // ToDo: better to switch encoding length using some bit predicate 418 // but it is unknown yet, so try all we can 419 420 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 421 // encodings 422 if (Bytes.size() >= 8) { 423 const uint64_t QW = eatBytes<uint64_t>(Bytes); 424 425 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 426 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 427 if (Res) { 428 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 429 == -1) 430 break; 431 if (convertDPP8Inst(MI) == MCDisassembler::Success) 432 break; 433 MI = MCInst(); // clear 434 } 435 } 436 437 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 438 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 439 break; 440 441 MI = MCInst(); // clear 442 443 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 444 if (Res) break; 445 446 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 447 if (Res) { IsSDWA = true; break; } 448 449 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 450 if (Res) { IsSDWA = true; break; } 451 452 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 453 if (Res) { IsSDWA = true; break; } 454 455 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 456 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 457 if (Res) 458 break; 459 } 460 461 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 462 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 463 // table first so we print the correct name. 464 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 465 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 466 if (Res) 467 break; 468 } 469 } 470 471 // Reinitialize Bytes as DPP64 could have eaten too much 472 Bytes = Bytes_.slice(0, MaxInstBytesNum); 473 474 // Try decode 32-bit instruction 475 if (Bytes.size() < 4) break; 476 const uint32_t DW = eatBytes<uint32_t>(Bytes); 477 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 478 if (Res) break; 479 480 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 481 if (Res) break; 482 483 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 484 if (Res) break; 485 486 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 487 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 488 if (Res) 489 break; 490 } 491 492 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 493 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 494 if (Res) break; 495 } 496 497 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 498 if (Res) break; 499 500 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 501 if (Res) break; 502 503 if (Bytes.size() < 4) break; 504 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 505 506 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 507 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 508 if (Res) 509 break; 510 } 511 512 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 513 if (Res) break; 514 515 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 516 if (Res) break; 517 518 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 519 if (Res) break; 520 521 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 522 if (Res) break; 523 524 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 525 } while (false); 526 527 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 528 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 529 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 530 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 531 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 532 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 533 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 534 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 535 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 536 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 537 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) { 538 // Insert dummy unused src2_modifiers. 539 insertNamedMCOperand(MI, MCOperand::createImm(0), 540 AMDGPU::OpName::src2_modifiers); 541 } 542 543 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 544 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 545 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 546 AMDGPU::OpName::cpol); 547 if (CPolPos != -1) { 548 unsigned CPol = 549 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 550 AMDGPU::CPol::GLC : 0; 551 if (MI.getNumOperands() <= (unsigned)CPolPos) { 552 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 553 AMDGPU::OpName::cpol); 554 } else if (CPol) { 555 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 556 } 557 } 558 } 559 560 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 561 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 562 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 563 // GFX90A lost TFE, its place is occupied by ACC. 564 int TFEOpIdx = 565 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 566 if (TFEOpIdx != -1) { 567 auto TFEIter = MI.begin(); 568 std::advance(TFEIter, TFEOpIdx); 569 MI.insert(TFEIter, MCOperand::createImm(0)); 570 } 571 } 572 573 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 574 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 575 int SWZOpIdx = 576 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 577 if (SWZOpIdx != -1) { 578 auto SWZIter = MI.begin(); 579 std::advance(SWZIter, SWZOpIdx); 580 MI.insert(SWZIter, MCOperand::createImm(0)); 581 } 582 } 583 584 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 585 int VAddr0Idx = 586 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 587 int RsrcIdx = 588 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 589 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 590 if (VAddr0Idx >= 0 && NSAArgs > 0) { 591 unsigned NSAWords = (NSAArgs + 3) / 4; 592 if (Bytes.size() < 4 * NSAWords) { 593 Res = MCDisassembler::Fail; 594 } else { 595 for (unsigned i = 0; i < NSAArgs; ++i) { 596 MI.insert(MI.begin() + VAddr0Idx + 1 + i, 597 decodeOperand_VGPR_32(Bytes[i])); 598 } 599 Bytes = Bytes.slice(4 * NSAWords); 600 } 601 } 602 603 if (Res) 604 Res = convertMIMGInst(MI); 605 } 606 607 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 608 Res = convertEXPInst(MI); 609 610 if (Res && IsSDWA) 611 Res = convertSDWAInst(MI); 612 613 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 614 AMDGPU::OpName::vdst_in); 615 if (VDstIn_Idx != -1) { 616 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 617 MCOI::OperandConstraint::TIED_TO); 618 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 619 !MI.getOperand(VDstIn_Idx).isReg() || 620 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 621 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 622 MI.erase(&MI.getOperand(VDstIn_Idx)); 623 insertNamedMCOperand(MI, 624 MCOperand::createReg(MI.getOperand(Tied).getReg()), 625 AMDGPU::OpName::vdst_in); 626 } 627 } 628 629 int ImmLitIdx = 630 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 631 if (Res && ImmLitIdx != -1) 632 Res = convertFMAanyK(MI, ImmLitIdx); 633 634 // if the opcode was not recognized we'll assume a Size of 4 bytes 635 // (unless there are fewer bytes left) 636 Size = Res ? (MaxInstBytesNum - Bytes.size()) 637 : std::min((size_t)4, Bytes_.size()); 638 return Res; 639 } 640 641 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 642 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 643 // The MCInst still has these fields even though they are no longer encoded 644 // in the GFX11 instruction. 645 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 646 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 647 } 648 return MCDisassembler::Success; 649 } 650 651 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 652 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 653 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 654 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 655 // VOPC - insert clamp 656 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 657 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 658 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 659 if (SDst != -1) { 660 // VOPC - insert VCC register as sdst 661 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 662 AMDGPU::OpName::sdst); 663 } else { 664 // VOP1/2 - insert omod if present in instruction 665 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 666 } 667 } 668 return MCDisassembler::Success; 669 } 670 671 // We must check FI == literal to reject not genuine dpp8 insts, and we must 672 // first add optional MI operands to check FI 673 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 674 unsigned Opc = MI.getOpcode(); 675 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 676 677 // Insert dummy unused src modifiers. 678 if (MI.getNumOperands() < DescNumOps && 679 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 680 insertNamedMCOperand(MI, MCOperand::createImm(0), 681 AMDGPU::OpName::src0_modifiers); 682 683 if (MI.getNumOperands() < DescNumOps && 684 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 685 insertNamedMCOperand(MI, MCOperand::createImm(0), 686 AMDGPU::OpName::src1_modifiers); 687 688 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 689 } 690 691 // Note that before gfx10, the MIMG encoding provided no information about 692 // VADDR size. Consequently, decoded instructions always show address as if it 693 // has 1 dword, which could be not really so. 694 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 695 696 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 697 AMDGPU::OpName::vdst); 698 699 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 700 AMDGPU::OpName::vdata); 701 int VAddr0Idx = 702 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 703 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 704 AMDGPU::OpName::dmask); 705 706 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 707 AMDGPU::OpName::tfe); 708 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 709 AMDGPU::OpName::d16); 710 711 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 712 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 713 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 714 715 assert(VDataIdx != -1); 716 if (BaseOpcode->BVH) { 717 // Add A16 operand for intersect_ray instructions 718 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 719 addOperand(MI, MCOperand::createImm(1)); 720 } 721 return MCDisassembler::Success; 722 } 723 724 bool IsAtomic = (VDstIdx != -1); 725 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 726 bool IsNSA = false; 727 unsigned AddrSize = Info->VAddrDwords; 728 729 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 730 unsigned DimIdx = 731 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 732 int A16Idx = 733 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 734 const AMDGPU::MIMGDimInfo *Dim = 735 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 736 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 737 738 AddrSize = 739 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 740 741 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA; 742 if (!IsNSA) { 743 if (AddrSize > 8) 744 AddrSize = 16; 745 } else { 746 if (AddrSize > Info->VAddrDwords) { 747 // The NSA encoding does not contain enough operands for the combination 748 // of base opcode / dimension. Should this be an error? 749 return MCDisassembler::Success; 750 } 751 } 752 } 753 754 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 755 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 756 757 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 758 if (D16 && AMDGPU::hasPackedD16(STI)) { 759 DstSize = (DstSize + 1) / 2; 760 } 761 762 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 763 DstSize += 1; 764 765 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 766 return MCDisassembler::Success; 767 768 int NewOpcode = 769 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 770 if (NewOpcode == -1) 771 return MCDisassembler::Success; 772 773 // Widen the register to the correct number of enabled channels. 774 unsigned NewVdata = AMDGPU::NoRegister; 775 if (DstSize != Info->VDataDwords) { 776 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 777 778 // Get first subregister of VData 779 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 780 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 781 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 782 783 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 784 &MRI.getRegClass(DataRCID)); 785 if (NewVdata == AMDGPU::NoRegister) { 786 // It's possible to encode this such that the low register + enabled 787 // components exceeds the register count. 788 return MCDisassembler::Success; 789 } 790 } 791 792 unsigned NewVAddr0 = AMDGPU::NoRegister; 793 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA && 794 AddrSize != Info->VAddrDwords) { 795 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 796 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 797 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 798 799 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 800 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 801 &MRI.getRegClass(AddrRCID)); 802 if (NewVAddr0 == AMDGPU::NoRegister) 803 return MCDisassembler::Success; 804 } 805 806 MI.setOpcode(NewOpcode); 807 808 if (NewVdata != AMDGPU::NoRegister) { 809 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 810 811 if (IsAtomic) { 812 // Atomic operations have an additional operand (a copy of data) 813 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 814 } 815 } 816 817 if (NewVAddr0 != AMDGPU::NoRegister) { 818 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 819 } else if (IsNSA) { 820 assert(AddrSize <= Info->VAddrDwords); 821 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 822 MI.begin() + VAddr0Idx + Info->VAddrDwords); 823 } 824 825 return MCDisassembler::Success; 826 } 827 828 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 829 int ImmLitIdx) const { 830 assert(HasLiteral && "Should have decoded a literal"); 831 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 832 unsigned DescNumOps = Desc.getNumOperands(); 833 assert(DescNumOps == MI.getNumOperands()); 834 for (unsigned I = 0; I < DescNumOps; ++I) { 835 auto &Op = MI.getOperand(I); 836 auto OpType = Desc.OpInfo[I].OperandType; 837 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 838 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 839 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 840 IsDeferredOp) 841 Op.setImm(Literal); 842 } 843 return MCDisassembler::Success; 844 } 845 846 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 847 return getContext().getRegisterInfo()-> 848 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 849 } 850 851 inline 852 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 853 const Twine& ErrMsg) const { 854 *CommentStream << "Error: " + ErrMsg; 855 856 // ToDo: add support for error operands to MCInst.h 857 // return MCOperand::createError(V); 858 return MCOperand(); 859 } 860 861 inline 862 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 863 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 864 } 865 866 inline 867 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 868 unsigned Val) const { 869 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 870 if (Val >= RegCl.getNumRegs()) 871 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 872 ": unknown register " + Twine(Val)); 873 return createRegOperand(RegCl.getRegister(Val)); 874 } 875 876 inline 877 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 878 unsigned Val) const { 879 // ToDo: SI/CI have 104 SGPRs, VI - 102 880 // Valery: here we accepting as much as we can, let assembler sort it out 881 int shift = 0; 882 switch (SRegClassID) { 883 case AMDGPU::SGPR_32RegClassID: 884 case AMDGPU::TTMP_32RegClassID: 885 break; 886 case AMDGPU::SGPR_64RegClassID: 887 case AMDGPU::TTMP_64RegClassID: 888 shift = 1; 889 break; 890 case AMDGPU::SGPR_128RegClassID: 891 case AMDGPU::TTMP_128RegClassID: 892 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 893 // this bundle? 894 case AMDGPU::SGPR_256RegClassID: 895 case AMDGPU::TTMP_256RegClassID: 896 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 897 // this bundle? 898 case AMDGPU::SGPR_512RegClassID: 899 case AMDGPU::TTMP_512RegClassID: 900 shift = 2; 901 break; 902 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 903 // this bundle? 904 default: 905 llvm_unreachable("unhandled register class"); 906 } 907 908 if (Val % (1 << shift)) { 909 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 910 << ": scalar reg isn't aligned " << Val; 911 } 912 913 return createRegOperand(SRegClassID, Val >> shift); 914 } 915 916 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 917 return decodeSrcOp(OPW32, Val); 918 } 919 920 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 921 return decodeSrcOp(OPW64, Val); 922 } 923 924 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 925 return decodeSrcOp(OPW128, Val); 926 } 927 928 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 929 return decodeSrcOp(OPW16, Val); 930 } 931 932 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 933 return decodeSrcOp(OPWV216, Val); 934 } 935 936 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 937 return decodeSrcOp(OPWV232, Val); 938 } 939 940 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 941 // Some instructions have operand restrictions beyond what the encoding 942 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 943 // high bit. 944 Val &= 255; 945 946 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 947 } 948 949 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 950 return decodeSrcOp(OPW32, Val); 951 } 952 953 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 954 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 955 } 956 957 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 958 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 959 } 960 961 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 962 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 963 } 964 965 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 966 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 967 } 968 969 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 970 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 971 } 972 973 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 974 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 975 } 976 977 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 978 return decodeSrcOp(OPW32, Val); 979 } 980 981 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 982 return decodeSrcOp(OPW64, Val); 983 } 984 985 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 986 return decodeSrcOp(OPW128, Val); 987 } 988 989 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 990 using namespace AMDGPU::EncValues; 991 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 992 return decodeSrcOp(OPW128, Val | IS_VGPR); 993 } 994 995 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 996 using namespace AMDGPU::EncValues; 997 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 998 return decodeSrcOp(OPW512, Val | IS_VGPR); 999 } 1000 1001 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1002 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1003 } 1004 1005 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1006 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1007 } 1008 1009 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1010 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1011 } 1012 1013 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1014 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1015 } 1016 1017 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1018 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1019 } 1020 1021 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1022 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1023 } 1024 1025 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1026 // table-gen generated disassembler doesn't care about operand types 1027 // leaving only registry class so SSrc_32 operand turns into SReg_32 1028 // and therefore we accept immediates and literals here as well 1029 return decodeSrcOp(OPW32, Val); 1030 } 1031 1032 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1033 unsigned Val) const { 1034 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1035 return decodeOperand_SReg_32(Val); 1036 } 1037 1038 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1039 unsigned Val) const { 1040 // SReg_32_XM0 is SReg_32 without EXEC_HI 1041 return decodeOperand_SReg_32(Val); 1042 } 1043 1044 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1045 // table-gen generated disassembler doesn't care about operand types 1046 // leaving only registry class so SSrc_32 operand turns into SReg_32 1047 // and therefore we accept immediates and literals here as well 1048 return decodeSrcOp(OPW32, Val); 1049 } 1050 1051 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1052 return decodeSrcOp(OPW64, Val); 1053 } 1054 1055 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1056 return decodeSrcOp(OPW64, Val); 1057 } 1058 1059 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1060 return decodeSrcOp(OPW128, Val); 1061 } 1062 1063 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1064 return decodeDstOp(OPW256, Val); 1065 } 1066 1067 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1068 return decodeDstOp(OPW512, Val); 1069 } 1070 1071 // Decode Literals for insts which always have a literal in the encoding 1072 MCOperand 1073 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1074 if (HasLiteral) { 1075 if (Literal != Val) 1076 return errOperand(Val, "More than one unique literal is illegal"); 1077 } 1078 HasLiteral = true; 1079 Literal = Val; 1080 return MCOperand::createImm(Literal); 1081 } 1082 1083 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1084 // For now all literal constants are supposed to be unsigned integer 1085 // ToDo: deal with signed/unsigned 64-bit integer constants 1086 // ToDo: deal with float/double constants 1087 if (!HasLiteral) { 1088 if (Bytes.size() < 4) { 1089 return errOperand(0, "cannot read literal, inst bytes left " + 1090 Twine(Bytes.size())); 1091 } 1092 HasLiteral = true; 1093 Literal = eatBytes<uint32_t>(Bytes); 1094 } 1095 return MCOperand::createImm(Literal); 1096 } 1097 1098 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1099 using namespace AMDGPU::EncValues; 1100 1101 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1102 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1103 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1104 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1105 // Cast prevents negative overflow. 1106 } 1107 1108 static int64_t getInlineImmVal32(unsigned Imm) { 1109 switch (Imm) { 1110 case 240: 1111 return FloatToBits(0.5f); 1112 case 241: 1113 return FloatToBits(-0.5f); 1114 case 242: 1115 return FloatToBits(1.0f); 1116 case 243: 1117 return FloatToBits(-1.0f); 1118 case 244: 1119 return FloatToBits(2.0f); 1120 case 245: 1121 return FloatToBits(-2.0f); 1122 case 246: 1123 return FloatToBits(4.0f); 1124 case 247: 1125 return FloatToBits(-4.0f); 1126 case 248: // 1 / (2 * PI) 1127 return 0x3e22f983; 1128 default: 1129 llvm_unreachable("invalid fp inline imm"); 1130 } 1131 } 1132 1133 static int64_t getInlineImmVal64(unsigned Imm) { 1134 switch (Imm) { 1135 case 240: 1136 return DoubleToBits(0.5); 1137 case 241: 1138 return DoubleToBits(-0.5); 1139 case 242: 1140 return DoubleToBits(1.0); 1141 case 243: 1142 return DoubleToBits(-1.0); 1143 case 244: 1144 return DoubleToBits(2.0); 1145 case 245: 1146 return DoubleToBits(-2.0); 1147 case 246: 1148 return DoubleToBits(4.0); 1149 case 247: 1150 return DoubleToBits(-4.0); 1151 case 248: // 1 / (2 * PI) 1152 return 0x3fc45f306dc9c882; 1153 default: 1154 llvm_unreachable("invalid fp inline imm"); 1155 } 1156 } 1157 1158 static int64_t getInlineImmVal16(unsigned Imm) { 1159 switch (Imm) { 1160 case 240: 1161 return 0x3800; 1162 case 241: 1163 return 0xB800; 1164 case 242: 1165 return 0x3C00; 1166 case 243: 1167 return 0xBC00; 1168 case 244: 1169 return 0x4000; 1170 case 245: 1171 return 0xC000; 1172 case 246: 1173 return 0x4400; 1174 case 247: 1175 return 0xC400; 1176 case 248: // 1 / (2 * PI) 1177 return 0x3118; 1178 default: 1179 llvm_unreachable("invalid fp inline imm"); 1180 } 1181 } 1182 1183 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1184 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1185 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1186 1187 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1188 switch (Width) { 1189 case OPW32: 1190 case OPW128: // splat constants 1191 case OPW512: 1192 case OPW1024: 1193 case OPWV232: 1194 return MCOperand::createImm(getInlineImmVal32(Imm)); 1195 case OPW64: 1196 case OPW256: 1197 return MCOperand::createImm(getInlineImmVal64(Imm)); 1198 case OPW16: 1199 case OPWV216: 1200 return MCOperand::createImm(getInlineImmVal16(Imm)); 1201 default: 1202 llvm_unreachable("implement me"); 1203 } 1204 } 1205 1206 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1207 using namespace AMDGPU; 1208 1209 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1210 switch (Width) { 1211 default: // fall 1212 case OPW32: 1213 case OPW16: 1214 case OPWV216: 1215 return VGPR_32RegClassID; 1216 case OPW64: 1217 case OPWV232: return VReg_64RegClassID; 1218 case OPW96: return VReg_96RegClassID; 1219 case OPW128: return VReg_128RegClassID; 1220 case OPW160: return VReg_160RegClassID; 1221 case OPW256: return VReg_256RegClassID; 1222 case OPW512: return VReg_512RegClassID; 1223 case OPW1024: return VReg_1024RegClassID; 1224 } 1225 } 1226 1227 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1228 using namespace AMDGPU; 1229 1230 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1231 switch (Width) { 1232 default: // fall 1233 case OPW32: 1234 case OPW16: 1235 case OPWV216: 1236 return AGPR_32RegClassID; 1237 case OPW64: 1238 case OPWV232: return AReg_64RegClassID; 1239 case OPW96: return AReg_96RegClassID; 1240 case OPW128: return AReg_128RegClassID; 1241 case OPW160: return AReg_160RegClassID; 1242 case OPW256: return AReg_256RegClassID; 1243 case OPW512: return AReg_512RegClassID; 1244 case OPW1024: return AReg_1024RegClassID; 1245 } 1246 } 1247 1248 1249 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1250 using namespace AMDGPU; 1251 1252 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1253 switch (Width) { 1254 default: // fall 1255 case OPW32: 1256 case OPW16: 1257 case OPWV216: 1258 return SGPR_32RegClassID; 1259 case OPW64: 1260 case OPWV232: return SGPR_64RegClassID; 1261 case OPW96: return SGPR_96RegClassID; 1262 case OPW128: return SGPR_128RegClassID; 1263 case OPW160: return SGPR_160RegClassID; 1264 case OPW256: return SGPR_256RegClassID; 1265 case OPW512: return SGPR_512RegClassID; 1266 } 1267 } 1268 1269 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1270 using namespace AMDGPU; 1271 1272 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1273 switch (Width) { 1274 default: // fall 1275 case OPW32: 1276 case OPW16: 1277 case OPWV216: 1278 return TTMP_32RegClassID; 1279 case OPW64: 1280 case OPWV232: return TTMP_64RegClassID; 1281 case OPW128: return TTMP_128RegClassID; 1282 case OPW256: return TTMP_256RegClassID; 1283 case OPW512: return TTMP_512RegClassID; 1284 } 1285 } 1286 1287 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1288 using namespace AMDGPU::EncValues; 1289 1290 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1291 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1292 1293 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1294 } 1295 1296 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1297 bool MandatoryLiteral) const { 1298 using namespace AMDGPU::EncValues; 1299 1300 assert(Val < 1024); // enum10 1301 1302 bool IsAGPR = Val & 512; 1303 Val &= 511; 1304 1305 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1306 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1307 : getVgprClassId(Width), Val - VGPR_MIN); 1308 } 1309 if (Val <= SGPR_MAX) { 1310 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1311 static_assert(SGPR_MIN == 0, ""); 1312 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1313 } 1314 1315 int TTmpIdx = getTTmpIdx(Val); 1316 if (TTmpIdx >= 0) { 1317 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1318 } 1319 1320 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1321 return decodeIntImmed(Val); 1322 1323 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1324 return decodeFPImmed(Width, Val); 1325 1326 if (Val == LITERAL_CONST) { 1327 if (MandatoryLiteral) 1328 // Keep a sentinel value for deferred setting 1329 return MCOperand::createImm(LITERAL_CONST); 1330 else 1331 return decodeLiteralConstant(); 1332 } 1333 1334 switch (Width) { 1335 case OPW32: 1336 case OPW16: 1337 case OPWV216: 1338 return decodeSpecialReg32(Val); 1339 case OPW64: 1340 case OPWV232: 1341 return decodeSpecialReg64(Val); 1342 default: 1343 llvm_unreachable("unexpected immediate type"); 1344 } 1345 } 1346 1347 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1348 using namespace AMDGPU::EncValues; 1349 1350 assert(Val < 128); 1351 assert(Width == OPW256 || Width == OPW512); 1352 1353 if (Val <= SGPR_MAX) { 1354 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1355 static_assert(SGPR_MIN == 0, ""); 1356 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1357 } 1358 1359 int TTmpIdx = getTTmpIdx(Val); 1360 if (TTmpIdx >= 0) { 1361 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1362 } 1363 1364 llvm_unreachable("unknown dst register"); 1365 } 1366 1367 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1368 using namespace AMDGPU; 1369 1370 switch (Val) { 1371 case 102: return createRegOperand(FLAT_SCR_LO); 1372 case 103: return createRegOperand(FLAT_SCR_HI); 1373 case 104: return createRegOperand(XNACK_MASK_LO); 1374 case 105: return createRegOperand(XNACK_MASK_HI); 1375 case 106: return createRegOperand(VCC_LO); 1376 case 107: return createRegOperand(VCC_HI); 1377 case 108: return createRegOperand(TBA_LO); 1378 case 109: return createRegOperand(TBA_HI); 1379 case 110: return createRegOperand(TMA_LO); 1380 case 111: return createRegOperand(TMA_HI); 1381 case 124: 1382 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1383 case 125: 1384 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1385 case 126: return createRegOperand(EXEC_LO); 1386 case 127: return createRegOperand(EXEC_HI); 1387 case 235: return createRegOperand(SRC_SHARED_BASE); 1388 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1389 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1390 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1391 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1392 case 251: return createRegOperand(SRC_VCCZ); 1393 case 252: return createRegOperand(SRC_EXECZ); 1394 case 253: return createRegOperand(SRC_SCC); 1395 case 254: return createRegOperand(LDS_DIRECT); 1396 default: break; 1397 } 1398 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1399 } 1400 1401 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1402 using namespace AMDGPU; 1403 1404 switch (Val) { 1405 case 102: return createRegOperand(FLAT_SCR); 1406 case 104: return createRegOperand(XNACK_MASK); 1407 case 106: return createRegOperand(VCC); 1408 case 108: return createRegOperand(TBA); 1409 case 110: return createRegOperand(TMA); 1410 case 124: 1411 if (isGFX11Plus()) 1412 return createRegOperand(SGPR_NULL); 1413 break; 1414 case 125: 1415 if (!isGFX11Plus()) 1416 return createRegOperand(SGPR_NULL); 1417 break; 1418 case 126: return createRegOperand(EXEC); 1419 case 235: return createRegOperand(SRC_SHARED_BASE); 1420 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1421 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1422 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1423 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1424 case 251: return createRegOperand(SRC_VCCZ); 1425 case 252: return createRegOperand(SRC_EXECZ); 1426 case 253: return createRegOperand(SRC_SCC); 1427 default: break; 1428 } 1429 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1430 } 1431 1432 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1433 const unsigned Val) const { 1434 using namespace AMDGPU::SDWA; 1435 using namespace AMDGPU::EncValues; 1436 1437 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1438 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1439 // XXX: cast to int is needed to avoid stupid warning: 1440 // compare with unsigned is always true 1441 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1442 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1443 return createRegOperand(getVgprClassId(Width), 1444 Val - SDWA9EncValues::SRC_VGPR_MIN); 1445 } 1446 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1447 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1448 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1449 return createSRegOperand(getSgprClassId(Width), 1450 Val - SDWA9EncValues::SRC_SGPR_MIN); 1451 } 1452 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1453 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1454 return createSRegOperand(getTtmpClassId(Width), 1455 Val - SDWA9EncValues::SRC_TTMP_MIN); 1456 } 1457 1458 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1459 1460 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1461 return decodeIntImmed(SVal); 1462 1463 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1464 return decodeFPImmed(Width, SVal); 1465 1466 return decodeSpecialReg32(SVal); 1467 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1468 return createRegOperand(getVgprClassId(Width), Val); 1469 } 1470 llvm_unreachable("unsupported target"); 1471 } 1472 1473 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1474 return decodeSDWASrc(OPW16, Val); 1475 } 1476 1477 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1478 return decodeSDWASrc(OPW32, Val); 1479 } 1480 1481 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1482 using namespace AMDGPU::SDWA; 1483 1484 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1485 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1486 "SDWAVopcDst should be present only on GFX9+"); 1487 1488 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1489 1490 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1491 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1492 1493 int TTmpIdx = getTTmpIdx(Val); 1494 if (TTmpIdx >= 0) { 1495 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1496 return createSRegOperand(TTmpClsId, TTmpIdx); 1497 } else if (Val > SGPR_MAX) { 1498 return IsWave64 ? decodeSpecialReg64(Val) 1499 : decodeSpecialReg32(Val); 1500 } else { 1501 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1502 } 1503 } else { 1504 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1505 } 1506 } 1507 1508 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1509 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1510 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1511 } 1512 1513 bool AMDGPUDisassembler::isVI() const { 1514 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1515 } 1516 1517 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1518 1519 bool AMDGPUDisassembler::isGFX90A() const { 1520 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1521 } 1522 1523 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1524 1525 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1526 1527 bool AMDGPUDisassembler::isGFX10Plus() const { 1528 return AMDGPU::isGFX10Plus(STI); 1529 } 1530 1531 bool AMDGPUDisassembler::isGFX11() const { 1532 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1533 } 1534 1535 bool AMDGPUDisassembler::isGFX11Plus() const { 1536 return AMDGPU::isGFX11Plus(STI); 1537 } 1538 1539 1540 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1541 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1542 } 1543 1544 //===----------------------------------------------------------------------===// 1545 // AMDGPU specific symbol handling 1546 //===----------------------------------------------------------------------===// 1547 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1548 do { \ 1549 KdStream << Indent << DIRECTIVE " " \ 1550 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1551 } while (0) 1552 1553 // NOLINTNEXTLINE(readability-identifier-naming) 1554 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1555 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1556 using namespace amdhsa; 1557 StringRef Indent = "\t"; 1558 1559 // We cannot accurately backward compute #VGPRs used from 1560 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1561 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1562 // simply calculate the inverse of what the assembler does. 1563 1564 uint32_t GranulatedWorkitemVGPRCount = 1565 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1566 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1567 1568 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1569 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1570 1571 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1572 1573 // We cannot backward compute values used to calculate 1574 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1575 // directives can't be computed: 1576 // .amdhsa_reserve_vcc 1577 // .amdhsa_reserve_flat_scratch 1578 // .amdhsa_reserve_xnack_mask 1579 // They take their respective default values if not specified in the assembly. 1580 // 1581 // GRANULATED_WAVEFRONT_SGPR_COUNT 1582 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1583 // 1584 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1585 // are set to 0. So while disassembling we consider that: 1586 // 1587 // GRANULATED_WAVEFRONT_SGPR_COUNT 1588 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1589 // 1590 // The disassembler cannot recover the original values of those 3 directives. 1591 1592 uint32_t GranulatedWavefrontSGPRCount = 1593 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1594 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1595 1596 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1597 return MCDisassembler::Fail; 1598 1599 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1600 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1601 1602 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1603 if (!hasArchitectedFlatScratch()) 1604 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1605 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1606 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1607 1608 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1609 return MCDisassembler::Fail; 1610 1611 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1612 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1613 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1614 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1615 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1616 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1617 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1618 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1619 1620 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1621 return MCDisassembler::Fail; 1622 1623 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1624 1625 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1626 return MCDisassembler::Fail; 1627 1628 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1629 1630 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1631 return MCDisassembler::Fail; 1632 1633 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1634 return MCDisassembler::Fail; 1635 1636 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1637 1638 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1639 return MCDisassembler::Fail; 1640 1641 if (isGFX10Plus()) { 1642 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1643 COMPUTE_PGM_RSRC1_WGP_MODE); 1644 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1645 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1646 } 1647 return MCDisassembler::Success; 1648 } 1649 1650 // NOLINTNEXTLINE(readability-identifier-naming) 1651 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1652 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1653 using namespace amdhsa; 1654 StringRef Indent = "\t"; 1655 if (hasArchitectedFlatScratch()) 1656 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1657 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1658 else 1659 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1660 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1661 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1662 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1663 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1664 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1665 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1666 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1667 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1668 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1669 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1670 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1671 1672 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1673 return MCDisassembler::Fail; 1674 1675 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1676 return MCDisassembler::Fail; 1677 1678 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1679 return MCDisassembler::Fail; 1680 1681 PRINT_DIRECTIVE( 1682 ".amdhsa_exception_fp_ieee_invalid_op", 1683 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1684 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1685 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1686 PRINT_DIRECTIVE( 1687 ".amdhsa_exception_fp_ieee_div_zero", 1688 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1689 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1690 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1691 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1692 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1693 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1694 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1695 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1696 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1697 1698 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1699 return MCDisassembler::Fail; 1700 1701 return MCDisassembler::Success; 1702 } 1703 1704 #undef PRINT_DIRECTIVE 1705 1706 MCDisassembler::DecodeStatus 1707 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1708 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1709 raw_string_ostream &KdStream) const { 1710 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1711 do { \ 1712 KdStream << Indent << DIRECTIVE " " \ 1713 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1714 } while (0) 1715 1716 uint16_t TwoByteBuffer = 0; 1717 uint32_t FourByteBuffer = 0; 1718 1719 StringRef ReservedBytes; 1720 StringRef Indent = "\t"; 1721 1722 assert(Bytes.size() == 64); 1723 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1724 1725 switch (Cursor.tell()) { 1726 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1727 FourByteBuffer = DE.getU32(Cursor); 1728 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1729 << '\n'; 1730 return MCDisassembler::Success; 1731 1732 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1733 FourByteBuffer = DE.getU32(Cursor); 1734 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1735 << FourByteBuffer << '\n'; 1736 return MCDisassembler::Success; 1737 1738 case amdhsa::KERNARG_SIZE_OFFSET: 1739 FourByteBuffer = DE.getU32(Cursor); 1740 KdStream << Indent << ".amdhsa_kernarg_size " 1741 << FourByteBuffer << '\n'; 1742 return MCDisassembler::Success; 1743 1744 case amdhsa::RESERVED0_OFFSET: 1745 // 4 reserved bytes, must be 0. 1746 ReservedBytes = DE.getBytes(Cursor, 4); 1747 for (int I = 0; I < 4; ++I) { 1748 if (ReservedBytes[I] != 0) { 1749 return MCDisassembler::Fail; 1750 } 1751 } 1752 return MCDisassembler::Success; 1753 1754 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1755 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1756 // So far no directive controls this for Code Object V3, so simply skip for 1757 // disassembly. 1758 DE.skip(Cursor, 8); 1759 return MCDisassembler::Success; 1760 1761 case amdhsa::RESERVED1_OFFSET: 1762 // 20 reserved bytes, must be 0. 1763 ReservedBytes = DE.getBytes(Cursor, 20); 1764 for (int I = 0; I < 20; ++I) { 1765 if (ReservedBytes[I] != 0) { 1766 return MCDisassembler::Fail; 1767 } 1768 } 1769 return MCDisassembler::Success; 1770 1771 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1772 // COMPUTE_PGM_RSRC3 1773 // - Only set for GFX10, GFX6-9 have this to be 0. 1774 // - Currently no directives directly control this. 1775 FourByteBuffer = DE.getU32(Cursor); 1776 if (!isGFX10Plus() && FourByteBuffer) { 1777 return MCDisassembler::Fail; 1778 } 1779 return MCDisassembler::Success; 1780 1781 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1782 FourByteBuffer = DE.getU32(Cursor); 1783 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1784 MCDisassembler::Fail) { 1785 return MCDisassembler::Fail; 1786 } 1787 return MCDisassembler::Success; 1788 1789 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1790 FourByteBuffer = DE.getU32(Cursor); 1791 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1792 MCDisassembler::Fail) { 1793 return MCDisassembler::Fail; 1794 } 1795 return MCDisassembler::Success; 1796 1797 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1798 using namespace amdhsa; 1799 TwoByteBuffer = DE.getU16(Cursor); 1800 1801 if (!hasArchitectedFlatScratch()) 1802 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1803 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1804 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1805 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1806 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1807 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1808 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1809 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1810 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1811 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1812 if (!hasArchitectedFlatScratch()) 1813 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1814 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1815 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1816 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1817 1818 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1819 return MCDisassembler::Fail; 1820 1821 // Reserved for GFX9 1822 if (isGFX9() && 1823 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1824 return MCDisassembler::Fail; 1825 } else if (isGFX10Plus()) { 1826 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1827 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1828 } 1829 1830 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1831 return MCDisassembler::Fail; 1832 1833 return MCDisassembler::Success; 1834 1835 case amdhsa::RESERVED2_OFFSET: 1836 // 6 bytes from here are reserved, must be 0. 1837 ReservedBytes = DE.getBytes(Cursor, 6); 1838 for (int I = 0; I < 6; ++I) { 1839 if (ReservedBytes[I] != 0) 1840 return MCDisassembler::Fail; 1841 } 1842 return MCDisassembler::Success; 1843 1844 default: 1845 llvm_unreachable("Unhandled index. Case statements cover everything."); 1846 return MCDisassembler::Fail; 1847 } 1848 #undef PRINT_DIRECTIVE 1849 } 1850 1851 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1852 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1853 // CP microcode requires the kernel descriptor to be 64 aligned. 1854 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1855 return MCDisassembler::Fail; 1856 1857 std::string Kd; 1858 raw_string_ostream KdStream(Kd); 1859 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1860 1861 DataExtractor::Cursor C(0); 1862 while (C && C.tell() < Bytes.size()) { 1863 MCDisassembler::DecodeStatus Status = 1864 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1865 1866 cantFail(C.takeError()); 1867 1868 if (Status == MCDisassembler::Fail) 1869 return MCDisassembler::Fail; 1870 } 1871 KdStream << ".end_amdhsa_kernel\n"; 1872 outs() << KdStream.str(); 1873 return MCDisassembler::Success; 1874 } 1875 1876 Optional<MCDisassembler::DecodeStatus> 1877 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1878 ArrayRef<uint8_t> Bytes, uint64_t Address, 1879 raw_ostream &CStream) const { 1880 // Right now only kernel descriptor needs to be handled. 1881 // We ignore all other symbols for target specific handling. 1882 // TODO: 1883 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1884 // Object V2 and V3 when symbols are marked protected. 1885 1886 // amd_kernel_code_t for Code Object V2. 1887 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1888 Size = 256; 1889 return MCDisassembler::Fail; 1890 } 1891 1892 // Code Object V3 kernel descriptors. 1893 StringRef Name = Symbol.Name; 1894 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1895 Size = 64; // Size = 64 regardless of success or failure. 1896 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1897 } 1898 return None; 1899 } 1900 1901 //===----------------------------------------------------------------------===// 1902 // AMDGPUSymbolizer 1903 //===----------------------------------------------------------------------===// 1904 1905 // Try to find symbol name for specified label 1906 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 1907 raw_ostream &/*cStream*/, int64_t Value, 1908 uint64_t /*Address*/, bool IsBranch, 1909 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 1910 1911 if (!IsBranch) { 1912 return false; 1913 } 1914 1915 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1916 if (!Symbols) 1917 return false; 1918 1919 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1920 return Val.Addr == static_cast<uint64_t>(Value) && 1921 Val.Type == ELF::STT_NOTYPE; 1922 }); 1923 if (Result != Symbols->end()) { 1924 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1925 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1926 Inst.addOperand(MCOperand::createExpr(Add)); 1927 return true; 1928 } 1929 // Add to list of referenced addresses, so caller can synthesize a label. 1930 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1931 return false; 1932 } 1933 1934 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1935 int64_t Value, 1936 uint64_t Address) { 1937 llvm_unreachable("unimplemented"); 1938 } 1939 1940 //===----------------------------------------------------------------------===// 1941 // Initialization 1942 //===----------------------------------------------------------------------===// 1943 1944 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 1945 LLVMOpInfoCallback /*GetOpInfo*/, 1946 LLVMSymbolLookupCallback /*SymbolLookUp*/, 1947 void *DisInfo, 1948 MCContext *Ctx, 1949 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 1950 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 1951 } 1952 1953 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 1954 const MCSubtargetInfo &STI, 1955 MCContext &Ctx) { 1956 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 1957 } 1958 1959 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 1960 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 1961 createAMDGPUDisassembler); 1962 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 1963 createAMDGPUSymbolizer); 1964 } 1965