1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, MCInstrInfo const *MCII) 49 : MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 50 MAI(*Ctx.getAsmInfo()), TargetMaxInstBytes(MAI.getMaxInstLength(&STI)) { 51 // ToDo: AMDGPUDisassembler supports only VI ISA. 52 if (!STI.hasFeature(AMDGPU::FeatureGCN3Encoding) && !isGFX10Plus()) 53 report_fatal_error("Disassembly not yet supported for subtarget"); 54 } 55 56 inline static MCDisassembler::DecodeStatus 57 addOperand(MCInst &Inst, const MCOperand& Opnd) { 58 Inst.addOperand(Opnd); 59 return Opnd.isValid() ? 60 MCDisassembler::Success : 61 MCDisassembler::Fail; 62 } 63 64 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 65 uint16_t NameIdx) { 66 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 67 if (OpIdx != -1) { 68 auto I = MI.begin(); 69 std::advance(I, OpIdx); 70 MI.insert(I, Op); 71 } 72 return OpIdx; 73 } 74 75 static DecodeStatus decodeSOPPBrTarget(MCInst &Inst, unsigned Imm, 76 uint64_t Addr, 77 const MCDisassembler *Decoder) { 78 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 79 80 // Our branches take a simm16, but we need two extra bits to account for the 81 // factor of 4. 82 APInt SignedOffset(18, Imm * 4, true); 83 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 84 85 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 86 return MCDisassembler::Success; 87 return addOperand(Inst, MCOperand::createImm(Imm)); 88 } 89 90 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 91 const MCDisassembler *Decoder) { 92 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 93 int64_t Offset; 94 if (DAsm->isGFX12Plus()) { // GFX12 supports 24-bit signed offsets. 95 Offset = SignExtend64<24>(Imm); 96 } else if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 // Decoder for registers, decode directly using RegClassID. Imm(8-bit) is 119 // number of register. Used by VGPR only and AGPR only operands. 120 #define DECODE_OPERAND_REG_8(RegClass) \ 121 static DecodeStatus Decode##RegClass##RegisterClass( \ 122 MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 123 const MCDisassembler *Decoder) { \ 124 assert(Imm < (1 << 8) && "8-bit encoding"); \ 125 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 126 return addOperand( \ 127 Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm)); \ 128 } 129 130 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm, MandatoryLiteral, \ 131 ImmWidth) \ 132 static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, \ 133 const MCDisassembler *Decoder) { \ 134 assert(Imm < (1 << EncSize) && #EncSize "-bit encoding"); \ 135 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 136 return addOperand(Inst, \ 137 DAsm->decodeSrcOp(AMDGPUDisassembler::OpWidth, EncImm, \ 138 MandatoryLiteral, ImmWidth)); \ 139 } 140 141 // Decoder for registers. Imm(7-bit) is number of register, uses decodeSrcOp to 142 // get register class. Used by SGPR only operands. 143 #define DECODE_OPERAND_REG_7(RegClass, OpWidth) \ 144 DECODE_SrcOp(Decode##RegClass##RegisterClass, 7, OpWidth, Imm, false, 0) 145 146 // Decoder for registers. Imm(10-bit): Imm{7-0} is number of register, 147 // Imm{9} is acc(agpr or vgpr) Imm{8} should be 0 (see VOP3Pe_SMFMAC). 148 // Set Imm{8} to 1 (IS_VGPR) to decode using 'enum10' from decodeSrcOp. 149 // Used by AV_ register classes (AGPR or VGPR only register operands). 150 #define DECODE_OPERAND_REG_AV10(RegClass, OpWidth) \ 151 DECODE_SrcOp(Decode##RegClass##RegisterClass, 10, OpWidth, \ 152 Imm | AMDGPU::EncValues::IS_VGPR, false, 0) 153 154 // Decoder for Src(9-bit encoding) registers only. 155 #define DECODE_OPERAND_SRC_REG_9(RegClass, OpWidth) \ 156 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm, false, 0) 157 158 // Decoder for Src(9-bit encoding) AGPR, register number encoded in 9bits, set 159 // Imm{9} to 1 (set acc) and decode using 'enum10' from decodeSrcOp, registers 160 // only. 161 #define DECODE_OPERAND_SRC_REG_A9(RegClass, OpWidth) \ 162 DECODE_SrcOp(decodeOperand_##RegClass, 9, OpWidth, Imm | 512, false, 0) 163 164 // Decoder for 'enum10' from decodeSrcOp, Imm{0-8} is 9-bit Src encoding 165 // Imm{9} is acc, registers only. 166 #define DECODE_SRC_OPERAND_REG_AV10(RegClass, OpWidth) \ 167 DECODE_SrcOp(decodeOperand_##RegClass, 10, OpWidth, Imm, false, 0) 168 169 // Decoder for RegisterOperands using 9-bit Src encoding. Operand can be 170 // register from RegClass or immediate. Registers that don't belong to RegClass 171 // will be decoded and InstPrinter will report warning. Immediate will be 172 // decoded into constant of size ImmWidth, should match width of immediate used 173 // by OperandType (important for floating point types). 174 #define DECODE_OPERAND_SRC_REG_OR_IMM_9(RegClass, OpWidth, ImmWidth) \ 175 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, Imm, \ 176 false, ImmWidth) 177 178 // Decoder for Src(9-bit encoding) AGPR or immediate. Set Imm{9} to 1 (set acc) 179 // and decode using 'enum10' from decodeSrcOp. 180 #define DECODE_OPERAND_SRC_REG_OR_IMM_A9(RegClass, OpWidth, ImmWidth) \ 181 DECODE_SrcOp(decodeOperand_##RegClass##_Imm##ImmWidth, 9, OpWidth, \ 182 Imm | 512, false, ImmWidth) 183 184 #define DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(RegClass, OpWidth, ImmWidth) \ 185 DECODE_SrcOp(decodeOperand_##RegClass##_Deferred##_Imm##ImmWidth, 9, \ 186 OpWidth, Imm, true, ImmWidth) 187 188 // Default decoders generated by tablegen: 'Decode<RegClass>RegisterClass' 189 // when RegisterClass is used as an operand. Most often used for destination 190 // operands. 191 192 DECODE_OPERAND_REG_8(VGPR_32) 193 DECODE_OPERAND_REG_8(VGPR_32_Lo128) 194 DECODE_OPERAND_REG_8(VReg_64) 195 DECODE_OPERAND_REG_8(VReg_96) 196 DECODE_OPERAND_REG_8(VReg_128) 197 DECODE_OPERAND_REG_8(VReg_256) 198 DECODE_OPERAND_REG_8(VReg_288) 199 DECODE_OPERAND_REG_8(VReg_352) 200 DECODE_OPERAND_REG_8(VReg_384) 201 DECODE_OPERAND_REG_8(VReg_512) 202 DECODE_OPERAND_REG_8(VReg_1024) 203 204 DECODE_OPERAND_REG_7(SReg_32, OPW32) 205 DECODE_OPERAND_REG_7(SReg_32_XM0_XEXEC, OPW32) 206 DECODE_OPERAND_REG_7(SReg_32_XEXEC_HI, OPW32) 207 DECODE_OPERAND_REG_7(SReg_64, OPW64) 208 DECODE_OPERAND_REG_7(SReg_64_XEXEC, OPW64) 209 DECODE_OPERAND_REG_7(SReg_128, OPW128) 210 DECODE_OPERAND_REG_7(SReg_256, OPW256) 211 DECODE_OPERAND_REG_7(SReg_512, OPW512) 212 213 DECODE_OPERAND_REG_8(AGPR_32) 214 DECODE_OPERAND_REG_8(AReg_64) 215 DECODE_OPERAND_REG_8(AReg_128) 216 DECODE_OPERAND_REG_8(AReg_256) 217 DECODE_OPERAND_REG_8(AReg_512) 218 DECODE_OPERAND_REG_8(AReg_1024) 219 220 DECODE_OPERAND_REG_AV10(AVDst_128, OPW128) 221 DECODE_OPERAND_REG_AV10(AVDst_512, OPW512) 222 223 // Decoders for register only source RegisterOperands that use use 9-bit Src 224 // encoding: 'decodeOperand_<RegClass>'. 225 226 DECODE_OPERAND_SRC_REG_9(VGPR_32, OPW32) 227 DECODE_OPERAND_SRC_REG_9(VReg_64, OPW64) 228 DECODE_OPERAND_SRC_REG_9(VReg_128, OPW128) 229 DECODE_OPERAND_SRC_REG_9(VReg_256, OPW256) 230 DECODE_OPERAND_SRC_REG_9(VRegOrLds_32, OPW32) 231 232 DECODE_OPERAND_SRC_REG_A9(AGPR_32, OPW32) 233 234 DECODE_SRC_OPERAND_REG_AV10(AV_32, OPW32) 235 DECODE_SRC_OPERAND_REG_AV10(AV_64, OPW64) 236 DECODE_SRC_OPERAND_REG_AV10(AV_128, OPW128) 237 238 // Decoders for register or immediate RegisterOperands that use 9-bit Src 239 // encoding: 'decodeOperand_<RegClass>_Imm<ImmWidth>'. 240 241 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_64, OPW64, 64) 242 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 32) 243 DECODE_OPERAND_SRC_REG_OR_IMM_9(SReg_32, OPW32, 16) 244 DECODE_OPERAND_SRC_REG_OR_IMM_9(SRegOrLds_32, OPW32, 32) 245 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32_Lo128, OPW16, 16) 246 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 16) 247 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_32, OPW32, 32) 248 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 64) 249 DECODE_OPERAND_SRC_REG_OR_IMM_9(VS_64, OPW64, 32) 250 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_64, OPW64, 64) 251 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_128, OPW128, 32) 252 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_256, OPW256, 64) 253 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_512, OPW512, 32) 254 DECODE_OPERAND_SRC_REG_OR_IMM_9(VReg_1024, OPW1024, 32) 255 256 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_64, OPW64, 64) 257 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_128, OPW128, 32) 258 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_256, OPW256, 64) 259 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_512, OPW512, 32) 260 DECODE_OPERAND_SRC_REG_OR_IMM_A9(AReg_1024, OPW1024, 32) 261 262 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32_Lo128, OPW16, 16) 263 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW16, 16) 264 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(VS_32, OPW32, 32) 265 DECODE_OPERAND_SRC_REG_OR_IMM_DEFERRED_9(SReg_32, OPW32, 32) 266 267 static DecodeStatus DecodeVGPR_16RegisterClass(MCInst &Inst, unsigned Imm, 268 uint64_t /*Addr*/, 269 const MCDisassembler *Decoder) { 270 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 271 assert((Imm & (1 << 8)) == 0 && "Imm{8} should not be used"); 272 273 bool IsHi = Imm & (1 << 9); 274 unsigned RegIdx = Imm & 0xff; 275 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 276 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 277 } 278 279 static DecodeStatus 280 DecodeVGPR_16_Lo128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/, 281 const MCDisassembler *Decoder) { 282 assert(isUInt<8>(Imm) && "8-bit encoding expected"); 283 284 bool IsHi = Imm & (1 << 7); 285 unsigned RegIdx = Imm & 0x7f; 286 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 288 } 289 290 static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm, 291 uint64_t /*Addr*/, 292 const MCDisassembler *Decoder) { 293 assert(isUInt<9>(Imm) && "9-bit encoding expected"); 294 295 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 296 bool IsVGPR = Imm & (1 << 8); 297 if (IsVGPR) { 298 bool IsHi = Imm & (1 << 7); 299 unsigned RegIdx = Imm & 0x7f; 300 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 301 } 302 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 303 Imm & 0xFF, false, 16)); 304 } 305 306 static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm, 307 uint64_t /*Addr*/, 308 const MCDisassembler *Decoder) { 309 assert(isUInt<10>(Imm) && "10-bit encoding expected"); 310 311 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 312 bool IsVGPR = Imm & (1 << 8); 313 if (IsVGPR) { 314 bool IsHi = Imm & (1 << 9); 315 unsigned RegIdx = Imm & 0xff; 316 return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi)); 317 } 318 return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(AMDGPUDisassembler::OPW16, 319 Imm & 0xFF, false, 16)); 320 } 321 322 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm, 323 uint64_t Addr, 324 const MCDisassembler *Decoder) { 325 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 326 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 327 } 328 329 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 330 uint64_t Addr, const void *Decoder) { 331 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 332 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 333 } 334 335 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 336 const MCRegisterInfo *MRI) { 337 if (OpIdx < 0) 338 return false; 339 340 const MCOperand &Op = Inst.getOperand(OpIdx); 341 if (!Op.isReg()) 342 return false; 343 344 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 345 auto Reg = Sub ? Sub : Op.getReg(); 346 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 347 } 348 349 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 350 AMDGPUDisassembler::OpWidthTy Opw, 351 const MCDisassembler *Decoder) { 352 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 353 if (!DAsm->isGFX90A()) { 354 Imm &= 511; 355 } else { 356 // If atomic has both vdata and vdst their register classes are tied. 357 // The bit is decoded along with the vdst, first operand. We need to 358 // change register class to AGPR if vdst was AGPR. 359 // If a DS instruction has both data0 and data1 their register classes 360 // are also tied. 361 unsigned Opc = Inst.getOpcode(); 362 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 363 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 364 : AMDGPU::OpName::vdata; 365 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 366 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 367 if ((int)Inst.getNumOperands() == DataIdx) { 368 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 369 if (IsAGPROperand(Inst, DstIdx, MRI)) 370 Imm |= 512; 371 } 372 373 if (TSFlags & SIInstrFlags::DS) { 374 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 375 if ((int)Inst.getNumOperands() == Data2Idx && 376 IsAGPROperand(Inst, DataIdx, MRI)) 377 Imm |= 512; 378 } 379 } 380 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 381 } 382 383 static DecodeStatus decodeOperand_VSrc_f64(MCInst &Inst, unsigned Imm, 384 uint64_t Addr, 385 const MCDisassembler *Decoder) { 386 assert(Imm < (1 << 9) && "9-bit encoding"); 387 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 388 return addOperand( 389 Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm, false, 64, true)); 390 } 391 392 static DecodeStatus 393 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 394 const MCDisassembler *Decoder) { 395 return decodeOperand_AVLdSt_Any(Inst, Imm, 396 AMDGPUDisassembler::OPW32, Decoder); 397 } 398 399 static DecodeStatus 400 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 401 const MCDisassembler *Decoder) { 402 return decodeOperand_AVLdSt_Any(Inst, Imm, 403 AMDGPUDisassembler::OPW64, Decoder); 404 } 405 406 static DecodeStatus 407 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 408 const MCDisassembler *Decoder) { 409 return decodeOperand_AVLdSt_Any(Inst, Imm, 410 AMDGPUDisassembler::OPW96, Decoder); 411 } 412 413 static DecodeStatus 414 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 415 const MCDisassembler *Decoder) { 416 return decodeOperand_AVLdSt_Any(Inst, Imm, 417 AMDGPUDisassembler::OPW128, Decoder); 418 } 419 420 static DecodeStatus 421 DecodeAVLdSt_160RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 422 const MCDisassembler *Decoder) { 423 return decodeOperand_AVLdSt_Any(Inst, Imm, AMDGPUDisassembler::OPW160, 424 Decoder); 425 } 426 427 #define DECODE_SDWA(DecName) \ 428 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 429 430 DECODE_SDWA(Src32) 431 DECODE_SDWA(Src16) 432 DECODE_SDWA(VopcDst) 433 434 #include "AMDGPUGenDisassemblerTables.inc" 435 436 //===----------------------------------------------------------------------===// 437 // 438 //===----------------------------------------------------------------------===// 439 440 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 441 assert(Bytes.size() >= sizeof(T)); 442 const auto Res = 443 support::endian::read<T, llvm::endianness::little>(Bytes.data()); 444 Bytes = Bytes.slice(sizeof(T)); 445 return Res; 446 } 447 448 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 449 assert(Bytes.size() >= 12); 450 uint64_t Lo = 451 support::endian::read<uint64_t, llvm::endianness::little>(Bytes.data()); 452 Bytes = Bytes.slice(8); 453 uint64_t Hi = 454 support::endian::read<uint32_t, llvm::endianness::little>(Bytes.data()); 455 Bytes = Bytes.slice(4); 456 return DecoderUInt128(Lo, Hi); 457 } 458 459 // The disassembler is greedy, so we need to check FI operand value to 460 // not parse a dpp if the correct literal is not set. For dpp16 the 461 // autogenerated decoder checks the dpp literal 462 static bool isValidDPP8(const MCInst &MI) { 463 using namespace llvm::AMDGPU::DPP; 464 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 465 assert(FiIdx != -1); 466 if ((unsigned)FiIdx >= MI.getNumOperands()) 467 return false; 468 unsigned Fi = MI.getOperand(FiIdx).getImm(); 469 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 470 } 471 472 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 473 ArrayRef<uint8_t> Bytes_, 474 uint64_t Address, 475 raw_ostream &CS) const { 476 bool IsSDWA = false; 477 478 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 479 Bytes = Bytes_.slice(0, MaxInstBytesNum); 480 481 DecodeStatus Res = MCDisassembler::Fail; 482 do { 483 // ToDo: better to switch encoding length using some bit predicate 484 // but it is unknown yet, so try all we can 485 486 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 487 // encodings 488 if (isGFX11Plus() && Bytes.size() >= 12 ) { 489 DecoderUInt128 DecW = eat12Bytes(Bytes); 490 Res = 491 tryDecodeInst(DecoderTableDPP8GFX1196, DecoderTableDPP8GFX11_FAKE1696, 492 MI, DecW, Address, CS); 493 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 494 break; 495 MI = MCInst(); // clear 496 Res = tryDecodeInst(DecoderTableDPPGFX1196, DecoderTableDPPGFX11_FAKE1696, 497 MI, DecW, Address, CS); 498 if (Res) { 499 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 500 convertVOP3PDPPInst(MI); 501 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 502 convertVOPCDPPInst(MI); // Special VOP3 case 503 else { 504 assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3); 505 convertVOP3DPPInst(MI); // Regular VOP3 case 506 } 507 break; 508 } 509 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS); 510 if (Res) 511 break; 512 513 Res = tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS); 514 if (Res) 515 break; 516 } 517 // Reinitialize Bytes 518 Bytes = Bytes_.slice(0, MaxInstBytesNum); 519 520 if (Bytes.size() >= 8) { 521 const uint64_t QW = eatBytes<uint64_t>(Bytes); 522 523 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 524 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address, CS); 525 if (Res) { 526 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 527 == -1) 528 break; 529 if (convertDPP8Inst(MI) == MCDisassembler::Success) 530 break; 531 MI = MCInst(); // clear 532 } 533 } 534 535 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address, CS); 536 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 537 break; 538 MI = MCInst(); // clear 539 540 Res = tryDecodeInst(DecoderTableDPP8GFX1164, 541 DecoderTableDPP8GFX11_FAKE1664, MI, QW, Address, CS); 542 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 543 break; 544 MI = MCInst(); // clear 545 546 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address, CS); 547 if (Res) break; 548 549 Res = tryDecodeInst(DecoderTableDPPGFX1164, DecoderTableDPPGFX11_FAKE1664, 550 MI, QW, Address, CS); 551 if (Res) { 552 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 553 convertVOPCDPPInst(MI); 554 break; 555 } 556 557 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address, CS); 558 if (Res) { IsSDWA = true; break; } 559 560 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address, CS); 561 if (Res) { IsSDWA = true; break; } 562 563 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address, CS); 564 if (Res) { IsSDWA = true; break; } 565 566 if (STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem)) { 567 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address, CS); 568 if (Res) 569 break; 570 } 571 572 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 573 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 574 // table first so we print the correct name. 575 if (STI.hasFeature(AMDGPU::FeatureFmaMixInsts)) { 576 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address, CS); 577 if (Res) 578 break; 579 } 580 } 581 582 // Reinitialize Bytes as DPP64 could have eaten too much 583 Bytes = Bytes_.slice(0, MaxInstBytesNum); 584 585 // Try decode 32-bit instruction 586 if (Bytes.size() < 4) break; 587 const uint32_t DW = eatBytes<uint32_t>(Bytes); 588 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address, CS); 589 if (Res) break; 590 591 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address, CS); 592 if (Res) break; 593 594 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address, CS); 595 if (Res) break; 596 597 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 598 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address, CS); 599 if (Res) 600 break; 601 } 602 603 if (STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding)) { 604 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address, CS); 605 if (Res) break; 606 } 607 608 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS); 609 if (Res) break; 610 611 Res = tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW, 612 Address, CS); 613 if (Res) break; 614 615 Res = tryDecodeInst(DecoderTableGFX1232, MI, DW, Address, CS); 616 if (Res) 617 break; 618 619 if (Bytes.size() < 4) break; 620 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 621 622 if (STI.hasFeature(AMDGPU::FeatureGFX940Insts)) { 623 Res = tryDecodeInst(DecoderTableGFX94064, MI, QW, Address, CS); 624 if (Res) 625 break; 626 } 627 628 if (STI.hasFeature(AMDGPU::FeatureGFX90AInsts)) { 629 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address, CS); 630 if (Res) 631 break; 632 } 633 634 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address, CS); 635 if (Res) break; 636 637 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address, CS); 638 if (Res) break; 639 640 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address, CS); 641 if (Res) break; 642 643 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address, CS); 644 if (Res) break; 645 646 Res = tryDecodeInst(DecoderTableGFX1264, MI, QW, Address, CS); 647 if (Res) 648 break; 649 650 Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW, 651 Address, CS); 652 if (Res) 653 break; 654 655 Res = tryDecodeInst(DecoderTableWMMAGFX1164, MI, QW, Address, CS); 656 } while (false); 657 658 if (Res && AMDGPU::isMAC(MI.getOpcode())) { 659 // Insert dummy unused src2_modifiers. 660 insertNamedMCOperand(MI, MCOperand::createImm(0), 661 AMDGPU::OpName::src2_modifiers); 662 } 663 664 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 665 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 666 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 667 AMDGPU::OpName::cpol); 668 if (CPolPos != -1) { 669 unsigned CPol = 670 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 671 AMDGPU::CPol::GLC : 0; 672 if (MI.getNumOperands() <= (unsigned)CPolPos) { 673 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 674 AMDGPU::OpName::cpol); 675 } else if (CPol) { 676 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 677 } 678 } 679 } 680 681 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 682 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 683 (STI.hasFeature(AMDGPU::FeatureGFX90AInsts))) { 684 // GFX90A lost TFE, its place is occupied by ACC. 685 int TFEOpIdx = 686 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 687 if (TFEOpIdx != -1) { 688 auto TFEIter = MI.begin(); 689 std::advance(TFEIter, TFEOpIdx); 690 MI.insert(TFEIter, MCOperand::createImm(0)); 691 } 692 } 693 694 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 695 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 696 int SWZOpIdx = 697 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 698 if (SWZOpIdx != -1) { 699 auto SWZIter = MI.begin(); 700 std::advance(SWZIter, SWZOpIdx); 701 MI.insert(SWZIter, MCOperand::createImm(0)); 702 } 703 } 704 705 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 706 int VAddr0Idx = 707 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 708 int RsrcIdx = 709 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 710 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 711 if (VAddr0Idx >= 0 && NSAArgs > 0) { 712 unsigned NSAWords = (NSAArgs + 3) / 4; 713 if (Bytes.size() < 4 * NSAWords) { 714 Res = MCDisassembler::Fail; 715 } else { 716 for (unsigned i = 0; i < NSAArgs; ++i) { 717 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 718 auto VAddrRCID = 719 MCII->get(MI.getOpcode()).operands()[VAddrIdx].RegClass; 720 MI.insert(MI.begin() + VAddrIdx, 721 createRegOperand(VAddrRCID, Bytes[i])); 722 } 723 Bytes = Bytes.slice(4 * NSAWords); 724 } 725 } 726 727 if (Res) 728 Res = convertMIMGInst(MI); 729 } 730 731 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 732 (SIInstrFlags::VIMAGE | SIInstrFlags::VSAMPLE))) 733 Res = convertMIMGInst(MI); 734 735 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 736 Res = convertEXPInst(MI); 737 738 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 739 Res = convertVINTERPInst(MI); 740 741 if (Res && IsSDWA) 742 Res = convertSDWAInst(MI); 743 744 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 745 AMDGPU::OpName::vdst_in); 746 if (VDstIn_Idx != -1) { 747 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 748 MCOI::OperandConstraint::TIED_TO); 749 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 750 !MI.getOperand(VDstIn_Idx).isReg() || 751 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 752 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 753 MI.erase(&MI.getOperand(VDstIn_Idx)); 754 insertNamedMCOperand(MI, 755 MCOperand::createReg(MI.getOperand(Tied).getReg()), 756 AMDGPU::OpName::vdst_in); 757 } 758 } 759 760 int ImmLitIdx = 761 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 762 bool IsSOPK = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::SOPK; 763 if (Res && ImmLitIdx != -1 && !IsSOPK) 764 Res = convertFMAanyK(MI, ImmLitIdx); 765 766 // if the opcode was not recognized we'll assume a Size of 4 bytes 767 // (unless there are fewer bytes left) 768 Size = Res ? (MaxInstBytesNum - Bytes.size()) 769 : std::min((size_t)4, Bytes_.size()); 770 return Res; 771 } 772 773 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 774 if (STI.hasFeature(AMDGPU::FeatureGFX11Insts)) { 775 // The MCInst still has these fields even though they are no longer encoded 776 // in the GFX11 instruction. 777 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 778 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 779 } 780 return MCDisassembler::Success; 781 } 782 783 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 784 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 785 MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx12 || 786 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 787 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx12 || 788 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 789 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx12 || 790 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11 || 791 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx12) { 792 // The MCInst has this field that is not directly encoded in the 793 // instruction. 794 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 795 } 796 return MCDisassembler::Success; 797 } 798 799 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 800 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 801 STI.hasFeature(AMDGPU::FeatureGFX10)) { 802 if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst)) 803 // VOPC - insert clamp 804 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 805 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 806 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 807 if (SDst != -1) { 808 // VOPC - insert VCC register as sdst 809 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 810 AMDGPU::OpName::sdst); 811 } else { 812 // VOP1/2 - insert omod if present in instruction 813 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 814 } 815 } 816 return MCDisassembler::Success; 817 } 818 819 struct VOPModifiers { 820 unsigned OpSel = 0; 821 unsigned OpSelHi = 0; 822 unsigned NegLo = 0; 823 unsigned NegHi = 0; 824 }; 825 826 // Reconstruct values of VOP3/VOP3P operands such as op_sel. 827 // Note that these values do not affect disassembler output, 828 // so this is only necessary for consistency with src_modifiers. 829 static VOPModifiers collectVOPModifiers(const MCInst &MI, 830 bool IsVOP3P = false) { 831 VOPModifiers Modifiers; 832 unsigned Opc = MI.getOpcode(); 833 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 834 AMDGPU::OpName::src1_modifiers, 835 AMDGPU::OpName::src2_modifiers}; 836 for (int J = 0; J < 3; ++J) { 837 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 838 if (OpIdx == -1) 839 continue; 840 841 unsigned Val = MI.getOperand(OpIdx).getImm(); 842 843 Modifiers.OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 844 if (IsVOP3P) { 845 Modifiers.OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 846 Modifiers.NegLo |= !!(Val & SISrcMods::NEG) << J; 847 Modifiers.NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 848 } else if (J == 0) { 849 Modifiers.OpSel |= !!(Val & SISrcMods::DST_OP_SEL) << 3; 850 } 851 } 852 853 return Modifiers; 854 } 855 856 // MAC opcodes have special old and src2 operands. 857 // src2 is tied to dst, while old is not tied (but assumed to be). 858 bool AMDGPUDisassembler::isMacDPP(MCInst &MI) const { 859 constexpr int DST_IDX = 0; 860 auto Opcode = MI.getOpcode(); 861 const auto &Desc = MCII->get(Opcode); 862 auto OldIdx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::old); 863 864 if (OldIdx != -1 && Desc.getOperandConstraint( 865 OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) { 866 assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2)); 867 assert(Desc.getOperandConstraint( 868 AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2), 869 MCOI::OperandConstraint::TIED_TO) == DST_IDX); 870 (void)DST_IDX; 871 return true; 872 } 873 874 return false; 875 } 876 877 // Create dummy old operand and insert dummy unused src2_modifiers 878 void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const { 879 assert(MI.getNumOperands() + 1 < MCII->get(MI.getOpcode()).getNumOperands()); 880 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 881 insertNamedMCOperand(MI, MCOperand::createImm(0), 882 AMDGPU::OpName::src2_modifiers); 883 } 884 885 // We must check FI == literal to reject not genuine dpp8 insts, and we must 886 // first add optional MI operands to check FI 887 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 888 unsigned Opc = MI.getOpcode(); 889 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 890 convertVOP3PDPPInst(MI); 891 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 892 AMDGPU::isVOPC64DPP(Opc)) { 893 convertVOPCDPPInst(MI); 894 } else { 895 if (isMacDPP(MI)) 896 convertMacDPPInst(MI); 897 898 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 899 if (MI.getNumOperands() < DescNumOps && 900 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 901 auto Mods = collectVOPModifiers(MI); 902 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 903 AMDGPU::OpName::op_sel); 904 } else { 905 // Insert dummy unused src modifiers. 906 if (MI.getNumOperands() < DescNumOps && 907 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 908 insertNamedMCOperand(MI, MCOperand::createImm(0), 909 AMDGPU::OpName::src0_modifiers); 910 911 if (MI.getNumOperands() < DescNumOps && 912 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 913 insertNamedMCOperand(MI, MCOperand::createImm(0), 914 AMDGPU::OpName::src1_modifiers); 915 } 916 } 917 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 918 } 919 920 DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { 921 if (isMacDPP(MI)) 922 convertMacDPPInst(MI); 923 924 unsigned Opc = MI.getOpcode(); 925 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 926 if (MI.getNumOperands() < DescNumOps && 927 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { 928 auto Mods = collectVOPModifiers(MI); 929 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 930 AMDGPU::OpName::op_sel); 931 } 932 return MCDisassembler::Success; 933 } 934 935 // Note that before gfx10, the MIMG encoding provided no information about 936 // VADDR size. Consequently, decoded instructions always show address as if it 937 // has 1 dword, which could be not really so. 938 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 939 auto TSFlags = MCII->get(MI.getOpcode()).TSFlags; 940 941 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 942 AMDGPU::OpName::vdst); 943 944 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 945 AMDGPU::OpName::vdata); 946 int VAddr0Idx = 947 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 948 int RsrcOpName = TSFlags & SIInstrFlags::MIMG ? AMDGPU::OpName::srsrc 949 : AMDGPU::OpName::rsrc; 950 int RsrcIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), RsrcOpName); 951 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 952 AMDGPU::OpName::dmask); 953 954 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 955 AMDGPU::OpName::tfe); 956 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 957 AMDGPU::OpName::d16); 958 959 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 960 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 961 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 962 963 assert(VDataIdx != -1); 964 if (BaseOpcode->BVH) { 965 // Add A16 operand for intersect_ray instructions 966 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); 967 return MCDisassembler::Success; 968 } 969 970 bool IsAtomic = (VDstIdx != -1); 971 bool IsGather4 = TSFlags & SIInstrFlags::Gather4; 972 bool IsVSample = TSFlags & SIInstrFlags::VSAMPLE; 973 bool IsNSA = false; 974 bool IsPartialNSA = false; 975 unsigned AddrSize = Info->VAddrDwords; 976 977 if (isGFX10Plus()) { 978 unsigned DimIdx = 979 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 980 int A16Idx = 981 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 982 const AMDGPU::MIMGDimInfo *Dim = 983 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 984 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 985 986 AddrSize = 987 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 988 989 // VSAMPLE insts that do not use vaddr3 behave the same as NSA forms. 990 // VIMAGE insts other than BVH never use vaddr4. 991 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 992 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA || 993 Info->MIMGEncoding == AMDGPU::MIMGEncGfx12; 994 if (!IsNSA) { 995 if (!IsVSample && AddrSize > 12) 996 AddrSize = 16; 997 } else { 998 if (AddrSize > Info->VAddrDwords) { 999 if (!STI.hasFeature(AMDGPU::FeaturePartialNSAEncoding)) { 1000 // The NSA encoding does not contain enough operands for the 1001 // combination of base opcode / dimension. Should this be an error? 1002 return MCDisassembler::Success; 1003 } 1004 IsPartialNSA = true; 1005 } 1006 } 1007 } 1008 1009 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 1010 unsigned DstSize = IsGather4 ? 4 : std::max(llvm::popcount(DMask), 1); 1011 1012 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 1013 if (D16 && AMDGPU::hasPackedD16(STI)) { 1014 DstSize = (DstSize + 1) / 2; 1015 } 1016 1017 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 1018 DstSize += 1; 1019 1020 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 1021 return MCDisassembler::Success; 1022 1023 int NewOpcode = 1024 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 1025 if (NewOpcode == -1) 1026 return MCDisassembler::Success; 1027 1028 // Widen the register to the correct number of enabled channels. 1029 unsigned NewVdata = AMDGPU::NoRegister; 1030 if (DstSize != Info->VDataDwords) { 1031 auto DataRCID = MCII->get(NewOpcode).operands()[VDataIdx].RegClass; 1032 1033 // Get first subregister of VData 1034 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 1035 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 1036 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 1037 1038 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 1039 &MRI.getRegClass(DataRCID)); 1040 if (NewVdata == AMDGPU::NoRegister) { 1041 // It's possible to encode this such that the low register + enabled 1042 // components exceeds the register count. 1043 return MCDisassembler::Success; 1044 } 1045 } 1046 1047 // If not using NSA on GFX10+, widen vaddr0 address register to correct size. 1048 // If using partial NSA on GFX11+ widen last address register. 1049 int VAddrSAIdx = IsPartialNSA ? (RsrcIdx - 1) : VAddr0Idx; 1050 unsigned NewVAddrSA = AMDGPU::NoRegister; 1051 if (STI.hasFeature(AMDGPU::FeatureNSAEncoding) && (!IsNSA || IsPartialNSA) && 1052 AddrSize != Info->VAddrDwords) { 1053 unsigned VAddrSA = MI.getOperand(VAddrSAIdx).getReg(); 1054 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); 1055 VAddrSA = VAddrSubSA ? VAddrSubSA : VAddrSA; 1056 1057 auto AddrRCID = MCII->get(NewOpcode).operands()[VAddrSAIdx].RegClass; 1058 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, 1059 &MRI.getRegClass(AddrRCID)); 1060 if (!NewVAddrSA) 1061 return MCDisassembler::Success; 1062 } 1063 1064 MI.setOpcode(NewOpcode); 1065 1066 if (NewVdata != AMDGPU::NoRegister) { 1067 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 1068 1069 if (IsAtomic) { 1070 // Atomic operations have an additional operand (a copy of data) 1071 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 1072 } 1073 } 1074 1075 if (NewVAddrSA) { 1076 MI.getOperand(VAddrSAIdx) = MCOperand::createReg(NewVAddrSA); 1077 } else if (IsNSA) { 1078 assert(AddrSize <= Info->VAddrDwords); 1079 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 1080 MI.begin() + VAddr0Idx + Info->VAddrDwords); 1081 } 1082 1083 return MCDisassembler::Success; 1084 } 1085 1086 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 1087 // decoder only adds to src_modifiers, so manually add the bits to the other 1088 // operands. 1089 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 1090 unsigned Opc = MI.getOpcode(); 1091 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1092 auto Mods = collectVOPModifiers(MI, true); 1093 1094 if (MI.getNumOperands() < DescNumOps && 1095 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) 1096 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 1097 1098 if (MI.getNumOperands() < DescNumOps && 1099 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) 1100 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel), 1101 AMDGPU::OpName::op_sel); 1102 if (MI.getNumOperands() < DescNumOps && 1103 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi)) 1104 insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi), 1105 AMDGPU::OpName::op_sel_hi); 1106 if (MI.getNumOperands() < DescNumOps && 1107 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo)) 1108 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo), 1109 AMDGPU::OpName::neg_lo); 1110 if (MI.getNumOperands() < DescNumOps && 1111 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi)) 1112 insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi), 1113 AMDGPU::OpName::neg_hi); 1114 1115 return MCDisassembler::Success; 1116 } 1117 1118 // Create dummy old operand and insert optional operands 1119 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 1120 unsigned Opc = MI.getOpcode(); 1121 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 1122 1123 if (MI.getNumOperands() < DescNumOps && 1124 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old)) 1125 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 1126 1127 if (MI.getNumOperands() < DescNumOps && 1128 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) 1129 insertNamedMCOperand(MI, MCOperand::createImm(0), 1130 AMDGPU::OpName::src0_modifiers); 1131 1132 if (MI.getNumOperands() < DescNumOps && 1133 AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers)) 1134 insertNamedMCOperand(MI, MCOperand::createImm(0), 1135 AMDGPU::OpName::src1_modifiers); 1136 return MCDisassembler::Success; 1137 } 1138 1139 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 1140 int ImmLitIdx) const { 1141 assert(HasLiteral && "Should have decoded a literal"); 1142 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 1143 unsigned DescNumOps = Desc.getNumOperands(); 1144 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 1145 AMDGPU::OpName::immDeferred); 1146 assert(DescNumOps == MI.getNumOperands()); 1147 for (unsigned I = 0; I < DescNumOps; ++I) { 1148 auto &Op = MI.getOperand(I); 1149 auto OpType = Desc.operands()[I].OperandType; 1150 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 1151 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 1152 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 1153 IsDeferredOp) 1154 Op.setImm(Literal); 1155 } 1156 return MCDisassembler::Success; 1157 } 1158 1159 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 1160 return getContext().getRegisterInfo()-> 1161 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1162 } 1163 1164 inline 1165 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1166 const Twine& ErrMsg) const { 1167 *CommentStream << "Error: " + ErrMsg; 1168 1169 // ToDo: add support for error operands to MCInst.h 1170 // return MCOperand::createError(V); 1171 return MCOperand(); 1172 } 1173 1174 inline 1175 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1176 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1177 } 1178 1179 inline 1180 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1181 unsigned Val) const { 1182 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1183 if (Val >= RegCl.getNumRegs()) 1184 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1185 ": unknown register " + Twine(Val)); 1186 return createRegOperand(RegCl.getRegister(Val)); 1187 } 1188 1189 inline 1190 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1191 unsigned Val) const { 1192 // ToDo: SI/CI have 104 SGPRs, VI - 102 1193 // Valery: here we accepting as much as we can, let assembler sort it out 1194 int shift = 0; 1195 switch (SRegClassID) { 1196 case AMDGPU::SGPR_32RegClassID: 1197 case AMDGPU::TTMP_32RegClassID: 1198 break; 1199 case AMDGPU::SGPR_64RegClassID: 1200 case AMDGPU::TTMP_64RegClassID: 1201 shift = 1; 1202 break; 1203 case AMDGPU::SGPR_128RegClassID: 1204 case AMDGPU::TTMP_128RegClassID: 1205 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1206 // this bundle? 1207 case AMDGPU::SGPR_256RegClassID: 1208 case AMDGPU::TTMP_256RegClassID: 1209 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1210 // this bundle? 1211 case AMDGPU::SGPR_288RegClassID: 1212 case AMDGPU::TTMP_288RegClassID: 1213 case AMDGPU::SGPR_320RegClassID: 1214 case AMDGPU::TTMP_320RegClassID: 1215 case AMDGPU::SGPR_352RegClassID: 1216 case AMDGPU::TTMP_352RegClassID: 1217 case AMDGPU::SGPR_384RegClassID: 1218 case AMDGPU::TTMP_384RegClassID: 1219 case AMDGPU::SGPR_512RegClassID: 1220 case AMDGPU::TTMP_512RegClassID: 1221 shift = 2; 1222 break; 1223 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1224 // this bundle? 1225 default: 1226 llvm_unreachable("unhandled register class"); 1227 } 1228 1229 if (Val % (1 << shift)) { 1230 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1231 << ": scalar reg isn't aligned " << Val; 1232 } 1233 1234 return createRegOperand(SRegClassID, Val >> shift); 1235 } 1236 1237 MCOperand AMDGPUDisassembler::createVGPR16Operand(unsigned RegIdx, 1238 bool IsHi) const { 1239 unsigned RCID = 1240 IsHi ? AMDGPU::VGPR_HI16RegClassID : AMDGPU::VGPR_LO16RegClassID; 1241 return createRegOperand(RCID, RegIdx); 1242 } 1243 1244 // Decode Literals for insts which always have a literal in the encoding 1245 MCOperand 1246 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1247 if (HasLiteral) { 1248 assert( 1249 AMDGPU::hasVOPD(STI) && 1250 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1251 if (Literal != Val) 1252 return errOperand(Val, "More than one unique literal is illegal"); 1253 } 1254 HasLiteral = true; 1255 Literal = Val; 1256 return MCOperand::createImm(Literal); 1257 } 1258 1259 MCOperand AMDGPUDisassembler::decodeLiteralConstant(bool ExtendFP64) const { 1260 // For now all literal constants are supposed to be unsigned integer 1261 // ToDo: deal with signed/unsigned 64-bit integer constants 1262 // ToDo: deal with float/double constants 1263 if (!HasLiteral) { 1264 if (Bytes.size() < 4) { 1265 return errOperand(0, "cannot read literal, inst bytes left " + 1266 Twine(Bytes.size())); 1267 } 1268 HasLiteral = true; 1269 Literal = Literal64 = eatBytes<uint32_t>(Bytes); 1270 if (ExtendFP64) 1271 Literal64 <<= 32; 1272 } 1273 return MCOperand::createImm(ExtendFP64 ? Literal64 : Literal); 1274 } 1275 1276 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1277 using namespace AMDGPU::EncValues; 1278 1279 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1280 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1281 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1282 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1283 // Cast prevents negative overflow. 1284 } 1285 1286 static int64_t getInlineImmVal32(unsigned Imm) { 1287 switch (Imm) { 1288 case 240: 1289 return llvm::bit_cast<uint32_t>(0.5f); 1290 case 241: 1291 return llvm::bit_cast<uint32_t>(-0.5f); 1292 case 242: 1293 return llvm::bit_cast<uint32_t>(1.0f); 1294 case 243: 1295 return llvm::bit_cast<uint32_t>(-1.0f); 1296 case 244: 1297 return llvm::bit_cast<uint32_t>(2.0f); 1298 case 245: 1299 return llvm::bit_cast<uint32_t>(-2.0f); 1300 case 246: 1301 return llvm::bit_cast<uint32_t>(4.0f); 1302 case 247: 1303 return llvm::bit_cast<uint32_t>(-4.0f); 1304 case 248: // 1 / (2 * PI) 1305 return 0x3e22f983; 1306 default: 1307 llvm_unreachable("invalid fp inline imm"); 1308 } 1309 } 1310 1311 static int64_t getInlineImmVal64(unsigned Imm) { 1312 switch (Imm) { 1313 case 240: 1314 return llvm::bit_cast<uint64_t>(0.5); 1315 case 241: 1316 return llvm::bit_cast<uint64_t>(-0.5); 1317 case 242: 1318 return llvm::bit_cast<uint64_t>(1.0); 1319 case 243: 1320 return llvm::bit_cast<uint64_t>(-1.0); 1321 case 244: 1322 return llvm::bit_cast<uint64_t>(2.0); 1323 case 245: 1324 return llvm::bit_cast<uint64_t>(-2.0); 1325 case 246: 1326 return llvm::bit_cast<uint64_t>(4.0); 1327 case 247: 1328 return llvm::bit_cast<uint64_t>(-4.0); 1329 case 248: // 1 / (2 * PI) 1330 return 0x3fc45f306dc9c882; 1331 default: 1332 llvm_unreachable("invalid fp inline imm"); 1333 } 1334 } 1335 1336 static int64_t getInlineImmVal16(unsigned Imm) { 1337 switch (Imm) { 1338 case 240: 1339 return 0x3800; 1340 case 241: 1341 return 0xB800; 1342 case 242: 1343 return 0x3C00; 1344 case 243: 1345 return 0xBC00; 1346 case 244: 1347 return 0x4000; 1348 case 245: 1349 return 0xC000; 1350 case 246: 1351 return 0x4400; 1352 case 247: 1353 return 0xC400; 1354 case 248: // 1 / (2 * PI) 1355 return 0x3118; 1356 default: 1357 llvm_unreachable("invalid fp inline imm"); 1358 } 1359 } 1360 1361 MCOperand AMDGPUDisassembler::decodeFPImmed(unsigned ImmWidth, unsigned Imm) { 1362 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1363 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1364 1365 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1366 // ImmWidth 0 is a default case where operand should not allow immediates. 1367 // Imm value is still decoded into 32 bit immediate operand, inst printer will 1368 // use it to print verbose error message. 1369 switch (ImmWidth) { 1370 case 0: 1371 case 32: 1372 return MCOperand::createImm(getInlineImmVal32(Imm)); 1373 case 64: 1374 return MCOperand::createImm(getInlineImmVal64(Imm)); 1375 case 16: 1376 return MCOperand::createImm(getInlineImmVal16(Imm)); 1377 default: 1378 llvm_unreachable("implement me"); 1379 } 1380 } 1381 1382 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1383 using namespace AMDGPU; 1384 1385 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1386 switch (Width) { 1387 default: // fall 1388 case OPW32: 1389 case OPW16: 1390 case OPWV216: 1391 return VGPR_32RegClassID; 1392 case OPW64: 1393 case OPWV232: return VReg_64RegClassID; 1394 case OPW96: return VReg_96RegClassID; 1395 case OPW128: return VReg_128RegClassID; 1396 case OPW160: return VReg_160RegClassID; 1397 case OPW256: return VReg_256RegClassID; 1398 case OPW288: return VReg_288RegClassID; 1399 case OPW320: return VReg_320RegClassID; 1400 case OPW352: return VReg_352RegClassID; 1401 case OPW384: return VReg_384RegClassID; 1402 case OPW512: return VReg_512RegClassID; 1403 case OPW1024: return VReg_1024RegClassID; 1404 } 1405 } 1406 1407 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1408 using namespace AMDGPU; 1409 1410 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1411 switch (Width) { 1412 default: // fall 1413 case OPW32: 1414 case OPW16: 1415 case OPWV216: 1416 return AGPR_32RegClassID; 1417 case OPW64: 1418 case OPWV232: return AReg_64RegClassID; 1419 case OPW96: return AReg_96RegClassID; 1420 case OPW128: return AReg_128RegClassID; 1421 case OPW160: return AReg_160RegClassID; 1422 case OPW256: return AReg_256RegClassID; 1423 case OPW288: return AReg_288RegClassID; 1424 case OPW320: return AReg_320RegClassID; 1425 case OPW352: return AReg_352RegClassID; 1426 case OPW384: return AReg_384RegClassID; 1427 case OPW512: return AReg_512RegClassID; 1428 case OPW1024: return AReg_1024RegClassID; 1429 } 1430 } 1431 1432 1433 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1434 using namespace AMDGPU; 1435 1436 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1437 switch (Width) { 1438 default: // fall 1439 case OPW32: 1440 case OPW16: 1441 case OPWV216: 1442 return SGPR_32RegClassID; 1443 case OPW64: 1444 case OPWV232: return SGPR_64RegClassID; 1445 case OPW96: return SGPR_96RegClassID; 1446 case OPW128: return SGPR_128RegClassID; 1447 case OPW160: return SGPR_160RegClassID; 1448 case OPW256: return SGPR_256RegClassID; 1449 case OPW288: return SGPR_288RegClassID; 1450 case OPW320: return SGPR_320RegClassID; 1451 case OPW352: return SGPR_352RegClassID; 1452 case OPW384: return SGPR_384RegClassID; 1453 case OPW512: return SGPR_512RegClassID; 1454 } 1455 } 1456 1457 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1458 using namespace AMDGPU; 1459 1460 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1461 switch (Width) { 1462 default: // fall 1463 case OPW32: 1464 case OPW16: 1465 case OPWV216: 1466 return TTMP_32RegClassID; 1467 case OPW64: 1468 case OPWV232: return TTMP_64RegClassID; 1469 case OPW128: return TTMP_128RegClassID; 1470 case OPW256: return TTMP_256RegClassID; 1471 case OPW288: return TTMP_288RegClassID; 1472 case OPW320: return TTMP_320RegClassID; 1473 case OPW352: return TTMP_352RegClassID; 1474 case OPW384: return TTMP_384RegClassID; 1475 case OPW512: return TTMP_512RegClassID; 1476 } 1477 } 1478 1479 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1480 using namespace AMDGPU::EncValues; 1481 1482 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1483 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1484 1485 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1486 } 1487 1488 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1489 bool MandatoryLiteral, 1490 unsigned ImmWidth, bool IsFP) const { 1491 using namespace AMDGPU::EncValues; 1492 1493 assert(Val < 1024); // enum10 1494 1495 bool IsAGPR = Val & 512; 1496 Val &= 511; 1497 1498 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1499 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1500 : getVgprClassId(Width), Val - VGPR_MIN); 1501 } 1502 return decodeNonVGPRSrcOp(Width, Val & 0xFF, MandatoryLiteral, ImmWidth, 1503 IsFP); 1504 } 1505 1506 MCOperand AMDGPUDisassembler::decodeNonVGPRSrcOp(const OpWidthTy Width, 1507 unsigned Val, 1508 bool MandatoryLiteral, 1509 unsigned ImmWidth, 1510 bool IsFP) const { 1511 // Cases when Val{8} is 1 (vgpr, agpr or true 16 vgpr) should have been 1512 // decoded earlier. 1513 assert(Val < (1 << 8) && "9-bit Src encoding when Val{8} is 0"); 1514 using namespace AMDGPU::EncValues; 1515 1516 if (Val <= SGPR_MAX) { 1517 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1518 static_assert(SGPR_MIN == 0); 1519 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1520 } 1521 1522 int TTmpIdx = getTTmpIdx(Val); 1523 if (TTmpIdx >= 0) { 1524 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1525 } 1526 1527 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1528 return decodeIntImmed(Val); 1529 1530 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1531 return decodeFPImmed(ImmWidth, Val); 1532 1533 if (Val == LITERAL_CONST) { 1534 if (MandatoryLiteral) 1535 // Keep a sentinel value for deferred setting 1536 return MCOperand::createImm(LITERAL_CONST); 1537 else 1538 return decodeLiteralConstant(IsFP && ImmWidth == 64); 1539 } 1540 1541 switch (Width) { 1542 case OPW32: 1543 case OPW16: 1544 case OPWV216: 1545 return decodeSpecialReg32(Val); 1546 case OPW64: 1547 case OPWV232: 1548 return decodeSpecialReg64(Val); 1549 default: 1550 llvm_unreachable("unexpected immediate type"); 1551 } 1552 } 1553 1554 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1555 // opposite of bit 0 of DstX. 1556 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1557 unsigned Val) const { 1558 int VDstXInd = 1559 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1560 assert(VDstXInd != -1); 1561 assert(Inst.getOperand(VDstXInd).isReg()); 1562 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1563 Val |= ~XDstReg & 1; 1564 auto Width = llvm::AMDGPUDisassembler::OPW32; 1565 return createRegOperand(getVgprClassId(Width), Val); 1566 } 1567 1568 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1569 using namespace AMDGPU; 1570 1571 switch (Val) { 1572 // clang-format off 1573 case 102: return createRegOperand(FLAT_SCR_LO); 1574 case 103: return createRegOperand(FLAT_SCR_HI); 1575 case 104: return createRegOperand(XNACK_MASK_LO); 1576 case 105: return createRegOperand(XNACK_MASK_HI); 1577 case 106: return createRegOperand(VCC_LO); 1578 case 107: return createRegOperand(VCC_HI); 1579 case 108: return createRegOperand(TBA_LO); 1580 case 109: return createRegOperand(TBA_HI); 1581 case 110: return createRegOperand(TMA_LO); 1582 case 111: return createRegOperand(TMA_HI); 1583 case 124: 1584 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1585 case 125: 1586 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1587 case 126: return createRegOperand(EXEC_LO); 1588 case 127: return createRegOperand(EXEC_HI); 1589 case 235: return createRegOperand(SRC_SHARED_BASE_LO); 1590 case 236: return createRegOperand(SRC_SHARED_LIMIT_LO); 1591 case 237: return createRegOperand(SRC_PRIVATE_BASE_LO); 1592 case 238: return createRegOperand(SRC_PRIVATE_LIMIT_LO); 1593 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1594 case 251: return createRegOperand(SRC_VCCZ); 1595 case 252: return createRegOperand(SRC_EXECZ); 1596 case 253: return createRegOperand(SRC_SCC); 1597 case 254: return createRegOperand(LDS_DIRECT); 1598 default: break; 1599 // clang-format on 1600 } 1601 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1602 } 1603 1604 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1605 using namespace AMDGPU; 1606 1607 switch (Val) { 1608 case 102: return createRegOperand(FLAT_SCR); 1609 case 104: return createRegOperand(XNACK_MASK); 1610 case 106: return createRegOperand(VCC); 1611 case 108: return createRegOperand(TBA); 1612 case 110: return createRegOperand(TMA); 1613 case 124: 1614 if (isGFX11Plus()) 1615 return createRegOperand(SGPR_NULL); 1616 break; 1617 case 125: 1618 if (!isGFX11Plus()) 1619 return createRegOperand(SGPR_NULL); 1620 break; 1621 case 126: return createRegOperand(EXEC); 1622 case 235: return createRegOperand(SRC_SHARED_BASE); 1623 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1624 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1625 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1626 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1627 case 251: return createRegOperand(SRC_VCCZ); 1628 case 252: return createRegOperand(SRC_EXECZ); 1629 case 253: return createRegOperand(SRC_SCC); 1630 default: break; 1631 } 1632 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1633 } 1634 1635 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1636 const unsigned Val, 1637 unsigned ImmWidth) const { 1638 using namespace AMDGPU::SDWA; 1639 using namespace AMDGPU::EncValues; 1640 1641 if (STI.hasFeature(AMDGPU::FeatureGFX9) || 1642 STI.hasFeature(AMDGPU::FeatureGFX10)) { 1643 // XXX: cast to int is needed to avoid stupid warning: 1644 // compare with unsigned is always true 1645 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1646 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1647 return createRegOperand(getVgprClassId(Width), 1648 Val - SDWA9EncValues::SRC_VGPR_MIN); 1649 } 1650 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1651 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1652 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1653 return createSRegOperand(getSgprClassId(Width), 1654 Val - SDWA9EncValues::SRC_SGPR_MIN); 1655 } 1656 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1657 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1658 return createSRegOperand(getTtmpClassId(Width), 1659 Val - SDWA9EncValues::SRC_TTMP_MIN); 1660 } 1661 1662 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1663 1664 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1665 return decodeIntImmed(SVal); 1666 1667 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1668 return decodeFPImmed(ImmWidth, SVal); 1669 1670 return decodeSpecialReg32(SVal); 1671 } else if (STI.hasFeature(AMDGPU::FeatureVolcanicIslands)) { 1672 return createRegOperand(getVgprClassId(Width), Val); 1673 } 1674 llvm_unreachable("unsupported target"); 1675 } 1676 1677 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1678 return decodeSDWASrc(OPW16, Val, 16); 1679 } 1680 1681 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1682 return decodeSDWASrc(OPW32, Val, 32); 1683 } 1684 1685 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1686 using namespace AMDGPU::SDWA; 1687 1688 assert((STI.hasFeature(AMDGPU::FeatureGFX9) || 1689 STI.hasFeature(AMDGPU::FeatureGFX10)) && 1690 "SDWAVopcDst should be present only on GFX9+"); 1691 1692 bool IsWave64 = STI.hasFeature(AMDGPU::FeatureWavefrontSize64); 1693 1694 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1695 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1696 1697 int TTmpIdx = getTTmpIdx(Val); 1698 if (TTmpIdx >= 0) { 1699 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1700 return createSRegOperand(TTmpClsId, TTmpIdx); 1701 } else if (Val > SGPR_MAX) { 1702 return IsWave64 ? decodeSpecialReg64(Val) 1703 : decodeSpecialReg32(Val); 1704 } else { 1705 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1706 } 1707 } else { 1708 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1709 } 1710 } 1711 1712 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1713 return STI.hasFeature(AMDGPU::FeatureWavefrontSize64) 1714 ? decodeSrcOp(OPW64, Val) 1715 : decodeSrcOp(OPW32, Val); 1716 } 1717 1718 bool AMDGPUDisassembler::isVI() const { 1719 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands); 1720 } 1721 1722 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1723 1724 bool AMDGPUDisassembler::isGFX90A() const { 1725 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts); 1726 } 1727 1728 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1729 1730 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1731 1732 bool AMDGPUDisassembler::isGFX10Plus() const { 1733 return AMDGPU::isGFX10Plus(STI); 1734 } 1735 1736 bool AMDGPUDisassembler::isGFX11() const { 1737 return STI.hasFeature(AMDGPU::FeatureGFX11); 1738 } 1739 1740 bool AMDGPUDisassembler::isGFX11Plus() const { 1741 return AMDGPU::isGFX11Plus(STI); 1742 } 1743 1744 bool AMDGPUDisassembler::isGFX12Plus() const { 1745 return AMDGPU::isGFX12Plus(STI); 1746 } 1747 1748 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1749 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch); 1750 } 1751 1752 bool AMDGPUDisassembler::hasKernargPreload() const { 1753 return AMDGPU::hasKernargPreload(STI); 1754 } 1755 1756 //===----------------------------------------------------------------------===// 1757 // AMDGPU specific symbol handling 1758 //===----------------------------------------------------------------------===// 1759 #define GET_FIELD(MASK) (AMDHSA_BITS_GET(FourByteBuffer, MASK)) 1760 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1761 do { \ 1762 KdStream << Indent << DIRECTIVE " " << GET_FIELD(MASK) << '\n'; \ 1763 } while (0) 1764 #define PRINT_PSEUDO_DIRECTIVE_COMMENT(DIRECTIVE, MASK) \ 1765 do { \ 1766 KdStream << Indent << MAI.getCommentString() << ' ' << DIRECTIVE " " \ 1767 << GET_FIELD(MASK) << '\n'; \ 1768 } while (0) 1769 1770 // NOLINTNEXTLINE(readability-identifier-naming) 1771 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1772 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1773 using namespace amdhsa; 1774 StringRef Indent = "\t"; 1775 1776 // We cannot accurately backward compute #VGPRs used from 1777 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1778 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1779 // simply calculate the inverse of what the assembler does. 1780 1781 uint32_t GranulatedWorkitemVGPRCount = 1782 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT); 1783 1784 uint32_t NextFreeVGPR = 1785 (GranulatedWorkitemVGPRCount + 1) * 1786 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI, EnableWavefrontSize32); 1787 1788 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1789 1790 // We cannot backward compute values used to calculate 1791 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1792 // directives can't be computed: 1793 // .amdhsa_reserve_vcc 1794 // .amdhsa_reserve_flat_scratch 1795 // .amdhsa_reserve_xnack_mask 1796 // They take their respective default values if not specified in the assembly. 1797 // 1798 // GRANULATED_WAVEFRONT_SGPR_COUNT 1799 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1800 // 1801 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1802 // are set to 0. So while disassembling we consider that: 1803 // 1804 // GRANULATED_WAVEFRONT_SGPR_COUNT 1805 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1806 // 1807 // The disassembler cannot recover the original values of those 3 directives. 1808 1809 uint32_t GranulatedWavefrontSGPRCount = 1810 GET_FIELD(COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT); 1811 1812 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1813 return MCDisassembler::Fail; 1814 1815 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1816 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1817 1818 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1819 if (!hasArchitectedFlatScratch()) 1820 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1821 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1822 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1823 1824 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1825 return MCDisassembler::Fail; 1826 1827 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1828 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1829 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1830 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1831 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1832 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1833 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1834 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1835 1836 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1837 return MCDisassembler::Fail; 1838 1839 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1840 1841 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1842 return MCDisassembler::Fail; 1843 1844 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1845 1846 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1847 return MCDisassembler::Fail; 1848 1849 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1850 return MCDisassembler::Fail; 1851 1852 if (isGFX9Plus()) 1853 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL); 1854 1855 if (!isGFX9Plus()) 1856 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX8_RESERVED0) 1857 return MCDisassembler::Fail; 1858 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED1) 1859 return MCDisassembler::Fail; 1860 if (!isGFX10Plus()) 1861 if (FourByteBuffer & COMPUTE_PGM_RSRC1_GFX6_GFX9_RESERVED2) 1862 return MCDisassembler::Fail; 1863 1864 if (isGFX10Plus()) { 1865 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1866 COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE); 1867 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED); 1868 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS); 1869 } 1870 return MCDisassembler::Success; 1871 } 1872 1873 // NOLINTNEXTLINE(readability-identifier-naming) 1874 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1875 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1876 using namespace amdhsa; 1877 StringRef Indent = "\t"; 1878 if (hasArchitectedFlatScratch()) 1879 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1880 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1881 else 1882 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1883 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1884 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1885 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1886 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1887 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1888 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1889 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1890 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1891 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1892 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1893 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1894 1895 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1896 return MCDisassembler::Fail; 1897 1898 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1899 return MCDisassembler::Fail; 1900 1901 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1902 return MCDisassembler::Fail; 1903 1904 PRINT_DIRECTIVE( 1905 ".amdhsa_exception_fp_ieee_invalid_op", 1906 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1907 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1908 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1909 PRINT_DIRECTIVE( 1910 ".amdhsa_exception_fp_ieee_div_zero", 1911 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1912 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1913 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1914 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1915 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1916 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1917 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1918 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1919 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1920 1921 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1922 return MCDisassembler::Fail; 1923 1924 return MCDisassembler::Success; 1925 } 1926 1927 // NOLINTNEXTLINE(readability-identifier-naming) 1928 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC3( 1929 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1930 using namespace amdhsa; 1931 StringRef Indent = "\t"; 1932 if (isGFX90A()) { 1933 KdStream << Indent << ".amdhsa_accum_offset " 1934 << (GET_FIELD(COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET) + 1) * 4 1935 << '\n'; 1936 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED0) 1937 return MCDisassembler::Fail; 1938 PRINT_DIRECTIVE(".amdhsa_tg_split", COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT); 1939 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX90A_RESERVED1) 1940 return MCDisassembler::Fail; 1941 } else if (isGFX10Plus()) { 1942 if (!EnableWavefrontSize32 || !*EnableWavefrontSize32) { 1943 PRINT_DIRECTIVE(".amdhsa_shared_vgpr_count", 1944 COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1945 } else { 1946 PRINT_PSEUDO_DIRECTIVE_COMMENT( 1947 "SHARED_VGPR_COUNT", COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT); 1948 } 1949 1950 if (isGFX11Plus()) { 1951 PRINT_PSEUDO_DIRECTIVE_COMMENT("INST_PREF_SIZE", 1952 COMPUTE_PGM_RSRC3_GFX11_PLUS_INST_PREF_SIZE); 1953 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_START", 1954 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 1955 PRINT_PSEUDO_DIRECTIVE_COMMENT("TRAP_ON_END", 1956 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_END); 1957 } else { 1958 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED0) 1959 return MCDisassembler::Fail; 1960 } 1961 1962 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_PLUS_RESERVED1) 1963 return MCDisassembler::Fail; 1964 1965 if (isGFX11Plus()) { 1966 PRINT_PSEUDO_DIRECTIVE_COMMENT("IMAGE_OP", 1967 COMPUTE_PGM_RSRC3_GFX11_PLUS_TRAP_ON_START); 1968 } else { 1969 if (FourByteBuffer & COMPUTE_PGM_RSRC3_GFX10_RESERVED2) 1970 return MCDisassembler::Fail; 1971 } 1972 } else if (FourByteBuffer) { 1973 return MCDisassembler::Fail; 1974 } 1975 return MCDisassembler::Success; 1976 } 1977 #undef PRINT_PSEUDO_DIRECTIVE_COMMENT 1978 #undef PRINT_DIRECTIVE 1979 #undef GET_FIELD 1980 1981 MCDisassembler::DecodeStatus 1982 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1983 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1984 raw_string_ostream &KdStream) const { 1985 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1986 do { \ 1987 KdStream << Indent << DIRECTIVE " " \ 1988 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1989 } while (0) 1990 1991 uint16_t TwoByteBuffer = 0; 1992 uint32_t FourByteBuffer = 0; 1993 1994 StringRef ReservedBytes; 1995 StringRef Indent = "\t"; 1996 1997 assert(Bytes.size() == 64); 1998 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1999 2000 switch (Cursor.tell()) { 2001 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 2002 FourByteBuffer = DE.getU32(Cursor); 2003 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 2004 << '\n'; 2005 return MCDisassembler::Success; 2006 2007 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 2008 FourByteBuffer = DE.getU32(Cursor); 2009 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 2010 << FourByteBuffer << '\n'; 2011 return MCDisassembler::Success; 2012 2013 case amdhsa::KERNARG_SIZE_OFFSET: 2014 FourByteBuffer = DE.getU32(Cursor); 2015 KdStream << Indent << ".amdhsa_kernarg_size " 2016 << FourByteBuffer << '\n'; 2017 return MCDisassembler::Success; 2018 2019 case amdhsa::RESERVED0_OFFSET: 2020 // 4 reserved bytes, must be 0. 2021 ReservedBytes = DE.getBytes(Cursor, 4); 2022 for (int I = 0; I < 4; ++I) { 2023 if (ReservedBytes[I] != 0) { 2024 return MCDisassembler::Fail; 2025 } 2026 } 2027 return MCDisassembler::Success; 2028 2029 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 2030 // KERNEL_CODE_ENTRY_BYTE_OFFSET 2031 // So far no directive controls this for Code Object V3, so simply skip for 2032 // disassembly. 2033 DE.skip(Cursor, 8); 2034 return MCDisassembler::Success; 2035 2036 case amdhsa::RESERVED1_OFFSET: 2037 // 20 reserved bytes, must be 0. 2038 ReservedBytes = DE.getBytes(Cursor, 20); 2039 for (int I = 0; I < 20; ++I) { 2040 if (ReservedBytes[I] != 0) { 2041 return MCDisassembler::Fail; 2042 } 2043 } 2044 return MCDisassembler::Success; 2045 2046 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 2047 FourByteBuffer = DE.getU32(Cursor); 2048 return decodeCOMPUTE_PGM_RSRC3(FourByteBuffer, KdStream); 2049 2050 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 2051 FourByteBuffer = DE.getU32(Cursor); 2052 return decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream); 2053 2054 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 2055 FourByteBuffer = DE.getU32(Cursor); 2056 return decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream); 2057 2058 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 2059 using namespace amdhsa; 2060 TwoByteBuffer = DE.getU16(Cursor); 2061 2062 if (!hasArchitectedFlatScratch()) 2063 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 2064 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 2065 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 2066 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 2067 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 2068 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 2069 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 2070 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 2071 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 2072 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 2073 if (!hasArchitectedFlatScratch()) 2074 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 2075 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 2076 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 2077 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 2078 2079 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 2080 return MCDisassembler::Fail; 2081 2082 // Reserved for GFX9 2083 if (isGFX9() && 2084 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 2085 return MCDisassembler::Fail; 2086 } else if (isGFX10Plus()) { 2087 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 2088 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2089 } 2090 2091 if (AMDGPU::getAmdhsaCodeObjectVersion() >= AMDGPU::AMDHSA_COV5) 2092 PRINT_DIRECTIVE(".amdhsa_uses_dynamic_stack", 2093 KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK); 2094 2095 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2096 return MCDisassembler::Fail; 2097 2098 return MCDisassembler::Success; 2099 2100 case amdhsa::KERNARG_PRELOAD_OFFSET: 2101 using namespace amdhsa; 2102 TwoByteBuffer = DE.getU16(Cursor); 2103 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_LENGTH) { 2104 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_length", 2105 KERNARG_PRELOAD_SPEC_LENGTH); 2106 } 2107 2108 if (TwoByteBuffer & KERNARG_PRELOAD_SPEC_OFFSET) { 2109 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_preload_offset", 2110 KERNARG_PRELOAD_SPEC_OFFSET); 2111 } 2112 return MCDisassembler::Success; 2113 2114 case amdhsa::RESERVED3_OFFSET: 2115 // 4 bytes from here are reserved, must be 0. 2116 ReservedBytes = DE.getBytes(Cursor, 4); 2117 for (int I = 0; I < 4; ++I) { 2118 if (ReservedBytes[I] != 0) 2119 return MCDisassembler::Fail; 2120 } 2121 return MCDisassembler::Success; 2122 2123 default: 2124 llvm_unreachable("Unhandled index. Case statements cover everything."); 2125 return MCDisassembler::Fail; 2126 } 2127 #undef PRINT_DIRECTIVE 2128 } 2129 2130 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2131 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2132 // CP microcode requires the kernel descriptor to be 64 aligned. 2133 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2134 return MCDisassembler::Fail; 2135 2136 // FIXME: We can't actually decode "in order" as is done below, as e.g. GFX10 2137 // requires us to know the setting of .amdhsa_wavefront_size32 in order to 2138 // accurately produce .amdhsa_next_free_vgpr, and they appear in the wrong 2139 // order. Workaround this by first looking up .amdhsa_wavefront_size32 here 2140 // when required. 2141 if (isGFX10Plus()) { 2142 uint16_t KernelCodeProperties = 2143 support::endian::read16(&Bytes[amdhsa::KERNEL_CODE_PROPERTIES_OFFSET], 2144 llvm::endianness::little); 2145 EnableWavefrontSize32 = 2146 AMDHSA_BITS_GET(KernelCodeProperties, 2147 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 2148 } 2149 2150 std::string Kd; 2151 raw_string_ostream KdStream(Kd); 2152 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2153 2154 DataExtractor::Cursor C(0); 2155 while (C && C.tell() < Bytes.size()) { 2156 MCDisassembler::DecodeStatus Status = 2157 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2158 2159 cantFail(C.takeError()); 2160 2161 if (Status == MCDisassembler::Fail) 2162 return MCDisassembler::Fail; 2163 } 2164 KdStream << ".end_amdhsa_kernel\n"; 2165 outs() << KdStream.str(); 2166 return MCDisassembler::Success; 2167 } 2168 2169 std::optional<MCDisassembler::DecodeStatus> 2170 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2171 ArrayRef<uint8_t> Bytes, uint64_t Address, 2172 raw_ostream &CStream) const { 2173 // Right now only kernel descriptor needs to be handled. 2174 // We ignore all other symbols for target specific handling. 2175 // TODO: 2176 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2177 // Object V2 and V3 when symbols are marked protected. 2178 2179 // amd_kernel_code_t for Code Object V2. 2180 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2181 Size = 256; 2182 return MCDisassembler::Fail; 2183 } 2184 2185 // Code Object V3 kernel descriptors. 2186 StringRef Name = Symbol.Name; 2187 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2188 Size = 64; // Size = 64 regardless of success or failure. 2189 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2190 } 2191 return std::nullopt; 2192 } 2193 2194 //===----------------------------------------------------------------------===// 2195 // AMDGPUSymbolizer 2196 //===----------------------------------------------------------------------===// 2197 2198 // Try to find symbol name for specified label 2199 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2200 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2201 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2202 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2203 2204 if (!IsBranch) { 2205 return false; 2206 } 2207 2208 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2209 if (!Symbols) 2210 return false; 2211 2212 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2213 return Val.Addr == static_cast<uint64_t>(Value) && 2214 Val.Type == ELF::STT_NOTYPE; 2215 }); 2216 if (Result != Symbols->end()) { 2217 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2218 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2219 Inst.addOperand(MCOperand::createExpr(Add)); 2220 return true; 2221 } 2222 // Add to list of referenced addresses, so caller can synthesize a label. 2223 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2224 return false; 2225 } 2226 2227 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2228 int64_t Value, 2229 uint64_t Address) { 2230 llvm_unreachable("unimplemented"); 2231 } 2232 2233 //===----------------------------------------------------------------------===// 2234 // Initialization 2235 //===----------------------------------------------------------------------===// 2236 2237 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2238 LLVMOpInfoCallback /*GetOpInfo*/, 2239 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2240 void *DisInfo, 2241 MCContext *Ctx, 2242 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2243 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2244 } 2245 2246 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2247 const MCSubtargetInfo &STI, 2248 MCContext &Ctx) { 2249 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2250 } 2251 2252 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2253 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2254 createAMDGPUDisassembler); 2255 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2256 createAMDGPUSymbolizer); 2257 } 2258