1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 //===----------------------------------------------------------------------===// 11 // 12 /// \file 13 /// 14 /// This file contains definition for AMDGPU ISA disassembler 15 // 16 //===----------------------------------------------------------------------===// 17 18 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 19 20 #include "Disassembler/AMDGPUDisassembler.h" 21 #include "AMDGPU.h" 22 #include "AMDGPURegisterInfo.h" 23 #include "SIDefines.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/Disassembler.h" 26 #include "llvm/ADT/APInt.h" 27 #include "llvm/ADT/ArrayRef.h" 28 #include "llvm/ADT/Twine.h" 29 #include "llvm/BinaryFormat/ELF.h" 30 #include "llvm/MC/MCContext.h" 31 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 32 #include "llvm/MC/MCExpr.h" 33 #include "llvm/MC/MCFixedLenDisassembler.h" 34 #include "llvm/MC/MCInst.h" 35 #include "llvm/MC/MCSubtargetInfo.h" 36 #include "llvm/Support/Endian.h" 37 #include "llvm/Support/ErrorHandling.h" 38 #include "llvm/Support/MathExtras.h" 39 #include "llvm/Support/TargetRegistry.h" 40 #include "llvm/Support/raw_ostream.h" 41 #include <algorithm> 42 #include <cassert> 43 #include <cstddef> 44 #include <cstdint> 45 #include <iterator> 46 #include <tuple> 47 #include <vector> 48 49 using namespace llvm; 50 51 #define DEBUG_TYPE "amdgpu-disassembler" 52 53 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 54 55 inline static MCDisassembler::DecodeStatus 56 addOperand(MCInst &Inst, const MCOperand& Opnd) { 57 Inst.addOperand(Opnd); 58 return Opnd.isValid() ? 59 MCDisassembler::Success : 60 MCDisassembler::SoftFail; 61 } 62 63 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 64 uint16_t NameIdx) { 65 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 66 if (OpIdx != -1) { 67 auto I = MI.begin(); 68 std::advance(I, OpIdx); 69 MI.insert(I, Op); 70 } 71 return OpIdx; 72 } 73 74 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 75 uint64_t Addr, const void *Decoder) { 76 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 77 78 APInt SignedOffset(18, Imm * 4, true); 79 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 80 81 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2)) 82 return MCDisassembler::Success; 83 return addOperand(Inst, MCOperand::createImm(Imm)); 84 } 85 86 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 87 static DecodeStatus StaticDecoderName(MCInst &Inst, \ 88 unsigned Imm, \ 89 uint64_t /*Addr*/, \ 90 const void *Decoder) { \ 91 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \ 92 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 93 } 94 95 #define DECODE_OPERAND_REG(RegClass) \ 96 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 97 98 DECODE_OPERAND_REG(VGPR_32) 99 DECODE_OPERAND_REG(VS_32) 100 DECODE_OPERAND_REG(VS_64) 101 DECODE_OPERAND_REG(VS_128) 102 103 DECODE_OPERAND_REG(VReg_64) 104 DECODE_OPERAND_REG(VReg_96) 105 DECODE_OPERAND_REG(VReg_128) 106 107 DECODE_OPERAND_REG(SReg_32) 108 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 109 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 110 DECODE_OPERAND_REG(SReg_64) 111 DECODE_OPERAND_REG(SReg_64_XEXEC) 112 DECODE_OPERAND_REG(SReg_128) 113 DECODE_OPERAND_REG(SReg_256) 114 DECODE_OPERAND_REG(SReg_512) 115 116 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, 117 unsigned Imm, 118 uint64_t Addr, 119 const void *Decoder) { 120 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 121 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 122 } 123 124 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, 125 unsigned Imm, 126 uint64_t Addr, 127 const void *Decoder) { 128 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 129 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 130 } 131 132 #define DECODE_SDWA(DecName) \ 133 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 134 135 DECODE_SDWA(Src32) 136 DECODE_SDWA(Src16) 137 DECODE_SDWA(VopcDst) 138 139 #include "AMDGPUGenDisassemblerTables.inc" 140 141 //===----------------------------------------------------------------------===// 142 // 143 //===----------------------------------------------------------------------===// 144 145 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 146 assert(Bytes.size() >= sizeof(T)); 147 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 148 Bytes = Bytes.slice(sizeof(T)); 149 return Res; 150 } 151 152 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table, 153 MCInst &MI, 154 uint64_t Inst, 155 uint64_t Address) const { 156 assert(MI.getOpcode() == 0); 157 assert(MI.getNumOperands() == 0); 158 MCInst TmpInst; 159 HasLiteral = false; 160 const auto SavedBytes = Bytes; 161 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) { 162 MI = TmpInst; 163 return MCDisassembler::Success; 164 } 165 Bytes = SavedBytes; 166 return MCDisassembler::Fail; 167 } 168 169 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 170 ArrayRef<uint8_t> Bytes_, 171 uint64_t Address, 172 raw_ostream &WS, 173 raw_ostream &CS) const { 174 CommentStream = &CS; 175 bool IsSDWA = false; 176 177 // ToDo: AMDGPUDisassembler supports only VI ISA. 178 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding]) 179 report_fatal_error("Disassembly not yet supported for subtarget"); 180 181 const unsigned MaxInstBytesNum = (std::min)((size_t)8, Bytes_.size()); 182 Bytes = Bytes_.slice(0, MaxInstBytesNum); 183 184 DecodeStatus Res = MCDisassembler::Fail; 185 do { 186 // ToDo: better to switch encoding length using some bit predicate 187 // but it is unknown yet, so try all we can 188 189 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 190 // encodings 191 if (Bytes.size() >= 8) { 192 const uint64_t QW = eatBytes<uint64_t>(Bytes); 193 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 194 if (Res) break; 195 196 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 197 if (Res) { IsSDWA = true; break; } 198 199 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 200 if (Res) { IsSDWA = true; break; } 201 } 202 203 // Reinitialize Bytes as DPP64 could have eaten too much 204 Bytes = Bytes_.slice(0, MaxInstBytesNum); 205 206 // Try decode 32-bit instruction 207 if (Bytes.size() < 4) break; 208 const uint32_t DW = eatBytes<uint32_t>(Bytes); 209 Res = tryDecodeInst(DecoderTableVI32, MI, DW, Address); 210 if (Res) break; 211 212 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 213 if (Res) break; 214 215 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 216 if (Res) break; 217 218 if (Bytes.size() < 4) break; 219 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 220 Res = tryDecodeInst(DecoderTableVI64, MI, QW, Address); 221 if (Res) break; 222 223 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 224 if (Res) break; 225 226 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 227 } while (false); 228 229 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 230 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si || 231 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) { 232 // Insert dummy unused src2_modifiers. 233 insertNamedMCOperand(MI, MCOperand::createImm(0), 234 AMDGPU::OpName::src2_modifiers); 235 } 236 237 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 238 Res = convertMIMGInst(MI); 239 } 240 241 if (Res && IsSDWA) 242 Res = convertSDWAInst(MI); 243 244 Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0; 245 return Res; 246 } 247 248 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 249 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 250 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 251 // VOPC - insert clamp 252 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 253 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 254 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 255 if (SDst != -1) { 256 // VOPC - insert VCC register as sdst 257 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 258 AMDGPU::OpName::sdst); 259 } else { 260 // VOP1/2 - insert omod if present in instruction 261 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 262 } 263 } 264 return MCDisassembler::Success; 265 } 266 267 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 268 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 269 AMDGPU::OpName::vdst); 270 271 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 272 AMDGPU::OpName::vdata); 273 274 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 275 AMDGPU::OpName::dmask); 276 277 assert(VDataIdx != -1); 278 assert(DMaskIdx != -1); 279 280 bool isAtomic = (VDstIdx != -1); 281 282 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 283 if (DMask == 0) 284 return MCDisassembler::Success; 285 286 unsigned ChannelCount = countPopulation(DMask); 287 if (ChannelCount == 1) 288 return MCDisassembler::Success; 289 290 int NewOpcode = -1; 291 292 if (isAtomic) { 293 if (DMask == 0x1 || DMask == 0x3 || DMask == 0xF) { 294 NewOpcode = AMDGPU::getMaskedMIMGAtomicOp(*MCII, MI.getOpcode(), ChannelCount); 295 } 296 if (NewOpcode == -1) return MCDisassembler::Success; 297 } else { 298 NewOpcode = AMDGPU::getMaskedMIMGOp(*MCII, MI.getOpcode(), ChannelCount); 299 assert(NewOpcode != -1 && "could not find matching mimg channel instruction"); 300 } 301 302 auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 303 304 // Get first subregister of VData 305 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 306 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 307 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 308 309 // Widen the register to the correct number of enabled channels. 310 auto NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 311 &MRI.getRegClass(RCID)); 312 if (NewVdata == AMDGPU::NoRegister) { 313 // It's possible to encode this such that the low register + enabled 314 // components exceeds the register count. 315 return MCDisassembler::Success; 316 } 317 318 MI.setOpcode(NewOpcode); 319 // vaddr will be always appear as a single VGPR. This will look different than 320 // how it is usually emitted because the number of register components is not 321 // in the instruction encoding. 322 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 323 324 if (isAtomic) { 325 // Atomic operations have an additional operand (a copy of data) 326 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 327 } 328 329 return MCDisassembler::Success; 330 } 331 332 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 333 return getContext().getRegisterInfo()-> 334 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 335 } 336 337 inline 338 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 339 const Twine& ErrMsg) const { 340 *CommentStream << "Error: " + ErrMsg; 341 342 // ToDo: add support for error operands to MCInst.h 343 // return MCOperand::createError(V); 344 return MCOperand(); 345 } 346 347 inline 348 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 349 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 350 } 351 352 inline 353 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 354 unsigned Val) const { 355 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 356 if (Val >= RegCl.getNumRegs()) 357 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 358 ": unknown register " + Twine(Val)); 359 return createRegOperand(RegCl.getRegister(Val)); 360 } 361 362 inline 363 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 364 unsigned Val) const { 365 // ToDo: SI/CI have 104 SGPRs, VI - 102 366 // Valery: here we accepting as much as we can, let assembler sort it out 367 int shift = 0; 368 switch (SRegClassID) { 369 case AMDGPU::SGPR_32RegClassID: 370 case AMDGPU::TTMP_32RegClassID: 371 break; 372 case AMDGPU::SGPR_64RegClassID: 373 case AMDGPU::TTMP_64RegClassID: 374 shift = 1; 375 break; 376 case AMDGPU::SGPR_128RegClassID: 377 case AMDGPU::TTMP_128RegClassID: 378 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 379 // this bundle? 380 case AMDGPU::SGPR_256RegClassID: 381 case AMDGPU::TTMP_256RegClassID: 382 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 383 // this bundle? 384 case AMDGPU::SGPR_512RegClassID: 385 case AMDGPU::TTMP_512RegClassID: 386 shift = 2; 387 break; 388 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 389 // this bundle? 390 default: 391 llvm_unreachable("unhandled register class"); 392 } 393 394 if (Val % (1 << shift)) { 395 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 396 << ": scalar reg isn't aligned " << Val; 397 } 398 399 return createRegOperand(SRegClassID, Val >> shift); 400 } 401 402 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 403 return decodeSrcOp(OPW32, Val); 404 } 405 406 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 407 return decodeSrcOp(OPW64, Val); 408 } 409 410 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 411 return decodeSrcOp(OPW128, Val); 412 } 413 414 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 415 return decodeSrcOp(OPW16, Val); 416 } 417 418 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 419 return decodeSrcOp(OPWV216, Val); 420 } 421 422 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 423 // Some instructions have operand restrictions beyond what the encoding 424 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 425 // high bit. 426 Val &= 255; 427 428 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 429 } 430 431 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 432 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 433 } 434 435 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 436 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 437 } 438 439 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 440 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 441 } 442 443 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 444 // table-gen generated disassembler doesn't care about operand types 445 // leaving only registry class so SSrc_32 operand turns into SReg_32 446 // and therefore we accept immediates and literals here as well 447 return decodeSrcOp(OPW32, Val); 448 } 449 450 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 451 unsigned Val) const { 452 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 453 return decodeOperand_SReg_32(Val); 454 } 455 456 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 457 unsigned Val) const { 458 // SReg_32_XM0 is SReg_32 without EXEC_HI 459 return decodeOperand_SReg_32(Val); 460 } 461 462 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 463 return decodeSrcOp(OPW64, Val); 464 } 465 466 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 467 return decodeSrcOp(OPW64, Val); 468 } 469 470 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 471 return decodeSrcOp(OPW128, Val); 472 } 473 474 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 475 return decodeDstOp(OPW256, Val); 476 } 477 478 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 479 return decodeDstOp(OPW512, Val); 480 } 481 482 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 483 // For now all literal constants are supposed to be unsigned integer 484 // ToDo: deal with signed/unsigned 64-bit integer constants 485 // ToDo: deal with float/double constants 486 if (!HasLiteral) { 487 if (Bytes.size() < 4) { 488 return errOperand(0, "cannot read literal, inst bytes left " + 489 Twine(Bytes.size())); 490 } 491 HasLiteral = true; 492 Literal = eatBytes<uint32_t>(Bytes); 493 } 494 return MCOperand::createImm(Literal); 495 } 496 497 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 498 using namespace AMDGPU::EncValues; 499 500 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 501 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 502 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 503 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 504 // Cast prevents negative overflow. 505 } 506 507 static int64_t getInlineImmVal32(unsigned Imm) { 508 switch (Imm) { 509 case 240: 510 return FloatToBits(0.5f); 511 case 241: 512 return FloatToBits(-0.5f); 513 case 242: 514 return FloatToBits(1.0f); 515 case 243: 516 return FloatToBits(-1.0f); 517 case 244: 518 return FloatToBits(2.0f); 519 case 245: 520 return FloatToBits(-2.0f); 521 case 246: 522 return FloatToBits(4.0f); 523 case 247: 524 return FloatToBits(-4.0f); 525 case 248: // 1 / (2 * PI) 526 return 0x3e22f983; 527 default: 528 llvm_unreachable("invalid fp inline imm"); 529 } 530 } 531 532 static int64_t getInlineImmVal64(unsigned Imm) { 533 switch (Imm) { 534 case 240: 535 return DoubleToBits(0.5); 536 case 241: 537 return DoubleToBits(-0.5); 538 case 242: 539 return DoubleToBits(1.0); 540 case 243: 541 return DoubleToBits(-1.0); 542 case 244: 543 return DoubleToBits(2.0); 544 case 245: 545 return DoubleToBits(-2.0); 546 case 246: 547 return DoubleToBits(4.0); 548 case 247: 549 return DoubleToBits(-4.0); 550 case 248: // 1 / (2 * PI) 551 return 0x3fc45f306dc9c882; 552 default: 553 llvm_unreachable("invalid fp inline imm"); 554 } 555 } 556 557 static int64_t getInlineImmVal16(unsigned Imm) { 558 switch (Imm) { 559 case 240: 560 return 0x3800; 561 case 241: 562 return 0xB800; 563 case 242: 564 return 0x3C00; 565 case 243: 566 return 0xBC00; 567 case 244: 568 return 0x4000; 569 case 245: 570 return 0xC000; 571 case 246: 572 return 0x4400; 573 case 247: 574 return 0xC400; 575 case 248: // 1 / (2 * PI) 576 return 0x3118; 577 default: 578 llvm_unreachable("invalid fp inline imm"); 579 } 580 } 581 582 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 583 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 584 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 585 586 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 587 switch (Width) { 588 case OPW32: 589 return MCOperand::createImm(getInlineImmVal32(Imm)); 590 case OPW64: 591 return MCOperand::createImm(getInlineImmVal64(Imm)); 592 case OPW16: 593 case OPWV216: 594 return MCOperand::createImm(getInlineImmVal16(Imm)); 595 default: 596 llvm_unreachable("implement me"); 597 } 598 } 599 600 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 601 using namespace AMDGPU; 602 603 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 604 switch (Width) { 605 default: // fall 606 case OPW32: 607 case OPW16: 608 case OPWV216: 609 return VGPR_32RegClassID; 610 case OPW64: return VReg_64RegClassID; 611 case OPW128: return VReg_128RegClassID; 612 } 613 } 614 615 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 616 using namespace AMDGPU; 617 618 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 619 switch (Width) { 620 default: // fall 621 case OPW32: 622 case OPW16: 623 case OPWV216: 624 return SGPR_32RegClassID; 625 case OPW64: return SGPR_64RegClassID; 626 case OPW128: return SGPR_128RegClassID; 627 case OPW256: return SGPR_256RegClassID; 628 case OPW512: return SGPR_512RegClassID; 629 } 630 } 631 632 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 633 using namespace AMDGPU; 634 635 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 636 switch (Width) { 637 default: // fall 638 case OPW32: 639 case OPW16: 640 case OPWV216: 641 return TTMP_32RegClassID; 642 case OPW64: return TTMP_64RegClassID; 643 case OPW128: return TTMP_128RegClassID; 644 case OPW256: return TTMP_256RegClassID; 645 case OPW512: return TTMP_512RegClassID; 646 } 647 } 648 649 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 650 using namespace AMDGPU::EncValues; 651 652 unsigned TTmpMin = isGFX9() ? TTMP_GFX9_MIN : TTMP_VI_MIN; 653 unsigned TTmpMax = isGFX9() ? TTMP_GFX9_MAX : TTMP_VI_MAX; 654 655 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 656 } 657 658 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const { 659 using namespace AMDGPU::EncValues; 660 661 assert(Val < 512); // enum9 662 663 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 664 return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN); 665 } 666 if (Val <= SGPR_MAX) { 667 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 668 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 669 } 670 671 int TTmpIdx = getTTmpIdx(Val); 672 if (TTmpIdx >= 0) { 673 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 674 } 675 676 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 677 return decodeIntImmed(Val); 678 679 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 680 return decodeFPImmed(Width, Val); 681 682 if (Val == LITERAL_CONST) 683 return decodeLiteralConstant(); 684 685 switch (Width) { 686 case OPW32: 687 case OPW16: 688 case OPWV216: 689 return decodeSpecialReg32(Val); 690 case OPW64: 691 return decodeSpecialReg64(Val); 692 default: 693 llvm_unreachable("unexpected immediate type"); 694 } 695 } 696 697 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 698 using namespace AMDGPU::EncValues; 699 700 assert(Val < 128); 701 assert(Width == OPW256 || Width == OPW512); 702 703 if (Val <= SGPR_MAX) { 704 assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning. 705 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 706 } 707 708 int TTmpIdx = getTTmpIdx(Val); 709 if (TTmpIdx >= 0) { 710 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 711 } 712 713 llvm_unreachable("unknown dst register"); 714 } 715 716 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 717 using namespace AMDGPU; 718 719 switch (Val) { 720 case 102: return createRegOperand(FLAT_SCR_LO); 721 case 103: return createRegOperand(FLAT_SCR_HI); 722 case 104: return createRegOperand(XNACK_MASK_LO); 723 case 105: return createRegOperand(XNACK_MASK_HI); 724 case 106: return createRegOperand(VCC_LO); 725 case 107: return createRegOperand(VCC_HI); 726 case 108: assert(!isGFX9()); return createRegOperand(TBA_LO); 727 case 109: assert(!isGFX9()); return createRegOperand(TBA_HI); 728 case 110: assert(!isGFX9()); return createRegOperand(TMA_LO); 729 case 111: assert(!isGFX9()); return createRegOperand(TMA_HI); 730 case 124: return createRegOperand(M0); 731 case 126: return createRegOperand(EXEC_LO); 732 case 127: return createRegOperand(EXEC_HI); 733 case 235: return createRegOperand(SRC_SHARED_BASE); 734 case 236: return createRegOperand(SRC_SHARED_LIMIT); 735 case 237: return createRegOperand(SRC_PRIVATE_BASE); 736 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 737 // TODO: SRC_POPS_EXITING_WAVE_ID 738 // ToDo: no support for vccz register 739 case 251: break; 740 // ToDo: no support for execz register 741 case 252: break; 742 case 253: return createRegOperand(SCC); 743 default: break; 744 } 745 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 746 } 747 748 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 749 using namespace AMDGPU; 750 751 switch (Val) { 752 case 102: return createRegOperand(FLAT_SCR); 753 case 104: return createRegOperand(XNACK_MASK); 754 case 106: return createRegOperand(VCC); 755 case 108: assert(!isGFX9()); return createRegOperand(TBA); 756 case 110: assert(!isGFX9()); return createRegOperand(TMA); 757 case 126: return createRegOperand(EXEC); 758 default: break; 759 } 760 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 761 } 762 763 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 764 const unsigned Val) const { 765 using namespace AMDGPU::SDWA; 766 using namespace AMDGPU::EncValues; 767 768 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9]) { 769 // XXX: static_cast<int> is needed to avoid stupid warning: 770 // compare with unsigned is always true 771 if (SDWA9EncValues::SRC_VGPR_MIN <= static_cast<int>(Val) && 772 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 773 return createRegOperand(getVgprClassId(Width), 774 Val - SDWA9EncValues::SRC_VGPR_MIN); 775 } 776 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 777 Val <= SDWA9EncValues::SRC_SGPR_MAX) { 778 return createSRegOperand(getSgprClassId(Width), 779 Val - SDWA9EncValues::SRC_SGPR_MIN); 780 } 781 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 782 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 783 return createSRegOperand(getTtmpClassId(Width), 784 Val - SDWA9EncValues::SRC_TTMP_MIN); 785 } 786 787 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 788 789 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 790 return decodeIntImmed(SVal); 791 792 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 793 return decodeFPImmed(Width, SVal); 794 795 return decodeSpecialReg32(SVal); 796 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 797 return createRegOperand(getVgprClassId(Width), Val); 798 } 799 llvm_unreachable("unsupported target"); 800 } 801 802 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 803 return decodeSDWASrc(OPW16, Val); 804 } 805 806 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 807 return decodeSDWASrc(OPW32, Val); 808 } 809 810 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 811 using namespace AMDGPU::SDWA; 812 813 assert(STI.getFeatureBits()[AMDGPU::FeatureGFX9] && 814 "SDWAVopcDst should be present only on GFX9"); 815 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 816 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 817 818 int TTmpIdx = getTTmpIdx(Val); 819 if (TTmpIdx >= 0) { 820 return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx); 821 } else if (Val > AMDGPU::EncValues::SGPR_MAX) { 822 return decodeSpecialReg64(Val); 823 } else { 824 return createSRegOperand(getSgprClassId(OPW64), Val); 825 } 826 } else { 827 return createRegOperand(AMDGPU::VCC); 828 } 829 } 830 831 bool AMDGPUDisassembler::isVI() const { 832 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 833 } 834 835 bool AMDGPUDisassembler::isGFX9() const { 836 return STI.getFeatureBits()[AMDGPU::FeatureGFX9]; 837 } 838 839 //===----------------------------------------------------------------------===// 840 // AMDGPUSymbolizer 841 //===----------------------------------------------------------------------===// 842 843 // Try to find symbol name for specified label 844 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst, 845 raw_ostream &/*cStream*/, int64_t Value, 846 uint64_t /*Address*/, bool IsBranch, 847 uint64_t /*Offset*/, uint64_t /*InstSize*/) { 848 using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>; 849 using SectionSymbolsTy = std::vector<SymbolInfoTy>; 850 851 if (!IsBranch) { 852 return false; 853 } 854 855 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 856 auto Result = std::find_if(Symbols->begin(), Symbols->end(), 857 [Value](const SymbolInfoTy& Val) { 858 return std::get<0>(Val) == static_cast<uint64_t>(Value) 859 && std::get<2>(Val) == ELF::STT_NOTYPE; 860 }); 861 if (Result != Symbols->end()) { 862 auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result)); 863 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 864 Inst.addOperand(MCOperand::createExpr(Add)); 865 return true; 866 } 867 return false; 868 } 869 870 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 871 int64_t Value, 872 uint64_t Address) { 873 llvm_unreachable("unimplemented"); 874 } 875 876 //===----------------------------------------------------------------------===// 877 // Initialization 878 //===----------------------------------------------------------------------===// 879 880 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 881 LLVMOpInfoCallback /*GetOpInfo*/, 882 LLVMSymbolLookupCallback /*SymbolLookUp*/, 883 void *DisInfo, 884 MCContext *Ctx, 885 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 886 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 887 } 888 889 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 890 const MCSubtargetInfo &STI, 891 MCContext &Ctx) { 892 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 893 } 894 895 extern "C" void LLVMInitializeAMDGPUDisassembler() { 896 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 897 createAMDGPUDisassembler); 898 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 899 createAMDGPUSymbolizer); 900 } 901