1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VRegOrLds_32) 123 DECODE_OPERAND_REG(VS_32) 124 DECODE_OPERAND_REG(VS_64) 125 DECODE_OPERAND_REG(VS_128) 126 127 DECODE_OPERAND_REG(VReg_64) 128 DECODE_OPERAND_REG(VReg_96) 129 DECODE_OPERAND_REG(VReg_128) 130 DECODE_OPERAND_REG(VReg_256) 131 DECODE_OPERAND_REG(VReg_512) 132 DECODE_OPERAND_REG(VReg_1024) 133 134 DECODE_OPERAND_REG(SReg_32) 135 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 136 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 137 DECODE_OPERAND_REG(SRegOrLds_32) 138 DECODE_OPERAND_REG(SReg_64) 139 DECODE_OPERAND_REG(SReg_64_XEXEC) 140 DECODE_OPERAND_REG(SReg_128) 141 DECODE_OPERAND_REG(SReg_256) 142 DECODE_OPERAND_REG(SReg_512) 143 144 DECODE_OPERAND_REG(AGPR_32) 145 DECODE_OPERAND_REG(AReg_64) 146 DECODE_OPERAND_REG(AReg_128) 147 DECODE_OPERAND_REG(AReg_256) 148 DECODE_OPERAND_REG(AReg_512) 149 DECODE_OPERAND_REG(AReg_1024) 150 DECODE_OPERAND_REG(AV_32) 151 DECODE_OPERAND_REG(AV_64) 152 DECODE_OPERAND_REG(AV_128) 153 DECODE_OPERAND_REG(AVDst_128) 154 DECODE_OPERAND_REG(AVDst_512) 155 156 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 157 uint64_t Addr, 158 const MCDisassembler *Decoder) { 159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 160 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 161 } 162 163 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 164 uint64_t Addr, 165 const MCDisassembler *Decoder) { 166 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 167 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 168 } 169 170 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, 172 const MCDisassembler *Decoder) { 173 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 174 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 175 } 176 177 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, 179 const MCDisassembler *Decoder) { 180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 181 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 182 } 183 184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, 186 const MCDisassembler *Decoder) { 187 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 188 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 189 } 190 191 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, 193 const MCDisassembler *Decoder) { 194 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 195 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 196 } 197 198 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const MCDisassembler *Decoder) { 201 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 202 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 203 } 204 205 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, 207 const MCDisassembler *Decoder) { 208 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 209 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 210 } 211 212 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, 214 const MCDisassembler *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 220 uint64_t Addr, 221 const MCDisassembler *Decoder) { 222 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 223 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 224 } 225 226 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 227 uint64_t Addr, 228 const MCDisassembler *Decoder) { 229 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 230 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 231 } 232 233 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 234 uint64_t Addr, 235 const MCDisassembler *Decoder) { 236 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 237 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 238 } 239 240 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 241 uint64_t Addr, 242 const MCDisassembler *Decoder) { 243 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 244 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 245 } 246 247 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 248 uint64_t Addr, 249 const MCDisassembler *Decoder) { 250 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 251 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 252 } 253 254 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 255 uint64_t Addr, 256 const MCDisassembler *Decoder) { 257 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 258 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 259 } 260 261 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 262 uint64_t Addr, 263 const MCDisassembler *Decoder) { 264 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 265 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 266 } 267 268 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 269 uint64_t Addr, 270 const MCDisassembler *Decoder) { 271 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 272 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 273 } 274 275 static DecodeStatus 276 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 277 const MCDisassembler *Decoder) { 278 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 279 return addOperand( 280 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 281 } 282 283 static DecodeStatus 284 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 285 const MCDisassembler *Decoder) { 286 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand( 288 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 289 } 290 291 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 292 const MCRegisterInfo *MRI) { 293 if (OpIdx < 0) 294 return false; 295 296 const MCOperand &Op = Inst.getOperand(OpIdx); 297 if (!Op.isReg()) 298 return false; 299 300 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 301 auto Reg = Sub ? Sub : Op.getReg(); 302 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 303 } 304 305 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 306 AMDGPUDisassembler::OpWidthTy Opw, 307 const MCDisassembler *Decoder) { 308 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 309 if (!DAsm->isGFX90A()) { 310 Imm &= 511; 311 } else { 312 // If atomic has both vdata and vdst their register classes are tied. 313 // The bit is decoded along with the vdst, first operand. We need to 314 // change register class to AGPR if vdst was AGPR. 315 // If a DS instruction has both data0 and data1 their register classes 316 // are also tied. 317 unsigned Opc = Inst.getOpcode(); 318 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 319 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 320 : AMDGPU::OpName::vdata; 321 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 322 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 323 if ((int)Inst.getNumOperands() == DataIdx) { 324 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 325 if (IsAGPROperand(Inst, DstIdx, MRI)) 326 Imm |= 512; 327 } 328 329 if (TSFlags & SIInstrFlags::DS) { 330 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 331 if ((int)Inst.getNumOperands() == Data2Idx && 332 IsAGPROperand(Inst, DataIdx, MRI)) 333 Imm |= 512; 334 } 335 } 336 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 337 } 338 339 static DecodeStatus 340 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 341 const MCDisassembler *Decoder) { 342 return decodeOperand_AVLdSt_Any(Inst, Imm, 343 AMDGPUDisassembler::OPW32, Decoder); 344 } 345 346 static DecodeStatus 347 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 348 const MCDisassembler *Decoder) { 349 return decodeOperand_AVLdSt_Any(Inst, Imm, 350 AMDGPUDisassembler::OPW64, Decoder); 351 } 352 353 static DecodeStatus 354 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 355 const MCDisassembler *Decoder) { 356 return decodeOperand_AVLdSt_Any(Inst, Imm, 357 AMDGPUDisassembler::OPW96, Decoder); 358 } 359 360 static DecodeStatus 361 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 362 const MCDisassembler *Decoder) { 363 return decodeOperand_AVLdSt_Any(Inst, Imm, 364 AMDGPUDisassembler::OPW128, Decoder); 365 } 366 367 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 368 uint64_t Addr, 369 const MCDisassembler *Decoder) { 370 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 371 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 372 } 373 374 #define DECODE_SDWA(DecName) \ 375 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 376 377 DECODE_SDWA(Src32) 378 DECODE_SDWA(Src16) 379 DECODE_SDWA(VopcDst) 380 381 #include "AMDGPUGenDisassemblerTables.inc" 382 383 //===----------------------------------------------------------------------===// 384 // 385 //===----------------------------------------------------------------------===// 386 387 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 388 assert(Bytes.size() >= sizeof(T)); 389 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 390 Bytes = Bytes.slice(sizeof(T)); 391 return Res; 392 } 393 394 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 395 assert(Bytes.size() >= 12); 396 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 397 Bytes.data()); 398 Bytes = Bytes.slice(8); 399 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 400 Bytes.data()); 401 Bytes = Bytes.slice(4); 402 return DecoderUInt128(Lo, Hi); 403 } 404 405 // The disassembler is greedy, so we need to check FI operand value to 406 // not parse a dpp if the correct literal is not set. For dpp16 the 407 // autogenerated decoder checks the dpp literal 408 static bool isValidDPP8(const MCInst &MI) { 409 using namespace llvm::AMDGPU::DPP; 410 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 411 assert(FiIdx != -1); 412 if ((unsigned)FiIdx >= MI.getNumOperands()) 413 return false; 414 unsigned Fi = MI.getOperand(FiIdx).getImm(); 415 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 416 } 417 418 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 419 ArrayRef<uint8_t> Bytes_, 420 uint64_t Address, 421 raw_ostream &CS) const { 422 CommentStream = &CS; 423 bool IsSDWA = false; 424 425 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 426 Bytes = Bytes_.slice(0, MaxInstBytesNum); 427 428 DecodeStatus Res = MCDisassembler::Fail; 429 do { 430 // ToDo: better to switch encoding length using some bit predicate 431 // but it is unknown yet, so try all we can 432 433 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 434 // encodings 435 if (isGFX11Plus() && Bytes.size() >= 12 ) { 436 DecoderUInt128 DecW = eat12Bytes(Bytes); 437 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 438 Address); 439 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 440 break; 441 MI = MCInst(); // clear 442 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 443 Address); 444 if (Res) 445 break; 446 } 447 // Reinitialize Bytes 448 Bytes = Bytes_.slice(0, MaxInstBytesNum); 449 450 if (Bytes.size() >= 8) { 451 const uint64_t QW = eatBytes<uint64_t>(Bytes); 452 453 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 454 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 455 if (Res) { 456 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 457 == -1) 458 break; 459 if (convertDPP8Inst(MI) == MCDisassembler::Success) 460 break; 461 MI = MCInst(); // clear 462 } 463 } 464 465 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 466 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 467 break; 468 MI = MCInst(); // clear 469 470 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 471 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 472 break; 473 MI = MCInst(); // clear 474 475 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 476 if (Res) break; 477 478 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 479 if (Res) 480 break; 481 482 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 483 if (Res) { IsSDWA = true; break; } 484 485 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 486 if (Res) { IsSDWA = true; break; } 487 488 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 489 if (Res) { IsSDWA = true; break; } 490 491 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 492 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 493 if (Res) 494 break; 495 } 496 497 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 498 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 499 // table first so we print the correct name. 500 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 501 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 502 if (Res) 503 break; 504 } 505 } 506 507 // Reinitialize Bytes as DPP64 could have eaten too much 508 Bytes = Bytes_.slice(0, MaxInstBytesNum); 509 510 // Try decode 32-bit instruction 511 if (Bytes.size() < 4) break; 512 const uint32_t DW = eatBytes<uint32_t>(Bytes); 513 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 514 if (Res) break; 515 516 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 517 if (Res) break; 518 519 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 520 if (Res) break; 521 522 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 523 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 524 if (Res) 525 break; 526 } 527 528 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 529 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 530 if (Res) break; 531 } 532 533 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 534 if (Res) break; 535 536 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 537 if (Res) break; 538 539 if (Bytes.size() < 4) break; 540 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 541 542 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 543 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 544 if (Res) 545 break; 546 } 547 548 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 549 if (Res) break; 550 551 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 552 if (Res) break; 553 554 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 555 if (Res) break; 556 557 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 558 if (Res) break; 559 560 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 561 } while (false); 562 563 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 564 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 565 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 566 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 567 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 568 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 569 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 570 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 571 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 572 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 || 573 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 574 MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || 575 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 || 576 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx11)) { 577 // Insert dummy unused src2_modifiers. 578 insertNamedMCOperand(MI, MCOperand::createImm(0), 579 AMDGPU::OpName::src2_modifiers); 580 } 581 582 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 583 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 584 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 585 AMDGPU::OpName::cpol); 586 if (CPolPos != -1) { 587 unsigned CPol = 588 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 589 AMDGPU::CPol::GLC : 0; 590 if (MI.getNumOperands() <= (unsigned)CPolPos) { 591 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 592 AMDGPU::OpName::cpol); 593 } else if (CPol) { 594 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 595 } 596 } 597 } 598 599 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 600 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 601 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 602 // GFX90A lost TFE, its place is occupied by ACC. 603 int TFEOpIdx = 604 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 605 if (TFEOpIdx != -1) { 606 auto TFEIter = MI.begin(); 607 std::advance(TFEIter, TFEOpIdx); 608 MI.insert(TFEIter, MCOperand::createImm(0)); 609 } 610 } 611 612 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 613 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 614 int SWZOpIdx = 615 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 616 if (SWZOpIdx != -1) { 617 auto SWZIter = MI.begin(); 618 std::advance(SWZIter, SWZOpIdx); 619 MI.insert(SWZIter, MCOperand::createImm(0)); 620 } 621 } 622 623 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 624 int VAddr0Idx = 625 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 626 int RsrcIdx = 627 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 628 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 629 if (VAddr0Idx >= 0 && NSAArgs > 0) { 630 unsigned NSAWords = (NSAArgs + 3) / 4; 631 if (Bytes.size() < 4 * NSAWords) { 632 Res = MCDisassembler::Fail; 633 } else { 634 for (unsigned i = 0; i < NSAArgs; ++i) { 635 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 636 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 637 MI.insert(MI.begin() + VAddrIdx, 638 createRegOperand(VAddrRCID, Bytes[i])); 639 } 640 Bytes = Bytes.slice(4 * NSAWords); 641 } 642 } 643 644 if (Res) 645 Res = convertMIMGInst(MI); 646 } 647 648 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 649 Res = convertEXPInst(MI); 650 651 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 652 Res = convertVINTERPInst(MI); 653 654 if (Res && IsSDWA) 655 Res = convertSDWAInst(MI); 656 657 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 658 AMDGPU::OpName::vdst_in); 659 if (VDstIn_Idx != -1) { 660 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 661 MCOI::OperandConstraint::TIED_TO); 662 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 663 !MI.getOperand(VDstIn_Idx).isReg() || 664 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 665 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 666 MI.erase(&MI.getOperand(VDstIn_Idx)); 667 insertNamedMCOperand(MI, 668 MCOperand::createReg(MI.getOperand(Tied).getReg()), 669 AMDGPU::OpName::vdst_in); 670 } 671 } 672 673 int ImmLitIdx = 674 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 675 if (Res && ImmLitIdx != -1) 676 Res = convertFMAanyK(MI, ImmLitIdx); 677 678 // if the opcode was not recognized we'll assume a Size of 4 bytes 679 // (unless there are fewer bytes left) 680 Size = Res ? (MaxInstBytesNum - Bytes.size()) 681 : std::min((size_t)4, Bytes_.size()); 682 return Res; 683 } 684 685 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 686 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 687 // The MCInst still has these fields even though they are no longer encoded 688 // in the GFX11 instruction. 689 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 690 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 691 } 692 return MCDisassembler::Success; 693 } 694 695 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 696 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 697 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 698 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 699 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 700 // The MCInst has this field that is not directly encoded in the 701 // instruction. 702 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 703 } 704 return MCDisassembler::Success; 705 } 706 707 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 708 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 709 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 710 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 711 // VOPC - insert clamp 712 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 713 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 714 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 715 if (SDst != -1) { 716 // VOPC - insert VCC register as sdst 717 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 718 AMDGPU::OpName::sdst); 719 } else { 720 // VOP1/2 - insert omod if present in instruction 721 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 722 } 723 } 724 return MCDisassembler::Success; 725 } 726 727 // We must check FI == literal to reject not genuine dpp8 insts, and we must 728 // first add optional MI operands to check FI 729 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 730 unsigned Opc = MI.getOpcode(); 731 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 732 733 // Insert dummy unused src modifiers. 734 if (MI.getNumOperands() < DescNumOps && 735 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 736 insertNamedMCOperand(MI, MCOperand::createImm(0), 737 AMDGPU::OpName::src0_modifiers); 738 739 if (MI.getNumOperands() < DescNumOps && 740 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 741 insertNamedMCOperand(MI, MCOperand::createImm(0), 742 AMDGPU::OpName::src1_modifiers); 743 744 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 745 } 746 747 // Note that before gfx10, the MIMG encoding provided no information about 748 // VADDR size. Consequently, decoded instructions always show address as if it 749 // has 1 dword, which could be not really so. 750 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 751 752 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 753 AMDGPU::OpName::vdst); 754 755 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 756 AMDGPU::OpName::vdata); 757 int VAddr0Idx = 758 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 759 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 760 AMDGPU::OpName::dmask); 761 762 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 763 AMDGPU::OpName::tfe); 764 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 765 AMDGPU::OpName::d16); 766 767 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 768 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 769 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 770 771 assert(VDataIdx != -1); 772 if (BaseOpcode->BVH) { 773 // Add A16 operand for intersect_ray instructions 774 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 775 addOperand(MI, MCOperand::createImm(1)); 776 } 777 return MCDisassembler::Success; 778 } 779 780 bool IsAtomic = (VDstIdx != -1); 781 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 782 bool IsNSA = false; 783 unsigned AddrSize = Info->VAddrDwords; 784 785 if (isGFX10Plus()) { 786 unsigned DimIdx = 787 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 788 int A16Idx = 789 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 790 const AMDGPU::MIMGDimInfo *Dim = 791 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 792 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 793 794 AddrSize = 795 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 796 797 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 798 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 799 if (!IsNSA) { 800 if (AddrSize > 8) 801 AddrSize = 16; 802 } else { 803 if (AddrSize > Info->VAddrDwords) { 804 // The NSA encoding does not contain enough operands for the combination 805 // of base opcode / dimension. Should this be an error? 806 return MCDisassembler::Success; 807 } 808 } 809 } 810 811 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 812 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 813 814 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 815 if (D16 && AMDGPU::hasPackedD16(STI)) { 816 DstSize = (DstSize + 1) / 2; 817 } 818 819 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 820 DstSize += 1; 821 822 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 823 return MCDisassembler::Success; 824 825 int NewOpcode = 826 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 827 if (NewOpcode == -1) 828 return MCDisassembler::Success; 829 830 // Widen the register to the correct number of enabled channels. 831 unsigned NewVdata = AMDGPU::NoRegister; 832 if (DstSize != Info->VDataDwords) { 833 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 834 835 // Get first subregister of VData 836 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 837 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 838 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 839 840 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 841 &MRI.getRegClass(DataRCID)); 842 if (NewVdata == AMDGPU::NoRegister) { 843 // It's possible to encode this such that the low register + enabled 844 // components exceeds the register count. 845 return MCDisassembler::Success; 846 } 847 } 848 849 // If not using NSA on GFX10+, widen address register to correct size. 850 unsigned NewVAddr0 = AMDGPU::NoRegister; 851 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 852 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 853 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 854 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 855 856 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 857 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 858 &MRI.getRegClass(AddrRCID)); 859 if (NewVAddr0 == AMDGPU::NoRegister) 860 return MCDisassembler::Success; 861 } 862 863 MI.setOpcode(NewOpcode); 864 865 if (NewVdata != AMDGPU::NoRegister) { 866 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 867 868 if (IsAtomic) { 869 // Atomic operations have an additional operand (a copy of data) 870 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 871 } 872 } 873 874 if (NewVAddr0 != AMDGPU::NoRegister) { 875 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 876 } else if (IsNSA) { 877 assert(AddrSize <= Info->VAddrDwords); 878 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 879 MI.begin() + VAddr0Idx + Info->VAddrDwords); 880 } 881 882 return MCDisassembler::Success; 883 } 884 885 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 886 int ImmLitIdx) const { 887 assert(HasLiteral && "Should have decoded a literal"); 888 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 889 unsigned DescNumOps = Desc.getNumOperands(); 890 assert(DescNumOps == MI.getNumOperands()); 891 for (unsigned I = 0; I < DescNumOps; ++I) { 892 auto &Op = MI.getOperand(I); 893 auto OpType = Desc.OpInfo[I].OperandType; 894 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 895 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 896 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 897 IsDeferredOp) 898 Op.setImm(Literal); 899 } 900 return MCDisassembler::Success; 901 } 902 903 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 904 return getContext().getRegisterInfo()-> 905 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 906 } 907 908 inline 909 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 910 const Twine& ErrMsg) const { 911 *CommentStream << "Error: " + ErrMsg; 912 913 // ToDo: add support for error operands to MCInst.h 914 // return MCOperand::createError(V); 915 return MCOperand(); 916 } 917 918 inline 919 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 920 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 921 } 922 923 inline 924 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 925 unsigned Val) const { 926 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 927 if (Val >= RegCl.getNumRegs()) 928 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 929 ": unknown register " + Twine(Val)); 930 return createRegOperand(RegCl.getRegister(Val)); 931 } 932 933 inline 934 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 935 unsigned Val) const { 936 // ToDo: SI/CI have 104 SGPRs, VI - 102 937 // Valery: here we accepting as much as we can, let assembler sort it out 938 int shift = 0; 939 switch (SRegClassID) { 940 case AMDGPU::SGPR_32RegClassID: 941 case AMDGPU::TTMP_32RegClassID: 942 break; 943 case AMDGPU::SGPR_64RegClassID: 944 case AMDGPU::TTMP_64RegClassID: 945 shift = 1; 946 break; 947 case AMDGPU::SGPR_128RegClassID: 948 case AMDGPU::TTMP_128RegClassID: 949 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 950 // this bundle? 951 case AMDGPU::SGPR_256RegClassID: 952 case AMDGPU::TTMP_256RegClassID: 953 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 954 // this bundle? 955 case AMDGPU::SGPR_512RegClassID: 956 case AMDGPU::TTMP_512RegClassID: 957 shift = 2; 958 break; 959 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 960 // this bundle? 961 default: 962 llvm_unreachable("unhandled register class"); 963 } 964 965 if (Val % (1 << shift)) { 966 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 967 << ": scalar reg isn't aligned " << Val; 968 } 969 970 return createRegOperand(SRegClassID, Val >> shift); 971 } 972 973 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 974 return decodeSrcOp(OPW32, Val); 975 } 976 977 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 978 return decodeSrcOp(OPW64, Val); 979 } 980 981 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 982 return decodeSrcOp(OPW128, Val); 983 } 984 985 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 986 return decodeSrcOp(OPW16, Val); 987 } 988 989 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 990 return decodeSrcOp(OPWV216, Val); 991 } 992 993 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 994 return decodeSrcOp(OPWV232, Val); 995 } 996 997 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 998 // Some instructions have operand restrictions beyond what the encoding 999 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1000 // high bit. 1001 Val &= 255; 1002 1003 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1004 } 1005 1006 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1007 return decodeSrcOp(OPW32, Val); 1008 } 1009 1010 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1011 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1012 } 1013 1014 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1015 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1016 } 1017 1018 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1019 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1020 } 1021 1022 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1023 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1024 } 1025 1026 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1027 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1028 } 1029 1030 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1031 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1032 } 1033 1034 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1035 return decodeSrcOp(OPW32, Val); 1036 } 1037 1038 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1039 return decodeSrcOp(OPW64, Val); 1040 } 1041 1042 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1043 return decodeSrcOp(OPW128, Val); 1044 } 1045 1046 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1047 using namespace AMDGPU::EncValues; 1048 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1049 return decodeSrcOp(OPW128, Val | IS_VGPR); 1050 } 1051 1052 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1053 using namespace AMDGPU::EncValues; 1054 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1055 return decodeSrcOp(OPW512, Val | IS_VGPR); 1056 } 1057 1058 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1059 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1060 } 1061 1062 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1063 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1064 } 1065 1066 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1067 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1068 } 1069 1070 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1071 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1072 } 1073 1074 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1075 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1076 } 1077 1078 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1079 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1080 } 1081 1082 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1083 // table-gen generated disassembler doesn't care about operand types 1084 // leaving only registry class so SSrc_32 operand turns into SReg_32 1085 // and therefore we accept immediates and literals here as well 1086 return decodeSrcOp(OPW32, Val); 1087 } 1088 1089 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1090 unsigned Val) const { 1091 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1092 return decodeOperand_SReg_32(Val); 1093 } 1094 1095 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1096 unsigned Val) const { 1097 // SReg_32_XM0 is SReg_32 without EXEC_HI 1098 return decodeOperand_SReg_32(Val); 1099 } 1100 1101 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1102 // table-gen generated disassembler doesn't care about operand types 1103 // leaving only registry class so SSrc_32 operand turns into SReg_32 1104 // and therefore we accept immediates and literals here as well 1105 return decodeSrcOp(OPW32, Val); 1106 } 1107 1108 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1109 return decodeSrcOp(OPW64, Val); 1110 } 1111 1112 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1113 return decodeSrcOp(OPW64, Val); 1114 } 1115 1116 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1117 return decodeSrcOp(OPW128, Val); 1118 } 1119 1120 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1121 return decodeDstOp(OPW256, Val); 1122 } 1123 1124 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1125 return decodeDstOp(OPW512, Val); 1126 } 1127 1128 // Decode Literals for insts which always have a literal in the encoding 1129 MCOperand 1130 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1131 if (HasLiteral) { 1132 if (Literal != Val) 1133 return errOperand(Val, "More than one unique literal is illegal"); 1134 } 1135 HasLiteral = true; 1136 Literal = Val; 1137 return MCOperand::createImm(Literal); 1138 } 1139 1140 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1141 // For now all literal constants are supposed to be unsigned integer 1142 // ToDo: deal with signed/unsigned 64-bit integer constants 1143 // ToDo: deal with float/double constants 1144 if (!HasLiteral) { 1145 if (Bytes.size() < 4) { 1146 return errOperand(0, "cannot read literal, inst bytes left " + 1147 Twine(Bytes.size())); 1148 } 1149 HasLiteral = true; 1150 Literal = eatBytes<uint32_t>(Bytes); 1151 } 1152 return MCOperand::createImm(Literal); 1153 } 1154 1155 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1156 using namespace AMDGPU::EncValues; 1157 1158 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1159 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1160 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1161 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1162 // Cast prevents negative overflow. 1163 } 1164 1165 static int64_t getInlineImmVal32(unsigned Imm) { 1166 switch (Imm) { 1167 case 240: 1168 return FloatToBits(0.5f); 1169 case 241: 1170 return FloatToBits(-0.5f); 1171 case 242: 1172 return FloatToBits(1.0f); 1173 case 243: 1174 return FloatToBits(-1.0f); 1175 case 244: 1176 return FloatToBits(2.0f); 1177 case 245: 1178 return FloatToBits(-2.0f); 1179 case 246: 1180 return FloatToBits(4.0f); 1181 case 247: 1182 return FloatToBits(-4.0f); 1183 case 248: // 1 / (2 * PI) 1184 return 0x3e22f983; 1185 default: 1186 llvm_unreachable("invalid fp inline imm"); 1187 } 1188 } 1189 1190 static int64_t getInlineImmVal64(unsigned Imm) { 1191 switch (Imm) { 1192 case 240: 1193 return DoubleToBits(0.5); 1194 case 241: 1195 return DoubleToBits(-0.5); 1196 case 242: 1197 return DoubleToBits(1.0); 1198 case 243: 1199 return DoubleToBits(-1.0); 1200 case 244: 1201 return DoubleToBits(2.0); 1202 case 245: 1203 return DoubleToBits(-2.0); 1204 case 246: 1205 return DoubleToBits(4.0); 1206 case 247: 1207 return DoubleToBits(-4.0); 1208 case 248: // 1 / (2 * PI) 1209 return 0x3fc45f306dc9c882; 1210 default: 1211 llvm_unreachable("invalid fp inline imm"); 1212 } 1213 } 1214 1215 static int64_t getInlineImmVal16(unsigned Imm) { 1216 switch (Imm) { 1217 case 240: 1218 return 0x3800; 1219 case 241: 1220 return 0xB800; 1221 case 242: 1222 return 0x3C00; 1223 case 243: 1224 return 0xBC00; 1225 case 244: 1226 return 0x4000; 1227 case 245: 1228 return 0xC000; 1229 case 246: 1230 return 0x4400; 1231 case 247: 1232 return 0xC400; 1233 case 248: // 1 / (2 * PI) 1234 return 0x3118; 1235 default: 1236 llvm_unreachable("invalid fp inline imm"); 1237 } 1238 } 1239 1240 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1241 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1242 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1243 1244 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1245 switch (Width) { 1246 case OPW32: 1247 case OPW128: // splat constants 1248 case OPW512: 1249 case OPW1024: 1250 case OPWV232: 1251 return MCOperand::createImm(getInlineImmVal32(Imm)); 1252 case OPW64: 1253 case OPW256: 1254 return MCOperand::createImm(getInlineImmVal64(Imm)); 1255 case OPW16: 1256 case OPWV216: 1257 return MCOperand::createImm(getInlineImmVal16(Imm)); 1258 default: 1259 llvm_unreachable("implement me"); 1260 } 1261 } 1262 1263 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1264 using namespace AMDGPU; 1265 1266 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1267 switch (Width) { 1268 default: // fall 1269 case OPW32: 1270 case OPW16: 1271 case OPWV216: 1272 return VGPR_32RegClassID; 1273 case OPW64: 1274 case OPWV232: return VReg_64RegClassID; 1275 case OPW96: return VReg_96RegClassID; 1276 case OPW128: return VReg_128RegClassID; 1277 case OPW160: return VReg_160RegClassID; 1278 case OPW256: return VReg_256RegClassID; 1279 case OPW512: return VReg_512RegClassID; 1280 case OPW1024: return VReg_1024RegClassID; 1281 } 1282 } 1283 1284 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1285 using namespace AMDGPU; 1286 1287 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1288 switch (Width) { 1289 default: // fall 1290 case OPW32: 1291 case OPW16: 1292 case OPWV216: 1293 return AGPR_32RegClassID; 1294 case OPW64: 1295 case OPWV232: return AReg_64RegClassID; 1296 case OPW96: return AReg_96RegClassID; 1297 case OPW128: return AReg_128RegClassID; 1298 case OPW160: return AReg_160RegClassID; 1299 case OPW256: return AReg_256RegClassID; 1300 case OPW512: return AReg_512RegClassID; 1301 case OPW1024: return AReg_1024RegClassID; 1302 } 1303 } 1304 1305 1306 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1307 using namespace AMDGPU; 1308 1309 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1310 switch (Width) { 1311 default: // fall 1312 case OPW32: 1313 case OPW16: 1314 case OPWV216: 1315 return SGPR_32RegClassID; 1316 case OPW64: 1317 case OPWV232: return SGPR_64RegClassID; 1318 case OPW96: return SGPR_96RegClassID; 1319 case OPW128: return SGPR_128RegClassID; 1320 case OPW160: return SGPR_160RegClassID; 1321 case OPW256: return SGPR_256RegClassID; 1322 case OPW512: return SGPR_512RegClassID; 1323 } 1324 } 1325 1326 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1327 using namespace AMDGPU; 1328 1329 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1330 switch (Width) { 1331 default: // fall 1332 case OPW32: 1333 case OPW16: 1334 case OPWV216: 1335 return TTMP_32RegClassID; 1336 case OPW64: 1337 case OPWV232: return TTMP_64RegClassID; 1338 case OPW128: return TTMP_128RegClassID; 1339 case OPW256: return TTMP_256RegClassID; 1340 case OPW512: return TTMP_512RegClassID; 1341 } 1342 } 1343 1344 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1345 using namespace AMDGPU::EncValues; 1346 1347 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1348 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1349 1350 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1351 } 1352 1353 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1354 bool MandatoryLiteral) const { 1355 using namespace AMDGPU::EncValues; 1356 1357 assert(Val < 1024); // enum10 1358 1359 bool IsAGPR = Val & 512; 1360 Val &= 511; 1361 1362 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1363 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1364 : getVgprClassId(Width), Val - VGPR_MIN); 1365 } 1366 if (Val <= SGPR_MAX) { 1367 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1368 static_assert(SGPR_MIN == 0, ""); 1369 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1370 } 1371 1372 int TTmpIdx = getTTmpIdx(Val); 1373 if (TTmpIdx >= 0) { 1374 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1375 } 1376 1377 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1378 return decodeIntImmed(Val); 1379 1380 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1381 return decodeFPImmed(Width, Val); 1382 1383 if (Val == LITERAL_CONST) { 1384 if (MandatoryLiteral) 1385 // Keep a sentinel value for deferred setting 1386 return MCOperand::createImm(LITERAL_CONST); 1387 else 1388 return decodeLiteralConstant(); 1389 } 1390 1391 switch (Width) { 1392 case OPW32: 1393 case OPW16: 1394 case OPWV216: 1395 return decodeSpecialReg32(Val); 1396 case OPW64: 1397 case OPWV232: 1398 return decodeSpecialReg64(Val); 1399 default: 1400 llvm_unreachable("unexpected immediate type"); 1401 } 1402 } 1403 1404 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1405 using namespace AMDGPU::EncValues; 1406 1407 assert(Val < 128); 1408 assert(Width == OPW256 || Width == OPW512); 1409 1410 if (Val <= SGPR_MAX) { 1411 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1412 static_assert(SGPR_MIN == 0, ""); 1413 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1414 } 1415 1416 int TTmpIdx = getTTmpIdx(Val); 1417 if (TTmpIdx >= 0) { 1418 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1419 } 1420 1421 llvm_unreachable("unknown dst register"); 1422 } 1423 1424 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1425 using namespace AMDGPU; 1426 1427 switch (Val) { 1428 case 102: return createRegOperand(FLAT_SCR_LO); 1429 case 103: return createRegOperand(FLAT_SCR_HI); 1430 case 104: return createRegOperand(XNACK_MASK_LO); 1431 case 105: return createRegOperand(XNACK_MASK_HI); 1432 case 106: return createRegOperand(VCC_LO); 1433 case 107: return createRegOperand(VCC_HI); 1434 case 108: return createRegOperand(TBA_LO); 1435 case 109: return createRegOperand(TBA_HI); 1436 case 110: return createRegOperand(TMA_LO); 1437 case 111: return createRegOperand(TMA_HI); 1438 case 124: 1439 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1440 case 125: 1441 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1442 case 126: return createRegOperand(EXEC_LO); 1443 case 127: return createRegOperand(EXEC_HI); 1444 case 235: return createRegOperand(SRC_SHARED_BASE); 1445 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1446 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1447 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1448 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1449 case 251: return createRegOperand(SRC_VCCZ); 1450 case 252: return createRegOperand(SRC_EXECZ); 1451 case 253: return createRegOperand(SRC_SCC); 1452 case 254: return createRegOperand(LDS_DIRECT); 1453 default: break; 1454 } 1455 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1456 } 1457 1458 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1459 using namespace AMDGPU; 1460 1461 switch (Val) { 1462 case 102: return createRegOperand(FLAT_SCR); 1463 case 104: return createRegOperand(XNACK_MASK); 1464 case 106: return createRegOperand(VCC); 1465 case 108: return createRegOperand(TBA); 1466 case 110: return createRegOperand(TMA); 1467 case 124: 1468 if (isGFX11Plus()) 1469 return createRegOperand(SGPR_NULL); 1470 break; 1471 case 125: 1472 if (!isGFX11Plus()) 1473 return createRegOperand(SGPR_NULL); 1474 break; 1475 case 126: return createRegOperand(EXEC); 1476 case 235: return createRegOperand(SRC_SHARED_BASE); 1477 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1478 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1479 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1480 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1481 case 251: return createRegOperand(SRC_VCCZ); 1482 case 252: return createRegOperand(SRC_EXECZ); 1483 case 253: return createRegOperand(SRC_SCC); 1484 default: break; 1485 } 1486 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1487 } 1488 1489 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1490 const unsigned Val) const { 1491 using namespace AMDGPU::SDWA; 1492 using namespace AMDGPU::EncValues; 1493 1494 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1495 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1496 // XXX: cast to int is needed to avoid stupid warning: 1497 // compare with unsigned is always true 1498 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1499 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1500 return createRegOperand(getVgprClassId(Width), 1501 Val - SDWA9EncValues::SRC_VGPR_MIN); 1502 } 1503 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1504 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1505 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1506 return createSRegOperand(getSgprClassId(Width), 1507 Val - SDWA9EncValues::SRC_SGPR_MIN); 1508 } 1509 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1510 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1511 return createSRegOperand(getTtmpClassId(Width), 1512 Val - SDWA9EncValues::SRC_TTMP_MIN); 1513 } 1514 1515 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1516 1517 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1518 return decodeIntImmed(SVal); 1519 1520 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1521 return decodeFPImmed(Width, SVal); 1522 1523 return decodeSpecialReg32(SVal); 1524 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1525 return createRegOperand(getVgprClassId(Width), Val); 1526 } 1527 llvm_unreachable("unsupported target"); 1528 } 1529 1530 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1531 return decodeSDWASrc(OPW16, Val); 1532 } 1533 1534 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1535 return decodeSDWASrc(OPW32, Val); 1536 } 1537 1538 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1539 using namespace AMDGPU::SDWA; 1540 1541 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1542 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1543 "SDWAVopcDst should be present only on GFX9+"); 1544 1545 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1546 1547 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1548 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1549 1550 int TTmpIdx = getTTmpIdx(Val); 1551 if (TTmpIdx >= 0) { 1552 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1553 return createSRegOperand(TTmpClsId, TTmpIdx); 1554 } else if (Val > SGPR_MAX) { 1555 return IsWave64 ? decodeSpecialReg64(Val) 1556 : decodeSpecialReg32(Val); 1557 } else { 1558 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1559 } 1560 } else { 1561 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1562 } 1563 } 1564 1565 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1566 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1567 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1568 } 1569 1570 bool AMDGPUDisassembler::isVI() const { 1571 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1572 } 1573 1574 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1575 1576 bool AMDGPUDisassembler::isGFX90A() const { 1577 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1578 } 1579 1580 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1581 1582 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1583 1584 bool AMDGPUDisassembler::isGFX10Plus() const { 1585 return AMDGPU::isGFX10Plus(STI); 1586 } 1587 1588 bool AMDGPUDisassembler::isGFX11() const { 1589 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1590 } 1591 1592 bool AMDGPUDisassembler::isGFX11Plus() const { 1593 return AMDGPU::isGFX11Plus(STI); 1594 } 1595 1596 1597 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1598 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1599 } 1600 1601 //===----------------------------------------------------------------------===// 1602 // AMDGPU specific symbol handling 1603 //===----------------------------------------------------------------------===// 1604 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1605 do { \ 1606 KdStream << Indent << DIRECTIVE " " \ 1607 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1608 } while (0) 1609 1610 // NOLINTNEXTLINE(readability-identifier-naming) 1611 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1612 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1613 using namespace amdhsa; 1614 StringRef Indent = "\t"; 1615 1616 // We cannot accurately backward compute #VGPRs used from 1617 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1618 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1619 // simply calculate the inverse of what the assembler does. 1620 1621 uint32_t GranulatedWorkitemVGPRCount = 1622 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1623 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1624 1625 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1626 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1627 1628 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1629 1630 // We cannot backward compute values used to calculate 1631 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1632 // directives can't be computed: 1633 // .amdhsa_reserve_vcc 1634 // .amdhsa_reserve_flat_scratch 1635 // .amdhsa_reserve_xnack_mask 1636 // They take their respective default values if not specified in the assembly. 1637 // 1638 // GRANULATED_WAVEFRONT_SGPR_COUNT 1639 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1640 // 1641 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1642 // are set to 0. So while disassembling we consider that: 1643 // 1644 // GRANULATED_WAVEFRONT_SGPR_COUNT 1645 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1646 // 1647 // The disassembler cannot recover the original values of those 3 directives. 1648 1649 uint32_t GranulatedWavefrontSGPRCount = 1650 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1651 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1652 1653 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1654 return MCDisassembler::Fail; 1655 1656 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1657 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1658 1659 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1660 if (!hasArchitectedFlatScratch()) 1661 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1662 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1663 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1664 1665 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1666 return MCDisassembler::Fail; 1667 1668 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1669 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1670 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1671 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1672 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1673 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1674 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1675 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1676 1677 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1678 return MCDisassembler::Fail; 1679 1680 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1681 1682 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1683 return MCDisassembler::Fail; 1684 1685 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1686 1687 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1688 return MCDisassembler::Fail; 1689 1690 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1691 return MCDisassembler::Fail; 1692 1693 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1694 1695 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1696 return MCDisassembler::Fail; 1697 1698 if (isGFX10Plus()) { 1699 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1700 COMPUTE_PGM_RSRC1_WGP_MODE); 1701 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1702 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1703 } 1704 return MCDisassembler::Success; 1705 } 1706 1707 // NOLINTNEXTLINE(readability-identifier-naming) 1708 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1709 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1710 using namespace amdhsa; 1711 StringRef Indent = "\t"; 1712 if (hasArchitectedFlatScratch()) 1713 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1714 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1715 else 1716 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1717 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1718 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1719 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1720 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1721 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1722 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1723 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1724 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1725 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1726 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1727 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1728 1729 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1730 return MCDisassembler::Fail; 1731 1732 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1733 return MCDisassembler::Fail; 1734 1735 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1736 return MCDisassembler::Fail; 1737 1738 PRINT_DIRECTIVE( 1739 ".amdhsa_exception_fp_ieee_invalid_op", 1740 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1741 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1742 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1743 PRINT_DIRECTIVE( 1744 ".amdhsa_exception_fp_ieee_div_zero", 1745 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1746 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1747 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1748 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1749 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1750 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1751 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1752 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1753 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1754 1755 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1756 return MCDisassembler::Fail; 1757 1758 return MCDisassembler::Success; 1759 } 1760 1761 #undef PRINT_DIRECTIVE 1762 1763 MCDisassembler::DecodeStatus 1764 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1765 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1766 raw_string_ostream &KdStream) const { 1767 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1768 do { \ 1769 KdStream << Indent << DIRECTIVE " " \ 1770 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1771 } while (0) 1772 1773 uint16_t TwoByteBuffer = 0; 1774 uint32_t FourByteBuffer = 0; 1775 1776 StringRef ReservedBytes; 1777 StringRef Indent = "\t"; 1778 1779 assert(Bytes.size() == 64); 1780 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1781 1782 switch (Cursor.tell()) { 1783 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1784 FourByteBuffer = DE.getU32(Cursor); 1785 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1786 << '\n'; 1787 return MCDisassembler::Success; 1788 1789 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1790 FourByteBuffer = DE.getU32(Cursor); 1791 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1792 << FourByteBuffer << '\n'; 1793 return MCDisassembler::Success; 1794 1795 case amdhsa::KERNARG_SIZE_OFFSET: 1796 FourByteBuffer = DE.getU32(Cursor); 1797 KdStream << Indent << ".amdhsa_kernarg_size " 1798 << FourByteBuffer << '\n'; 1799 return MCDisassembler::Success; 1800 1801 case amdhsa::RESERVED0_OFFSET: 1802 // 4 reserved bytes, must be 0. 1803 ReservedBytes = DE.getBytes(Cursor, 4); 1804 for (int I = 0; I < 4; ++I) { 1805 if (ReservedBytes[I] != 0) { 1806 return MCDisassembler::Fail; 1807 } 1808 } 1809 return MCDisassembler::Success; 1810 1811 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1812 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1813 // So far no directive controls this for Code Object V3, so simply skip for 1814 // disassembly. 1815 DE.skip(Cursor, 8); 1816 return MCDisassembler::Success; 1817 1818 case amdhsa::RESERVED1_OFFSET: 1819 // 20 reserved bytes, must be 0. 1820 ReservedBytes = DE.getBytes(Cursor, 20); 1821 for (int I = 0; I < 20; ++I) { 1822 if (ReservedBytes[I] != 0) { 1823 return MCDisassembler::Fail; 1824 } 1825 } 1826 return MCDisassembler::Success; 1827 1828 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1829 // COMPUTE_PGM_RSRC3 1830 // - Only set for GFX10, GFX6-9 have this to be 0. 1831 // - Currently no directives directly control this. 1832 FourByteBuffer = DE.getU32(Cursor); 1833 if (!isGFX10Plus() && FourByteBuffer) { 1834 return MCDisassembler::Fail; 1835 } 1836 return MCDisassembler::Success; 1837 1838 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1839 FourByteBuffer = DE.getU32(Cursor); 1840 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1841 MCDisassembler::Fail) { 1842 return MCDisassembler::Fail; 1843 } 1844 return MCDisassembler::Success; 1845 1846 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1847 FourByteBuffer = DE.getU32(Cursor); 1848 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1849 MCDisassembler::Fail) { 1850 return MCDisassembler::Fail; 1851 } 1852 return MCDisassembler::Success; 1853 1854 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1855 using namespace amdhsa; 1856 TwoByteBuffer = DE.getU16(Cursor); 1857 1858 if (!hasArchitectedFlatScratch()) 1859 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1860 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1861 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1862 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1863 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1864 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1865 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1866 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1867 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1868 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1869 if (!hasArchitectedFlatScratch()) 1870 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1871 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1872 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1873 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1874 1875 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1876 return MCDisassembler::Fail; 1877 1878 // Reserved for GFX9 1879 if (isGFX9() && 1880 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1881 return MCDisassembler::Fail; 1882 } else if (isGFX10Plus()) { 1883 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1884 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1885 } 1886 1887 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 1888 return MCDisassembler::Fail; 1889 1890 return MCDisassembler::Success; 1891 1892 case amdhsa::RESERVED2_OFFSET: 1893 // 6 bytes from here are reserved, must be 0. 1894 ReservedBytes = DE.getBytes(Cursor, 6); 1895 for (int I = 0; I < 6; ++I) { 1896 if (ReservedBytes[I] != 0) 1897 return MCDisassembler::Fail; 1898 } 1899 return MCDisassembler::Success; 1900 1901 default: 1902 llvm_unreachable("Unhandled index. Case statements cover everything."); 1903 return MCDisassembler::Fail; 1904 } 1905 #undef PRINT_DIRECTIVE 1906 } 1907 1908 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 1909 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 1910 // CP microcode requires the kernel descriptor to be 64 aligned. 1911 if (Bytes.size() != 64 || KdAddress % 64 != 0) 1912 return MCDisassembler::Fail; 1913 1914 std::string Kd; 1915 raw_string_ostream KdStream(Kd); 1916 KdStream << ".amdhsa_kernel " << KdName << '\n'; 1917 1918 DataExtractor::Cursor C(0); 1919 while (C && C.tell() < Bytes.size()) { 1920 MCDisassembler::DecodeStatus Status = 1921 decodeKernelDescriptorDirective(C, Bytes, KdStream); 1922 1923 cantFail(C.takeError()); 1924 1925 if (Status == MCDisassembler::Fail) 1926 return MCDisassembler::Fail; 1927 } 1928 KdStream << ".end_amdhsa_kernel\n"; 1929 outs() << KdStream.str(); 1930 return MCDisassembler::Success; 1931 } 1932 1933 Optional<MCDisassembler::DecodeStatus> 1934 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 1935 ArrayRef<uint8_t> Bytes, uint64_t Address, 1936 raw_ostream &CStream) const { 1937 // Right now only kernel descriptor needs to be handled. 1938 // We ignore all other symbols for target specific handling. 1939 // TODO: 1940 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 1941 // Object V2 and V3 when symbols are marked protected. 1942 1943 // amd_kernel_code_t for Code Object V2. 1944 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 1945 Size = 256; 1946 return MCDisassembler::Fail; 1947 } 1948 1949 // Code Object V3 kernel descriptors. 1950 StringRef Name = Symbol.Name; 1951 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 1952 Size = 64; // Size = 64 regardless of success or failure. 1953 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 1954 } 1955 return None; 1956 } 1957 1958 //===----------------------------------------------------------------------===// 1959 // AMDGPUSymbolizer 1960 //===----------------------------------------------------------------------===// 1961 1962 // Try to find symbol name for specified label 1963 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 1964 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 1965 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 1966 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 1967 1968 if (!IsBranch) { 1969 return false; 1970 } 1971 1972 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 1973 if (!Symbols) 1974 return false; 1975 1976 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 1977 return Val.Addr == static_cast<uint64_t>(Value) && 1978 Val.Type == ELF::STT_NOTYPE; 1979 }); 1980 if (Result != Symbols->end()) { 1981 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 1982 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 1983 Inst.addOperand(MCOperand::createExpr(Add)); 1984 return true; 1985 } 1986 // Add to list of referenced addresses, so caller can synthesize a label. 1987 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 1988 return false; 1989 } 1990 1991 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 1992 int64_t Value, 1993 uint64_t Address) { 1994 llvm_unreachable("unimplemented"); 1995 } 1996 1997 //===----------------------------------------------------------------------===// 1998 // Initialization 1999 //===----------------------------------------------------------------------===// 2000 2001 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2002 LLVMOpInfoCallback /*GetOpInfo*/, 2003 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2004 void *DisInfo, 2005 MCContext *Ctx, 2006 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2007 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2008 } 2009 2010 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2011 const MCSubtargetInfo &STI, 2012 MCContext &Ctx) { 2013 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2014 } 2015 2016 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2017 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2018 createAMDGPUDisassembler); 2019 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2020 createAMDGPUSymbolizer); 2021 } 2022