xref: /llvm-project/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp (revision 0846c125f98ba6e1013b5acd1b161bd32b395bf8) 
1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 //===----------------------------------------------------------------------===//
10 //
11 /// \file
12 ///
13 /// This file contains definition for AMDGPU ISA disassembler
14 //
15 //===----------------------------------------------------------------------===//
16 
17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)?
18 
19 #include "Disassembler/AMDGPUDisassembler.h"
20 #include "AMDGPU.h"
21 #include "AMDGPURegisterInfo.h"
22 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
23 #include "SIDefines.h"
24 #include "TargetInfo/AMDGPUTargetInfo.h"
25 #include "Utils/AMDGPUBaseInfo.h"
26 #include "llvm-c/Disassembler.h"
27 #include "llvm/ADT/APInt.h"
28 #include "llvm/ADT/ArrayRef.h"
29 #include "llvm/ADT/Twine.h"
30 #include "llvm/BinaryFormat/ELF.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
34 #include "llvm/MC/MCExpr.h"
35 #include "llvm/MC/MCFixedLenDisassembler.h"
36 #include "llvm/MC/MCInst.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/Support/Endian.h"
39 #include "llvm/Support/ErrorHandling.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/TargetRegistry.h"
42 #include "llvm/Support/raw_ostream.h"
43 #include <algorithm>
44 #include <cassert>
45 #include <cstddef>
46 #include <cstdint>
47 #include <iterator>
48 #include <tuple>
49 #include <vector>
50 
51 using namespace llvm;
52 
53 #define DEBUG_TYPE "amdgpu-disassembler"
54 
55 #define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
56                             : AMDGPU::EncValues::SGPR_MAX_SI)
57 
58 using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
59 
60 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
61                                        MCContext &Ctx,
62                                        MCInstrInfo const *MCII) :
63   MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()),
64   TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
65 
66   // ToDo: AMDGPUDisassembler supports only VI ISA.
67   if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
68     report_fatal_error("Disassembly not yet supported for subtarget");
69 }
70 
71 inline static MCDisassembler::DecodeStatus
72 addOperand(MCInst &Inst, const MCOperand& Opnd) {
73   Inst.addOperand(Opnd);
74   return Opnd.isValid() ?
75     MCDisassembler::Success :
76     MCDisassembler::SoftFail;
77 }
78 
79 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op,
80                                 uint16_t NameIdx) {
81   int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
82   if (OpIdx != -1) {
83     auto I = MI.begin();
84     std::advance(I, OpIdx);
85     MI.insert(I, Op);
86   }
87   return OpIdx;
88 }
89 
90 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm,
91                                        uint64_t Addr, const void *Decoder) {
92   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
93 
94   // Our branches take a simm16, but we need two extra bits to account for the
95   // factor of 4.
96   APInt SignedOffset(18, Imm * 4, true);
97   int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue();
98 
99   if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2))
100     return MCDisassembler::Success;
101   return addOperand(Inst, MCOperand::createImm(Imm));
102 }
103 
104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val,
105                                   uint64_t Addr, const void *Decoder) {
106   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
107   return addOperand(Inst, DAsm->decodeBoolReg(Val));
108 }
109 
110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \
111 static DecodeStatus StaticDecoderName(MCInst &Inst, \
112                                        unsigned Imm, \
113                                        uint64_t /*Addr*/, \
114                                        const void *Decoder) { \
115   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); \
116   return addOperand(Inst, DAsm->DecoderName(Imm)); \
117 }
118 
119 #define DECODE_OPERAND_REG(RegClass) \
120 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass)
121 
122 DECODE_OPERAND_REG(VGPR_32)
123 DECODE_OPERAND_REG(VRegOrLds_32)
124 DECODE_OPERAND_REG(VS_32)
125 DECODE_OPERAND_REG(VS_64)
126 DECODE_OPERAND_REG(VS_128)
127 
128 DECODE_OPERAND_REG(VReg_64)
129 DECODE_OPERAND_REG(VReg_96)
130 DECODE_OPERAND_REG(VReg_128)
131 
132 DECODE_OPERAND_REG(SReg_32)
133 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC)
134 DECODE_OPERAND_REG(SReg_32_XEXEC_HI)
135 DECODE_OPERAND_REG(SRegOrLds_32)
136 DECODE_OPERAND_REG(SReg_64)
137 DECODE_OPERAND_REG(SReg_64_XEXEC)
138 DECODE_OPERAND_REG(SReg_128)
139 DECODE_OPERAND_REG(SReg_256)
140 DECODE_OPERAND_REG(SReg_512)
141 
142 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst,
143                                          unsigned Imm,
144                                          uint64_t Addr,
145                                          const void *Decoder) {
146   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
147   return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm));
148 }
149 
150 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
151                                          unsigned Imm,
152                                          uint64_t Addr,
153                                          const void *Decoder) {
154   auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder);
155   return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
156 }
157 
158 #define DECODE_SDWA(DecName) \
159 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName)
160 
161 DECODE_SDWA(Src32)
162 DECODE_SDWA(Src16)
163 DECODE_SDWA(VopcDst)
164 
165 #include "AMDGPUGenDisassemblerTables.inc"
166 
167 //===----------------------------------------------------------------------===//
168 //
169 //===----------------------------------------------------------------------===//
170 
171 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) {
172   assert(Bytes.size() >= sizeof(T));
173   const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data());
174   Bytes = Bytes.slice(sizeof(T));
175   return Res;
176 }
177 
178 DecodeStatus AMDGPUDisassembler::tryDecodeInst(const uint8_t* Table,
179                                                MCInst &MI,
180                                                uint64_t Inst,
181                                                uint64_t Address) const {
182   assert(MI.getOpcode() == 0);
183   assert(MI.getNumOperands() == 0);
184   MCInst TmpInst;
185   HasLiteral = false;
186   const auto SavedBytes = Bytes;
187   if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
188     MI = TmpInst;
189     return MCDisassembler::Success;
190   }
191   Bytes = SavedBytes;
192   return MCDisassembler::Fail;
193 }
194 
195 static bool isValidDPP8(const MCInst &MI) {
196   using namespace llvm::AMDGPU::DPP;
197   int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
198   assert(FiIdx != -1);
199   if ((unsigned)FiIdx >= MI.getNumOperands())
200     return false;
201   unsigned Fi = MI.getOperand(FiIdx).getImm();
202   return Fi == DPP8_FI_0 || Fi == DPP8_FI_1;
203 }
204 
205 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
206                                                 ArrayRef<uint8_t> Bytes_,
207                                                 uint64_t Address,
208                                                 raw_ostream &WS,
209                                                 raw_ostream &CS) const {
210   CommentStream = &CS;
211   bool IsSDWA = false;
212 
213   unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size());
214   Bytes = Bytes_.slice(0, MaxInstBytesNum);
215 
216   DecodeStatus Res = MCDisassembler::Fail;
217   do {
218     // ToDo: better to switch encoding length using some bit predicate
219     // but it is unknown yet, so try all we can
220 
221     // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
222     // encodings
223     if (Bytes.size() >= 8) {
224       const uint64_t QW = eatBytes<uint64_t>(Bytes);
225 
226       Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address);
227       if (Res && convertDPP8Inst(MI) == MCDisassembler::Success)
228         break;
229 
230       MI = MCInst(); // clear
231 
232       Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address);
233       if (Res) break;
234 
235       Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address);
236       if (Res) { IsSDWA = true;  break; }
237 
238       Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address);
239       if (Res) { IsSDWA = true;  break; }
240 
241       Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address);
242       if (Res) { IsSDWA = true;  break; }
243 
244       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
245       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
246       // table first so we print the correct name.
247 
248       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
249         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
250         if (Res) break;
251       }
252 
253       if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
254         Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address);
255         if (Res)
256           break;
257       }
258 
259       // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and
260       // v_mad_mixhi_f16 for FMA variants. Try to decode using this special
261       // table first so we print the correct name.
262       if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
263         Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address);
264         if (Res)
265           break;
266       }
267     }
268 
269     // Reinitialize Bytes as DPP64 could have eaten too much
270     Bytes = Bytes_.slice(0, MaxInstBytesNum);
271 
272     // Try decode 32-bit instruction
273     if (Bytes.size() < 4) break;
274     const uint32_t DW = eatBytes<uint32_t>(Bytes);
275     Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address);
276     if (Res) break;
277 
278     Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address);
279     if (Res) break;
280 
281     Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address);
282     if (Res) break;
283 
284     Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address);
285     if (Res) break;
286 
287     if (Bytes.size() < 4) break;
288     const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW;
289     Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address);
290     if (Res) break;
291 
292     Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
293     if (Res) break;
294 
295     Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address);
296     if (Res) break;
297 
298     Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address);
299   } while (false);
300 
301   if (Res && (MaxInstBytesNum - Bytes.size()) == 12 && (!HasLiteral ||
302         !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
303     MaxInstBytesNum = 8;
304     Bytes = Bytes_.slice(0, MaxInstBytesNum);
305     eatBytes<uint64_t>(Bytes);
306   }
307 
308   if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
309               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
310               MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
311               MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
312               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
313               MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
314               MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
315     // Insert dummy unused src2_modifiers.
316     insertNamedMCOperand(MI, MCOperand::createImm(0),
317                          AMDGPU::OpName::src2_modifiers);
318   }
319 
320   if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
321     int VAddr0Idx =
322         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
323     int RsrcIdx =
324         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
325     unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1;
326     if (VAddr0Idx >= 0 && NSAArgs > 0) {
327       unsigned NSAWords = (NSAArgs + 3) / 4;
328       if (Bytes.size() < 4 * NSAWords) {
329         Res = MCDisassembler::Fail;
330       } else {
331         for (unsigned i = 0; i < NSAArgs; ++i) {
332           MI.insert(MI.begin() + VAddr0Idx + 1 + i,
333                     decodeOperand_VGPR_32(Bytes[i]));
334         }
335         Bytes = Bytes.slice(4 * NSAWords);
336       }
337     }
338 
339     if (Res)
340       Res = convertMIMGInst(MI);
341   }
342 
343   if (Res && IsSDWA)
344     Res = convertSDWAInst(MI);
345 
346   int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
347                                               AMDGPU::OpName::vdst_in);
348   if (VDstIn_Idx != -1) {
349     int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
350                            MCOI::OperandConstraint::TIED_TO);
351     if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx ||
352          !MI.getOperand(VDstIn_Idx).isReg() ||
353          MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) {
354       if (MI.getNumOperands() > (unsigned)VDstIn_Idx)
355         MI.erase(&MI.getOperand(VDstIn_Idx));
356       insertNamedMCOperand(MI,
357         MCOperand::createReg(MI.getOperand(Tied).getReg()),
358         AMDGPU::OpName::vdst_in);
359     }
360   }
361 
362   // if the opcode was not recognized we'll assume a Size of 4 bytes
363   // (unless there are fewer bytes left)
364   Size = Res ? (MaxInstBytesNum - Bytes.size())
365              : std::min((size_t)4, Bytes_.size());
366   return Res;
367 }
368 
369 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
370   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
371       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
372     if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
373       // VOPC - insert clamp
374       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
375   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
376     int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
377     if (SDst != -1) {
378       // VOPC - insert VCC register as sdst
379       insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC),
380                            AMDGPU::OpName::sdst);
381     } else {
382       // VOP1/2 - insert omod if present in instruction
383       insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
384     }
385   }
386   return MCDisassembler::Success;
387 }
388 
389 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
390   unsigned Opc = MI.getOpcode();
391   unsigned DescNumOps = MCII->get(Opc).getNumOperands();
392 
393   // Insert dummy unused src modifiers.
394   if (MI.getNumOperands() < DescNumOps &&
395       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
396     insertNamedMCOperand(MI, MCOperand::createImm(0),
397                          AMDGPU::OpName::src0_modifiers);
398 
399   if (MI.getNumOperands() < DescNumOps &&
400       AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
401     insertNamedMCOperand(MI, MCOperand::createImm(0),
402                          AMDGPU::OpName::src1_modifiers);
403 
404   return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail;
405 }
406 
407 // Note that before gfx10, the MIMG encoding provided no information about
408 // VADDR size. Consequently, decoded instructions always show address as if it
409 // has 1 dword, which could be not really so.
410 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
411 
412   int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
413                                            AMDGPU::OpName::vdst);
414 
415   int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
416                                             AMDGPU::OpName::vdata);
417   int VAddr0Idx =
418       AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
419   int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
420                                             AMDGPU::OpName::dmask);
421 
422   int TFEIdx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
423                                             AMDGPU::OpName::tfe);
424   int D16Idx   = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
425                                             AMDGPU::OpName::d16);
426 
427   assert(VDataIdx != -1);
428   assert(DMaskIdx != -1);
429   assert(TFEIdx != -1);
430 
431   const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
432   bool IsAtomic = (VDstIdx != -1);
433   bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
434 
435   bool IsNSA = false;
436   unsigned AddrSize = Info->VAddrDwords;
437 
438   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
439     unsigned DimIdx =
440         AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
441     const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
442         AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
443     const AMDGPU::MIMGDimInfo *Dim =
444         AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm());
445 
446     AddrSize = BaseOpcode->NumExtraArgs +
447                (BaseOpcode->Gradients ? Dim->NumGradients : 0) +
448                (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
449                (BaseOpcode->LodOrClampOrMip ? 1 : 0);
450     IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA;
451     if (!IsNSA) {
452       if (AddrSize > 8)
453         AddrSize = 16;
454       else if (AddrSize > 4)
455         AddrSize = 8;
456     } else {
457       if (AddrSize > Info->VAddrDwords) {
458         // The NSA encoding does not contain enough operands for the combination
459         // of base opcode / dimension. Should this be an error?
460         return MCDisassembler::Success;
461       }
462     }
463   }
464 
465   unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf;
466   unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u);
467 
468   bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm();
469   if (D16 && AMDGPU::hasPackedD16(STI)) {
470     DstSize = (DstSize + 1) / 2;
471   }
472 
473   // FIXME: Add tfe support
474   if (MI.getOperand(TFEIdx).getImm())
475     return MCDisassembler::Success;
476 
477   if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords)
478     return MCDisassembler::Success;
479 
480   int NewOpcode =
481       AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize);
482   if (NewOpcode == -1)
483     return MCDisassembler::Success;
484 
485   // Widen the register to the correct number of enabled channels.
486   unsigned NewVdata = AMDGPU::NoRegister;
487   if (DstSize != Info->VDataDwords) {
488     auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass;
489 
490     // Get first subregister of VData
491     unsigned Vdata0 = MI.getOperand(VDataIdx).getReg();
492     unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0);
493     Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0;
494 
495     NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0,
496                                        &MRI.getRegClass(DataRCID));
497     if (NewVdata == AMDGPU::NoRegister) {
498       // It's possible to encode this such that the low register + enabled
499       // components exceeds the register count.
500       return MCDisassembler::Success;
501     }
502   }
503 
504   unsigned NewVAddr0 = AMDGPU::NoRegister;
505   if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
506       AddrSize != Info->VAddrDwords) {
507     unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg();
508     unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0);
509     VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0;
510 
511     auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass;
512     NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0,
513                                         &MRI.getRegClass(AddrRCID));
514     if (NewVAddr0 == AMDGPU::NoRegister)
515       return MCDisassembler::Success;
516   }
517 
518   MI.setOpcode(NewOpcode);
519 
520   if (NewVdata != AMDGPU::NoRegister) {
521     MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata);
522 
523     if (IsAtomic) {
524       // Atomic operations have an additional operand (a copy of data)
525       MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata);
526     }
527   }
528 
529   if (NewVAddr0 != AMDGPU::NoRegister) {
530     MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0);
531   } else if (IsNSA) {
532     assert(AddrSize <= Info->VAddrDwords);
533     MI.erase(MI.begin() + VAddr0Idx + AddrSize,
534              MI.begin() + VAddr0Idx + Info->VAddrDwords);
535   }
536 
537   return MCDisassembler::Success;
538 }
539 
540 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const {
541   return getContext().getRegisterInfo()->
542     getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]);
543 }
544 
545 inline
546 MCOperand AMDGPUDisassembler::errOperand(unsigned V,
547                                          const Twine& ErrMsg) const {
548   *CommentStream << "Error: " + ErrMsg;
549 
550   // ToDo: add support for error operands to MCInst.h
551   // return MCOperand::createError(V);
552   return MCOperand();
553 }
554 
555 inline
556 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const {
557   return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
558 }
559 
560 inline
561 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID,
562                                                unsigned Val) const {
563   const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID];
564   if (Val >= RegCl.getNumRegs())
565     return errOperand(Val, Twine(getRegClassName(RegClassID)) +
566                            ": unknown register " + Twine(Val));
567   return createRegOperand(RegCl.getRegister(Val));
568 }
569 
570 inline
571 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID,
572                                                 unsigned Val) const {
573   // ToDo: SI/CI have 104 SGPRs, VI - 102
574   // Valery: here we accepting as much as we can, let assembler sort it out
575   int shift = 0;
576   switch (SRegClassID) {
577   case AMDGPU::SGPR_32RegClassID:
578   case AMDGPU::TTMP_32RegClassID:
579     break;
580   case AMDGPU::SGPR_64RegClassID:
581   case AMDGPU::TTMP_64RegClassID:
582     shift = 1;
583     break;
584   case AMDGPU::SGPR_128RegClassID:
585   case AMDGPU::TTMP_128RegClassID:
586   // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in
587   // this bundle?
588   case AMDGPU::SGPR_256RegClassID:
589   case AMDGPU::TTMP_256RegClassID:
590     // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in
591   // this bundle?
592   case AMDGPU::SGPR_512RegClassID:
593   case AMDGPU::TTMP_512RegClassID:
594     shift = 2;
595     break;
596   // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in
597   // this bundle?
598   default:
599     llvm_unreachable("unhandled register class");
600   }
601 
602   if (Val % (1 << shift)) {
603     *CommentStream << "Warning: " << getRegClassName(SRegClassID)
604                    << ": scalar reg isn't aligned " << Val;
605   }
606 
607   return createRegOperand(SRegClassID, Val >> shift);
608 }
609 
610 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const {
611   return decodeSrcOp(OPW32, Val);
612 }
613 
614 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const {
615   return decodeSrcOp(OPW64, Val);
616 }
617 
618 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const {
619   return decodeSrcOp(OPW128, Val);
620 }
621 
622 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const {
623   return decodeSrcOp(OPW16, Val);
624 }
625 
626 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const {
627   return decodeSrcOp(OPWV216, Val);
628 }
629 
630 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const {
631   // Some instructions have operand restrictions beyond what the encoding
632   // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra
633   // high bit.
634   Val &= 255;
635 
636   return createRegOperand(AMDGPU::VGPR_32RegClassID, Val);
637 }
638 
639 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const {
640   return decodeSrcOp(OPW32, Val);
641 }
642 
643 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const {
644   return createRegOperand(AMDGPU::VReg_64RegClassID, Val);
645 }
646 
647 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const {
648   return createRegOperand(AMDGPU::VReg_96RegClassID, Val);
649 }
650 
651 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const {
652   return createRegOperand(AMDGPU::VReg_128RegClassID, Val);
653 }
654 
655 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const {
656   // table-gen generated disassembler doesn't care about operand types
657   // leaving only registry class so SSrc_32 operand turns into SReg_32
658   // and therefore we accept immediates and literals here as well
659   return decodeSrcOp(OPW32, Val);
660 }
661 
662 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC(
663   unsigned Val) const {
664   // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI
665   return decodeOperand_SReg_32(Val);
666 }
667 
668 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI(
669   unsigned Val) const {
670   // SReg_32_XM0 is SReg_32 without EXEC_HI
671   return decodeOperand_SReg_32(Val);
672 }
673 
674 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const {
675   // table-gen generated disassembler doesn't care about operand types
676   // leaving only registry class so SSrc_32 operand turns into SReg_32
677   // and therefore we accept immediates and literals here as well
678   return decodeSrcOp(OPW32, Val);
679 }
680 
681 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const {
682   return decodeSrcOp(OPW64, Val);
683 }
684 
685 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const {
686   return decodeSrcOp(OPW64, Val);
687 }
688 
689 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const {
690   return decodeSrcOp(OPW128, Val);
691 }
692 
693 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const {
694   return decodeDstOp(OPW256, Val);
695 }
696 
697 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const {
698   return decodeDstOp(OPW512, Val);
699 }
700 
701 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const {
702   // For now all literal constants are supposed to be unsigned integer
703   // ToDo: deal with signed/unsigned 64-bit integer constants
704   // ToDo: deal with float/double constants
705   if (!HasLiteral) {
706     if (Bytes.size() < 4) {
707       return errOperand(0, "cannot read literal, inst bytes left " +
708                         Twine(Bytes.size()));
709     }
710     HasLiteral = true;
711     Literal = eatBytes<uint32_t>(Bytes);
712   }
713   return MCOperand::createImm(Literal);
714 }
715 
716 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) {
717   using namespace AMDGPU::EncValues;
718 
719   assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX);
720   return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ?
721     (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) :
722     (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm)));
723       // Cast prevents negative overflow.
724 }
725 
726 static int64_t getInlineImmVal32(unsigned Imm) {
727   switch (Imm) {
728   case 240:
729     return FloatToBits(0.5f);
730   case 241:
731     return FloatToBits(-0.5f);
732   case 242:
733     return FloatToBits(1.0f);
734   case 243:
735     return FloatToBits(-1.0f);
736   case 244:
737     return FloatToBits(2.0f);
738   case 245:
739     return FloatToBits(-2.0f);
740   case 246:
741     return FloatToBits(4.0f);
742   case 247:
743     return FloatToBits(-4.0f);
744   case 248: // 1 / (2 * PI)
745     return 0x3e22f983;
746   default:
747     llvm_unreachable("invalid fp inline imm");
748   }
749 }
750 
751 static int64_t getInlineImmVal64(unsigned Imm) {
752   switch (Imm) {
753   case 240:
754     return DoubleToBits(0.5);
755   case 241:
756     return DoubleToBits(-0.5);
757   case 242:
758     return DoubleToBits(1.0);
759   case 243:
760     return DoubleToBits(-1.0);
761   case 244:
762     return DoubleToBits(2.0);
763   case 245:
764     return DoubleToBits(-2.0);
765   case 246:
766     return DoubleToBits(4.0);
767   case 247:
768     return DoubleToBits(-4.0);
769   case 248: // 1 / (2 * PI)
770     return 0x3fc45f306dc9c882;
771   default:
772     llvm_unreachable("invalid fp inline imm");
773   }
774 }
775 
776 static int64_t getInlineImmVal16(unsigned Imm) {
777   switch (Imm) {
778   case 240:
779     return 0x3800;
780   case 241:
781     return 0xB800;
782   case 242:
783     return 0x3C00;
784   case 243:
785     return 0xBC00;
786   case 244:
787     return 0x4000;
788   case 245:
789     return 0xC000;
790   case 246:
791     return 0x4400;
792   case 247:
793     return 0xC400;
794   case 248: // 1 / (2 * PI)
795     return 0x3118;
796   default:
797     llvm_unreachable("invalid fp inline imm");
798   }
799 }
800 
801 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) {
802   assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN
803       && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX);
804 
805   // ToDo: case 248: 1/(2*PI) - is allowed only on VI
806   switch (Width) {
807   case OPW32:
808     return MCOperand::createImm(getInlineImmVal32(Imm));
809   case OPW64:
810     return MCOperand::createImm(getInlineImmVal64(Imm));
811   case OPW16:
812   case OPWV216:
813     return MCOperand::createImm(getInlineImmVal16(Imm));
814   default:
815     llvm_unreachable("implement me");
816   }
817 }
818 
819 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const {
820   using namespace AMDGPU;
821 
822   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
823   switch (Width) {
824   default: // fall
825   case OPW32:
826   case OPW16:
827   case OPWV216:
828     return VGPR_32RegClassID;
829   case OPW64: return VReg_64RegClassID;
830   case OPW128: return VReg_128RegClassID;
831   }
832 }
833 
834 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const {
835   using namespace AMDGPU;
836 
837   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
838   switch (Width) {
839   default: // fall
840   case OPW32:
841   case OPW16:
842   case OPWV216:
843     return SGPR_32RegClassID;
844   case OPW64: return SGPR_64RegClassID;
845   case OPW128: return SGPR_128RegClassID;
846   case OPW256: return SGPR_256RegClassID;
847   case OPW512: return SGPR_512RegClassID;
848   }
849 }
850 
851 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
852   using namespace AMDGPU;
853 
854   assert(OPW_FIRST_ <= Width && Width < OPW_LAST_);
855   switch (Width) {
856   default: // fall
857   case OPW32:
858   case OPW16:
859   case OPWV216:
860     return TTMP_32RegClassID;
861   case OPW64: return TTMP_64RegClassID;
862   case OPW128: return TTMP_128RegClassID;
863   case OPW256: return TTMP_256RegClassID;
864   case OPW512: return TTMP_512RegClassID;
865   }
866 }
867 
868 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
869   using namespace AMDGPU::EncValues;
870 
871   unsigned TTmpMin =
872       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
873   unsigned TTmpMax =
874       (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
875 
876   return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
877 }
878 
879 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val) const {
880   using namespace AMDGPU::EncValues;
881 
882   assert(Val < 512); // enum9
883 
884   if (VGPR_MIN <= Val && Val <= VGPR_MAX) {
885     return createRegOperand(getVgprClassId(Width), Val - VGPR_MIN);
886   }
887   if (Val <= SGPR_MAX) {
888     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
889     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
890   }
891 
892   int TTmpIdx = getTTmpIdx(Val);
893   if (TTmpIdx >= 0) {
894     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
895   }
896 
897   if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX)
898     return decodeIntImmed(Val);
899 
900   if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX)
901     return decodeFPImmed(Width, Val);
902 
903   if (Val == LITERAL_CONST)
904     return decodeLiteralConstant();
905 
906   switch (Width) {
907   case OPW32:
908   case OPW16:
909   case OPWV216:
910     return decodeSpecialReg32(Val);
911   case OPW64:
912     return decodeSpecialReg64(Val);
913   default:
914     llvm_unreachable("unexpected immediate type");
915   }
916 }
917 
918 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const {
919   using namespace AMDGPU::EncValues;
920 
921   assert(Val < 128);
922   assert(Width == OPW256 || Width == OPW512);
923 
924   if (Val <= SGPR_MAX) {
925     assert(SGPR_MIN == 0); // "SGPR_MIN <= Val" is always true and causes compilation warning.
926     return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN);
927   }
928 
929   int TTmpIdx = getTTmpIdx(Val);
930   if (TTmpIdx >= 0) {
931     return createSRegOperand(getTtmpClassId(Width), TTmpIdx);
932   }
933 
934   llvm_unreachable("unknown dst register");
935 }
936 
937 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const {
938   using namespace AMDGPU;
939 
940   switch (Val) {
941   case 102: return createRegOperand(FLAT_SCR_LO);
942   case 103: return createRegOperand(FLAT_SCR_HI);
943   case 104: return createRegOperand(XNACK_MASK_LO);
944   case 105: return createRegOperand(XNACK_MASK_HI);
945   case 106: return createRegOperand(VCC_LO);
946   case 107: return createRegOperand(VCC_HI);
947   case 108: return createRegOperand(TBA_LO);
948   case 109: return createRegOperand(TBA_HI);
949   case 110: return createRegOperand(TMA_LO);
950   case 111: return createRegOperand(TMA_HI);
951   case 124: return createRegOperand(M0);
952   case 125: return createRegOperand(SGPR_NULL);
953   case 126: return createRegOperand(EXEC_LO);
954   case 127: return createRegOperand(EXEC_HI);
955   case 235: return createRegOperand(SRC_SHARED_BASE);
956   case 236: return createRegOperand(SRC_SHARED_LIMIT);
957   case 237: return createRegOperand(SRC_PRIVATE_BASE);
958   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
959   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
960   case 251: return createRegOperand(SRC_VCCZ);
961   case 252: return createRegOperand(SRC_EXECZ);
962   case 253: return createRegOperand(SRC_SCC);
963   case 254: return createRegOperand(LDS_DIRECT);
964   default: break;
965   }
966   return errOperand(Val, "unknown operand encoding " + Twine(Val));
967 }
968 
969 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const {
970   using namespace AMDGPU;
971 
972   switch (Val) {
973   case 102: return createRegOperand(FLAT_SCR);
974   case 104: return createRegOperand(XNACK_MASK);
975   case 106: return createRegOperand(VCC);
976   case 108: return createRegOperand(TBA);
977   case 110: return createRegOperand(TMA);
978   case 126: return createRegOperand(EXEC);
979   case 235: return createRegOperand(SRC_SHARED_BASE);
980   case 236: return createRegOperand(SRC_SHARED_LIMIT);
981   case 237: return createRegOperand(SRC_PRIVATE_BASE);
982   case 238: return createRegOperand(SRC_PRIVATE_LIMIT);
983   case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID);
984   case 251: return createRegOperand(SRC_VCCZ);
985   case 252: return createRegOperand(SRC_EXECZ);
986   case 253: return createRegOperand(SRC_SCC);
987   default: break;
988   }
989   return errOperand(Val, "unknown operand encoding " + Twine(Val));
990 }
991 
992 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
993                                             const unsigned Val) const {
994   using namespace AMDGPU::SDWA;
995   using namespace AMDGPU::EncValues;
996 
997   if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
998       STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
999     // XXX: cast to int is needed to avoid stupid warning:
1000     // compare with unsigned is always true
1001     if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) &&
1002         Val <= SDWA9EncValues::SRC_VGPR_MAX) {
1003       return createRegOperand(getVgprClassId(Width),
1004                               Val - SDWA9EncValues::SRC_VGPR_MIN);
1005     }
1006     if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
1007         Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
1008                           : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
1009       return createSRegOperand(getSgprClassId(Width),
1010                                Val - SDWA9EncValues::SRC_SGPR_MIN);
1011     }
1012     if (SDWA9EncValues::SRC_TTMP_MIN <= Val &&
1013         Val <= SDWA9EncValues::SRC_TTMP_MAX) {
1014       return createSRegOperand(getTtmpClassId(Width),
1015                                Val - SDWA9EncValues::SRC_TTMP_MIN);
1016     }
1017 
1018     const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN;
1019 
1020     if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX)
1021       return decodeIntImmed(SVal);
1022 
1023     if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX)
1024       return decodeFPImmed(Width, SVal);
1025 
1026     return decodeSpecialReg32(SVal);
1027   } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1028     return createRegOperand(getVgprClassId(Width), Val);
1029   }
1030   llvm_unreachable("unsupported target");
1031 }
1032 
1033 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const {
1034   return decodeSDWASrc(OPW16, Val);
1035 }
1036 
1037 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const {
1038   return decodeSDWASrc(OPW32, Val);
1039 }
1040 
1041 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const {
1042   using namespace AMDGPU::SDWA;
1043 
1044   assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1045           STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1046          "SDWAVopcDst should be present only on GFX9+");
1047 
1048   bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1049 
1050   if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) {
1051     Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
1052 
1053     int TTmpIdx = getTTmpIdx(Val);
1054     if (TTmpIdx >= 0) {
1055       return createSRegOperand(getTtmpClassId(OPW64), TTmpIdx);
1056     } else if (Val > SGPR_MAX) {
1057       return IsWave64 ? decodeSpecialReg64(Val)
1058                       : decodeSpecialReg32(Val);
1059     } else {
1060       return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val);
1061     }
1062   } else {
1063     return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO);
1064   }
1065 }
1066 
1067 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const {
1068   return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1069     decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val);
1070 }
1071 
1072 bool AMDGPUDisassembler::isVI() const {
1073   return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1074 }
1075 
1076 bool AMDGPUDisassembler::isGFX9() const {
1077   return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1078 }
1079 
1080 bool AMDGPUDisassembler::isGFX10() const {
1081   return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
1082 }
1083 
1084 //===----------------------------------------------------------------------===//
1085 // AMDGPUSymbolizer
1086 //===----------------------------------------------------------------------===//
1087 
1088 // Try to find symbol name for specified label
1089 bool AMDGPUSymbolizer::tryAddingSymbolicOperand(MCInst &Inst,
1090                                 raw_ostream &/*cStream*/, int64_t Value,
1091                                 uint64_t /*Address*/, bool IsBranch,
1092                                 uint64_t /*Offset*/, uint64_t /*InstSize*/) {
1093   using SymbolInfoTy = std::tuple<uint64_t, StringRef, uint8_t>;
1094   using SectionSymbolsTy = std::vector<SymbolInfoTy>;
1095 
1096   if (!IsBranch) {
1097     return false;
1098   }
1099 
1100   auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo);
1101   if (!Symbols)
1102     return false;
1103 
1104   auto Result = std::find_if(Symbols->begin(), Symbols->end(),
1105                              [Value](const SymbolInfoTy& Val) {
1106                                 return std::get<0>(Val) == static_cast<uint64_t>(Value)
1107                                     && std::get<2>(Val) == ELF::STT_NOTYPE;
1108                              });
1109   if (Result != Symbols->end()) {
1110     auto *Sym = Ctx.getOrCreateSymbol(std::get<1>(*Result));
1111     const auto *Add = MCSymbolRefExpr::create(Sym, Ctx);
1112     Inst.addOperand(MCOperand::createExpr(Add));
1113     return true;
1114   }
1115   return false;
1116 }
1117 
1118 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream,
1119                                                        int64_t Value,
1120                                                        uint64_t Address) {
1121   llvm_unreachable("unimplemented");
1122 }
1123 
1124 //===----------------------------------------------------------------------===//
1125 // Initialization
1126 //===----------------------------------------------------------------------===//
1127 
1128 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/,
1129                               LLVMOpInfoCallback /*GetOpInfo*/,
1130                               LLVMSymbolLookupCallback /*SymbolLookUp*/,
1131                               void *DisInfo,
1132                               MCContext *Ctx,
1133                               std::unique_ptr<MCRelocationInfo> &&RelInfo) {
1134   return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo);
1135 }
1136 
1137 static MCDisassembler *createAMDGPUDisassembler(const Target &T,
1138                                                 const MCSubtargetInfo &STI,
1139                                                 MCContext &Ctx) {
1140   return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo());
1141 }
1142 
1143 extern "C" void LLVMInitializeAMDGPUDisassembler() {
1144   TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(),
1145                                          createAMDGPUDisassembler);
1146   TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(),
1147                                        createAMDGPUSymbolizer);
1148 }
1149