1 //===- AMDGPUDisassembler.cpp - Disassembler for AMDGPU ISA ---------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 /// \file 12 /// 13 /// This file contains definition for AMDGPU ISA disassembler 14 // 15 //===----------------------------------------------------------------------===// 16 17 // ToDo: What to do with instruction suffixes (v_mov_b32 vs v_mov_b32_e32)? 18 19 #include "Disassembler/AMDGPUDisassembler.h" 20 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 21 #include "SIDefines.h" 22 #include "SIRegisterInfo.h" 23 #include "TargetInfo/AMDGPUTargetInfo.h" 24 #include "Utils/AMDGPUBaseInfo.h" 25 #include "llvm-c/DisassemblerTypes.h" 26 #include "llvm/BinaryFormat/ELF.h" 27 #include "llvm/MC/MCAsmInfo.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCDecoderOps.h" 30 #include "llvm/MC/MCExpr.h" 31 #include "llvm/MC/MCInstrDesc.h" 32 #include "llvm/MC/MCRegisterInfo.h" 33 #include "llvm/MC/MCSubtargetInfo.h" 34 #include "llvm/MC/TargetRegistry.h" 35 #include "llvm/Support/AMDHSAKernelDescriptor.h" 36 37 using namespace llvm; 38 39 #define DEBUG_TYPE "amdgpu-disassembler" 40 41 #define SGPR_MAX \ 42 (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \ 43 : AMDGPU::EncValues::SGPR_MAX_SI) 44 45 using DecodeStatus = llvm::MCDisassembler::DecodeStatus; 46 47 AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI, 48 MCContext &Ctx, 49 MCInstrInfo const *MCII) : 50 MCDisassembler(STI, Ctx), MCII(MCII), MRI(*Ctx.getRegisterInfo()), 51 TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) { 52 53 // ToDo: AMDGPUDisassembler supports only VI ISA. 54 if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus()) 55 report_fatal_error("Disassembly not yet supported for subtarget"); 56 } 57 58 inline static MCDisassembler::DecodeStatus 59 addOperand(MCInst &Inst, const MCOperand& Opnd) { 60 Inst.addOperand(Opnd); 61 return Opnd.isValid() ? 62 MCDisassembler::Success : 63 MCDisassembler::Fail; 64 } 65 66 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, 67 uint16_t NameIdx) { 68 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx); 69 if (OpIdx != -1) { 70 auto I = MI.begin(); 71 std::advance(I, OpIdx); 72 MI.insert(I, Op); 73 } 74 return OpIdx; 75 } 76 77 static DecodeStatus decodeSoppBrTarget(MCInst &Inst, unsigned Imm, 78 uint64_t Addr, 79 const MCDisassembler *Decoder) { 80 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 81 82 // Our branches take a simm16, but we need two extra bits to account for the 83 // factor of 4. 84 APInt SignedOffset(18, Imm * 4, true); 85 int64_t Offset = (SignedOffset.sext(64) + 4 + Addr).getSExtValue(); 86 87 if (DAsm->tryAddingSymbolicOperand(Inst, Offset, Addr, true, 2, 2, 0)) 88 return MCDisassembler::Success; 89 return addOperand(Inst, MCOperand::createImm(Imm)); 90 } 91 92 static DecodeStatus decodeSMEMOffset(MCInst &Inst, unsigned Imm, uint64_t Addr, 93 const MCDisassembler *Decoder) { 94 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 95 int64_t Offset; 96 if (DAsm->isVI()) { // VI supports 20-bit unsigned offsets. 97 Offset = Imm & 0xFFFFF; 98 } else { // GFX9+ supports 21-bit signed offsets. 99 Offset = SignExtend64<21>(Imm); 100 } 101 return addOperand(Inst, MCOperand::createImm(Offset)); 102 } 103 104 static DecodeStatus decodeBoolReg(MCInst &Inst, unsigned Val, uint64_t Addr, 105 const MCDisassembler *Decoder) { 106 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 107 return addOperand(Inst, DAsm->decodeBoolReg(Val)); 108 } 109 110 #define DECODE_OPERAND(StaticDecoderName, DecoderName) \ 111 static DecodeStatus StaticDecoderName(MCInst &Inst, unsigned Imm, \ 112 uint64_t /*Addr*/, \ 113 const MCDisassembler *Decoder) { \ 114 auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); \ 115 return addOperand(Inst, DAsm->DecoderName(Imm)); \ 116 } 117 118 #define DECODE_OPERAND_REG(RegClass) \ 119 DECODE_OPERAND(Decode##RegClass##RegisterClass, decodeOperand_##RegClass) 120 121 DECODE_OPERAND_REG(VGPR_32) 122 DECODE_OPERAND_REG(VRegOrLds_32) 123 DECODE_OPERAND_REG(VS_32) 124 DECODE_OPERAND_REG(VS_64) 125 DECODE_OPERAND_REG(VS_128) 126 127 DECODE_OPERAND_REG(VReg_64) 128 DECODE_OPERAND_REG(VReg_96) 129 DECODE_OPERAND_REG(VReg_128) 130 DECODE_OPERAND_REG(VReg_256) 131 DECODE_OPERAND_REG(VReg_512) 132 DECODE_OPERAND_REG(VReg_1024) 133 134 DECODE_OPERAND_REG(SReg_32) 135 DECODE_OPERAND_REG(SReg_32_XM0_XEXEC) 136 DECODE_OPERAND_REG(SReg_32_XEXEC_HI) 137 DECODE_OPERAND_REG(SRegOrLds_32) 138 DECODE_OPERAND_REG(SReg_64) 139 DECODE_OPERAND_REG(SReg_64_XEXEC) 140 DECODE_OPERAND_REG(SReg_128) 141 DECODE_OPERAND_REG(SReg_256) 142 DECODE_OPERAND_REG(SReg_512) 143 144 DECODE_OPERAND_REG(AGPR_32) 145 DECODE_OPERAND_REG(AReg_64) 146 DECODE_OPERAND_REG(AReg_128) 147 DECODE_OPERAND_REG(AReg_256) 148 DECODE_OPERAND_REG(AReg_512) 149 DECODE_OPERAND_REG(AReg_1024) 150 DECODE_OPERAND_REG(AV_32) 151 DECODE_OPERAND_REG(AV_64) 152 DECODE_OPERAND_REG(AV_128) 153 DECODE_OPERAND_REG(AVDst_128) 154 DECODE_OPERAND_REG(AVDst_512) 155 156 static DecodeStatus decodeOperand_VSrc16(MCInst &Inst, unsigned Imm, 157 uint64_t Addr, 158 const MCDisassembler *Decoder) { 159 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 160 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 161 } 162 163 static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst, unsigned Imm, 164 uint64_t Addr, 165 const MCDisassembler *Decoder) { 166 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 167 return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm)); 168 } 169 170 static DecodeStatus decodeOperand_VSrcV232(MCInst &Inst, unsigned Imm, 171 uint64_t Addr, 172 const MCDisassembler *Decoder) { 173 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 174 return addOperand(Inst, DAsm->decodeOperand_VSrcV232(Imm)); 175 } 176 177 static DecodeStatus decodeOperand_VS_16(MCInst &Inst, unsigned Imm, 178 uint64_t Addr, 179 const MCDisassembler *Decoder) { 180 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 181 return addOperand(Inst, DAsm->decodeOperand_VSrc16(Imm)); 182 } 183 184 static DecodeStatus decodeOperand_VS_32(MCInst &Inst, unsigned Imm, 185 uint64_t Addr, 186 const MCDisassembler *Decoder) { 187 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 188 return addOperand(Inst, DAsm->decodeOperand_VS_32(Imm)); 189 } 190 191 static DecodeStatus decodeOperand_AReg_64(MCInst &Inst, unsigned Imm, 192 uint64_t Addr, 193 const MCDisassembler *Decoder) { 194 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 195 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm | 512)); 196 } 197 198 static DecodeStatus decodeOperand_AReg_128(MCInst &Inst, unsigned Imm, 199 uint64_t Addr, 200 const MCDisassembler *Decoder) { 201 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 202 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm | 512)); 203 } 204 205 static DecodeStatus decodeOperand_AReg_256(MCInst &Inst, unsigned Imm, 206 uint64_t Addr, 207 const MCDisassembler *Decoder) { 208 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 209 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm | 512)); 210 } 211 212 static DecodeStatus decodeOperand_AReg_512(MCInst &Inst, unsigned Imm, 213 uint64_t Addr, 214 const MCDisassembler *Decoder) { 215 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 216 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm | 512)); 217 } 218 219 static DecodeStatus decodeOperand_AReg_1024(MCInst &Inst, unsigned Imm, 220 uint64_t Addr, 221 const MCDisassembler *Decoder) { 222 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 223 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm | 512)); 224 } 225 226 static DecodeStatus decodeOperand_VReg_64(MCInst &Inst, unsigned Imm, 227 uint64_t Addr, 228 const MCDisassembler *Decoder) { 229 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 230 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW64, Imm)); 231 } 232 233 static DecodeStatus decodeOperand_VReg_128(MCInst &Inst, unsigned Imm, 234 uint64_t Addr, 235 const MCDisassembler *Decoder) { 236 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 237 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW128, Imm)); 238 } 239 240 static DecodeStatus decodeOperand_VReg_256(MCInst &Inst, unsigned Imm, 241 uint64_t Addr, 242 const MCDisassembler *Decoder) { 243 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 244 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW256, Imm)); 245 } 246 247 static DecodeStatus decodeOperand_VReg_512(MCInst &Inst, unsigned Imm, 248 uint64_t Addr, 249 const MCDisassembler *Decoder) { 250 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 251 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW512, Imm)); 252 } 253 254 static DecodeStatus decodeOperand_VReg_1024(MCInst &Inst, unsigned Imm, 255 uint64_t Addr, 256 const MCDisassembler *Decoder) { 257 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 258 return addOperand(Inst, DAsm->decodeSrcOp(AMDGPUDisassembler::OPW1024, Imm)); 259 } 260 261 static DecodeStatus decodeOperand_f32kimm(MCInst &Inst, unsigned Imm, 262 uint64_t Addr, 263 const MCDisassembler *Decoder) { 264 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 265 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 266 } 267 268 static DecodeStatus decodeOperand_f16kimm(MCInst &Inst, unsigned Imm, 269 uint64_t Addr, 270 const MCDisassembler *Decoder) { 271 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 272 return addOperand(Inst, DAsm->decodeMandatoryLiteralConstant(Imm)); 273 } 274 275 static DecodeStatus 276 decodeOperand_VS_16_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 277 const MCDisassembler *Decoder) { 278 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 279 return addOperand( 280 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW16, Imm, true)); 281 } 282 283 static DecodeStatus 284 decodeOperand_VS_32_Deferred(MCInst &Inst, unsigned Imm, uint64_t Addr, 285 const MCDisassembler *Decoder) { 286 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 287 return addOperand( 288 Inst, DAsm->decodeSrcOp(llvm::AMDGPUDisassembler::OPW32, Imm, true)); 289 } 290 291 static DecodeStatus decodeOperandVOPDDstY(MCInst &Inst, unsigned Val, 292 uint64_t Addr, const void *Decoder) { 293 const auto *DAsm = static_cast<const AMDGPUDisassembler *>(Decoder); 294 return addOperand(Inst, DAsm->decodeVOPDDstYOp(Inst, Val)); 295 } 296 297 static bool IsAGPROperand(const MCInst &Inst, int OpIdx, 298 const MCRegisterInfo *MRI) { 299 if (OpIdx < 0) 300 return false; 301 302 const MCOperand &Op = Inst.getOperand(OpIdx); 303 if (!Op.isReg()) 304 return false; 305 306 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); 307 auto Reg = Sub ? Sub : Op.getReg(); 308 return Reg >= AMDGPU::AGPR0 && Reg <= AMDGPU::AGPR255; 309 } 310 311 static DecodeStatus decodeOperand_AVLdSt_Any(MCInst &Inst, unsigned Imm, 312 AMDGPUDisassembler::OpWidthTy Opw, 313 const MCDisassembler *Decoder) { 314 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 315 if (!DAsm->isGFX90A()) { 316 Imm &= 511; 317 } else { 318 // If atomic has both vdata and vdst their register classes are tied. 319 // The bit is decoded along with the vdst, first operand. We need to 320 // change register class to AGPR if vdst was AGPR. 321 // If a DS instruction has both data0 and data1 their register classes 322 // are also tied. 323 unsigned Opc = Inst.getOpcode(); 324 uint64_t TSFlags = DAsm->getMCII()->get(Opc).TSFlags; 325 uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0 326 : AMDGPU::OpName::vdata; 327 const MCRegisterInfo *MRI = DAsm->getContext().getRegisterInfo(); 328 int DataIdx = AMDGPU::getNamedOperandIdx(Opc, DataNameIdx); 329 if ((int)Inst.getNumOperands() == DataIdx) { 330 int DstIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst); 331 if (IsAGPROperand(Inst, DstIdx, MRI)) 332 Imm |= 512; 333 } 334 335 if (TSFlags & SIInstrFlags::DS) { 336 int Data2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data1); 337 if ((int)Inst.getNumOperands() == Data2Idx && 338 IsAGPROperand(Inst, DataIdx, MRI)) 339 Imm |= 512; 340 } 341 } 342 return addOperand(Inst, DAsm->decodeSrcOp(Opw, Imm | 256)); 343 } 344 345 static DecodeStatus 346 DecodeAVLdSt_32RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 347 const MCDisassembler *Decoder) { 348 return decodeOperand_AVLdSt_Any(Inst, Imm, 349 AMDGPUDisassembler::OPW32, Decoder); 350 } 351 352 static DecodeStatus 353 DecodeAVLdSt_64RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 354 const MCDisassembler *Decoder) { 355 return decodeOperand_AVLdSt_Any(Inst, Imm, 356 AMDGPUDisassembler::OPW64, Decoder); 357 } 358 359 static DecodeStatus 360 DecodeAVLdSt_96RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 361 const MCDisassembler *Decoder) { 362 return decodeOperand_AVLdSt_Any(Inst, Imm, 363 AMDGPUDisassembler::OPW96, Decoder); 364 } 365 366 static DecodeStatus 367 DecodeAVLdSt_128RegisterClass(MCInst &Inst, unsigned Imm, uint64_t Addr, 368 const MCDisassembler *Decoder) { 369 return decodeOperand_AVLdSt_Any(Inst, Imm, 370 AMDGPUDisassembler::OPW128, Decoder); 371 } 372 373 static DecodeStatus decodeOperand_SReg_32(MCInst &Inst, unsigned Imm, 374 uint64_t Addr, 375 const MCDisassembler *Decoder) { 376 auto DAsm = static_cast<const AMDGPUDisassembler*>(Decoder); 377 return addOperand(Inst, DAsm->decodeOperand_SReg_32(Imm)); 378 } 379 380 #define DECODE_SDWA(DecName) \ 381 DECODE_OPERAND(decodeSDWA##DecName, decodeSDWA##DecName) 382 383 DECODE_SDWA(Src32) 384 DECODE_SDWA(Src16) 385 DECODE_SDWA(VopcDst) 386 387 #include "AMDGPUGenDisassemblerTables.inc" 388 389 //===----------------------------------------------------------------------===// 390 // 391 //===----------------------------------------------------------------------===// 392 393 template <typename T> static inline T eatBytes(ArrayRef<uint8_t>& Bytes) { 394 assert(Bytes.size() >= sizeof(T)); 395 const auto Res = support::endian::read<T, support::endianness::little>(Bytes.data()); 396 Bytes = Bytes.slice(sizeof(T)); 397 return Res; 398 } 399 400 static inline DecoderUInt128 eat12Bytes(ArrayRef<uint8_t> &Bytes) { 401 assert(Bytes.size() >= 12); 402 uint64_t Lo = support::endian::read<uint64_t, support::endianness::little>( 403 Bytes.data()); 404 Bytes = Bytes.slice(8); 405 uint64_t Hi = support::endian::read<uint32_t, support::endianness::little>( 406 Bytes.data()); 407 Bytes = Bytes.slice(4); 408 return DecoderUInt128(Lo, Hi); 409 } 410 411 // The disassembler is greedy, so we need to check FI operand value to 412 // not parse a dpp if the correct literal is not set. For dpp16 the 413 // autogenerated decoder checks the dpp literal 414 static bool isValidDPP8(const MCInst &MI) { 415 using namespace llvm::AMDGPU::DPP; 416 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi); 417 assert(FiIdx != -1); 418 if ((unsigned)FiIdx >= MI.getNumOperands()) 419 return false; 420 unsigned Fi = MI.getOperand(FiIdx).getImm(); 421 return Fi == DPP8_FI_0 || Fi == DPP8_FI_1; 422 } 423 424 DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 425 ArrayRef<uint8_t> Bytes_, 426 uint64_t Address, 427 raw_ostream &CS) const { 428 CommentStream = &CS; 429 bool IsSDWA = false; 430 431 unsigned MaxInstBytesNum = std::min((size_t)TargetMaxInstBytes, Bytes_.size()); 432 Bytes = Bytes_.slice(0, MaxInstBytesNum); 433 434 DecodeStatus Res = MCDisassembler::Fail; 435 do { 436 // ToDo: better to switch encoding length using some bit predicate 437 // but it is unknown yet, so try all we can 438 439 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2 440 // encodings 441 if (isGFX11Plus() && Bytes.size() >= 12 ) { 442 DecoderUInt128 DecW = eat12Bytes(Bytes); 443 Res = tryDecodeInst(DecoderTableDPP8GFX1196, MI, DecW, 444 Address); 445 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 446 break; 447 MI = MCInst(); // clear 448 Res = tryDecodeInst(DecoderTableDPPGFX1196, MI, DecW, 449 Address); 450 if (Res) { 451 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3P) 452 convertVOP3PDPPInst(MI); 453 else if (AMDGPU::isVOPC64DPP(MI.getOpcode())) 454 convertVOPCDPPInst(MI); 455 break; 456 } 457 Res = tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address); 458 if (Res) 459 break; 460 } 461 // Reinitialize Bytes 462 Bytes = Bytes_.slice(0, MaxInstBytesNum); 463 464 if (Bytes.size() >= 8) { 465 const uint64_t QW = eatBytes<uint64_t>(Bytes); 466 467 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 468 Res = tryDecodeInst(DecoderTableGFX10_B64, MI, QW, Address); 469 if (Res) { 470 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dpp8) 471 == -1) 472 break; 473 if (convertDPP8Inst(MI) == MCDisassembler::Success) 474 break; 475 MI = MCInst(); // clear 476 } 477 } 478 479 Res = tryDecodeInst(DecoderTableDPP864, MI, QW, Address); 480 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 481 break; 482 MI = MCInst(); // clear 483 484 Res = tryDecodeInst(DecoderTableDPP8GFX1164, MI, QW, Address); 485 if (Res && convertDPP8Inst(MI) == MCDisassembler::Success) 486 break; 487 MI = MCInst(); // clear 488 489 Res = tryDecodeInst(DecoderTableDPP64, MI, QW, Address); 490 if (Res) break; 491 492 Res = tryDecodeInst(DecoderTableDPPGFX1164, MI, QW, Address); 493 if (Res) { 494 if (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOPC) 495 convertVOPCDPPInst(MI); 496 break; 497 } 498 499 Res = tryDecodeInst(DecoderTableSDWA64, MI, QW, Address); 500 if (Res) { IsSDWA = true; break; } 501 502 Res = tryDecodeInst(DecoderTableSDWA964, MI, QW, Address); 503 if (Res) { IsSDWA = true; break; } 504 505 Res = tryDecodeInst(DecoderTableSDWA1064, MI, QW, Address); 506 if (Res) { IsSDWA = true; break; } 507 508 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) { 509 Res = tryDecodeInst(DecoderTableGFX80_UNPACKED64, MI, QW, Address); 510 if (Res) 511 break; 512 } 513 514 // Some GFX9 subtargets repurposed the v_mad_mix_f32, v_mad_mixlo_f16 and 515 // v_mad_mixhi_f16 for FMA variants. Try to decode using this special 516 // table first so we print the correct name. 517 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) { 518 Res = tryDecodeInst(DecoderTableGFX9_DL64, MI, QW, Address); 519 if (Res) 520 break; 521 } 522 } 523 524 // Reinitialize Bytes as DPP64 could have eaten too much 525 Bytes = Bytes_.slice(0, MaxInstBytesNum); 526 527 // Try decode 32-bit instruction 528 if (Bytes.size() < 4) break; 529 const uint32_t DW = eatBytes<uint32_t>(Bytes); 530 Res = tryDecodeInst(DecoderTableGFX832, MI, DW, Address); 531 if (Res) break; 532 533 Res = tryDecodeInst(DecoderTableAMDGPU32, MI, DW, Address); 534 if (Res) break; 535 536 Res = tryDecodeInst(DecoderTableGFX932, MI, DW, Address); 537 if (Res) break; 538 539 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 540 Res = tryDecodeInst(DecoderTableGFX90A32, MI, DW, Address); 541 if (Res) 542 break; 543 } 544 545 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10_BEncoding]) { 546 Res = tryDecodeInst(DecoderTableGFX10_B32, MI, DW, Address); 547 if (Res) break; 548 } 549 550 Res = tryDecodeInst(DecoderTableGFX1032, MI, DW, Address); 551 if (Res) break; 552 553 Res = tryDecodeInst(DecoderTableGFX1132, MI, DW, Address); 554 if (Res) break; 555 556 if (Bytes.size() < 4) break; 557 const uint64_t QW = ((uint64_t)eatBytes<uint32_t>(Bytes) << 32) | DW; 558 559 if (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]) { 560 Res = tryDecodeInst(DecoderTableGFX90A64, MI, QW, Address); 561 if (Res) 562 break; 563 } 564 565 Res = tryDecodeInst(DecoderTableGFX864, MI, QW, Address); 566 if (Res) break; 567 568 Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address); 569 if (Res) break; 570 571 Res = tryDecodeInst(DecoderTableGFX964, MI, QW, Address); 572 if (Res) break; 573 574 Res = tryDecodeInst(DecoderTableGFX1064, MI, QW, Address); 575 if (Res) break; 576 577 Res = tryDecodeInst(DecoderTableGFX1164, MI, QW, Address); 578 } while (false); 579 580 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi || 581 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 || 582 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 || 583 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 || 584 MI.getOpcode() == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 || 585 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi || 586 MI.getOpcode() == AMDGPU::V_FMAC_F64_e64_gfx90a || 587 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi || 588 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 || 589 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx11 || 590 MI.getOpcode() == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 || 591 MI.getOpcode() == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 || 592 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10 || 593 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx11)) { 594 // Insert dummy unused src2_modifiers. 595 insertNamedMCOperand(MI, MCOperand::createImm(0), 596 AMDGPU::OpName::src2_modifiers); 597 } 598 599 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 600 (SIInstrFlags::MUBUF | SIInstrFlags::FLAT | SIInstrFlags::SMRD))) { 601 int CPolPos = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 602 AMDGPU::OpName::cpol); 603 if (CPolPos != -1) { 604 unsigned CPol = 605 (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::IsAtomicRet) ? 606 AMDGPU::CPol::GLC : 0; 607 if (MI.getNumOperands() <= (unsigned)CPolPos) { 608 insertNamedMCOperand(MI, MCOperand::createImm(CPol), 609 AMDGPU::OpName::cpol); 610 } else if (CPol) { 611 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); 612 } 613 } 614 } 615 616 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 617 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF)) && 618 (STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts])) { 619 // GFX90A lost TFE, its place is occupied by ACC. 620 int TFEOpIdx = 621 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::tfe); 622 if (TFEOpIdx != -1) { 623 auto TFEIter = MI.begin(); 624 std::advance(TFEIter, TFEOpIdx); 625 MI.insert(TFEIter, MCOperand::createImm(0)); 626 } 627 } 628 629 if (Res && (MCII->get(MI.getOpcode()).TSFlags & 630 (SIInstrFlags::MTBUF | SIInstrFlags::MUBUF))) { 631 int SWZOpIdx = 632 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::swz); 633 if (SWZOpIdx != -1) { 634 auto SWZIter = MI.begin(); 635 std::advance(SWZIter, SWZOpIdx); 636 MI.insert(SWZIter, MCOperand::createImm(0)); 637 } 638 } 639 640 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) { 641 int VAddr0Idx = 642 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 643 int RsrcIdx = 644 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc); 645 unsigned NSAArgs = RsrcIdx - VAddr0Idx - 1; 646 if (VAddr0Idx >= 0 && NSAArgs > 0) { 647 unsigned NSAWords = (NSAArgs + 3) / 4; 648 if (Bytes.size() < 4 * NSAWords) { 649 Res = MCDisassembler::Fail; 650 } else { 651 for (unsigned i = 0; i < NSAArgs; ++i) { 652 const unsigned VAddrIdx = VAddr0Idx + 1 + i; 653 auto VAddrRCID = MCII->get(MI.getOpcode()).OpInfo[VAddrIdx].RegClass; 654 MI.insert(MI.begin() + VAddrIdx, 655 createRegOperand(VAddrRCID, Bytes[i])); 656 } 657 Bytes = Bytes.slice(4 * NSAWords); 658 } 659 } 660 661 if (Res) 662 Res = convertMIMGInst(MI); 663 } 664 665 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::EXP)) 666 Res = convertEXPInst(MI); 667 668 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VINTERP)) 669 Res = convertVINTERPInst(MI); 670 671 if (Res && IsSDWA) 672 Res = convertSDWAInst(MI); 673 674 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 675 AMDGPU::OpName::vdst_in); 676 if (VDstIn_Idx != -1) { 677 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx, 678 MCOI::OperandConstraint::TIED_TO); 679 if (Tied != -1 && (MI.getNumOperands() <= (unsigned)VDstIn_Idx || 680 !MI.getOperand(VDstIn_Idx).isReg() || 681 MI.getOperand(VDstIn_Idx).getReg() != MI.getOperand(Tied).getReg())) { 682 if (MI.getNumOperands() > (unsigned)VDstIn_Idx) 683 MI.erase(&MI.getOperand(VDstIn_Idx)); 684 insertNamedMCOperand(MI, 685 MCOperand::createReg(MI.getOperand(Tied).getReg()), 686 AMDGPU::OpName::vdst_in); 687 } 688 } 689 690 int ImmLitIdx = 691 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm); 692 if (Res && ImmLitIdx != -1) 693 Res = convertFMAanyK(MI, ImmLitIdx); 694 695 // if the opcode was not recognized we'll assume a Size of 4 bytes 696 // (unless there are fewer bytes left) 697 Size = Res ? (MaxInstBytesNum - Bytes.size()) 698 : std::min((size_t)4, Bytes_.size()); 699 return Res; 700 } 701 702 DecodeStatus AMDGPUDisassembler::convertEXPInst(MCInst &MI) const { 703 if (STI.getFeatureBits()[AMDGPU::FeatureGFX11]) { 704 // The MCInst still has these fields even though they are no longer encoded 705 // in the GFX11 instruction. 706 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vm); 707 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::compr); 708 } 709 return MCDisassembler::Success; 710 } 711 712 DecodeStatus AMDGPUDisassembler::convertVINTERPInst(MCInst &MI) const { 713 if (MI.getOpcode() == AMDGPU::V_INTERP_P10_F16_F32_inreg_gfx11 || 714 MI.getOpcode() == AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg_gfx11 || 715 MI.getOpcode() == AMDGPU::V_INTERP_P2_F16_F32_inreg_gfx11 || 716 MI.getOpcode() == AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg_gfx11) { 717 // The MCInst has this field that is not directly encoded in the 718 // instruction. 719 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::op_sel); 720 } 721 return MCDisassembler::Success; 722 } 723 724 DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const { 725 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 726 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 727 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1) 728 // VOPC - insert clamp 729 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); 730 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 731 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst); 732 if (SDst != -1) { 733 // VOPC - insert VCC register as sdst 734 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), 735 AMDGPU::OpName::sdst); 736 } else { 737 // VOP1/2 - insert omod if present in instruction 738 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); 739 } 740 } 741 return MCDisassembler::Success; 742 } 743 744 // We must check FI == literal to reject not genuine dpp8 insts, and we must 745 // first add optional MI operands to check FI 746 DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { 747 unsigned Opc = MI.getOpcode(); 748 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 749 if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) { 750 convertVOP3PDPPInst(MI); 751 } else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) || 752 AMDGPU::isVOPC64DPP(Opc)) { 753 convertVOPCDPPInst(MI); 754 } else { 755 // Insert dummy unused src modifiers. 756 if (MI.getNumOperands() < DescNumOps && 757 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 758 insertNamedMCOperand(MI, MCOperand::createImm(0), 759 AMDGPU::OpName::src0_modifiers); 760 761 if (MI.getNumOperands() < DescNumOps && 762 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 763 insertNamedMCOperand(MI, MCOperand::createImm(0), 764 AMDGPU::OpName::src1_modifiers); 765 } 766 return isValidDPP8(MI) ? MCDisassembler::Success : MCDisassembler::SoftFail; 767 } 768 769 // Note that before gfx10, the MIMG encoding provided no information about 770 // VADDR size. Consequently, decoded instructions always show address as if it 771 // has 1 dword, which could be not really so. 772 DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const { 773 774 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 775 AMDGPU::OpName::vdst); 776 777 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 778 AMDGPU::OpName::vdata); 779 int VAddr0Idx = 780 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0); 781 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 782 AMDGPU::OpName::dmask); 783 784 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 785 AMDGPU::OpName::tfe); 786 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), 787 AMDGPU::OpName::d16); 788 789 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode()); 790 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = 791 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); 792 793 assert(VDataIdx != -1); 794 if (BaseOpcode->BVH) { 795 // Add A16 operand for intersect_ray instructions 796 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) { 797 addOperand(MI, MCOperand::createImm(1)); 798 } 799 return MCDisassembler::Success; 800 } 801 802 bool IsAtomic = (VDstIdx != -1); 803 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4; 804 bool IsNSA = false; 805 unsigned AddrSize = Info->VAddrDwords; 806 807 if (isGFX10Plus()) { 808 unsigned DimIdx = 809 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim); 810 int A16Idx = 811 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16); 812 const AMDGPU::MIMGDimInfo *Dim = 813 AMDGPU::getMIMGDimInfoByEncoding(MI.getOperand(DimIdx).getImm()); 814 const bool IsA16 = (A16Idx != -1 && MI.getOperand(A16Idx).getImm()); 815 816 AddrSize = 817 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); 818 819 IsNSA = Info->MIMGEncoding == AMDGPU::MIMGEncGfx10NSA || 820 Info->MIMGEncoding == AMDGPU::MIMGEncGfx11NSA; 821 if (!IsNSA) { 822 if (AddrSize > 8) 823 AddrSize = 16; 824 } else { 825 if (AddrSize > Info->VAddrDwords) { 826 // The NSA encoding does not contain enough operands for the combination 827 // of base opcode / dimension. Should this be an error? 828 return MCDisassembler::Success; 829 } 830 } 831 } 832 833 unsigned DMask = MI.getOperand(DMaskIdx).getImm() & 0xf; 834 unsigned DstSize = IsGather4 ? 4 : std::max(countPopulation(DMask), 1u); 835 836 bool D16 = D16Idx >= 0 && MI.getOperand(D16Idx).getImm(); 837 if (D16 && AMDGPU::hasPackedD16(STI)) { 838 DstSize = (DstSize + 1) / 2; 839 } 840 841 if (TFEIdx != -1 && MI.getOperand(TFEIdx).getImm()) 842 DstSize += 1; 843 844 if (DstSize == Info->VDataDwords && AddrSize == Info->VAddrDwords) 845 return MCDisassembler::Success; 846 847 int NewOpcode = 848 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); 849 if (NewOpcode == -1) 850 return MCDisassembler::Success; 851 852 // Widen the register to the correct number of enabled channels. 853 unsigned NewVdata = AMDGPU::NoRegister; 854 if (DstSize != Info->VDataDwords) { 855 auto DataRCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; 856 857 // Get first subregister of VData 858 unsigned Vdata0 = MI.getOperand(VDataIdx).getReg(); 859 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); 860 Vdata0 = (VdataSub0 != 0)? VdataSub0 : Vdata0; 861 862 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, 863 &MRI.getRegClass(DataRCID)); 864 if (NewVdata == AMDGPU::NoRegister) { 865 // It's possible to encode this such that the low register + enabled 866 // components exceeds the register count. 867 return MCDisassembler::Success; 868 } 869 } 870 871 // If not using NSA on GFX10+, widen address register to correct size. 872 unsigned NewVAddr0 = AMDGPU::NoRegister; 873 if (isGFX10Plus() && !IsNSA && AddrSize != Info->VAddrDwords) { 874 unsigned VAddr0 = MI.getOperand(VAddr0Idx).getReg(); 875 unsigned VAddrSub0 = MRI.getSubReg(VAddr0, AMDGPU::sub0); 876 VAddr0 = (VAddrSub0 != 0) ? VAddrSub0 : VAddr0; 877 878 auto AddrRCID = MCII->get(NewOpcode).OpInfo[VAddr0Idx].RegClass; 879 NewVAddr0 = MRI.getMatchingSuperReg(VAddr0, AMDGPU::sub0, 880 &MRI.getRegClass(AddrRCID)); 881 if (NewVAddr0 == AMDGPU::NoRegister) 882 return MCDisassembler::Success; 883 } 884 885 MI.setOpcode(NewOpcode); 886 887 if (NewVdata != AMDGPU::NoRegister) { 888 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); 889 890 if (IsAtomic) { 891 // Atomic operations have an additional operand (a copy of data) 892 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); 893 } 894 } 895 896 if (NewVAddr0 != AMDGPU::NoRegister) { 897 MI.getOperand(VAddr0Idx) = MCOperand::createReg(NewVAddr0); 898 } else if (IsNSA) { 899 assert(AddrSize <= Info->VAddrDwords); 900 MI.erase(MI.begin() + VAddr0Idx + AddrSize, 901 MI.begin() + VAddr0Idx + Info->VAddrDwords); 902 } 903 904 return MCDisassembler::Success; 905 } 906 907 // Opsel and neg bits are used in src_modifiers and standalone operands. Autogen 908 // decoder only adds to src_modifiers, so manually add the bits to the other 909 // operands. 910 DecodeStatus AMDGPUDisassembler::convertVOP3PDPPInst(MCInst &MI) const { 911 unsigned Opc = MI.getOpcode(); 912 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 913 914 if (MI.getNumOperands() < DescNumOps && 915 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) 916 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in); 917 918 const int ModOps[] = {AMDGPU::OpName::src0_modifiers, 919 AMDGPU::OpName::src1_modifiers, 920 AMDGPU::OpName::src2_modifiers}; 921 unsigned OpSel = 0; 922 unsigned OpSelHi = 0; 923 unsigned NegLo = 0; 924 unsigned NegHi = 0; 925 for (int J = 0; J < 3; ++J) { 926 int OpIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]); 927 if (OpIdx == -1) 928 break; 929 unsigned Val = MI.getOperand(OpIdx).getImm(); 930 931 OpSel |= !!(Val & SISrcMods::OP_SEL_0) << J; 932 OpSelHi |= !!(Val & SISrcMods::OP_SEL_1) << J; 933 NegLo |= !!(Val & SISrcMods::NEG) << J; 934 NegHi |= !!(Val & SISrcMods::NEG_HI) << J; 935 } 936 937 if (MI.getNumOperands() < DescNumOps && 938 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) 939 insertNamedMCOperand(MI, MCOperand::createImm(OpSel), 940 AMDGPU::OpName::op_sel); 941 if (MI.getNumOperands() < DescNumOps && 942 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi) != -1) 943 insertNamedMCOperand(MI, MCOperand::createImm(OpSelHi), 944 AMDGPU::OpName::op_sel_hi); 945 if (MI.getNumOperands() < DescNumOps && 946 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1) 947 insertNamedMCOperand(MI, MCOperand::createImm(NegLo), 948 AMDGPU::OpName::neg_lo); 949 if (MI.getNumOperands() < DescNumOps && 950 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1) 951 insertNamedMCOperand(MI, MCOperand::createImm(NegHi), 952 AMDGPU::OpName::neg_hi); 953 954 return MCDisassembler::Success; 955 } 956 957 // Create dummy old operand and insert optional operands 958 DecodeStatus AMDGPUDisassembler::convertVOPCDPPInst(MCInst &MI) const { 959 unsigned Opc = MI.getOpcode(); 960 unsigned DescNumOps = MCII->get(Opc).getNumOperands(); 961 962 if (MI.getNumOperands() < DescNumOps && 963 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1) 964 insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old); 965 966 if (MI.getNumOperands() < DescNumOps && 967 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) 968 insertNamedMCOperand(MI, MCOperand::createImm(0), 969 AMDGPU::OpName::src0_modifiers); 970 971 if (MI.getNumOperands() < DescNumOps && 972 AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1) 973 insertNamedMCOperand(MI, MCOperand::createImm(0), 974 AMDGPU::OpName::src1_modifiers); 975 return MCDisassembler::Success; 976 } 977 978 DecodeStatus AMDGPUDisassembler::convertFMAanyK(MCInst &MI, 979 int ImmLitIdx) const { 980 assert(HasLiteral && "Should have decoded a literal"); 981 const MCInstrDesc &Desc = MCII->get(MI.getOpcode()); 982 unsigned DescNumOps = Desc.getNumOperands(); 983 insertNamedMCOperand(MI, MCOperand::createImm(Literal), 984 AMDGPU::OpName::immDeferred); 985 assert(DescNumOps == MI.getNumOperands()); 986 for (unsigned I = 0; I < DescNumOps; ++I) { 987 auto &Op = MI.getOperand(I); 988 auto OpType = Desc.OpInfo[I].OperandType; 989 bool IsDeferredOp = (OpType == AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED || 990 OpType == AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED); 991 if (Op.isImm() && Op.getImm() == AMDGPU::EncValues::LITERAL_CONST && 992 IsDeferredOp) 993 Op.setImm(Literal); 994 } 995 return MCDisassembler::Success; 996 } 997 998 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { 999 return getContext().getRegisterInfo()-> 1000 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); 1001 } 1002 1003 inline 1004 MCOperand AMDGPUDisassembler::errOperand(unsigned V, 1005 const Twine& ErrMsg) const { 1006 *CommentStream << "Error: " + ErrMsg; 1007 1008 // ToDo: add support for error operands to MCInst.h 1009 // return MCOperand::createError(V); 1010 return MCOperand(); 1011 } 1012 1013 inline 1014 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { 1015 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI)); 1016 } 1017 1018 inline 1019 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, 1020 unsigned Val) const { 1021 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; 1022 if (Val >= RegCl.getNumRegs()) 1023 return errOperand(Val, Twine(getRegClassName(RegClassID)) + 1024 ": unknown register " + Twine(Val)); 1025 return createRegOperand(RegCl.getRegister(Val)); 1026 } 1027 1028 inline 1029 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, 1030 unsigned Val) const { 1031 // ToDo: SI/CI have 104 SGPRs, VI - 102 1032 // Valery: here we accepting as much as we can, let assembler sort it out 1033 int shift = 0; 1034 switch (SRegClassID) { 1035 case AMDGPU::SGPR_32RegClassID: 1036 case AMDGPU::TTMP_32RegClassID: 1037 break; 1038 case AMDGPU::SGPR_64RegClassID: 1039 case AMDGPU::TTMP_64RegClassID: 1040 shift = 1; 1041 break; 1042 case AMDGPU::SGPR_128RegClassID: 1043 case AMDGPU::TTMP_128RegClassID: 1044 // ToDo: unclear if s[100:104] is available on VI. Can we use VCC as SGPR in 1045 // this bundle? 1046 case AMDGPU::SGPR_256RegClassID: 1047 case AMDGPU::TTMP_256RegClassID: 1048 // ToDo: unclear if s[96:104] is available on VI. Can we use VCC as SGPR in 1049 // this bundle? 1050 case AMDGPU::SGPR_512RegClassID: 1051 case AMDGPU::TTMP_512RegClassID: 1052 shift = 2; 1053 break; 1054 // ToDo: unclear if s[88:104] is available on VI. Can we use VCC as SGPR in 1055 // this bundle? 1056 default: 1057 llvm_unreachable("unhandled register class"); 1058 } 1059 1060 if (Val % (1 << shift)) { 1061 *CommentStream << "Warning: " << getRegClassName(SRegClassID) 1062 << ": scalar reg isn't aligned " << Val; 1063 } 1064 1065 return createRegOperand(SRegClassID, Val >> shift); 1066 } 1067 1068 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { 1069 return decodeSrcOp(OPW32, Val); 1070 } 1071 1072 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { 1073 return decodeSrcOp(OPW64, Val); 1074 } 1075 1076 MCOperand AMDGPUDisassembler::decodeOperand_VS_128(unsigned Val) const { 1077 return decodeSrcOp(OPW128, Val); 1078 } 1079 1080 MCOperand AMDGPUDisassembler::decodeOperand_VSrc16(unsigned Val) const { 1081 return decodeSrcOp(OPW16, Val); 1082 } 1083 1084 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV216(unsigned Val) const { 1085 return decodeSrcOp(OPWV216, Val); 1086 } 1087 1088 MCOperand AMDGPUDisassembler::decodeOperand_VSrcV232(unsigned Val) const { 1089 return decodeSrcOp(OPWV232, Val); 1090 } 1091 1092 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { 1093 // Some instructions have operand restrictions beyond what the encoding 1094 // allows. Some ordinarily VSrc_32 operands are VGPR_32, so clear the extra 1095 // high bit. 1096 Val &= 255; 1097 1098 return createRegOperand(AMDGPU::VGPR_32RegClassID, Val); 1099 } 1100 1101 MCOperand AMDGPUDisassembler::decodeOperand_VRegOrLds_32(unsigned Val) const { 1102 return decodeSrcOp(OPW32, Val); 1103 } 1104 1105 MCOperand AMDGPUDisassembler::decodeOperand_AGPR_32(unsigned Val) const { 1106 return createRegOperand(AMDGPU::AGPR_32RegClassID, Val & 255); 1107 } 1108 1109 MCOperand AMDGPUDisassembler::decodeOperand_AReg_64(unsigned Val) const { 1110 return createRegOperand(AMDGPU::AReg_64RegClassID, Val & 255); 1111 } 1112 1113 MCOperand AMDGPUDisassembler::decodeOperand_AReg_128(unsigned Val) const { 1114 return createRegOperand(AMDGPU::AReg_128RegClassID, Val & 255); 1115 } 1116 1117 MCOperand AMDGPUDisassembler::decodeOperand_AReg_256(unsigned Val) const { 1118 return createRegOperand(AMDGPU::AReg_256RegClassID, Val & 255); 1119 } 1120 1121 MCOperand AMDGPUDisassembler::decodeOperand_AReg_512(unsigned Val) const { 1122 return createRegOperand(AMDGPU::AReg_512RegClassID, Val & 255); 1123 } 1124 1125 MCOperand AMDGPUDisassembler::decodeOperand_AReg_1024(unsigned Val) const { 1126 return createRegOperand(AMDGPU::AReg_1024RegClassID, Val & 255); 1127 } 1128 1129 MCOperand AMDGPUDisassembler::decodeOperand_AV_32(unsigned Val) const { 1130 return decodeSrcOp(OPW32, Val); 1131 } 1132 1133 MCOperand AMDGPUDisassembler::decodeOperand_AV_64(unsigned Val) const { 1134 return decodeSrcOp(OPW64, Val); 1135 } 1136 1137 MCOperand AMDGPUDisassembler::decodeOperand_AV_128(unsigned Val) const { 1138 return decodeSrcOp(OPW128, Val); 1139 } 1140 1141 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_128(unsigned Val) const { 1142 using namespace AMDGPU::EncValues; 1143 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1144 return decodeSrcOp(OPW128, Val | IS_VGPR); 1145 } 1146 1147 MCOperand AMDGPUDisassembler::decodeOperand_AVDst_512(unsigned Val) const { 1148 using namespace AMDGPU::EncValues; 1149 assert((Val & IS_VGPR) == 0); // Val{8} is not encoded but assumed to be 1. 1150 return decodeSrcOp(OPW512, Val | IS_VGPR); 1151 } 1152 1153 MCOperand AMDGPUDisassembler::decodeOperand_VReg_64(unsigned Val) const { 1154 return createRegOperand(AMDGPU::VReg_64RegClassID, Val); 1155 } 1156 1157 MCOperand AMDGPUDisassembler::decodeOperand_VReg_96(unsigned Val) const { 1158 return createRegOperand(AMDGPU::VReg_96RegClassID, Val); 1159 } 1160 1161 MCOperand AMDGPUDisassembler::decodeOperand_VReg_128(unsigned Val) const { 1162 return createRegOperand(AMDGPU::VReg_128RegClassID, Val); 1163 } 1164 1165 MCOperand AMDGPUDisassembler::decodeOperand_VReg_256(unsigned Val) const { 1166 return createRegOperand(AMDGPU::VReg_256RegClassID, Val); 1167 } 1168 1169 MCOperand AMDGPUDisassembler::decodeOperand_VReg_512(unsigned Val) const { 1170 return createRegOperand(AMDGPU::VReg_512RegClassID, Val); 1171 } 1172 1173 MCOperand AMDGPUDisassembler::decodeOperand_VReg_1024(unsigned Val) const { 1174 return createRegOperand(AMDGPU::VReg_1024RegClassID, Val); 1175 } 1176 1177 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32(unsigned Val) const { 1178 // table-gen generated disassembler doesn't care about operand types 1179 // leaving only registry class so SSrc_32 operand turns into SReg_32 1180 // and therefore we accept immediates and literals here as well 1181 return decodeSrcOp(OPW32, Val); 1182 } 1183 1184 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XM0_XEXEC( 1185 unsigned Val) const { 1186 // SReg_32_XM0 is SReg_32 without M0 or EXEC_LO/EXEC_HI 1187 return decodeOperand_SReg_32(Val); 1188 } 1189 1190 MCOperand AMDGPUDisassembler::decodeOperand_SReg_32_XEXEC_HI( 1191 unsigned Val) const { 1192 // SReg_32_XM0 is SReg_32 without EXEC_HI 1193 return decodeOperand_SReg_32(Val); 1194 } 1195 1196 MCOperand AMDGPUDisassembler::decodeOperand_SRegOrLds_32(unsigned Val) const { 1197 // table-gen generated disassembler doesn't care about operand types 1198 // leaving only registry class so SSrc_32 operand turns into SReg_32 1199 // and therefore we accept immediates and literals here as well 1200 return decodeSrcOp(OPW32, Val); 1201 } 1202 1203 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64(unsigned Val) const { 1204 return decodeSrcOp(OPW64, Val); 1205 } 1206 1207 MCOperand AMDGPUDisassembler::decodeOperand_SReg_64_XEXEC(unsigned Val) const { 1208 return decodeSrcOp(OPW64, Val); 1209 } 1210 1211 MCOperand AMDGPUDisassembler::decodeOperand_SReg_128(unsigned Val) const { 1212 return decodeSrcOp(OPW128, Val); 1213 } 1214 1215 MCOperand AMDGPUDisassembler::decodeOperand_SReg_256(unsigned Val) const { 1216 return decodeDstOp(OPW256, Val); 1217 } 1218 1219 MCOperand AMDGPUDisassembler::decodeOperand_SReg_512(unsigned Val) const { 1220 return decodeDstOp(OPW512, Val); 1221 } 1222 1223 // Decode Literals for insts which always have a literal in the encoding 1224 MCOperand 1225 AMDGPUDisassembler::decodeMandatoryLiteralConstant(unsigned Val) const { 1226 if (HasLiteral) { 1227 assert( 1228 AMDGPU::hasVOPD(STI) && 1229 "Should only decode multiple kimm with VOPD, check VSrc operand types"); 1230 if (Literal != Val) 1231 return errOperand(Val, "More than one unique literal is illegal"); 1232 } 1233 HasLiteral = true; 1234 Literal = Val; 1235 return MCOperand::createImm(Literal); 1236 } 1237 1238 MCOperand AMDGPUDisassembler::decodeLiteralConstant() const { 1239 // For now all literal constants are supposed to be unsigned integer 1240 // ToDo: deal with signed/unsigned 64-bit integer constants 1241 // ToDo: deal with float/double constants 1242 if (!HasLiteral) { 1243 if (Bytes.size() < 4) { 1244 return errOperand(0, "cannot read literal, inst bytes left " + 1245 Twine(Bytes.size())); 1246 } 1247 HasLiteral = true; 1248 Literal = eatBytes<uint32_t>(Bytes); 1249 } 1250 return MCOperand::createImm(Literal); 1251 } 1252 1253 MCOperand AMDGPUDisassembler::decodeIntImmed(unsigned Imm) { 1254 using namespace AMDGPU::EncValues; 1255 1256 assert(Imm >= INLINE_INTEGER_C_MIN && Imm <= INLINE_INTEGER_C_MAX); 1257 return MCOperand::createImm((Imm <= INLINE_INTEGER_C_POSITIVE_MAX) ? 1258 (static_cast<int64_t>(Imm) - INLINE_INTEGER_C_MIN) : 1259 (INLINE_INTEGER_C_POSITIVE_MAX - static_cast<int64_t>(Imm))); 1260 // Cast prevents negative overflow. 1261 } 1262 1263 static int64_t getInlineImmVal32(unsigned Imm) { 1264 switch (Imm) { 1265 case 240: 1266 return FloatToBits(0.5f); 1267 case 241: 1268 return FloatToBits(-0.5f); 1269 case 242: 1270 return FloatToBits(1.0f); 1271 case 243: 1272 return FloatToBits(-1.0f); 1273 case 244: 1274 return FloatToBits(2.0f); 1275 case 245: 1276 return FloatToBits(-2.0f); 1277 case 246: 1278 return FloatToBits(4.0f); 1279 case 247: 1280 return FloatToBits(-4.0f); 1281 case 248: // 1 / (2 * PI) 1282 return 0x3e22f983; 1283 default: 1284 llvm_unreachable("invalid fp inline imm"); 1285 } 1286 } 1287 1288 static int64_t getInlineImmVal64(unsigned Imm) { 1289 switch (Imm) { 1290 case 240: 1291 return DoubleToBits(0.5); 1292 case 241: 1293 return DoubleToBits(-0.5); 1294 case 242: 1295 return DoubleToBits(1.0); 1296 case 243: 1297 return DoubleToBits(-1.0); 1298 case 244: 1299 return DoubleToBits(2.0); 1300 case 245: 1301 return DoubleToBits(-2.0); 1302 case 246: 1303 return DoubleToBits(4.0); 1304 case 247: 1305 return DoubleToBits(-4.0); 1306 case 248: // 1 / (2 * PI) 1307 return 0x3fc45f306dc9c882; 1308 default: 1309 llvm_unreachable("invalid fp inline imm"); 1310 } 1311 } 1312 1313 static int64_t getInlineImmVal16(unsigned Imm) { 1314 switch (Imm) { 1315 case 240: 1316 return 0x3800; 1317 case 241: 1318 return 0xB800; 1319 case 242: 1320 return 0x3C00; 1321 case 243: 1322 return 0xBC00; 1323 case 244: 1324 return 0x4000; 1325 case 245: 1326 return 0xC000; 1327 case 246: 1328 return 0x4400; 1329 case 247: 1330 return 0xC400; 1331 case 248: // 1 / (2 * PI) 1332 return 0x3118; 1333 default: 1334 llvm_unreachable("invalid fp inline imm"); 1335 } 1336 } 1337 1338 MCOperand AMDGPUDisassembler::decodeFPImmed(OpWidthTy Width, unsigned Imm) { 1339 assert(Imm >= AMDGPU::EncValues::INLINE_FLOATING_C_MIN 1340 && Imm <= AMDGPU::EncValues::INLINE_FLOATING_C_MAX); 1341 1342 // ToDo: case 248: 1/(2*PI) - is allowed only on VI 1343 switch (Width) { 1344 case OPW32: 1345 case OPW128: // splat constants 1346 case OPW512: 1347 case OPW1024: 1348 case OPWV232: 1349 return MCOperand::createImm(getInlineImmVal32(Imm)); 1350 case OPW64: 1351 case OPW256: 1352 return MCOperand::createImm(getInlineImmVal64(Imm)); 1353 case OPW16: 1354 case OPWV216: 1355 return MCOperand::createImm(getInlineImmVal16(Imm)); 1356 default: 1357 llvm_unreachable("implement me"); 1358 } 1359 } 1360 1361 unsigned AMDGPUDisassembler::getVgprClassId(const OpWidthTy Width) const { 1362 using namespace AMDGPU; 1363 1364 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1365 switch (Width) { 1366 default: // fall 1367 case OPW32: 1368 case OPW16: 1369 case OPWV216: 1370 return VGPR_32RegClassID; 1371 case OPW64: 1372 case OPWV232: return VReg_64RegClassID; 1373 case OPW96: return VReg_96RegClassID; 1374 case OPW128: return VReg_128RegClassID; 1375 case OPW160: return VReg_160RegClassID; 1376 case OPW256: return VReg_256RegClassID; 1377 case OPW512: return VReg_512RegClassID; 1378 case OPW1024: return VReg_1024RegClassID; 1379 } 1380 } 1381 1382 unsigned AMDGPUDisassembler::getAgprClassId(const OpWidthTy Width) const { 1383 using namespace AMDGPU; 1384 1385 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1386 switch (Width) { 1387 default: // fall 1388 case OPW32: 1389 case OPW16: 1390 case OPWV216: 1391 return AGPR_32RegClassID; 1392 case OPW64: 1393 case OPWV232: return AReg_64RegClassID; 1394 case OPW96: return AReg_96RegClassID; 1395 case OPW128: return AReg_128RegClassID; 1396 case OPW160: return AReg_160RegClassID; 1397 case OPW256: return AReg_256RegClassID; 1398 case OPW512: return AReg_512RegClassID; 1399 case OPW1024: return AReg_1024RegClassID; 1400 } 1401 } 1402 1403 1404 unsigned AMDGPUDisassembler::getSgprClassId(const OpWidthTy Width) const { 1405 using namespace AMDGPU; 1406 1407 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1408 switch (Width) { 1409 default: // fall 1410 case OPW32: 1411 case OPW16: 1412 case OPWV216: 1413 return SGPR_32RegClassID; 1414 case OPW64: 1415 case OPWV232: return SGPR_64RegClassID; 1416 case OPW96: return SGPR_96RegClassID; 1417 case OPW128: return SGPR_128RegClassID; 1418 case OPW160: return SGPR_160RegClassID; 1419 case OPW256: return SGPR_256RegClassID; 1420 case OPW512: return SGPR_512RegClassID; 1421 } 1422 } 1423 1424 unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const { 1425 using namespace AMDGPU; 1426 1427 assert(OPW_FIRST_ <= Width && Width < OPW_LAST_); 1428 switch (Width) { 1429 default: // fall 1430 case OPW32: 1431 case OPW16: 1432 case OPWV216: 1433 return TTMP_32RegClassID; 1434 case OPW64: 1435 case OPWV232: return TTMP_64RegClassID; 1436 case OPW128: return TTMP_128RegClassID; 1437 case OPW256: return TTMP_256RegClassID; 1438 case OPW512: return TTMP_512RegClassID; 1439 } 1440 } 1441 1442 int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const { 1443 using namespace AMDGPU::EncValues; 1444 1445 unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9PLUS_MIN : TTMP_VI_MIN; 1446 unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9PLUS_MAX : TTMP_VI_MAX; 1447 1448 return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1; 1449 } 1450 1451 MCOperand AMDGPUDisassembler::decodeSrcOp(const OpWidthTy Width, unsigned Val, 1452 bool MandatoryLiteral) const { 1453 using namespace AMDGPU::EncValues; 1454 1455 assert(Val < 1024); // enum10 1456 1457 bool IsAGPR = Val & 512; 1458 Val &= 511; 1459 1460 if (VGPR_MIN <= Val && Val <= VGPR_MAX) { 1461 return createRegOperand(IsAGPR ? getAgprClassId(Width) 1462 : getVgprClassId(Width), Val - VGPR_MIN); 1463 } 1464 if (Val <= SGPR_MAX) { 1465 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1466 static_assert(SGPR_MIN == 0, ""); 1467 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1468 } 1469 1470 int TTmpIdx = getTTmpIdx(Val); 1471 if (TTmpIdx >= 0) { 1472 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1473 } 1474 1475 if (INLINE_INTEGER_C_MIN <= Val && Val <= INLINE_INTEGER_C_MAX) 1476 return decodeIntImmed(Val); 1477 1478 if (INLINE_FLOATING_C_MIN <= Val && Val <= INLINE_FLOATING_C_MAX) 1479 return decodeFPImmed(Width, Val); 1480 1481 if (Val == LITERAL_CONST) { 1482 if (MandatoryLiteral) 1483 // Keep a sentinel value for deferred setting 1484 return MCOperand::createImm(LITERAL_CONST); 1485 else 1486 return decodeLiteralConstant(); 1487 } 1488 1489 switch (Width) { 1490 case OPW32: 1491 case OPW16: 1492 case OPWV216: 1493 return decodeSpecialReg32(Val); 1494 case OPW64: 1495 case OPWV232: 1496 return decodeSpecialReg64(Val); 1497 default: 1498 llvm_unreachable("unexpected immediate type"); 1499 } 1500 } 1501 1502 MCOperand AMDGPUDisassembler::decodeDstOp(const OpWidthTy Width, unsigned Val) const { 1503 using namespace AMDGPU::EncValues; 1504 1505 assert(Val < 128); 1506 assert(Width == OPW256 || Width == OPW512); 1507 1508 if (Val <= SGPR_MAX) { 1509 // "SGPR_MIN <= Val" is always true and causes compilation warning. 1510 static_assert(SGPR_MIN == 0, ""); 1511 return createSRegOperand(getSgprClassId(Width), Val - SGPR_MIN); 1512 } 1513 1514 int TTmpIdx = getTTmpIdx(Val); 1515 if (TTmpIdx >= 0) { 1516 return createSRegOperand(getTtmpClassId(Width), TTmpIdx); 1517 } 1518 1519 llvm_unreachable("unknown dst register"); 1520 } 1521 1522 // Bit 0 of DstY isn't stored in the instruction, because it's always the 1523 // opposite of bit 0 of DstX. 1524 MCOperand AMDGPUDisassembler::decodeVOPDDstYOp(MCInst &Inst, 1525 unsigned Val) const { 1526 int VDstXInd = 1527 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::vdstX); 1528 assert(VDstXInd != -1); 1529 assert(Inst.getOperand(VDstXInd).isReg()); 1530 unsigned XDstReg = MRI.getEncodingValue(Inst.getOperand(VDstXInd).getReg()); 1531 Val |= ~XDstReg & 1; 1532 auto Width = llvm::AMDGPUDisassembler::OPW32; 1533 return createRegOperand(getVgprClassId(Width), Val); 1534 } 1535 1536 MCOperand AMDGPUDisassembler::decodeSpecialReg32(unsigned Val) const { 1537 using namespace AMDGPU; 1538 1539 switch (Val) { 1540 case 102: return createRegOperand(FLAT_SCR_LO); 1541 case 103: return createRegOperand(FLAT_SCR_HI); 1542 case 104: return createRegOperand(XNACK_MASK_LO); 1543 case 105: return createRegOperand(XNACK_MASK_HI); 1544 case 106: return createRegOperand(VCC_LO); 1545 case 107: return createRegOperand(VCC_HI); 1546 case 108: return createRegOperand(TBA_LO); 1547 case 109: return createRegOperand(TBA_HI); 1548 case 110: return createRegOperand(TMA_LO); 1549 case 111: return createRegOperand(TMA_HI); 1550 case 124: 1551 return isGFX11Plus() ? createRegOperand(SGPR_NULL) : createRegOperand(M0); 1552 case 125: 1553 return isGFX11Plus() ? createRegOperand(M0) : createRegOperand(SGPR_NULL); 1554 case 126: return createRegOperand(EXEC_LO); 1555 case 127: return createRegOperand(EXEC_HI); 1556 case 235: return createRegOperand(SRC_SHARED_BASE); 1557 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1558 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1559 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1560 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1561 case 251: return createRegOperand(SRC_VCCZ); 1562 case 252: return createRegOperand(SRC_EXECZ); 1563 case 253: return createRegOperand(SRC_SCC); 1564 case 254: return createRegOperand(LDS_DIRECT); 1565 default: break; 1566 } 1567 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1568 } 1569 1570 MCOperand AMDGPUDisassembler::decodeSpecialReg64(unsigned Val) const { 1571 using namespace AMDGPU; 1572 1573 switch (Val) { 1574 case 102: return createRegOperand(FLAT_SCR); 1575 case 104: return createRegOperand(XNACK_MASK); 1576 case 106: return createRegOperand(VCC); 1577 case 108: return createRegOperand(TBA); 1578 case 110: return createRegOperand(TMA); 1579 case 124: 1580 if (isGFX11Plus()) 1581 return createRegOperand(SGPR_NULL); 1582 break; 1583 case 125: 1584 if (!isGFX11Plus()) 1585 return createRegOperand(SGPR_NULL); 1586 break; 1587 case 126: return createRegOperand(EXEC); 1588 case 235: return createRegOperand(SRC_SHARED_BASE); 1589 case 236: return createRegOperand(SRC_SHARED_LIMIT); 1590 case 237: return createRegOperand(SRC_PRIVATE_BASE); 1591 case 238: return createRegOperand(SRC_PRIVATE_LIMIT); 1592 case 239: return createRegOperand(SRC_POPS_EXITING_WAVE_ID); 1593 case 251: return createRegOperand(SRC_VCCZ); 1594 case 252: return createRegOperand(SRC_EXECZ); 1595 case 253: return createRegOperand(SRC_SCC); 1596 default: break; 1597 } 1598 return errOperand(Val, "unknown operand encoding " + Twine(Val)); 1599 } 1600 1601 MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width, 1602 const unsigned Val) const { 1603 using namespace AMDGPU::SDWA; 1604 using namespace AMDGPU::EncValues; 1605 1606 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1607 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) { 1608 // XXX: cast to int is needed to avoid stupid warning: 1609 // compare with unsigned is always true 1610 if (int(SDWA9EncValues::SRC_VGPR_MIN) <= int(Val) && 1611 Val <= SDWA9EncValues::SRC_VGPR_MAX) { 1612 return createRegOperand(getVgprClassId(Width), 1613 Val - SDWA9EncValues::SRC_VGPR_MIN); 1614 } 1615 if (SDWA9EncValues::SRC_SGPR_MIN <= Val && 1616 Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10 1617 : SDWA9EncValues::SRC_SGPR_MAX_SI)) { 1618 return createSRegOperand(getSgprClassId(Width), 1619 Val - SDWA9EncValues::SRC_SGPR_MIN); 1620 } 1621 if (SDWA9EncValues::SRC_TTMP_MIN <= Val && 1622 Val <= SDWA9EncValues::SRC_TTMP_MAX) { 1623 return createSRegOperand(getTtmpClassId(Width), 1624 Val - SDWA9EncValues::SRC_TTMP_MIN); 1625 } 1626 1627 const unsigned SVal = Val - SDWA9EncValues::SRC_SGPR_MIN; 1628 1629 if (INLINE_INTEGER_C_MIN <= SVal && SVal <= INLINE_INTEGER_C_MAX) 1630 return decodeIntImmed(SVal); 1631 1632 if (INLINE_FLOATING_C_MIN <= SVal && SVal <= INLINE_FLOATING_C_MAX) 1633 return decodeFPImmed(Width, SVal); 1634 1635 return decodeSpecialReg32(SVal); 1636 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) { 1637 return createRegOperand(getVgprClassId(Width), Val); 1638 } 1639 llvm_unreachable("unsupported target"); 1640 } 1641 1642 MCOperand AMDGPUDisassembler::decodeSDWASrc16(unsigned Val) const { 1643 return decodeSDWASrc(OPW16, Val); 1644 } 1645 1646 MCOperand AMDGPUDisassembler::decodeSDWASrc32(unsigned Val) const { 1647 return decodeSDWASrc(OPW32, Val); 1648 } 1649 1650 MCOperand AMDGPUDisassembler::decodeSDWAVopcDst(unsigned Val) const { 1651 using namespace AMDGPU::SDWA; 1652 1653 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] || 1654 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) && 1655 "SDWAVopcDst should be present only on GFX9+"); 1656 1657 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64]; 1658 1659 if (Val & SDWA9EncValues::VOPC_DST_VCC_MASK) { 1660 Val &= SDWA9EncValues::VOPC_DST_SGPR_MASK; 1661 1662 int TTmpIdx = getTTmpIdx(Val); 1663 if (TTmpIdx >= 0) { 1664 auto TTmpClsId = getTtmpClassId(IsWave64 ? OPW64 : OPW32); 1665 return createSRegOperand(TTmpClsId, TTmpIdx); 1666 } else if (Val > SGPR_MAX) { 1667 return IsWave64 ? decodeSpecialReg64(Val) 1668 : decodeSpecialReg32(Val); 1669 } else { 1670 return createSRegOperand(getSgprClassId(IsWave64 ? OPW64 : OPW32), Val); 1671 } 1672 } else { 1673 return createRegOperand(IsWave64 ? AMDGPU::VCC : AMDGPU::VCC_LO); 1674 } 1675 } 1676 1677 MCOperand AMDGPUDisassembler::decodeBoolReg(unsigned Val) const { 1678 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ? 1679 decodeOperand_SReg_64(Val) : decodeOperand_SReg_32(Val); 1680 } 1681 1682 bool AMDGPUDisassembler::isVI() const { 1683 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]; 1684 } 1685 1686 bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); } 1687 1688 bool AMDGPUDisassembler::isGFX90A() const { 1689 return STI.getFeatureBits()[AMDGPU::FeatureGFX90AInsts]; 1690 } 1691 1692 bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); } 1693 1694 bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); } 1695 1696 bool AMDGPUDisassembler::isGFX10Plus() const { 1697 return AMDGPU::isGFX10Plus(STI); 1698 } 1699 1700 bool AMDGPUDisassembler::isGFX11() const { 1701 return STI.getFeatureBits()[AMDGPU::FeatureGFX11]; 1702 } 1703 1704 bool AMDGPUDisassembler::isGFX11Plus() const { 1705 return AMDGPU::isGFX11Plus(STI); 1706 } 1707 1708 1709 bool AMDGPUDisassembler::hasArchitectedFlatScratch() const { 1710 return STI.getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch]; 1711 } 1712 1713 //===----------------------------------------------------------------------===// 1714 // AMDGPU specific symbol handling 1715 //===----------------------------------------------------------------------===// 1716 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1717 do { \ 1718 KdStream << Indent << DIRECTIVE " " \ 1719 << ((FourByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1720 } while (0) 1721 1722 // NOLINTNEXTLINE(readability-identifier-naming) 1723 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1( 1724 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1725 using namespace amdhsa; 1726 StringRef Indent = "\t"; 1727 1728 // We cannot accurately backward compute #VGPRs used from 1729 // GRANULATED_WORKITEM_VGPR_COUNT. But we are concerned with getting the same 1730 // value of GRANULATED_WORKITEM_VGPR_COUNT in the reassembled binary. So we 1731 // simply calculate the inverse of what the assembler does. 1732 1733 uint32_t GranulatedWorkitemVGPRCount = 1734 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT) >> 1735 COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_SHIFT; 1736 1737 uint32_t NextFreeVGPR = (GranulatedWorkitemVGPRCount + 1) * 1738 AMDGPU::IsaInfo::getVGPREncodingGranule(&STI); 1739 1740 KdStream << Indent << ".amdhsa_next_free_vgpr " << NextFreeVGPR << '\n'; 1741 1742 // We cannot backward compute values used to calculate 1743 // GRANULATED_WAVEFRONT_SGPR_COUNT. Hence the original values for following 1744 // directives can't be computed: 1745 // .amdhsa_reserve_vcc 1746 // .amdhsa_reserve_flat_scratch 1747 // .amdhsa_reserve_xnack_mask 1748 // They take their respective default values if not specified in the assembly. 1749 // 1750 // GRANULATED_WAVEFRONT_SGPR_COUNT 1751 // = f(NEXT_FREE_SGPR + VCC + FLAT_SCRATCH + XNACK_MASK) 1752 // 1753 // We compute the inverse as though all directives apart from NEXT_FREE_SGPR 1754 // are set to 0. So while disassembling we consider that: 1755 // 1756 // GRANULATED_WAVEFRONT_SGPR_COUNT 1757 // = f(NEXT_FREE_SGPR + 0 + 0 + 0) 1758 // 1759 // The disassembler cannot recover the original values of those 3 directives. 1760 1761 uint32_t GranulatedWavefrontSGPRCount = 1762 (FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >> 1763 COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT; 1764 1765 if (isGFX10Plus() && GranulatedWavefrontSGPRCount) 1766 return MCDisassembler::Fail; 1767 1768 uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) * 1769 AMDGPU::IsaInfo::getSGPREncodingGranule(&STI); 1770 1771 KdStream << Indent << ".amdhsa_reserve_vcc " << 0 << '\n'; 1772 if (!hasArchitectedFlatScratch()) 1773 KdStream << Indent << ".amdhsa_reserve_flat_scratch " << 0 << '\n'; 1774 KdStream << Indent << ".amdhsa_reserve_xnack_mask " << 0 << '\n'; 1775 KdStream << Indent << ".amdhsa_next_free_sgpr " << NextFreeSGPR << "\n"; 1776 1777 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIORITY) 1778 return MCDisassembler::Fail; 1779 1780 PRINT_DIRECTIVE(".amdhsa_float_round_mode_32", 1781 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32); 1782 PRINT_DIRECTIVE(".amdhsa_float_round_mode_16_64", 1783 COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64); 1784 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_32", 1785 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32); 1786 PRINT_DIRECTIVE(".amdhsa_float_denorm_mode_16_64", 1787 COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64); 1788 1789 if (FourByteBuffer & COMPUTE_PGM_RSRC1_PRIV) 1790 return MCDisassembler::Fail; 1791 1792 PRINT_DIRECTIVE(".amdhsa_dx10_clamp", COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP); 1793 1794 if (FourByteBuffer & COMPUTE_PGM_RSRC1_DEBUG_MODE) 1795 return MCDisassembler::Fail; 1796 1797 PRINT_DIRECTIVE(".amdhsa_ieee_mode", COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE); 1798 1799 if (FourByteBuffer & COMPUTE_PGM_RSRC1_BULKY) 1800 return MCDisassembler::Fail; 1801 1802 if (FourByteBuffer & COMPUTE_PGM_RSRC1_CDBG_USER) 1803 return MCDisassembler::Fail; 1804 1805 PRINT_DIRECTIVE(".amdhsa_fp16_overflow", COMPUTE_PGM_RSRC1_FP16_OVFL); 1806 1807 if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0) 1808 return MCDisassembler::Fail; 1809 1810 if (isGFX10Plus()) { 1811 PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode", 1812 COMPUTE_PGM_RSRC1_WGP_MODE); 1813 PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED); 1814 PRINT_DIRECTIVE(".amdhsa_forward_progress", COMPUTE_PGM_RSRC1_FWD_PROGRESS); 1815 } 1816 return MCDisassembler::Success; 1817 } 1818 1819 // NOLINTNEXTLINE(readability-identifier-naming) 1820 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC2( 1821 uint32_t FourByteBuffer, raw_string_ostream &KdStream) const { 1822 using namespace amdhsa; 1823 StringRef Indent = "\t"; 1824 if (hasArchitectedFlatScratch()) 1825 PRINT_DIRECTIVE(".amdhsa_enable_private_segment", 1826 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1827 else 1828 PRINT_DIRECTIVE(".amdhsa_system_sgpr_private_segment_wavefront_offset", 1829 COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT); 1830 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_x", 1831 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X); 1832 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_y", 1833 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y); 1834 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_id_z", 1835 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z); 1836 PRINT_DIRECTIVE(".amdhsa_system_sgpr_workgroup_info", 1837 COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO); 1838 PRINT_DIRECTIVE(".amdhsa_system_vgpr_workitem_id", 1839 COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID); 1840 1841 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_ADDRESS_WATCH) 1842 return MCDisassembler::Fail; 1843 1844 if (FourByteBuffer & COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_MEMORY) 1845 return MCDisassembler::Fail; 1846 1847 if (FourByteBuffer & COMPUTE_PGM_RSRC2_GRANULATED_LDS_SIZE) 1848 return MCDisassembler::Fail; 1849 1850 PRINT_DIRECTIVE( 1851 ".amdhsa_exception_fp_ieee_invalid_op", 1852 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION); 1853 PRINT_DIRECTIVE(".amdhsa_exception_fp_denorm_src", 1854 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE); 1855 PRINT_DIRECTIVE( 1856 ".amdhsa_exception_fp_ieee_div_zero", 1857 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO); 1858 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_overflow", 1859 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW); 1860 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_underflow", 1861 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW); 1862 PRINT_DIRECTIVE(".amdhsa_exception_fp_ieee_inexact", 1863 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT); 1864 PRINT_DIRECTIVE(".amdhsa_exception_int_div_zero", 1865 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO); 1866 1867 if (FourByteBuffer & COMPUTE_PGM_RSRC2_RESERVED0) 1868 return MCDisassembler::Fail; 1869 1870 return MCDisassembler::Success; 1871 } 1872 1873 #undef PRINT_DIRECTIVE 1874 1875 MCDisassembler::DecodeStatus 1876 AMDGPUDisassembler::decodeKernelDescriptorDirective( 1877 DataExtractor::Cursor &Cursor, ArrayRef<uint8_t> Bytes, 1878 raw_string_ostream &KdStream) const { 1879 #define PRINT_DIRECTIVE(DIRECTIVE, MASK) \ 1880 do { \ 1881 KdStream << Indent << DIRECTIVE " " \ 1882 << ((TwoByteBuffer & MASK) >> (MASK##_SHIFT)) << '\n'; \ 1883 } while (0) 1884 1885 uint16_t TwoByteBuffer = 0; 1886 uint32_t FourByteBuffer = 0; 1887 1888 StringRef ReservedBytes; 1889 StringRef Indent = "\t"; 1890 1891 assert(Bytes.size() == 64); 1892 DataExtractor DE(Bytes, /*IsLittleEndian=*/true, /*AddressSize=*/8); 1893 1894 switch (Cursor.tell()) { 1895 case amdhsa::GROUP_SEGMENT_FIXED_SIZE_OFFSET: 1896 FourByteBuffer = DE.getU32(Cursor); 1897 KdStream << Indent << ".amdhsa_group_segment_fixed_size " << FourByteBuffer 1898 << '\n'; 1899 return MCDisassembler::Success; 1900 1901 case amdhsa::PRIVATE_SEGMENT_FIXED_SIZE_OFFSET: 1902 FourByteBuffer = DE.getU32(Cursor); 1903 KdStream << Indent << ".amdhsa_private_segment_fixed_size " 1904 << FourByteBuffer << '\n'; 1905 return MCDisassembler::Success; 1906 1907 case amdhsa::KERNARG_SIZE_OFFSET: 1908 FourByteBuffer = DE.getU32(Cursor); 1909 KdStream << Indent << ".amdhsa_kernarg_size " 1910 << FourByteBuffer << '\n'; 1911 return MCDisassembler::Success; 1912 1913 case amdhsa::RESERVED0_OFFSET: 1914 // 4 reserved bytes, must be 0. 1915 ReservedBytes = DE.getBytes(Cursor, 4); 1916 for (int I = 0; I < 4; ++I) { 1917 if (ReservedBytes[I] != 0) { 1918 return MCDisassembler::Fail; 1919 } 1920 } 1921 return MCDisassembler::Success; 1922 1923 case amdhsa::KERNEL_CODE_ENTRY_BYTE_OFFSET_OFFSET: 1924 // KERNEL_CODE_ENTRY_BYTE_OFFSET 1925 // So far no directive controls this for Code Object V3, so simply skip for 1926 // disassembly. 1927 DE.skip(Cursor, 8); 1928 return MCDisassembler::Success; 1929 1930 case amdhsa::RESERVED1_OFFSET: 1931 // 20 reserved bytes, must be 0. 1932 ReservedBytes = DE.getBytes(Cursor, 20); 1933 for (int I = 0; I < 20; ++I) { 1934 if (ReservedBytes[I] != 0) { 1935 return MCDisassembler::Fail; 1936 } 1937 } 1938 return MCDisassembler::Success; 1939 1940 case amdhsa::COMPUTE_PGM_RSRC3_OFFSET: 1941 // COMPUTE_PGM_RSRC3 1942 // - Only set for GFX10, GFX6-9 have this to be 0. 1943 // - Currently no directives directly control this. 1944 FourByteBuffer = DE.getU32(Cursor); 1945 if (!isGFX10Plus() && FourByteBuffer) { 1946 return MCDisassembler::Fail; 1947 } 1948 return MCDisassembler::Success; 1949 1950 case amdhsa::COMPUTE_PGM_RSRC1_OFFSET: 1951 FourByteBuffer = DE.getU32(Cursor); 1952 if (decodeCOMPUTE_PGM_RSRC1(FourByteBuffer, KdStream) == 1953 MCDisassembler::Fail) { 1954 return MCDisassembler::Fail; 1955 } 1956 return MCDisassembler::Success; 1957 1958 case amdhsa::COMPUTE_PGM_RSRC2_OFFSET: 1959 FourByteBuffer = DE.getU32(Cursor); 1960 if (decodeCOMPUTE_PGM_RSRC2(FourByteBuffer, KdStream) == 1961 MCDisassembler::Fail) { 1962 return MCDisassembler::Fail; 1963 } 1964 return MCDisassembler::Success; 1965 1966 case amdhsa::KERNEL_CODE_PROPERTIES_OFFSET: 1967 using namespace amdhsa; 1968 TwoByteBuffer = DE.getU16(Cursor); 1969 1970 if (!hasArchitectedFlatScratch()) 1971 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_buffer", 1972 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER); 1973 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_ptr", 1974 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR); 1975 PRINT_DIRECTIVE(".amdhsa_user_sgpr_queue_ptr", 1976 KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR); 1977 PRINT_DIRECTIVE(".amdhsa_user_sgpr_kernarg_segment_ptr", 1978 KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR); 1979 PRINT_DIRECTIVE(".amdhsa_user_sgpr_dispatch_id", 1980 KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID); 1981 if (!hasArchitectedFlatScratch()) 1982 PRINT_DIRECTIVE(".amdhsa_user_sgpr_flat_scratch_init", 1983 KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT); 1984 PRINT_DIRECTIVE(".amdhsa_user_sgpr_private_segment_size", 1985 KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE); 1986 1987 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED0) 1988 return MCDisassembler::Fail; 1989 1990 // Reserved for GFX9 1991 if (isGFX9() && 1992 (TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) { 1993 return MCDisassembler::Fail; 1994 } else if (isGFX10Plus()) { 1995 PRINT_DIRECTIVE(".amdhsa_wavefront_size32", 1996 KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32); 1997 } 1998 1999 if (TwoByteBuffer & KERNEL_CODE_PROPERTY_RESERVED1) 2000 return MCDisassembler::Fail; 2001 2002 return MCDisassembler::Success; 2003 2004 case amdhsa::RESERVED2_OFFSET: 2005 // 6 bytes from here are reserved, must be 0. 2006 ReservedBytes = DE.getBytes(Cursor, 6); 2007 for (int I = 0; I < 6; ++I) { 2008 if (ReservedBytes[I] != 0) 2009 return MCDisassembler::Fail; 2010 } 2011 return MCDisassembler::Success; 2012 2013 default: 2014 llvm_unreachable("Unhandled index. Case statements cover everything."); 2015 return MCDisassembler::Fail; 2016 } 2017 #undef PRINT_DIRECTIVE 2018 } 2019 2020 MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeKernelDescriptor( 2021 StringRef KdName, ArrayRef<uint8_t> Bytes, uint64_t KdAddress) const { 2022 // CP microcode requires the kernel descriptor to be 64 aligned. 2023 if (Bytes.size() != 64 || KdAddress % 64 != 0) 2024 return MCDisassembler::Fail; 2025 2026 std::string Kd; 2027 raw_string_ostream KdStream(Kd); 2028 KdStream << ".amdhsa_kernel " << KdName << '\n'; 2029 2030 DataExtractor::Cursor C(0); 2031 while (C && C.tell() < Bytes.size()) { 2032 MCDisassembler::DecodeStatus Status = 2033 decodeKernelDescriptorDirective(C, Bytes, KdStream); 2034 2035 cantFail(C.takeError()); 2036 2037 if (Status == MCDisassembler::Fail) 2038 return MCDisassembler::Fail; 2039 } 2040 KdStream << ".end_amdhsa_kernel\n"; 2041 outs() << KdStream.str(); 2042 return MCDisassembler::Success; 2043 } 2044 2045 Optional<MCDisassembler::DecodeStatus> 2046 AMDGPUDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, 2047 ArrayRef<uint8_t> Bytes, uint64_t Address, 2048 raw_ostream &CStream) const { 2049 // Right now only kernel descriptor needs to be handled. 2050 // We ignore all other symbols for target specific handling. 2051 // TODO: 2052 // Fix the spurious symbol issue for AMDGPU kernels. Exists for both Code 2053 // Object V2 and V3 when symbols are marked protected. 2054 2055 // amd_kernel_code_t for Code Object V2. 2056 if (Symbol.Type == ELF::STT_AMDGPU_HSA_KERNEL) { 2057 Size = 256; 2058 return MCDisassembler::Fail; 2059 } 2060 2061 // Code Object V3 kernel descriptors. 2062 StringRef Name = Symbol.Name; 2063 if (Symbol.Type == ELF::STT_OBJECT && Name.endswith(StringRef(".kd"))) { 2064 Size = 64; // Size = 64 regardless of success or failure. 2065 return decodeKernelDescriptor(Name.drop_back(3), Bytes, Address); 2066 } 2067 return None; 2068 } 2069 2070 //===----------------------------------------------------------------------===// 2071 // AMDGPUSymbolizer 2072 //===----------------------------------------------------------------------===// 2073 2074 // Try to find symbol name for specified label 2075 bool AMDGPUSymbolizer::tryAddingSymbolicOperand( 2076 MCInst &Inst, raw_ostream & /*cStream*/, int64_t Value, 2077 uint64_t /*Address*/, bool IsBranch, uint64_t /*Offset*/, 2078 uint64_t /*OpSize*/, uint64_t /*InstSize*/) { 2079 2080 if (!IsBranch) { 2081 return false; 2082 } 2083 2084 auto *Symbols = static_cast<SectionSymbolsTy *>(DisInfo); 2085 if (!Symbols) 2086 return false; 2087 2088 auto Result = llvm::find_if(*Symbols, [Value](const SymbolInfoTy &Val) { 2089 return Val.Addr == static_cast<uint64_t>(Value) && 2090 Val.Type == ELF::STT_NOTYPE; 2091 }); 2092 if (Result != Symbols->end()) { 2093 auto *Sym = Ctx.getOrCreateSymbol(Result->Name); 2094 const auto *Add = MCSymbolRefExpr::create(Sym, Ctx); 2095 Inst.addOperand(MCOperand::createExpr(Add)); 2096 return true; 2097 } 2098 // Add to list of referenced addresses, so caller can synthesize a label. 2099 ReferencedAddresses.push_back(static_cast<uint64_t>(Value)); 2100 return false; 2101 } 2102 2103 void AMDGPUSymbolizer::tryAddingPcLoadReferenceComment(raw_ostream &cStream, 2104 int64_t Value, 2105 uint64_t Address) { 2106 llvm_unreachable("unimplemented"); 2107 } 2108 2109 //===----------------------------------------------------------------------===// 2110 // Initialization 2111 //===----------------------------------------------------------------------===// 2112 2113 static MCSymbolizer *createAMDGPUSymbolizer(const Triple &/*TT*/, 2114 LLVMOpInfoCallback /*GetOpInfo*/, 2115 LLVMSymbolLookupCallback /*SymbolLookUp*/, 2116 void *DisInfo, 2117 MCContext *Ctx, 2118 std::unique_ptr<MCRelocationInfo> &&RelInfo) { 2119 return new AMDGPUSymbolizer(*Ctx, std::move(RelInfo), DisInfo); 2120 } 2121 2122 static MCDisassembler *createAMDGPUDisassembler(const Target &T, 2123 const MCSubtargetInfo &STI, 2124 MCContext &Ctx) { 2125 return new AMDGPUDisassembler(STI, Ctx, T.createMCInstrInfo()); 2126 } 2127 2128 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUDisassembler() { 2129 TargetRegistry::RegisterMCDisassembler(getTheGCNTarget(), 2130 createAMDGPUDisassembler); 2131 TargetRegistry::RegisterMCSymbolizer(getTheGCNTarget(), 2132 createAMDGPUSymbolizer); 2133 } 2134