1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst. 12 // 13 //===----------------------------------------------------------------------===// 14 // 15 16 #include "AMDGPUMCInstLower.h" 17 #include "AMDGPUAsmPrinter.h" 18 #include "AMDGPUSubtarget.h" 19 #include "AMDGPUTargetMachine.h" 20 #include "InstPrinter/AMDGPUInstPrinter.h" 21 #include "SIInstrInfo.h" 22 #include "llvm/CodeGen/MachineBasicBlock.h" 23 #include "llvm/CodeGen/MachineInstr.h" 24 #include "llvm/IR/Constants.h" 25 #include "llvm/IR/Function.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/MC/MCCodeEmitter.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCExpr.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/MC/MCObjectStreamer.h" 32 #include "llvm/MC/MCStreamer.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/Format.h" 35 #include <algorithm> 36 37 using namespace llvm; 38 39 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st, 40 const AsmPrinter &ap): 41 Ctx(ctx), ST(st), AP(ap) { } 42 43 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) { 44 switch (MOFlags) { 45 default: return MCSymbolRefExpr::VK_None; 46 case SIInstrInfo::MO_GOTPCREL: return MCSymbolRefExpr::VK_GOTPCREL; 47 } 48 } 49 50 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr( 51 const MachineBasicBlock &SrcBB, 52 const MachineOperand &MO) const { 53 const MCExpr *DestBBSym 54 = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx); 55 const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx); 56 57 assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 && 58 ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4); 59 60 // s_getpc_b64 returns the address of next instruction. 61 const MCConstantExpr *One = MCConstantExpr::create(4, Ctx); 62 SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx); 63 64 if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD) 65 return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx); 66 67 assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD); 68 return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx); 69 } 70 71 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { 72 73 int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode()); 74 75 if (MCOpcode == -1) { 76 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext(); 77 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have " 78 "a target-specific version: " + Twine(MI->getOpcode())); 79 } 80 81 OutMI.setOpcode(MCOpcode); 82 83 for (const MachineOperand &MO : MI->explicit_operands()) { 84 MCOperand MCOp; 85 switch (MO.getType()) { 86 default: 87 llvm_unreachable("unknown operand type"); 88 case MachineOperand::MO_Immediate: 89 MCOp = MCOperand::createImm(MO.getImm()); 90 break; 91 case MachineOperand::MO_Register: 92 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST)); 93 break; 94 case MachineOperand::MO_MachineBasicBlock: 95 if (MO.getTargetFlags() != 0) { 96 MCOp = MCOperand::createExpr( 97 getLongBranchBlockExpr(*MI->getParent(), MO)); 98 } else { 99 MCOp = MCOperand::createExpr( 100 MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx)); 101 } 102 103 break; 104 case MachineOperand::MO_GlobalAddress: { 105 const GlobalValue *GV = MO.getGlobal(); 106 SmallString<128> SymbolName; 107 AP.getNameWithPrefix(SymbolName, GV); 108 MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName); 109 const MCExpr *SymExpr = 110 MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx); 111 const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr, 112 MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); 113 MCOp = MCOperand::createExpr(Expr); 114 break; 115 } 116 case MachineOperand::MO_ExternalSymbol: { 117 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName())); 118 Sym->setExternal(true); 119 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx); 120 MCOp = MCOperand::createExpr(Expr); 121 break; 122 } 123 case MachineOperand::MO_MCSymbol: 124 MCOp = MCOperand::createExpr( 125 MCSymbolRefExpr::create(MO.getMCSymbol(), Ctx)); 126 break; 127 } 128 OutMI.addOperand(MCOp); 129 } 130 } 131 132 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { 133 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>(); 134 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this); 135 136 StringRef Err; 137 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) { 138 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext(); 139 C.emitError("Illegal instruction detected: " + Err); 140 MI->dump(); 141 } 142 143 if (MI->isBundle()) { 144 const MachineBasicBlock *MBB = MI->getParent(); 145 MachineBasicBlock::const_instr_iterator I = ++MI->getIterator(); 146 while (I != MBB->instr_end() && I->isInsideBundle()) { 147 EmitInstruction(&*I); 148 ++I; 149 } 150 } else { 151 // We don't want SI_MASK_BRANCH/SI_RETURN encoded. They are placeholder 152 // terminator instructions and should only be printed as comments. 153 if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) { 154 if (isVerbose()) { 155 SmallVector<char, 16> BBStr; 156 raw_svector_ostream Str(BBStr); 157 158 const MachineBasicBlock *MBB = MI->getOperand(0).getMBB(); 159 const MCSymbolRefExpr *Expr 160 = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext); 161 Expr->print(Str, MAI); 162 OutStreamer->emitRawComment(" mask branch " + BBStr); 163 } 164 165 return; 166 } 167 168 if (MI->getOpcode() == AMDGPU::SI_RETURN) { 169 if (isVerbose()) 170 OutStreamer->emitRawComment(" return"); 171 return; 172 } 173 174 MCInst TmpInst; 175 MCInstLowering.lower(MI, TmpInst); 176 EmitToStreamer(*OutStreamer, TmpInst); 177 178 if (STI.dumpCode()) { 179 // Disassemble instruction/operands to text. 180 DisasmLines.resize(DisasmLines.size() + 1); 181 std::string &DisasmLine = DisasmLines.back(); 182 raw_string_ostream DisasmStream(DisasmLine); 183 184 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), 185 *STI.getInstrInfo(), 186 *STI.getRegisterInfo()); 187 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI); 188 189 // Disassemble instruction/operands to hex representation. 190 SmallVector<MCFixup, 4> Fixups; 191 SmallVector<char, 16> CodeBytes; 192 raw_svector_ostream CodeStream(CodeBytes); 193 194 auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer); 195 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter(); 196 InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups, 197 MF->getSubtarget<MCSubtargetInfo>()); 198 HexLines.resize(HexLines.size() + 1); 199 std::string &HexLine = HexLines.back(); 200 raw_string_ostream HexStream(HexLine); 201 202 for (size_t i = 0; i < CodeBytes.size(); i += 4) { 203 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i]; 204 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord); 205 } 206 207 DisasmStream.flush(); 208 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size()); 209 } 210 } 211 } 212