1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst. 12 // 13 //===----------------------------------------------------------------------===// 14 // 15 16 #include "AMDGPUMCInstLower.h" 17 #include "AMDGPUAsmPrinter.h" 18 #include "AMDGPUSubtarget.h" 19 #include "AMDGPUTargetMachine.h" 20 #include "InstPrinter/AMDGPUInstPrinter.h" 21 #include "SIInstrInfo.h" 22 #include "llvm/CodeGen/MachineBasicBlock.h" 23 #include "llvm/CodeGen/MachineInstr.h" 24 #include "llvm/IR/Constants.h" 25 #include "llvm/IR/Function.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/MC/MCCodeEmitter.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCExpr.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/MC/MCObjectStreamer.h" 32 #include "llvm/MC/MCStreamer.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/Format.h" 35 #include <algorithm> 36 37 using namespace llvm; 38 39 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st): 40 Ctx(ctx), ST(st) { } 41 42 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { 43 44 int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode()); 45 46 if (MCOpcode == -1) { 47 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext(); 48 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have " 49 "a target-specific version: " + Twine(MI->getOpcode())); 50 } 51 52 OutMI.setOpcode(MCOpcode); 53 54 for (const MachineOperand &MO : MI->explicit_operands()) { 55 MCOperand MCOp; 56 switch (MO.getType()) { 57 default: 58 llvm_unreachable("unknown operand type"); 59 case MachineOperand::MO_Immediate: 60 MCOp = MCOperand::createImm(MO.getImm()); 61 break; 62 case MachineOperand::MO_Register: 63 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST)); 64 break; 65 case MachineOperand::MO_MachineBasicBlock: 66 MCOp = MCOperand::createExpr(MCSymbolRefExpr::create( 67 MO.getMBB()->getSymbol(), Ctx)); 68 break; 69 case MachineOperand::MO_GlobalAddress: { 70 const GlobalValue *GV = MO.getGlobal(); 71 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(GV->getName())); 72 const MCExpr *SymExpr = MCSymbolRefExpr::create(Sym, Ctx); 73 const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr, 74 MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); 75 MCOp = MCOperand::createExpr(Expr); 76 break; 77 } 78 case MachineOperand::MO_ExternalSymbol: { 79 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName())); 80 Sym->setExternal(true); 81 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx); 82 MCOp = MCOperand::createExpr(Expr); 83 break; 84 } 85 } 86 OutMI.addOperand(MCOp); 87 } 88 } 89 90 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { 91 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>(); 92 AMDGPUMCInstLower MCInstLowering(OutContext, STI); 93 94 StringRef Err; 95 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) { 96 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext(); 97 C.emitError("Illegal instruction detected: " + Err); 98 MI->dump(); 99 } 100 101 if (MI->isBundle()) { 102 const MachineBasicBlock *MBB = MI->getParent(); 103 MachineBasicBlock::const_instr_iterator I = ++MI->getIterator(); 104 while (I != MBB->instr_end() && I->isInsideBundle()) { 105 EmitInstruction(&*I); 106 ++I; 107 } 108 } else { 109 // We don't want SI_MASK_BRANCH/SI_RETURN encoded. They are placeholder 110 // terminator instructions and should only be printed as comments. 111 if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) { 112 if (isVerbose()) { 113 SmallVector<char, 16> BBStr; 114 raw_svector_ostream Str(BBStr); 115 116 const MachineBasicBlock *MBB = MI->getOperand(0).getMBB(); 117 const MCSymbolRefExpr *Expr 118 = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext); 119 Expr->print(Str, MAI); 120 OutStreamer->emitRawComment(" mask branch " + BBStr); 121 } 122 123 return; 124 } 125 126 if (MI->getOpcode() == AMDGPU::SI_RETURN) { 127 if (isVerbose()) 128 OutStreamer->emitRawComment(" return"); 129 return; 130 } 131 132 MCInst TmpInst; 133 MCInstLowering.lower(MI, TmpInst); 134 EmitToStreamer(*OutStreamer, TmpInst); 135 136 if (STI.dumpCode()) { 137 // Disassemble instruction/operands to text. 138 DisasmLines.resize(DisasmLines.size() + 1); 139 std::string &DisasmLine = DisasmLines.back(); 140 raw_string_ostream DisasmStream(DisasmLine); 141 142 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), 143 *STI.getInstrInfo(), 144 *STI.getRegisterInfo()); 145 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI); 146 147 // Disassemble instruction/operands to hex representation. 148 SmallVector<MCFixup, 4> Fixups; 149 SmallVector<char, 16> CodeBytes; 150 raw_svector_ostream CodeStream(CodeBytes); 151 152 auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer); 153 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter(); 154 InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups, 155 MF->getSubtarget<MCSubtargetInfo>()); 156 HexLines.resize(HexLines.size() + 1); 157 std::string &HexLine = HexLines.back(); 158 raw_string_ostream HexStream(HexLine); 159 160 for (size_t i = 0; i < CodeBytes.size(); i += 4) { 161 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i]; 162 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord); 163 } 164 165 DisasmStream.flush(); 166 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size()); 167 } 168 } 169 } 170