1 //===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 /// \file 11 /// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst. 12 // 13 //===----------------------------------------------------------------------===// 14 // 15 16 #include "AMDGPUMCInstLower.h" 17 #include "AMDGPUAsmPrinter.h" 18 #include "AMDGPUSubtarget.h" 19 #include "AMDGPUTargetMachine.h" 20 #include "InstPrinter/AMDGPUInstPrinter.h" 21 #include "SIInstrInfo.h" 22 #include "llvm/CodeGen/MachineBasicBlock.h" 23 #include "llvm/CodeGen/MachineInstr.h" 24 #include "llvm/IR/Constants.h" 25 #include "llvm/IR/Function.h" 26 #include "llvm/IR/GlobalVariable.h" 27 #include "llvm/MC/MCCodeEmitter.h" 28 #include "llvm/MC/MCContext.h" 29 #include "llvm/MC/MCExpr.h" 30 #include "llvm/MC/MCInst.h" 31 #include "llvm/MC/MCObjectStreamer.h" 32 #include "llvm/MC/MCStreamer.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/Format.h" 35 #include <algorithm> 36 37 using namespace llvm; 38 39 #include "AMDGPUGenMCPseudoLowering.inc" 40 41 42 AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx, const AMDGPUSubtarget &st, 43 const AsmPrinter &ap): 44 Ctx(ctx), ST(st), AP(ap) { } 45 46 static MCSymbolRefExpr::VariantKind getVariantKind(unsigned MOFlags) { 47 switch (MOFlags) { 48 default: return MCSymbolRefExpr::VK_None; 49 case SIInstrInfo::MO_GOTPCREL: return MCSymbolRefExpr::VK_GOTPCREL; 50 } 51 } 52 53 const MCExpr *AMDGPUMCInstLower::getLongBranchBlockExpr( 54 const MachineBasicBlock &SrcBB, 55 const MachineOperand &MO) const { 56 const MCExpr *DestBBSym 57 = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx); 58 const MCExpr *SrcBBSym = MCSymbolRefExpr::create(SrcBB.getSymbol(), Ctx); 59 60 assert(SrcBB.front().getOpcode() == AMDGPU::S_GETPC_B64 && 61 ST.getInstrInfo()->get(AMDGPU::S_GETPC_B64).Size == 4); 62 63 // s_getpc_b64 returns the address of next instruction. 64 const MCConstantExpr *One = MCConstantExpr::create(4, Ctx); 65 SrcBBSym = MCBinaryExpr::createAdd(SrcBBSym, One, Ctx); 66 67 if (MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_FORWARD) 68 return MCBinaryExpr::createSub(DestBBSym, SrcBBSym, Ctx); 69 70 assert(MO.getTargetFlags() == AMDGPU::TF_LONG_BRANCH_BACKWARD); 71 return MCBinaryExpr::createSub(SrcBBSym, DestBBSym, Ctx); 72 } 73 74 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO, 75 MCOperand &MCOp) const { 76 switch (MO.getType()) { 77 default: 78 llvm_unreachable("unknown operand type"); 79 case MachineOperand::MO_Immediate: 80 MCOp = MCOperand::createImm(MO.getImm()); 81 return true; 82 case MachineOperand::MO_Register: 83 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST)); 84 return true; 85 case MachineOperand::MO_MachineBasicBlock: { 86 if (MO.getTargetFlags() != 0) { 87 MCOp = MCOperand::createExpr( 88 getLongBranchBlockExpr(*MO.getParent()->getParent(), MO)); 89 } else { 90 MCOp = MCOperand::createExpr( 91 MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), Ctx)); 92 } 93 94 return true; 95 } 96 case MachineOperand::MO_GlobalAddress: { 97 const GlobalValue *GV = MO.getGlobal(); 98 SmallString<128> SymbolName; 99 AP.getNameWithPrefix(SymbolName, GV); 100 MCSymbol *Sym = Ctx.getOrCreateSymbol(SymbolName); 101 const MCExpr *SymExpr = 102 MCSymbolRefExpr::create(Sym, getVariantKind(MO.getTargetFlags()),Ctx); 103 const MCExpr *Expr = MCBinaryExpr::createAdd(SymExpr, 104 MCConstantExpr::create(MO.getOffset(), Ctx), Ctx); 105 MCOp = MCOperand::createExpr(Expr); 106 return true; 107 } 108 case MachineOperand::MO_ExternalSymbol: { 109 MCSymbol *Sym = Ctx.getOrCreateSymbol(StringRef(MO.getSymbolName())); 110 Sym->setExternal(true); 111 const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(Sym, Ctx); 112 MCOp = MCOperand::createExpr(Expr); 113 return true; 114 } 115 } 116 } 117 118 void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const { 119 120 int MCOpcode = ST.getInstrInfo()->pseudoToMCOpcode(MI->getOpcode()); 121 122 if (MCOpcode == -1) { 123 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext(); 124 C.emitError("AMDGPUMCInstLower::lower - Pseudo instruction doesn't have " 125 "a target-specific version: " + Twine(MI->getOpcode())); 126 } 127 128 OutMI.setOpcode(MCOpcode); 129 130 for (const MachineOperand &MO : MI->explicit_operands()) { 131 MCOperand MCOp; 132 lowerOperand(MO, MCOp); 133 OutMI.addOperand(MCOp); 134 } 135 } 136 137 bool AMDGPUAsmPrinter::lowerOperand(const MachineOperand &MO, 138 MCOperand &MCOp) const { 139 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>(); 140 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this); 141 return MCInstLowering.lowerOperand(MO, MCOp); 142 } 143 144 void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { 145 if (emitPseudoExpansionLowering(*OutStreamer, MI)) 146 return; 147 148 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>(); 149 AMDGPUMCInstLower MCInstLowering(OutContext, STI, *this); 150 151 StringRef Err; 152 if (!STI.getInstrInfo()->verifyInstruction(*MI, Err)) { 153 LLVMContext &C = MI->getParent()->getParent()->getFunction()->getContext(); 154 C.emitError("Illegal instruction detected: " + Err); 155 MI->dump(); 156 } 157 158 if (MI->isBundle()) { 159 const MachineBasicBlock *MBB = MI->getParent(); 160 MachineBasicBlock::const_instr_iterator I = ++MI->getIterator(); 161 while (I != MBB->instr_end() && I->isInsideBundle()) { 162 EmitInstruction(&*I); 163 ++I; 164 } 165 } else { 166 // We don't want SI_MASK_BRANCH/SI_RETURN encoded. They are placeholder 167 // terminator instructions and should only be printed as comments. 168 if (MI->getOpcode() == AMDGPU::SI_MASK_BRANCH) { 169 if (isVerbose()) { 170 SmallVector<char, 16> BBStr; 171 raw_svector_ostream Str(BBStr); 172 173 const MachineBasicBlock *MBB = MI->getOperand(0).getMBB(); 174 const MCSymbolRefExpr *Expr 175 = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext); 176 Expr->print(Str, MAI); 177 OutStreamer->emitRawComment(" mask branch " + BBStr); 178 } 179 180 return; 181 } 182 183 if (MI->getOpcode() == AMDGPU::SI_RETURN) { 184 if (isVerbose()) 185 OutStreamer->emitRawComment(" return"); 186 return; 187 } 188 189 MCInst TmpInst; 190 MCInstLowering.lower(MI, TmpInst); 191 EmitToStreamer(*OutStreamer, TmpInst); 192 193 if (STI.dumpCode()) { 194 // Disassemble instruction/operands to text. 195 DisasmLines.resize(DisasmLines.size() + 1); 196 std::string &DisasmLine = DisasmLines.back(); 197 raw_string_ostream DisasmStream(DisasmLine); 198 199 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), 200 *STI.getInstrInfo(), 201 *STI.getRegisterInfo()); 202 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef(), STI); 203 204 // Disassemble instruction/operands to hex representation. 205 SmallVector<MCFixup, 4> Fixups; 206 SmallVector<char, 16> CodeBytes; 207 raw_svector_ostream CodeStream(CodeBytes); 208 209 auto &ObjStreamer = static_cast<MCObjectStreamer&>(*OutStreamer); 210 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter(); 211 InstEmitter.encodeInstruction(TmpInst, CodeStream, Fixups, 212 MF->getSubtarget<MCSubtargetInfo>()); 213 HexLines.resize(HexLines.size() + 1); 214 std::string &HexLine = HexLines.back(); 215 raw_string_ostream HexStream(HexLine); 216 217 for (size_t i = 0; i < CodeBytes.size(); i += 4) { 218 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i]; 219 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord); 220 } 221 222 DisasmStream.flush(); 223 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size()); 224 } 225 } 226 } 227