1 //===- AArch64MachineScheduler.cpp - MI Scheduler for AArch64 -------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "AArch64MachineScheduler.h" 10 #include "MCTargetDesc/AArch64MCTargetDesc.h" 11 12 using namespace llvm; 13 14 bool AArch64PostRASchedStrategy::tryCandidate(SchedCandidate &Cand, 15 SchedCandidate &TryCand) { 16 bool OriginalResult = PostGenericScheduler::tryCandidate(Cand, TryCand); 17 18 if (Cand.isValid()) { 19 MachineInstr *Instr0 = TryCand.SU->getInstr(); 20 MachineInstr *Instr1 = Cand.SU->getInstr(); 21 // When dealing with two STPqi's. 22 if (Instr0 && Instr1 && Instr0->getOpcode() == Instr1->getOpcode () && 23 Instr0->getOpcode() == AArch64::STPQi) 24 { 25 MachineOperand &Base0 = Instr0->getOperand(2); 26 MachineOperand &Base1 = Instr1->getOperand(2); 27 int64_t Off0 = Instr0->getOperand(3).getImm(); 28 int64_t Off1 = Instr1->getOperand(3).getImm(); 29 // With the same base address and non-overlapping writes. 30 if (Base0.isIdenticalTo(Base1) && llabs (Off0 - Off1) >= 2) { 31 TryCand.Reason = NodeOrder; 32 // Order them by ascending offsets. 33 return Off0 < Off1; 34 } 35 } 36 } 37 38 return OriginalResult; 39 } 40