1 //===- ELFObjectFile.cpp - ELF object file implementation -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // Part of the ELFObjectFile class implementation. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/Object/ELFObjectFile.h" 14 #include "llvm/BinaryFormat/ELF.h" 15 #include "llvm/MC/MCInstrAnalysis.h" 16 #include "llvm/MC/TargetRegistry.h" 17 #include "llvm/Object/ELF.h" 18 #include "llvm/Object/ELFTypes.h" 19 #include "llvm/Object/Error.h" 20 #include "llvm/Support/ARMAttributeParser.h" 21 #include "llvm/Support/ARMBuildAttributes.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/HexagonAttributeParser.h" 24 #include "llvm/Support/MathExtras.h" 25 #include "llvm/Support/RISCVAttributeParser.h" 26 #include "llvm/Support/RISCVAttributes.h" 27 #include "llvm/TargetParser/RISCVISAInfo.h" 28 #include "llvm/TargetParser/SubtargetFeature.h" 29 #include "llvm/TargetParser/Triple.h" 30 #include <algorithm> 31 #include <cstddef> 32 #include <cstdint> 33 #include <memory> 34 #include <optional> 35 #include <string> 36 #include <utility> 37 38 using namespace llvm; 39 using namespace object; 40 41 const EnumEntry<unsigned> llvm::object::ElfSymbolTypes[NumElfSymbolTypes] = { 42 {"None", "NOTYPE", ELF::STT_NOTYPE}, 43 {"Object", "OBJECT", ELF::STT_OBJECT}, 44 {"Function", "FUNC", ELF::STT_FUNC}, 45 {"Section", "SECTION", ELF::STT_SECTION}, 46 {"File", "FILE", ELF::STT_FILE}, 47 {"Common", "COMMON", ELF::STT_COMMON}, 48 {"TLS", "TLS", ELF::STT_TLS}, 49 {"Unknown", "<unknown>: 7", 7}, 50 {"Unknown", "<unknown>: 8", 8}, 51 {"Unknown", "<unknown>: 9", 9}, 52 {"GNU_IFunc", "IFUNC", ELF::STT_GNU_IFUNC}, 53 {"OS Specific", "<OS specific>: 11", 11}, 54 {"OS Specific", "<OS specific>: 12", 12}, 55 {"Proc Specific", "<processor specific>: 13", 13}, 56 {"Proc Specific", "<processor specific>: 14", 14}, 57 {"Proc Specific", "<processor specific>: 15", 15} 58 }; 59 60 ELFObjectFileBase::ELFObjectFileBase(unsigned int Type, MemoryBufferRef Source) 61 : ObjectFile(Type, Source) {} 62 63 template <class ELFT> 64 static Expected<std::unique_ptr<ELFObjectFile<ELFT>>> 65 createPtr(MemoryBufferRef Object, bool InitContent) { 66 auto Ret = ELFObjectFile<ELFT>::create(Object, InitContent); 67 if (Error E = Ret.takeError()) 68 return std::move(E); 69 return std::make_unique<ELFObjectFile<ELFT>>(std::move(*Ret)); 70 } 71 72 Expected<std::unique_ptr<ObjectFile>> 73 ObjectFile::createELFObjectFile(MemoryBufferRef Obj, bool InitContent) { 74 std::pair<unsigned char, unsigned char> Ident = 75 getElfArchType(Obj.getBuffer()); 76 std::size_t MaxAlignment = 77 1ULL << llvm::countr_zero( 78 reinterpret_cast<uintptr_t>(Obj.getBufferStart())); 79 80 if (MaxAlignment < 2) 81 return createError("Insufficient alignment"); 82 83 if (Ident.first == ELF::ELFCLASS32) { 84 if (Ident.second == ELF::ELFDATA2LSB) 85 return createPtr<ELF32LE>(Obj, InitContent); 86 else if (Ident.second == ELF::ELFDATA2MSB) 87 return createPtr<ELF32BE>(Obj, InitContent); 88 else 89 return createError("Invalid ELF data"); 90 } else if (Ident.first == ELF::ELFCLASS64) { 91 if (Ident.second == ELF::ELFDATA2LSB) 92 return createPtr<ELF64LE>(Obj, InitContent); 93 else if (Ident.second == ELF::ELFDATA2MSB) 94 return createPtr<ELF64BE>(Obj, InitContent); 95 else 96 return createError("Invalid ELF data"); 97 } 98 return createError("Invalid ELF class"); 99 } 100 101 SubtargetFeatures ELFObjectFileBase::getMIPSFeatures() const { 102 SubtargetFeatures Features; 103 unsigned PlatformFlags = getPlatformFlags(); 104 105 switch (PlatformFlags & ELF::EF_MIPS_ARCH) { 106 case ELF::EF_MIPS_ARCH_1: 107 break; 108 case ELF::EF_MIPS_ARCH_2: 109 Features.AddFeature("mips2"); 110 break; 111 case ELF::EF_MIPS_ARCH_3: 112 Features.AddFeature("mips3"); 113 break; 114 case ELF::EF_MIPS_ARCH_4: 115 Features.AddFeature("mips4"); 116 break; 117 case ELF::EF_MIPS_ARCH_5: 118 Features.AddFeature("mips5"); 119 break; 120 case ELF::EF_MIPS_ARCH_32: 121 Features.AddFeature("mips32"); 122 break; 123 case ELF::EF_MIPS_ARCH_64: 124 Features.AddFeature("mips64"); 125 break; 126 case ELF::EF_MIPS_ARCH_32R2: 127 Features.AddFeature("mips32r2"); 128 break; 129 case ELF::EF_MIPS_ARCH_64R2: 130 Features.AddFeature("mips64r2"); 131 break; 132 case ELF::EF_MIPS_ARCH_32R6: 133 Features.AddFeature("mips32r6"); 134 break; 135 case ELF::EF_MIPS_ARCH_64R6: 136 Features.AddFeature("mips64r6"); 137 break; 138 default: 139 llvm_unreachable("Unknown EF_MIPS_ARCH value"); 140 } 141 142 switch (PlatformFlags & ELF::EF_MIPS_MACH) { 143 case ELF::EF_MIPS_MACH_NONE: 144 // No feature associated with this value. 145 break; 146 case ELF::EF_MIPS_MACH_OCTEON: 147 Features.AddFeature("cnmips"); 148 break; 149 default: 150 llvm_unreachable("Unknown EF_MIPS_ARCH value"); 151 } 152 153 if (PlatformFlags & ELF::EF_MIPS_ARCH_ASE_M16) 154 Features.AddFeature("mips16"); 155 if (PlatformFlags & ELF::EF_MIPS_MICROMIPS) 156 Features.AddFeature("micromips"); 157 158 return Features; 159 } 160 161 SubtargetFeatures ELFObjectFileBase::getARMFeatures() const { 162 SubtargetFeatures Features; 163 ARMAttributeParser Attributes; 164 if (Error E = getBuildAttributes(Attributes)) { 165 consumeError(std::move(E)); 166 return SubtargetFeatures(); 167 } 168 169 // both ARMv7-M and R have to support thumb hardware div 170 bool isV7 = false; 171 std::optional<unsigned> Attr = 172 Attributes.getAttributeValue(ARMBuildAttrs::CPU_arch); 173 if (Attr) 174 isV7 = *Attr == ARMBuildAttrs::v7; 175 176 Attr = Attributes.getAttributeValue(ARMBuildAttrs::CPU_arch_profile); 177 if (Attr) { 178 switch (*Attr) { 179 case ARMBuildAttrs::ApplicationProfile: 180 Features.AddFeature("aclass"); 181 break; 182 case ARMBuildAttrs::RealTimeProfile: 183 Features.AddFeature("rclass"); 184 if (isV7) 185 Features.AddFeature("hwdiv"); 186 break; 187 case ARMBuildAttrs::MicroControllerProfile: 188 Features.AddFeature("mclass"); 189 if (isV7) 190 Features.AddFeature("hwdiv"); 191 break; 192 } 193 } 194 195 Attr = Attributes.getAttributeValue(ARMBuildAttrs::THUMB_ISA_use); 196 if (Attr) { 197 switch (*Attr) { 198 default: 199 break; 200 case ARMBuildAttrs::Not_Allowed: 201 Features.AddFeature("thumb", false); 202 Features.AddFeature("thumb2", false); 203 break; 204 case ARMBuildAttrs::AllowThumb32: 205 Features.AddFeature("thumb2"); 206 break; 207 } 208 } 209 210 Attr = Attributes.getAttributeValue(ARMBuildAttrs::FP_arch); 211 if (Attr) { 212 switch (*Attr) { 213 default: 214 break; 215 case ARMBuildAttrs::Not_Allowed: 216 Features.AddFeature("vfp2sp", false); 217 Features.AddFeature("vfp3d16sp", false); 218 Features.AddFeature("vfp4d16sp", false); 219 break; 220 case ARMBuildAttrs::AllowFPv2: 221 Features.AddFeature("vfp2"); 222 break; 223 case ARMBuildAttrs::AllowFPv3A: 224 case ARMBuildAttrs::AllowFPv3B: 225 Features.AddFeature("vfp3"); 226 break; 227 case ARMBuildAttrs::AllowFPv4A: 228 case ARMBuildAttrs::AllowFPv4B: 229 Features.AddFeature("vfp4"); 230 break; 231 } 232 } 233 234 Attr = Attributes.getAttributeValue(ARMBuildAttrs::Advanced_SIMD_arch); 235 if (Attr) { 236 switch (*Attr) { 237 default: 238 break; 239 case ARMBuildAttrs::Not_Allowed: 240 Features.AddFeature("neon", false); 241 Features.AddFeature("fp16", false); 242 break; 243 case ARMBuildAttrs::AllowNeon: 244 Features.AddFeature("neon"); 245 break; 246 case ARMBuildAttrs::AllowNeon2: 247 Features.AddFeature("neon"); 248 Features.AddFeature("fp16"); 249 break; 250 } 251 } 252 253 Attr = Attributes.getAttributeValue(ARMBuildAttrs::MVE_arch); 254 if (Attr) { 255 switch (*Attr) { 256 default: 257 break; 258 case ARMBuildAttrs::Not_Allowed: 259 Features.AddFeature("mve", false); 260 Features.AddFeature("mve.fp", false); 261 break; 262 case ARMBuildAttrs::AllowMVEInteger: 263 Features.AddFeature("mve.fp", false); 264 Features.AddFeature("mve"); 265 break; 266 case ARMBuildAttrs::AllowMVEIntegerAndFloat: 267 Features.AddFeature("mve.fp"); 268 break; 269 } 270 } 271 272 Attr = Attributes.getAttributeValue(ARMBuildAttrs::DIV_use); 273 if (Attr) { 274 switch (*Attr) { 275 default: 276 break; 277 case ARMBuildAttrs::DisallowDIV: 278 Features.AddFeature("hwdiv", false); 279 Features.AddFeature("hwdiv-arm", false); 280 break; 281 case ARMBuildAttrs::AllowDIVExt: 282 Features.AddFeature("hwdiv"); 283 Features.AddFeature("hwdiv-arm"); 284 break; 285 } 286 } 287 288 return Features; 289 } 290 291 static std::optional<std::string> hexagonAttrToFeatureString(unsigned Attr) { 292 switch (Attr) { 293 case 5: 294 return "v5"; 295 case 55: 296 return "v55"; 297 case 60: 298 return "v60"; 299 case 62: 300 return "v62"; 301 case 65: 302 return "v65"; 303 case 67: 304 return "v67"; 305 case 68: 306 return "v68"; 307 case 69: 308 return "v69"; 309 case 71: 310 return "v71"; 311 case 73: 312 return "v73"; 313 default: 314 return {}; 315 } 316 } 317 318 SubtargetFeatures ELFObjectFileBase::getHexagonFeatures() const { 319 SubtargetFeatures Features; 320 HexagonAttributeParser Parser; 321 if (Error E = getBuildAttributes(Parser)) { 322 // Return no attributes if none can be read. 323 // This behavior is important for backwards compatibility. 324 consumeError(std::move(E)); 325 return Features; 326 } 327 std::optional<unsigned> Attr; 328 329 if ((Attr = Parser.getAttributeValue(HexagonAttrs::ARCH))) { 330 if (std::optional<std::string> FeatureString = 331 hexagonAttrToFeatureString(*Attr)) 332 Features.AddFeature(*FeatureString); 333 } 334 335 if ((Attr = Parser.getAttributeValue(HexagonAttrs::HVXARCH))) { 336 std::optional<std::string> FeatureString = 337 hexagonAttrToFeatureString(*Attr); 338 // There is no corresponding hvx arch for v5 and v55. 339 if (FeatureString && *Attr >= 60) 340 Features.AddFeature("hvx" + *FeatureString); 341 } 342 343 if ((Attr = Parser.getAttributeValue(HexagonAttrs::HVXIEEEFP))) 344 if (*Attr) 345 Features.AddFeature("hvx-ieee-fp"); 346 347 if ((Attr = Parser.getAttributeValue(HexagonAttrs::HVXQFLOAT))) 348 if (*Attr) 349 Features.AddFeature("hvx-qfloat"); 350 351 if ((Attr = Parser.getAttributeValue(HexagonAttrs::ZREG))) 352 if (*Attr) 353 Features.AddFeature("zreg"); 354 355 if ((Attr = Parser.getAttributeValue(HexagonAttrs::AUDIO))) 356 if (*Attr) 357 Features.AddFeature("audio"); 358 359 if ((Attr = Parser.getAttributeValue(HexagonAttrs::CABAC))) 360 if (*Attr) 361 Features.AddFeature("cabac"); 362 363 return Features; 364 } 365 366 Expected<SubtargetFeatures> ELFObjectFileBase::getRISCVFeatures() const { 367 SubtargetFeatures Features; 368 unsigned PlatformFlags = getPlatformFlags(); 369 370 if (PlatformFlags & ELF::EF_RISCV_RVC) { 371 Features.AddFeature("zca"); 372 } 373 374 RISCVAttributeParser Attributes; 375 if (Error E = getBuildAttributes(Attributes)) { 376 return std::move(E); 377 } 378 379 std::optional<StringRef> Attr = 380 Attributes.getAttributeString(RISCVAttrs::ARCH); 381 if (Attr) { 382 auto ParseResult = RISCVISAInfo::parseNormalizedArchString(*Attr); 383 if (!ParseResult) 384 return ParseResult.takeError(); 385 auto &ISAInfo = *ParseResult; 386 387 if (ISAInfo->getXLen() == 32) 388 Features.AddFeature("64bit", false); 389 else if (ISAInfo->getXLen() == 64) 390 Features.AddFeature("64bit"); 391 else 392 llvm_unreachable("XLEN should be 32 or 64."); 393 394 Features.addFeaturesVector(ISAInfo->toFeatures()); 395 } 396 397 return Features; 398 } 399 400 SubtargetFeatures ELFObjectFileBase::getLoongArchFeatures() const { 401 SubtargetFeatures Features; 402 403 switch (getPlatformFlags() & ELF::EF_LOONGARCH_ABI_MODIFIER_MASK) { 404 case ELF::EF_LOONGARCH_ABI_SOFT_FLOAT: 405 break; 406 case ELF::EF_LOONGARCH_ABI_DOUBLE_FLOAT: 407 Features.AddFeature("d"); 408 // D implies F according to LoongArch ISA spec. 409 [[fallthrough]]; 410 case ELF::EF_LOONGARCH_ABI_SINGLE_FLOAT: 411 Features.AddFeature("f"); 412 break; 413 } 414 415 return Features; 416 } 417 418 Expected<SubtargetFeatures> ELFObjectFileBase::getFeatures() const { 419 switch (getEMachine()) { 420 case ELF::EM_MIPS: 421 return getMIPSFeatures(); 422 case ELF::EM_ARM: 423 return getARMFeatures(); 424 case ELF::EM_RISCV: 425 return getRISCVFeatures(); 426 case ELF::EM_LOONGARCH: 427 return getLoongArchFeatures(); 428 case ELF::EM_HEXAGON: 429 return getHexagonFeatures(); 430 default: 431 return SubtargetFeatures(); 432 } 433 } 434 435 std::optional<StringRef> ELFObjectFileBase::tryGetCPUName() const { 436 switch (getEMachine()) { 437 case ELF::EM_AMDGPU: 438 return getAMDGPUCPUName(); 439 case ELF::EM_CUDA: 440 return getNVPTXCPUName(); 441 case ELF::EM_PPC: 442 case ELF::EM_PPC64: 443 return StringRef("future"); 444 default: 445 return std::nullopt; 446 } 447 } 448 449 StringRef ELFObjectFileBase::getAMDGPUCPUName() const { 450 assert(getEMachine() == ELF::EM_AMDGPU); 451 unsigned CPU = getPlatformFlags() & ELF::EF_AMDGPU_MACH; 452 453 switch (CPU) { 454 // Radeon HD 2000/3000 Series (R600). 455 case ELF::EF_AMDGPU_MACH_R600_R600: 456 return "r600"; 457 case ELF::EF_AMDGPU_MACH_R600_R630: 458 return "r630"; 459 case ELF::EF_AMDGPU_MACH_R600_RS880: 460 return "rs880"; 461 case ELF::EF_AMDGPU_MACH_R600_RV670: 462 return "rv670"; 463 464 // Radeon HD 4000 Series (R700). 465 case ELF::EF_AMDGPU_MACH_R600_RV710: 466 return "rv710"; 467 case ELF::EF_AMDGPU_MACH_R600_RV730: 468 return "rv730"; 469 case ELF::EF_AMDGPU_MACH_R600_RV770: 470 return "rv770"; 471 472 // Radeon HD 5000 Series (Evergreen). 473 case ELF::EF_AMDGPU_MACH_R600_CEDAR: 474 return "cedar"; 475 case ELF::EF_AMDGPU_MACH_R600_CYPRESS: 476 return "cypress"; 477 case ELF::EF_AMDGPU_MACH_R600_JUNIPER: 478 return "juniper"; 479 case ELF::EF_AMDGPU_MACH_R600_REDWOOD: 480 return "redwood"; 481 case ELF::EF_AMDGPU_MACH_R600_SUMO: 482 return "sumo"; 483 484 // Radeon HD 6000 Series (Northern Islands). 485 case ELF::EF_AMDGPU_MACH_R600_BARTS: 486 return "barts"; 487 case ELF::EF_AMDGPU_MACH_R600_CAICOS: 488 return "caicos"; 489 case ELF::EF_AMDGPU_MACH_R600_CAYMAN: 490 return "cayman"; 491 case ELF::EF_AMDGPU_MACH_R600_TURKS: 492 return "turks"; 493 494 // AMDGCN GFX6. 495 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX600: 496 return "gfx600"; 497 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX601: 498 return "gfx601"; 499 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX602: 500 return "gfx602"; 501 502 // AMDGCN GFX7. 503 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX700: 504 return "gfx700"; 505 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX701: 506 return "gfx701"; 507 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX702: 508 return "gfx702"; 509 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX703: 510 return "gfx703"; 511 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX704: 512 return "gfx704"; 513 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX705: 514 return "gfx705"; 515 516 // AMDGCN GFX8. 517 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX801: 518 return "gfx801"; 519 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX802: 520 return "gfx802"; 521 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX803: 522 return "gfx803"; 523 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX805: 524 return "gfx805"; 525 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX810: 526 return "gfx810"; 527 528 // AMDGCN GFX9. 529 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX900: 530 return "gfx900"; 531 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX902: 532 return "gfx902"; 533 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX904: 534 return "gfx904"; 535 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX906: 536 return "gfx906"; 537 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX908: 538 return "gfx908"; 539 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX909: 540 return "gfx909"; 541 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90A: 542 return "gfx90a"; 543 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C: 544 return "gfx90c"; 545 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX940: 546 return "gfx940"; 547 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX941: 548 return "gfx941"; 549 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX942: 550 return "gfx942"; 551 552 // AMDGCN GFX10. 553 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1010: 554 return "gfx1010"; 555 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1011: 556 return "gfx1011"; 557 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1012: 558 return "gfx1012"; 559 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1013: 560 return "gfx1013"; 561 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1030: 562 return "gfx1030"; 563 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1031: 564 return "gfx1031"; 565 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1032: 566 return "gfx1032"; 567 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1033: 568 return "gfx1033"; 569 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1034: 570 return "gfx1034"; 571 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1035: 572 return "gfx1035"; 573 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1036: 574 return "gfx1036"; 575 576 // AMDGCN GFX11. 577 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1100: 578 return "gfx1100"; 579 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1101: 580 return "gfx1101"; 581 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1102: 582 return "gfx1102"; 583 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1103: 584 return "gfx1103"; 585 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1150: 586 return "gfx1150"; 587 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1151: 588 return "gfx1151"; 589 590 // AMDGCN GFX12. 591 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1200: 592 return "gfx1200"; 593 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX1201: 594 return "gfx1201"; 595 596 // Generic AMDGCN targets 597 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC: 598 return "gfx9-generic"; 599 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC: 600 return "gfx10-1-generic"; 601 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC: 602 return "gfx10-3-generic"; 603 case ELF::EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC: 604 return "gfx11-generic"; 605 default: 606 llvm_unreachable("Unknown EF_AMDGPU_MACH value"); 607 } 608 } 609 610 StringRef ELFObjectFileBase::getNVPTXCPUName() const { 611 assert(getEMachine() == ELF::EM_CUDA); 612 unsigned SM = getPlatformFlags() & ELF::EF_CUDA_SM; 613 614 switch (SM) { 615 // Fermi architecture. 616 case ELF::EF_CUDA_SM20: 617 return "sm_20"; 618 case ELF::EF_CUDA_SM21: 619 return "sm_21"; 620 621 // Kepler architecture. 622 case ELF::EF_CUDA_SM30: 623 return "sm_30"; 624 case ELF::EF_CUDA_SM32: 625 return "sm_32"; 626 case ELF::EF_CUDA_SM35: 627 return "sm_35"; 628 case ELF::EF_CUDA_SM37: 629 return "sm_37"; 630 631 // Maxwell architecture. 632 case ELF::EF_CUDA_SM50: 633 return "sm_50"; 634 case ELF::EF_CUDA_SM52: 635 return "sm_52"; 636 case ELF::EF_CUDA_SM53: 637 return "sm_53"; 638 639 // Pascal architecture. 640 case ELF::EF_CUDA_SM60: 641 return "sm_60"; 642 case ELF::EF_CUDA_SM61: 643 return "sm_61"; 644 case ELF::EF_CUDA_SM62: 645 return "sm_62"; 646 647 // Volta architecture. 648 case ELF::EF_CUDA_SM70: 649 return "sm_70"; 650 case ELF::EF_CUDA_SM72: 651 return "sm_72"; 652 653 // Turing architecture. 654 case ELF::EF_CUDA_SM75: 655 return "sm_75"; 656 657 // Ampere architecture. 658 case ELF::EF_CUDA_SM80: 659 return "sm_80"; 660 case ELF::EF_CUDA_SM86: 661 return "sm_86"; 662 case ELF::EF_CUDA_SM87: 663 return "sm_87"; 664 665 // Ada architecture. 666 case ELF::EF_CUDA_SM89: 667 return "sm_89"; 668 669 // Hopper architecture. 670 case ELF::EF_CUDA_SM90: 671 return getPlatformFlags() & ELF::EF_CUDA_ACCELERATORS ? "sm_90a" : "sm_90"; 672 default: 673 llvm_unreachable("Unknown EF_CUDA_SM value"); 674 } 675 } 676 677 // FIXME Encode from a tablegen description or target parser. 678 void ELFObjectFileBase::setARMSubArch(Triple &TheTriple) const { 679 if (TheTriple.getSubArch() != Triple::NoSubArch) 680 return; 681 682 ARMAttributeParser Attributes; 683 if (Error E = getBuildAttributes(Attributes)) { 684 // TODO Propagate Error. 685 consumeError(std::move(E)); 686 return; 687 } 688 689 std::string Triple; 690 // Default to ARM, but use the triple if it's been set. 691 if (TheTriple.isThumb()) 692 Triple = "thumb"; 693 else 694 Triple = "arm"; 695 696 std::optional<unsigned> Attr = 697 Attributes.getAttributeValue(ARMBuildAttrs::CPU_arch); 698 if (Attr) { 699 switch (*Attr) { 700 case ARMBuildAttrs::v4: 701 Triple += "v4"; 702 break; 703 case ARMBuildAttrs::v4T: 704 Triple += "v4t"; 705 break; 706 case ARMBuildAttrs::v5T: 707 Triple += "v5t"; 708 break; 709 case ARMBuildAttrs::v5TE: 710 Triple += "v5te"; 711 break; 712 case ARMBuildAttrs::v5TEJ: 713 Triple += "v5tej"; 714 break; 715 case ARMBuildAttrs::v6: 716 Triple += "v6"; 717 break; 718 case ARMBuildAttrs::v6KZ: 719 Triple += "v6kz"; 720 break; 721 case ARMBuildAttrs::v6T2: 722 Triple += "v6t2"; 723 break; 724 case ARMBuildAttrs::v6K: 725 Triple += "v6k"; 726 break; 727 case ARMBuildAttrs::v7: { 728 std::optional<unsigned> ArchProfileAttr = 729 Attributes.getAttributeValue(ARMBuildAttrs::CPU_arch_profile); 730 if (ArchProfileAttr && 731 *ArchProfileAttr == ARMBuildAttrs::MicroControllerProfile) 732 Triple += "v7m"; 733 else 734 Triple += "v7"; 735 break; 736 } 737 case ARMBuildAttrs::v6_M: 738 Triple += "v6m"; 739 break; 740 case ARMBuildAttrs::v6S_M: 741 Triple += "v6sm"; 742 break; 743 case ARMBuildAttrs::v7E_M: 744 Triple += "v7em"; 745 break; 746 case ARMBuildAttrs::v8_A: 747 Triple += "v8a"; 748 break; 749 case ARMBuildAttrs::v8_R: 750 Triple += "v8r"; 751 break; 752 case ARMBuildAttrs::v8_M_Base: 753 Triple += "v8m.base"; 754 break; 755 case ARMBuildAttrs::v8_M_Main: 756 Triple += "v8m.main"; 757 break; 758 case ARMBuildAttrs::v8_1_M_Main: 759 Triple += "v8.1m.main"; 760 break; 761 case ARMBuildAttrs::v9_A: 762 Triple += "v9a"; 763 break; 764 } 765 } 766 if (!isLittleEndian()) 767 Triple += "eb"; 768 769 TheTriple.setArchName(Triple); 770 } 771 772 std::vector<ELFPltEntry> ELFObjectFileBase::getPltEntries() const { 773 std::string Err; 774 const auto Triple = makeTriple(); 775 const auto *T = TargetRegistry::lookupTarget(Triple.str(), Err); 776 if (!T) 777 return {}; 778 uint32_t JumpSlotReloc = 0, GlobDatReloc = 0; 779 switch (Triple.getArch()) { 780 case Triple::x86: 781 JumpSlotReloc = ELF::R_386_JUMP_SLOT; 782 GlobDatReloc = ELF::R_386_GLOB_DAT; 783 break; 784 case Triple::x86_64: 785 JumpSlotReloc = ELF::R_X86_64_JUMP_SLOT; 786 GlobDatReloc = ELF::R_X86_64_GLOB_DAT; 787 break; 788 case Triple::aarch64: 789 case Triple::aarch64_be: 790 JumpSlotReloc = ELF::R_AARCH64_JUMP_SLOT; 791 break; 792 default: 793 return {}; 794 } 795 std::unique_ptr<const MCInstrInfo> MII(T->createMCInstrInfo()); 796 std::unique_ptr<const MCInstrAnalysis> MIA( 797 T->createMCInstrAnalysis(MII.get())); 798 if (!MIA) 799 return {}; 800 std::vector<std::pair<uint64_t, uint64_t>> PltEntries; 801 std::optional<SectionRef> RelaPlt, RelaDyn; 802 uint64_t GotBaseVA = 0; 803 for (const SectionRef &Section : sections()) { 804 Expected<StringRef> NameOrErr = Section.getName(); 805 if (!NameOrErr) { 806 consumeError(NameOrErr.takeError()); 807 continue; 808 } 809 StringRef Name = *NameOrErr; 810 811 if (Name == ".rela.plt" || Name == ".rel.plt") { 812 RelaPlt = Section; 813 } else if (Name == ".rela.dyn" || Name == ".rel.dyn") { 814 RelaDyn = Section; 815 } else if (Name == ".got.plt") { 816 GotBaseVA = Section.getAddress(); 817 } else if (Name == ".plt" || Name == ".plt.got") { 818 Expected<StringRef> PltContents = Section.getContents(); 819 if (!PltContents) { 820 consumeError(PltContents.takeError()); 821 return {}; 822 } 823 llvm::append_range( 824 PltEntries, 825 MIA->findPltEntries(Section.getAddress(), 826 arrayRefFromStringRef(*PltContents), Triple)); 827 } 828 } 829 830 // Build a map from GOT entry virtual address to PLT entry virtual address. 831 DenseMap<uint64_t, uint64_t> GotToPlt; 832 for (auto [Plt, GotPlt] : PltEntries) { 833 uint64_t GotPltEntry = GotPlt; 834 // An x86-32 PIC PLT uses jmp DWORD PTR [ebx-offset]. Add 835 // _GLOBAL_OFFSET_TABLE_ (EBX) to get the .got.plt (or .got) entry address. 836 // See X86MCTargetDesc.cpp:findPltEntries for the 1 << 32 bit. 837 if (GotPltEntry & (uint64_t(1) << 32) && getEMachine() == ELF::EM_386) 838 GotPltEntry = static_cast<int32_t>(GotPltEntry) + GotBaseVA; 839 GotToPlt.insert(std::make_pair(GotPltEntry, Plt)); 840 } 841 842 // Find the relocations in the dynamic relocation table that point to 843 // locations in the GOT for which we know the corresponding PLT entry. 844 std::vector<ELFPltEntry> Result; 845 auto handleRels = [&](iterator_range<relocation_iterator> Rels, 846 uint32_t RelType, StringRef PltSec) { 847 for (const auto &R : Rels) { 848 if (R.getType() != RelType) 849 continue; 850 auto PltEntryIter = GotToPlt.find(R.getOffset()); 851 if (PltEntryIter != GotToPlt.end()) { 852 symbol_iterator Sym = R.getSymbol(); 853 if (Sym == symbol_end()) 854 Result.push_back( 855 ELFPltEntry{PltSec, std::nullopt, PltEntryIter->second}); 856 else 857 Result.push_back(ELFPltEntry{PltSec, Sym->getRawDataRefImpl(), 858 PltEntryIter->second}); 859 } 860 } 861 }; 862 863 if (RelaPlt) 864 handleRels(RelaPlt->relocations(), JumpSlotReloc, ".plt"); 865 866 // If a symbol needing a PLT entry also needs a GLOB_DAT relocation, GNU ld's 867 // x86 port places the PLT entry in the .plt.got section. 868 if (RelaDyn) 869 handleRels(RelaDyn->relocations(), GlobDatReloc, ".plt.got"); 870 871 return Result; 872 } 873 874 template <class ELFT> 875 Expected<std::vector<BBAddrMap>> static readBBAddrMapImpl( 876 const ELFFile<ELFT> &EF, std::optional<unsigned> TextSectionIndex, 877 std::vector<PGOAnalysisMap> *PGOAnalyses) { 878 using Elf_Shdr = typename ELFT::Shdr; 879 bool IsRelocatable = EF.getHeader().e_type == ELF::ET_REL; 880 std::vector<BBAddrMap> BBAddrMaps; 881 if (PGOAnalyses) 882 PGOAnalyses->clear(); 883 884 const auto &Sections = cantFail(EF.sections()); 885 auto IsMatch = [&](const Elf_Shdr &Sec) -> Expected<bool> { 886 if (Sec.sh_type != ELF::SHT_LLVM_BB_ADDR_MAP && 887 Sec.sh_type != ELF::SHT_LLVM_BB_ADDR_MAP_V0) 888 return false; 889 if (!TextSectionIndex) 890 return true; 891 Expected<const Elf_Shdr *> TextSecOrErr = EF.getSection(Sec.sh_link); 892 if (!TextSecOrErr) 893 return createError("unable to get the linked-to section for " + 894 describe(EF, Sec) + ": " + 895 toString(TextSecOrErr.takeError())); 896 assert(*TextSecOrErr >= Sections.begin() && 897 "Text section pointer outside of bounds"); 898 if (*TextSectionIndex != 899 (unsigned)std::distance(Sections.begin(), *TextSecOrErr)) 900 return false; 901 return true; 902 }; 903 904 Expected<MapVector<const Elf_Shdr *, const Elf_Shdr *>> SectionRelocMapOrErr = 905 EF.getSectionAndRelocations(IsMatch); 906 if (!SectionRelocMapOrErr) 907 return SectionRelocMapOrErr.takeError(); 908 909 for (auto const &[Sec, RelocSec] : *SectionRelocMapOrErr) { 910 if (IsRelocatable && !RelocSec) 911 return createError("unable to get relocation section for " + 912 describe(EF, *Sec)); 913 Expected<std::vector<BBAddrMap>> BBAddrMapOrErr = 914 EF.decodeBBAddrMap(*Sec, RelocSec, PGOAnalyses); 915 if (!BBAddrMapOrErr) { 916 if (PGOAnalyses) 917 PGOAnalyses->clear(); 918 return createError("unable to read " + describe(EF, *Sec) + ": " + 919 toString(BBAddrMapOrErr.takeError())); 920 } 921 std::move(BBAddrMapOrErr->begin(), BBAddrMapOrErr->end(), 922 std::back_inserter(BBAddrMaps)); 923 } 924 if (PGOAnalyses) 925 assert(PGOAnalyses->size() == BBAddrMaps.size() && 926 "The same number of BBAddrMaps and PGOAnalysisMaps should be " 927 "returned when PGO information is requested"); 928 return BBAddrMaps; 929 } 930 931 template <class ELFT> 932 static Expected<std::vector<VersionEntry>> 933 readDynsymVersionsImpl(const ELFFile<ELFT> &EF, 934 ELFObjectFileBase::elf_symbol_iterator_range Symbols) { 935 using Elf_Shdr = typename ELFT::Shdr; 936 const Elf_Shdr *VerSec = nullptr; 937 const Elf_Shdr *VerNeedSec = nullptr; 938 const Elf_Shdr *VerDefSec = nullptr; 939 // The user should ensure sections() can't fail here. 940 for (const Elf_Shdr &Sec : cantFail(EF.sections())) { 941 if (Sec.sh_type == ELF::SHT_GNU_versym) 942 VerSec = &Sec; 943 else if (Sec.sh_type == ELF::SHT_GNU_verdef) 944 VerDefSec = &Sec; 945 else if (Sec.sh_type == ELF::SHT_GNU_verneed) 946 VerNeedSec = &Sec; 947 } 948 if (!VerSec) 949 return std::vector<VersionEntry>(); 950 951 Expected<SmallVector<std::optional<VersionEntry>, 0>> MapOrErr = 952 EF.loadVersionMap(VerNeedSec, VerDefSec); 953 if (!MapOrErr) 954 return MapOrErr.takeError(); 955 956 std::vector<VersionEntry> Ret; 957 size_t I = 0; 958 for (const ELFSymbolRef &Sym : Symbols) { 959 ++I; 960 Expected<const typename ELFT::Versym *> VerEntryOrErr = 961 EF.template getEntry<typename ELFT::Versym>(*VerSec, I); 962 if (!VerEntryOrErr) 963 return createError("unable to read an entry with index " + Twine(I) + 964 " from " + describe(EF, *VerSec) + ": " + 965 toString(VerEntryOrErr.takeError())); 966 967 Expected<uint32_t> FlagsOrErr = Sym.getFlags(); 968 if (!FlagsOrErr) 969 return createError("unable to read flags for symbol with index " + 970 Twine(I) + ": " + toString(FlagsOrErr.takeError())); 971 972 bool IsDefault; 973 Expected<StringRef> VerOrErr = EF.getSymbolVersionByIndex( 974 (*VerEntryOrErr)->vs_index, IsDefault, *MapOrErr, 975 (*FlagsOrErr) & SymbolRef::SF_Undefined); 976 if (!VerOrErr) 977 return createError("unable to get a version for entry " + Twine(I) + 978 " of " + describe(EF, *VerSec) + ": " + 979 toString(VerOrErr.takeError())); 980 981 Ret.push_back({(*VerOrErr).str(), IsDefault}); 982 } 983 984 return Ret; 985 } 986 987 Expected<std::vector<VersionEntry>> 988 ELFObjectFileBase::readDynsymVersions() const { 989 elf_symbol_iterator_range Symbols = getDynamicSymbolIterators(); 990 if (const auto *Obj = dyn_cast<ELF32LEObjectFile>(this)) 991 return readDynsymVersionsImpl(Obj->getELFFile(), Symbols); 992 if (const auto *Obj = dyn_cast<ELF32BEObjectFile>(this)) 993 return readDynsymVersionsImpl(Obj->getELFFile(), Symbols); 994 if (const auto *Obj = dyn_cast<ELF64LEObjectFile>(this)) 995 return readDynsymVersionsImpl(Obj->getELFFile(), Symbols); 996 return readDynsymVersionsImpl(cast<ELF64BEObjectFile>(this)->getELFFile(), 997 Symbols); 998 } 999 1000 Expected<std::vector<BBAddrMap>> ELFObjectFileBase::readBBAddrMap( 1001 std::optional<unsigned> TextSectionIndex, 1002 std::vector<PGOAnalysisMap> *PGOAnalyses) const { 1003 if (const auto *Obj = dyn_cast<ELF32LEObjectFile>(this)) 1004 return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex, PGOAnalyses); 1005 if (const auto *Obj = dyn_cast<ELF64LEObjectFile>(this)) 1006 return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex, PGOAnalyses); 1007 if (const auto *Obj = dyn_cast<ELF32BEObjectFile>(this)) 1008 return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex, PGOAnalyses); 1009 return readBBAddrMapImpl(cast<ELF64BEObjectFile>(this)->getELFFile(), 1010 TextSectionIndex, PGOAnalyses); 1011 } 1012