1 //===- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This implements the TargetLoweringBase class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/ADT/BitVector.h" 14 #include "llvm/ADT/STLExtras.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringExtras.h" 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Twine.h" 19 #include "llvm/Analysis/Loads.h" 20 #include "llvm/Analysis/TargetTransformInfo.h" 21 #include "llvm/CodeGen/Analysis.h" 22 #include "llvm/CodeGen/ISDOpcodes.h" 23 #include "llvm/CodeGen/MachineBasicBlock.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunction.h" 26 #include "llvm/CodeGen/MachineInstr.h" 27 #include "llvm/CodeGen/MachineInstrBuilder.h" 28 #include "llvm/CodeGen/MachineMemOperand.h" 29 #include "llvm/CodeGen/MachineOperand.h" 30 #include "llvm/CodeGen/MachineRegisterInfo.h" 31 #include "llvm/CodeGen/RuntimeLibcalls.h" 32 #include "llvm/CodeGen/StackMaps.h" 33 #include "llvm/CodeGen/TargetLowering.h" 34 #include "llvm/CodeGen/TargetOpcodes.h" 35 #include "llvm/CodeGen/TargetRegisterInfo.h" 36 #include "llvm/CodeGen/ValueTypes.h" 37 #include "llvm/CodeGenTypes/MachineValueType.h" 38 #include "llvm/IR/Attributes.h" 39 #include "llvm/IR/CallingConv.h" 40 #include "llvm/IR/DataLayout.h" 41 #include "llvm/IR/DerivedTypes.h" 42 #include "llvm/IR/Function.h" 43 #include "llvm/IR/GlobalValue.h" 44 #include "llvm/IR/GlobalVariable.h" 45 #include "llvm/IR/IRBuilder.h" 46 #include "llvm/IR/Module.h" 47 #include "llvm/IR/Type.h" 48 #include "llvm/Support/Casting.h" 49 #include "llvm/Support/CommandLine.h" 50 #include "llvm/Support/Compiler.h" 51 #include "llvm/Support/ErrorHandling.h" 52 #include "llvm/Support/MathExtras.h" 53 #include "llvm/Target/TargetMachine.h" 54 #include "llvm/Target/TargetOptions.h" 55 #include "llvm/TargetParser/Triple.h" 56 #include "llvm/Transforms/Utils/SizeOpts.h" 57 #include <algorithm> 58 #include <cassert> 59 #include <cstdint> 60 #include <cstring> 61 #include <iterator> 62 #include <string> 63 #include <tuple> 64 #include <utility> 65 66 using namespace llvm; 67 68 static cl::opt<bool> JumpIsExpensiveOverride( 69 "jump-is-expensive", cl::init(false), 70 cl::desc("Do not create extra branches to split comparison logic."), 71 cl::Hidden); 72 73 static cl::opt<unsigned> MinimumJumpTableEntries 74 ("min-jump-table-entries", cl::init(4), cl::Hidden, 75 cl::desc("Set minimum number of entries to use a jump table.")); 76 77 static cl::opt<unsigned> MaximumJumpTableSize 78 ("max-jump-table-size", cl::init(UINT_MAX), cl::Hidden, 79 cl::desc("Set maximum size of jump tables.")); 80 81 /// Minimum jump table density for normal functions. 82 static cl::opt<unsigned> 83 JumpTableDensity("jump-table-density", cl::init(10), cl::Hidden, 84 cl::desc("Minimum density for building a jump table in " 85 "a normal function")); 86 87 /// Minimum jump table density for -Os or -Oz functions. 88 static cl::opt<unsigned> OptsizeJumpTableDensity( 89 "optsize-jump-table-density", cl::init(40), cl::Hidden, 90 cl::desc("Minimum density for building a jump table in " 91 "an optsize function")); 92 93 // FIXME: This option is only to test if the strict fp operation processed 94 // correctly by preventing mutating strict fp operation to normal fp operation 95 // during development. When the backend supports strict float operation, this 96 // option will be meaningless. 97 static cl::opt<bool> DisableStrictNodeMutation("disable-strictnode-mutation", 98 cl::desc("Don't mutate strict-float node to a legalize node"), 99 cl::init(false), cl::Hidden); 100 101 static bool darwinHasSinCos(const Triple &TT) { 102 assert(TT.isOSDarwin() && "should be called with darwin triple"); 103 // Don't bother with 32 bit x86. 104 if (TT.getArch() == Triple::x86) 105 return false; 106 // Macos < 10.9 has no sincos_stret. 107 if (TT.isMacOSX()) 108 return !TT.isMacOSXVersionLT(10, 9) && TT.isArch64Bit(); 109 // iOS < 7.0 has no sincos_stret. 110 if (TT.isiOS()) 111 return !TT.isOSVersionLT(7, 0); 112 // Any other darwin such as WatchOS/TvOS is new enough. 113 return true; 114 } 115 116 void TargetLoweringBase::InitLibcalls(const Triple &TT) { 117 #define HANDLE_LIBCALL(code, name) \ 118 setLibcallName(RTLIB::code, name); 119 #include "llvm/IR/RuntimeLibcalls.def" 120 #undef HANDLE_LIBCALL 121 // Initialize calling conventions to their default. 122 for (int LC = 0; LC < RTLIB::UNKNOWN_LIBCALL; ++LC) 123 setLibcallCallingConv((RTLIB::Libcall)LC, CallingConv::C); 124 125 // Use the f128 variants of math functions on x86_64 126 if (TT.getArch() == Triple::ArchType::x86_64 && TT.isGNUEnvironment()) { 127 setLibcallName(RTLIB::REM_F128, "fmodf128"); 128 setLibcallName(RTLIB::FMA_F128, "fmaf128"); 129 setLibcallName(RTLIB::SQRT_F128, "sqrtf128"); 130 setLibcallName(RTLIB::CBRT_F128, "cbrtf128"); 131 setLibcallName(RTLIB::LOG_F128, "logf128"); 132 setLibcallName(RTLIB::LOG_FINITE_F128, "__logf128_finite"); 133 setLibcallName(RTLIB::LOG2_F128, "log2f128"); 134 setLibcallName(RTLIB::LOG2_FINITE_F128, "__log2f128_finite"); 135 setLibcallName(RTLIB::LOG10_F128, "log10f128"); 136 setLibcallName(RTLIB::LOG10_FINITE_F128, "__log10f128_finite"); 137 setLibcallName(RTLIB::EXP_F128, "expf128"); 138 setLibcallName(RTLIB::EXP_FINITE_F128, "__expf128_finite"); 139 setLibcallName(RTLIB::EXP2_F128, "exp2f128"); 140 setLibcallName(RTLIB::EXP2_FINITE_F128, "__exp2f128_finite"); 141 setLibcallName(RTLIB::EXP10_F128, "exp10f128"); 142 setLibcallName(RTLIB::SIN_F128, "sinf128"); 143 setLibcallName(RTLIB::COS_F128, "cosf128"); 144 setLibcallName(RTLIB::SINCOS_F128, "sincosf128"); 145 setLibcallName(RTLIB::POW_F128, "powf128"); 146 setLibcallName(RTLIB::POW_FINITE_F128, "__powf128_finite"); 147 setLibcallName(RTLIB::CEIL_F128, "ceilf128"); 148 setLibcallName(RTLIB::TRUNC_F128, "truncf128"); 149 setLibcallName(RTLIB::RINT_F128, "rintf128"); 150 setLibcallName(RTLIB::NEARBYINT_F128, "nearbyintf128"); 151 setLibcallName(RTLIB::ROUND_F128, "roundf128"); 152 setLibcallName(RTLIB::ROUNDEVEN_F128, "roundevenf128"); 153 setLibcallName(RTLIB::FLOOR_F128, "floorf128"); 154 setLibcallName(RTLIB::COPYSIGN_F128, "copysignf128"); 155 setLibcallName(RTLIB::FMIN_F128, "fminf128"); 156 setLibcallName(RTLIB::FMAX_F128, "fmaxf128"); 157 setLibcallName(RTLIB::LROUND_F128, "lroundf128"); 158 setLibcallName(RTLIB::LLROUND_F128, "llroundf128"); 159 setLibcallName(RTLIB::LRINT_F128, "lrintf128"); 160 setLibcallName(RTLIB::LLRINT_F128, "llrintf128"); 161 setLibcallName(RTLIB::LDEXP_F128, "ldexpf128"); 162 setLibcallName(RTLIB::FREXP_F128, "frexpf128"); 163 } 164 165 // For IEEE quad-precision libcall names, PPC uses "kf" instead of "tf". 166 if (TT.isPPC()) { 167 setLibcallName(RTLIB::ADD_F128, "__addkf3"); 168 setLibcallName(RTLIB::SUB_F128, "__subkf3"); 169 setLibcallName(RTLIB::MUL_F128, "__mulkf3"); 170 setLibcallName(RTLIB::DIV_F128, "__divkf3"); 171 setLibcallName(RTLIB::POWI_F128, "__powikf2"); 172 setLibcallName(RTLIB::FPEXT_F32_F128, "__extendsfkf2"); 173 setLibcallName(RTLIB::FPEXT_F64_F128, "__extenddfkf2"); 174 setLibcallName(RTLIB::FPROUND_F128_F32, "__trunckfsf2"); 175 setLibcallName(RTLIB::FPROUND_F128_F64, "__trunckfdf2"); 176 setLibcallName(RTLIB::FPTOSINT_F128_I32, "__fixkfsi"); 177 setLibcallName(RTLIB::FPTOSINT_F128_I64, "__fixkfdi"); 178 setLibcallName(RTLIB::FPTOSINT_F128_I128, "__fixkfti"); 179 setLibcallName(RTLIB::FPTOUINT_F128_I32, "__fixunskfsi"); 180 setLibcallName(RTLIB::FPTOUINT_F128_I64, "__fixunskfdi"); 181 setLibcallName(RTLIB::FPTOUINT_F128_I128, "__fixunskfti"); 182 setLibcallName(RTLIB::SINTTOFP_I32_F128, "__floatsikf"); 183 setLibcallName(RTLIB::SINTTOFP_I64_F128, "__floatdikf"); 184 setLibcallName(RTLIB::SINTTOFP_I128_F128, "__floattikf"); 185 setLibcallName(RTLIB::UINTTOFP_I32_F128, "__floatunsikf"); 186 setLibcallName(RTLIB::UINTTOFP_I64_F128, "__floatundikf"); 187 setLibcallName(RTLIB::UINTTOFP_I128_F128, "__floatuntikf"); 188 setLibcallName(RTLIB::OEQ_F128, "__eqkf2"); 189 setLibcallName(RTLIB::UNE_F128, "__nekf2"); 190 setLibcallName(RTLIB::OGE_F128, "__gekf2"); 191 setLibcallName(RTLIB::OLT_F128, "__ltkf2"); 192 setLibcallName(RTLIB::OLE_F128, "__lekf2"); 193 setLibcallName(RTLIB::OGT_F128, "__gtkf2"); 194 setLibcallName(RTLIB::UO_F128, "__unordkf2"); 195 } 196 197 // A few names are different on particular architectures or environments. 198 if (TT.isOSDarwin()) { 199 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead 200 // of the gnueabi-style __gnu_*_ieee. 201 // FIXME: What about other targets? 202 setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2"); 203 setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2"); 204 205 // Some darwins have an optimized __bzero/bzero function. 206 switch (TT.getArch()) { 207 case Triple::x86: 208 case Triple::x86_64: 209 if (TT.isMacOSX() && !TT.isMacOSXVersionLT(10, 6)) 210 setLibcallName(RTLIB::BZERO, "__bzero"); 211 break; 212 case Triple::aarch64: 213 case Triple::aarch64_32: 214 setLibcallName(RTLIB::BZERO, "bzero"); 215 break; 216 default: 217 break; 218 } 219 220 if (darwinHasSinCos(TT)) { 221 setLibcallName(RTLIB::SINCOS_STRET_F32, "__sincosf_stret"); 222 setLibcallName(RTLIB::SINCOS_STRET_F64, "__sincos_stret"); 223 if (TT.isWatchABI()) { 224 setLibcallCallingConv(RTLIB::SINCOS_STRET_F32, 225 CallingConv::ARM_AAPCS_VFP); 226 setLibcallCallingConv(RTLIB::SINCOS_STRET_F64, 227 CallingConv::ARM_AAPCS_VFP); 228 } 229 } 230 } else { 231 setLibcallName(RTLIB::FPEXT_F16_F32, "__gnu_h2f_ieee"); 232 setLibcallName(RTLIB::FPROUND_F32_F16, "__gnu_f2h_ieee"); 233 } 234 235 if (TT.isGNUEnvironment() || TT.isOSFuchsia() || 236 (TT.isAndroid() && !TT.isAndroidVersionLT(9))) { 237 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 238 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 239 setLibcallName(RTLIB::SINCOS_F80, "sincosl"); 240 setLibcallName(RTLIB::SINCOS_F128, "sincosl"); 241 setLibcallName(RTLIB::SINCOS_PPCF128, "sincosl"); 242 } 243 244 if (TT.isPS()) { 245 setLibcallName(RTLIB::SINCOS_F32, "sincosf"); 246 setLibcallName(RTLIB::SINCOS_F64, "sincos"); 247 } 248 249 if (TT.isOSOpenBSD()) { 250 setLibcallName(RTLIB::STACKPROTECTOR_CHECK_FAIL, nullptr); 251 } 252 253 if (TT.isOSWindows() && !TT.isOSCygMing()) { 254 setLibcallName(RTLIB::LDEXP_F32, nullptr); 255 setLibcallName(RTLIB::LDEXP_F80, nullptr); 256 setLibcallName(RTLIB::LDEXP_F128, nullptr); 257 setLibcallName(RTLIB::LDEXP_PPCF128, nullptr); 258 259 setLibcallName(RTLIB::FREXP_F32, nullptr); 260 setLibcallName(RTLIB::FREXP_F80, nullptr); 261 setLibcallName(RTLIB::FREXP_F128, nullptr); 262 setLibcallName(RTLIB::FREXP_PPCF128, nullptr); 263 } 264 } 265 266 /// GetFPLibCall - Helper to return the right libcall for the given floating 267 /// point type, or UNKNOWN_LIBCALL if there is none. 268 RTLIB::Libcall RTLIB::getFPLibCall(EVT VT, 269 RTLIB::Libcall Call_F32, 270 RTLIB::Libcall Call_F64, 271 RTLIB::Libcall Call_F80, 272 RTLIB::Libcall Call_F128, 273 RTLIB::Libcall Call_PPCF128) { 274 return 275 VT == MVT::f32 ? Call_F32 : 276 VT == MVT::f64 ? Call_F64 : 277 VT == MVT::f80 ? Call_F80 : 278 VT == MVT::f128 ? Call_F128 : 279 VT == MVT::ppcf128 ? Call_PPCF128 : 280 RTLIB::UNKNOWN_LIBCALL; 281 } 282 283 /// getFPEXT - Return the FPEXT_*_* value for the given types, or 284 /// UNKNOWN_LIBCALL if there is none. 285 RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { 286 if (OpVT == MVT::f16) { 287 if (RetVT == MVT::f32) 288 return FPEXT_F16_F32; 289 if (RetVT == MVT::f64) 290 return FPEXT_F16_F64; 291 if (RetVT == MVT::f80) 292 return FPEXT_F16_F80; 293 if (RetVT == MVT::f128) 294 return FPEXT_F16_F128; 295 } else if (OpVT == MVT::f32) { 296 if (RetVT == MVT::f64) 297 return FPEXT_F32_F64; 298 if (RetVT == MVT::f128) 299 return FPEXT_F32_F128; 300 if (RetVT == MVT::ppcf128) 301 return FPEXT_F32_PPCF128; 302 } else if (OpVT == MVT::f64) { 303 if (RetVT == MVT::f128) 304 return FPEXT_F64_F128; 305 else if (RetVT == MVT::ppcf128) 306 return FPEXT_F64_PPCF128; 307 } else if (OpVT == MVT::f80) { 308 if (RetVT == MVT::f128) 309 return FPEXT_F80_F128; 310 } else if (OpVT == MVT::bf16) { 311 if (RetVT == MVT::f32) 312 return FPEXT_BF16_F32; 313 } 314 315 return UNKNOWN_LIBCALL; 316 } 317 318 /// getFPROUND - Return the FPROUND_*_* value for the given types, or 319 /// UNKNOWN_LIBCALL if there is none. 320 RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { 321 if (RetVT == MVT::f16) { 322 if (OpVT == MVT::f32) 323 return FPROUND_F32_F16; 324 if (OpVT == MVT::f64) 325 return FPROUND_F64_F16; 326 if (OpVT == MVT::f80) 327 return FPROUND_F80_F16; 328 if (OpVT == MVT::f128) 329 return FPROUND_F128_F16; 330 if (OpVT == MVT::ppcf128) 331 return FPROUND_PPCF128_F16; 332 } else if (RetVT == MVT::bf16) { 333 if (OpVT == MVT::f32) 334 return FPROUND_F32_BF16; 335 if (OpVT == MVT::f64) 336 return FPROUND_F64_BF16; 337 } else if (RetVT == MVT::f32) { 338 if (OpVT == MVT::f64) 339 return FPROUND_F64_F32; 340 if (OpVT == MVT::f80) 341 return FPROUND_F80_F32; 342 if (OpVT == MVT::f128) 343 return FPROUND_F128_F32; 344 if (OpVT == MVT::ppcf128) 345 return FPROUND_PPCF128_F32; 346 } else if (RetVT == MVT::f64) { 347 if (OpVT == MVT::f80) 348 return FPROUND_F80_F64; 349 if (OpVT == MVT::f128) 350 return FPROUND_F128_F64; 351 if (OpVT == MVT::ppcf128) 352 return FPROUND_PPCF128_F64; 353 } else if (RetVT == MVT::f80) { 354 if (OpVT == MVT::f128) 355 return FPROUND_F128_F80; 356 } 357 358 return UNKNOWN_LIBCALL; 359 } 360 361 /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or 362 /// UNKNOWN_LIBCALL if there is none. 363 RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { 364 if (OpVT == MVT::f16) { 365 if (RetVT == MVT::i32) 366 return FPTOSINT_F16_I32; 367 if (RetVT == MVT::i64) 368 return FPTOSINT_F16_I64; 369 if (RetVT == MVT::i128) 370 return FPTOSINT_F16_I128; 371 } else if (OpVT == MVT::f32) { 372 if (RetVT == MVT::i32) 373 return FPTOSINT_F32_I32; 374 if (RetVT == MVT::i64) 375 return FPTOSINT_F32_I64; 376 if (RetVT == MVT::i128) 377 return FPTOSINT_F32_I128; 378 } else if (OpVT == MVT::f64) { 379 if (RetVT == MVT::i32) 380 return FPTOSINT_F64_I32; 381 if (RetVT == MVT::i64) 382 return FPTOSINT_F64_I64; 383 if (RetVT == MVT::i128) 384 return FPTOSINT_F64_I128; 385 } else if (OpVT == MVT::f80) { 386 if (RetVT == MVT::i32) 387 return FPTOSINT_F80_I32; 388 if (RetVT == MVT::i64) 389 return FPTOSINT_F80_I64; 390 if (RetVT == MVT::i128) 391 return FPTOSINT_F80_I128; 392 } else if (OpVT == MVT::f128) { 393 if (RetVT == MVT::i32) 394 return FPTOSINT_F128_I32; 395 if (RetVT == MVT::i64) 396 return FPTOSINT_F128_I64; 397 if (RetVT == MVT::i128) 398 return FPTOSINT_F128_I128; 399 } else if (OpVT == MVT::ppcf128) { 400 if (RetVT == MVT::i32) 401 return FPTOSINT_PPCF128_I32; 402 if (RetVT == MVT::i64) 403 return FPTOSINT_PPCF128_I64; 404 if (RetVT == MVT::i128) 405 return FPTOSINT_PPCF128_I128; 406 } 407 return UNKNOWN_LIBCALL; 408 } 409 410 /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or 411 /// UNKNOWN_LIBCALL if there is none. 412 RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { 413 if (OpVT == MVT::f16) { 414 if (RetVT == MVT::i32) 415 return FPTOUINT_F16_I32; 416 if (RetVT == MVT::i64) 417 return FPTOUINT_F16_I64; 418 if (RetVT == MVT::i128) 419 return FPTOUINT_F16_I128; 420 } else if (OpVT == MVT::f32) { 421 if (RetVT == MVT::i32) 422 return FPTOUINT_F32_I32; 423 if (RetVT == MVT::i64) 424 return FPTOUINT_F32_I64; 425 if (RetVT == MVT::i128) 426 return FPTOUINT_F32_I128; 427 } else if (OpVT == MVT::f64) { 428 if (RetVT == MVT::i32) 429 return FPTOUINT_F64_I32; 430 if (RetVT == MVT::i64) 431 return FPTOUINT_F64_I64; 432 if (RetVT == MVT::i128) 433 return FPTOUINT_F64_I128; 434 } else if (OpVT == MVT::f80) { 435 if (RetVT == MVT::i32) 436 return FPTOUINT_F80_I32; 437 if (RetVT == MVT::i64) 438 return FPTOUINT_F80_I64; 439 if (RetVT == MVT::i128) 440 return FPTOUINT_F80_I128; 441 } else if (OpVT == MVT::f128) { 442 if (RetVT == MVT::i32) 443 return FPTOUINT_F128_I32; 444 if (RetVT == MVT::i64) 445 return FPTOUINT_F128_I64; 446 if (RetVT == MVT::i128) 447 return FPTOUINT_F128_I128; 448 } else if (OpVT == MVT::ppcf128) { 449 if (RetVT == MVT::i32) 450 return FPTOUINT_PPCF128_I32; 451 if (RetVT == MVT::i64) 452 return FPTOUINT_PPCF128_I64; 453 if (RetVT == MVT::i128) 454 return FPTOUINT_PPCF128_I128; 455 } 456 return UNKNOWN_LIBCALL; 457 } 458 459 /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or 460 /// UNKNOWN_LIBCALL if there is none. 461 RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { 462 if (OpVT == MVT::i32) { 463 if (RetVT == MVT::f16) 464 return SINTTOFP_I32_F16; 465 if (RetVT == MVT::f32) 466 return SINTTOFP_I32_F32; 467 if (RetVT == MVT::f64) 468 return SINTTOFP_I32_F64; 469 if (RetVT == MVT::f80) 470 return SINTTOFP_I32_F80; 471 if (RetVT == MVT::f128) 472 return SINTTOFP_I32_F128; 473 if (RetVT == MVT::ppcf128) 474 return SINTTOFP_I32_PPCF128; 475 } else if (OpVT == MVT::i64) { 476 if (RetVT == MVT::f16) 477 return SINTTOFP_I64_F16; 478 if (RetVT == MVT::f32) 479 return SINTTOFP_I64_F32; 480 if (RetVT == MVT::f64) 481 return SINTTOFP_I64_F64; 482 if (RetVT == MVT::f80) 483 return SINTTOFP_I64_F80; 484 if (RetVT == MVT::f128) 485 return SINTTOFP_I64_F128; 486 if (RetVT == MVT::ppcf128) 487 return SINTTOFP_I64_PPCF128; 488 } else if (OpVT == MVT::i128) { 489 if (RetVT == MVT::f16) 490 return SINTTOFP_I128_F16; 491 if (RetVT == MVT::f32) 492 return SINTTOFP_I128_F32; 493 if (RetVT == MVT::f64) 494 return SINTTOFP_I128_F64; 495 if (RetVT == MVT::f80) 496 return SINTTOFP_I128_F80; 497 if (RetVT == MVT::f128) 498 return SINTTOFP_I128_F128; 499 if (RetVT == MVT::ppcf128) 500 return SINTTOFP_I128_PPCF128; 501 } 502 return UNKNOWN_LIBCALL; 503 } 504 505 /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or 506 /// UNKNOWN_LIBCALL if there is none. 507 RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { 508 if (OpVT == MVT::i32) { 509 if (RetVT == MVT::f16) 510 return UINTTOFP_I32_F16; 511 if (RetVT == MVT::f32) 512 return UINTTOFP_I32_F32; 513 if (RetVT == MVT::f64) 514 return UINTTOFP_I32_F64; 515 if (RetVT == MVT::f80) 516 return UINTTOFP_I32_F80; 517 if (RetVT == MVT::f128) 518 return UINTTOFP_I32_F128; 519 if (RetVT == MVT::ppcf128) 520 return UINTTOFP_I32_PPCF128; 521 } else if (OpVT == MVT::i64) { 522 if (RetVT == MVT::f16) 523 return UINTTOFP_I64_F16; 524 if (RetVT == MVT::f32) 525 return UINTTOFP_I64_F32; 526 if (RetVT == MVT::f64) 527 return UINTTOFP_I64_F64; 528 if (RetVT == MVT::f80) 529 return UINTTOFP_I64_F80; 530 if (RetVT == MVT::f128) 531 return UINTTOFP_I64_F128; 532 if (RetVT == MVT::ppcf128) 533 return UINTTOFP_I64_PPCF128; 534 } else if (OpVT == MVT::i128) { 535 if (RetVT == MVT::f16) 536 return UINTTOFP_I128_F16; 537 if (RetVT == MVT::f32) 538 return UINTTOFP_I128_F32; 539 if (RetVT == MVT::f64) 540 return UINTTOFP_I128_F64; 541 if (RetVT == MVT::f80) 542 return UINTTOFP_I128_F80; 543 if (RetVT == MVT::f128) 544 return UINTTOFP_I128_F128; 545 if (RetVT == MVT::ppcf128) 546 return UINTTOFP_I128_PPCF128; 547 } 548 return UNKNOWN_LIBCALL; 549 } 550 551 RTLIB::Libcall RTLIB::getPOWI(EVT RetVT) { 552 return getFPLibCall(RetVT, POWI_F32, POWI_F64, POWI_F80, POWI_F128, 553 POWI_PPCF128); 554 } 555 556 RTLIB::Libcall RTLIB::getLDEXP(EVT RetVT) { 557 return getFPLibCall(RetVT, LDEXP_F32, LDEXP_F64, LDEXP_F80, LDEXP_F128, 558 LDEXP_PPCF128); 559 } 560 561 RTLIB::Libcall RTLIB::getFREXP(EVT RetVT) { 562 return getFPLibCall(RetVT, FREXP_F32, FREXP_F64, FREXP_F80, FREXP_F128, 563 FREXP_PPCF128); 564 } 565 566 RTLIB::Libcall RTLIB::getOutlineAtomicHelper(const Libcall (&LC)[5][4], 567 AtomicOrdering Order, 568 uint64_t MemSize) { 569 unsigned ModeN, ModelN; 570 switch (MemSize) { 571 case 1: 572 ModeN = 0; 573 break; 574 case 2: 575 ModeN = 1; 576 break; 577 case 4: 578 ModeN = 2; 579 break; 580 case 8: 581 ModeN = 3; 582 break; 583 case 16: 584 ModeN = 4; 585 break; 586 default: 587 return RTLIB::UNKNOWN_LIBCALL; 588 } 589 590 switch (Order) { 591 case AtomicOrdering::Monotonic: 592 ModelN = 0; 593 break; 594 case AtomicOrdering::Acquire: 595 ModelN = 1; 596 break; 597 case AtomicOrdering::Release: 598 ModelN = 2; 599 break; 600 case AtomicOrdering::AcquireRelease: 601 case AtomicOrdering::SequentiallyConsistent: 602 ModelN = 3; 603 break; 604 default: 605 return UNKNOWN_LIBCALL; 606 } 607 608 return LC[ModeN][ModelN]; 609 } 610 611 RTLIB::Libcall RTLIB::getOUTLINE_ATOMIC(unsigned Opc, AtomicOrdering Order, 612 MVT VT) { 613 if (!VT.isScalarInteger()) 614 return UNKNOWN_LIBCALL; 615 uint64_t MemSize = VT.getScalarSizeInBits() / 8; 616 617 #define LCALLS(A, B) \ 618 { A##B##_RELAX, A##B##_ACQ, A##B##_REL, A##B##_ACQ_REL } 619 #define LCALL5(A) \ 620 LCALLS(A, 1), LCALLS(A, 2), LCALLS(A, 4), LCALLS(A, 8), LCALLS(A, 16) 621 switch (Opc) { 622 case ISD::ATOMIC_CMP_SWAP: { 623 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_CAS)}; 624 return getOutlineAtomicHelper(LC, Order, MemSize); 625 } 626 case ISD::ATOMIC_SWAP: { 627 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_SWP)}; 628 return getOutlineAtomicHelper(LC, Order, MemSize); 629 } 630 case ISD::ATOMIC_LOAD_ADD: { 631 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDADD)}; 632 return getOutlineAtomicHelper(LC, Order, MemSize); 633 } 634 case ISD::ATOMIC_LOAD_OR: { 635 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDSET)}; 636 return getOutlineAtomicHelper(LC, Order, MemSize); 637 } 638 case ISD::ATOMIC_LOAD_CLR: { 639 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDCLR)}; 640 return getOutlineAtomicHelper(LC, Order, MemSize); 641 } 642 case ISD::ATOMIC_LOAD_XOR: { 643 const Libcall LC[5][4] = {LCALL5(OUTLINE_ATOMIC_LDEOR)}; 644 return getOutlineAtomicHelper(LC, Order, MemSize); 645 } 646 default: 647 return UNKNOWN_LIBCALL; 648 } 649 #undef LCALLS 650 #undef LCALL5 651 } 652 653 RTLIB::Libcall RTLIB::getSYNC(unsigned Opc, MVT VT) { 654 #define OP_TO_LIBCALL(Name, Enum) \ 655 case Name: \ 656 switch (VT.SimpleTy) { \ 657 default: \ 658 return UNKNOWN_LIBCALL; \ 659 case MVT::i8: \ 660 return Enum##_1; \ 661 case MVT::i16: \ 662 return Enum##_2; \ 663 case MVT::i32: \ 664 return Enum##_4; \ 665 case MVT::i64: \ 666 return Enum##_8; \ 667 case MVT::i128: \ 668 return Enum##_16; \ 669 } 670 671 switch (Opc) { 672 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET) 673 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP) 674 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD) 675 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB) 676 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND) 677 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR) 678 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR) 679 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND) 680 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX) 681 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX) 682 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN) 683 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN) 684 } 685 686 #undef OP_TO_LIBCALL 687 688 return UNKNOWN_LIBCALL; 689 } 690 691 RTLIB::Libcall RTLIB::getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 692 switch (ElementSize) { 693 case 1: 694 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_1; 695 case 2: 696 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_2; 697 case 4: 698 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_4; 699 case 8: 700 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_8; 701 case 16: 702 return MEMCPY_ELEMENT_UNORDERED_ATOMIC_16; 703 default: 704 return UNKNOWN_LIBCALL; 705 } 706 } 707 708 RTLIB::Libcall RTLIB::getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 709 switch (ElementSize) { 710 case 1: 711 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_1; 712 case 2: 713 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_2; 714 case 4: 715 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_4; 716 case 8: 717 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_8; 718 case 16: 719 return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_16; 720 default: 721 return UNKNOWN_LIBCALL; 722 } 723 } 724 725 RTLIB::Libcall RTLIB::getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize) { 726 switch (ElementSize) { 727 case 1: 728 return MEMSET_ELEMENT_UNORDERED_ATOMIC_1; 729 case 2: 730 return MEMSET_ELEMENT_UNORDERED_ATOMIC_2; 731 case 4: 732 return MEMSET_ELEMENT_UNORDERED_ATOMIC_4; 733 case 8: 734 return MEMSET_ELEMENT_UNORDERED_ATOMIC_8; 735 case 16: 736 return MEMSET_ELEMENT_UNORDERED_ATOMIC_16; 737 default: 738 return UNKNOWN_LIBCALL; 739 } 740 } 741 742 /// InitCmpLibcallCCs - Set default comparison libcall CC. 743 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { 744 std::fill(CCs, CCs + RTLIB::UNKNOWN_LIBCALL, ISD::SETCC_INVALID); 745 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; 746 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; 747 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; 748 CCs[RTLIB::OEQ_PPCF128] = ISD::SETEQ; 749 CCs[RTLIB::UNE_F32] = ISD::SETNE; 750 CCs[RTLIB::UNE_F64] = ISD::SETNE; 751 CCs[RTLIB::UNE_F128] = ISD::SETNE; 752 CCs[RTLIB::UNE_PPCF128] = ISD::SETNE; 753 CCs[RTLIB::OGE_F32] = ISD::SETGE; 754 CCs[RTLIB::OGE_F64] = ISD::SETGE; 755 CCs[RTLIB::OGE_F128] = ISD::SETGE; 756 CCs[RTLIB::OGE_PPCF128] = ISD::SETGE; 757 CCs[RTLIB::OLT_F32] = ISD::SETLT; 758 CCs[RTLIB::OLT_F64] = ISD::SETLT; 759 CCs[RTLIB::OLT_F128] = ISD::SETLT; 760 CCs[RTLIB::OLT_PPCF128] = ISD::SETLT; 761 CCs[RTLIB::OLE_F32] = ISD::SETLE; 762 CCs[RTLIB::OLE_F64] = ISD::SETLE; 763 CCs[RTLIB::OLE_F128] = ISD::SETLE; 764 CCs[RTLIB::OLE_PPCF128] = ISD::SETLE; 765 CCs[RTLIB::OGT_F32] = ISD::SETGT; 766 CCs[RTLIB::OGT_F64] = ISD::SETGT; 767 CCs[RTLIB::OGT_F128] = ISD::SETGT; 768 CCs[RTLIB::OGT_PPCF128] = ISD::SETGT; 769 CCs[RTLIB::UO_F32] = ISD::SETNE; 770 CCs[RTLIB::UO_F64] = ISD::SETNE; 771 CCs[RTLIB::UO_F128] = ISD::SETNE; 772 CCs[RTLIB::UO_PPCF128] = ISD::SETNE; 773 } 774 775 /// NOTE: The TargetMachine owns TLOF. 776 TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) { 777 initActions(); 778 779 // Perform these initializations only once. 780 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 781 MaxLoadsPerMemcmp = 8; 782 MaxGluedStoresPerMemcpy = 0; 783 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize = 784 MaxStoresPerMemmoveOptSize = MaxLoadsPerMemcmpOptSize = 4; 785 HasMultipleConditionRegisters = false; 786 HasExtractBitsInsn = false; 787 JumpIsExpensive = JumpIsExpensiveOverride; 788 PredictableSelectIsExpensive = false; 789 EnableExtLdPromotion = false; 790 StackPointerRegisterToSaveRestore = 0; 791 BooleanContents = UndefinedBooleanContent; 792 BooleanFloatContents = UndefinedBooleanContent; 793 BooleanVectorContents = UndefinedBooleanContent; 794 SchedPreferenceInfo = Sched::ILP; 795 GatherAllAliasesMaxDepth = 18; 796 IsStrictFPEnabled = DisableStrictNodeMutation; 797 MaxBytesForAlignment = 0; 798 MaxAtomicSizeInBitsSupported = 0; 799 800 // Assume that even with libcalls, no target supports wider than 128 bit 801 // division. 802 MaxDivRemBitWidthSupported = 128; 803 804 MaxLargeFPConvertBitWidthSupported = llvm::IntegerType::MAX_INT_BITS; 805 806 MinCmpXchgSizeInBits = 0; 807 SupportsUnalignedAtomics = false; 808 809 std::fill(std::begin(LibcallRoutineNames), std::end(LibcallRoutineNames), nullptr); 810 811 InitLibcalls(TM.getTargetTriple()); 812 InitCmpLibcallCCs(CmpLibcallCCs); 813 } 814 815 void TargetLoweringBase::initActions() { 816 // All operations default to being supported. 817 memset(OpActions, 0, sizeof(OpActions)); 818 memset(LoadExtActions, 0, sizeof(LoadExtActions)); 819 memset(TruncStoreActions, 0, sizeof(TruncStoreActions)); 820 memset(IndexedModeActions, 0, sizeof(IndexedModeActions)); 821 memset(CondCodeActions, 0, sizeof(CondCodeActions)); 822 std::fill(std::begin(RegClassForVT), std::end(RegClassForVT), nullptr); 823 std::fill(std::begin(TargetDAGCombineArray), 824 std::end(TargetDAGCombineArray), 0); 825 826 // We're somewhat special casing MVT::i2 and MVT::i4. Ideally we want to 827 // remove this and targets should individually set these types if not legal. 828 for (ISD::NodeType NT : enum_seq(ISD::DELETED_NODE, ISD::BUILTIN_OP_END, 829 force_iteration_on_noniterable_enum)) { 830 for (MVT VT : {MVT::i2, MVT::i4}) 831 OpActions[(unsigned)VT.SimpleTy][NT] = Expand; 832 } 833 for (MVT AVT : MVT::all_valuetypes()) { 834 for (MVT VT : {MVT::i2, MVT::i4, MVT::v128i2, MVT::v64i4}) { 835 setTruncStoreAction(AVT, VT, Expand); 836 setLoadExtAction(ISD::EXTLOAD, AVT, VT, Expand); 837 setLoadExtAction(ISD::ZEXTLOAD, AVT, VT, Expand); 838 } 839 } 840 for (unsigned IM = (unsigned)ISD::PRE_INC; 841 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 842 for (MVT VT : {MVT::i2, MVT::i4}) { 843 setIndexedLoadAction(IM, VT, Expand); 844 setIndexedStoreAction(IM, VT, Expand); 845 setIndexedMaskedLoadAction(IM, VT, Expand); 846 setIndexedMaskedStoreAction(IM, VT, Expand); 847 } 848 } 849 850 for (MVT VT : MVT::fp_valuetypes()) { 851 MVT IntVT = MVT::getIntegerVT(VT.getFixedSizeInBits()); 852 if (IntVT.isValid()) { 853 setOperationAction(ISD::ATOMIC_SWAP, VT, Promote); 854 AddPromotedToType(ISD::ATOMIC_SWAP, VT, IntVT); 855 } 856 } 857 858 // Set default actions for various operations. 859 for (MVT VT : MVT::all_valuetypes()) { 860 // Default all indexed load / store to expand. 861 for (unsigned IM = (unsigned)ISD::PRE_INC; 862 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { 863 setIndexedLoadAction(IM, VT, Expand); 864 setIndexedStoreAction(IM, VT, Expand); 865 setIndexedMaskedLoadAction(IM, VT, Expand); 866 setIndexedMaskedStoreAction(IM, VT, Expand); 867 } 868 869 // Most backends expect to see the node which just returns the value loaded. 870 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand); 871 872 // These operations default to expand. 873 setOperationAction({ISD::FGETSIGN, ISD::CONCAT_VECTORS, 874 ISD::FMINNUM, ISD::FMAXNUM, 875 ISD::FMINNUM_IEEE, ISD::FMAXNUM_IEEE, 876 ISD::FMINIMUM, ISD::FMAXIMUM, 877 ISD::FMAD, ISD::SMIN, 878 ISD::SMAX, ISD::UMIN, 879 ISD::UMAX, ISD::ABS, 880 ISD::FSHL, ISD::FSHR, 881 ISD::SADDSAT, ISD::UADDSAT, 882 ISD::SSUBSAT, ISD::USUBSAT, 883 ISD::SSHLSAT, ISD::USHLSAT, 884 ISD::SMULFIX, ISD::SMULFIXSAT, 885 ISD::UMULFIX, ISD::UMULFIXSAT, 886 ISD::SDIVFIX, ISD::SDIVFIXSAT, 887 ISD::UDIVFIX, ISD::UDIVFIXSAT, 888 ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, 889 ISD::IS_FPCLASS}, 890 VT, Expand); 891 892 // Overflow operations default to expand 893 setOperationAction({ISD::SADDO, ISD::SSUBO, ISD::UADDO, ISD::USUBO, 894 ISD::SMULO, ISD::UMULO}, 895 VT, Expand); 896 897 // Carry-using overflow operations default to expand. 898 setOperationAction({ISD::UADDO_CARRY, ISD::USUBO_CARRY, ISD::SETCCCARRY, 899 ISD::SADDO_CARRY, ISD::SSUBO_CARRY}, 900 VT, Expand); 901 902 // ADDC/ADDE/SUBC/SUBE default to expand. 903 setOperationAction({ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}, VT, 904 Expand); 905 906 // Halving adds 907 setOperationAction( 908 {ISD::AVGFLOORS, ISD::AVGFLOORU, ISD::AVGCEILS, ISD::AVGCEILU}, VT, 909 Expand); 910 911 // Absolute difference 912 setOperationAction({ISD::ABDS, ISD::ABDU}, VT, Expand); 913 914 // These default to Expand so they will be expanded to CTLZ/CTTZ by default. 915 setOperationAction({ISD::CTLZ_ZERO_UNDEF, ISD::CTTZ_ZERO_UNDEF}, VT, 916 Expand); 917 918 setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand); 919 920 // These library functions default to expand. 921 setOperationAction({ISD::FROUND, ISD::FPOWI, ISD::FLDEXP, ISD::FFREXP}, VT, 922 Expand); 923 924 // These operations default to expand for vector types. 925 if (VT.isVector()) 926 setOperationAction( 927 {ISD::FCOPYSIGN, ISD::SIGN_EXTEND_INREG, ISD::ANY_EXTEND_VECTOR_INREG, 928 ISD::SIGN_EXTEND_VECTOR_INREG, ISD::ZERO_EXTEND_VECTOR_INREG, 929 ISD::SPLAT_VECTOR, ISD::LRINT, ISD::LLRINT}, 930 VT, Expand); 931 932 // Constrained floating-point operations default to expand. 933 #define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \ 934 setOperationAction(ISD::STRICT_##DAGN, VT, Expand); 935 #include "llvm/IR/ConstrainedOps.def" 936 937 // For most targets @llvm.get.dynamic.area.offset just returns 0. 938 setOperationAction(ISD::GET_DYNAMIC_AREA_OFFSET, VT, Expand); 939 940 // Vector reduction default to expand. 941 setOperationAction( 942 {ISD::VECREDUCE_FADD, ISD::VECREDUCE_FMUL, ISD::VECREDUCE_ADD, 943 ISD::VECREDUCE_MUL, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR, 944 ISD::VECREDUCE_XOR, ISD::VECREDUCE_SMAX, ISD::VECREDUCE_SMIN, 945 ISD::VECREDUCE_UMAX, ISD::VECREDUCE_UMIN, ISD::VECREDUCE_FMAX, 946 ISD::VECREDUCE_FMIN, ISD::VECREDUCE_FMAXIMUM, ISD::VECREDUCE_FMINIMUM, 947 ISD::VECREDUCE_SEQ_FADD, ISD::VECREDUCE_SEQ_FMUL}, 948 VT, Expand); 949 950 // Named vector shuffles default to expand. 951 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); 952 953 // VP operations default to expand. 954 #define BEGIN_REGISTER_VP_SDNODE(SDOPC, ...) \ 955 setOperationAction(ISD::SDOPC, VT, Expand); 956 #include "llvm/IR/VPIntrinsics.def" 957 958 // FP environment operations default to expand. 959 setOperationAction(ISD::GET_FPENV, VT, Expand); 960 setOperationAction(ISD::SET_FPENV, VT, Expand); 961 setOperationAction(ISD::RESET_FPENV, VT, Expand); 962 } 963 964 // Most targets ignore the @llvm.prefetch intrinsic. 965 setOperationAction(ISD::PREFETCH, MVT::Other, Expand); 966 967 // Most targets also ignore the @llvm.readcyclecounter intrinsic. 968 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Expand); 969 970 // Most targets also ignore the @llvm.readsteadycounter intrinsic. 971 setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64, Expand); 972 973 // ConstantFP nodes default to expand. Targets can either change this to 974 // Legal, in which case all fp constants are legal, or use isFPImmLegal() 975 // to optimize expansions for certain constants. 976 setOperationAction(ISD::ConstantFP, 977 {MVT::bf16, MVT::f16, MVT::f32, MVT::f64, MVT::f80, MVT::f128}, 978 Expand); 979 980 // These library functions default to expand. 981 setOperationAction({ISD::FCBRT, ISD::FLOG, ISD::FLOG2, ISD::FLOG10, ISD::FEXP, 982 ISD::FEXP2, ISD::FEXP10, ISD::FFLOOR, ISD::FNEARBYINT, 983 ISD::FCEIL, ISD::FRINT, ISD::FTRUNC, ISD::LROUND, 984 ISD::LLROUND, ISD::LRINT, ISD::LLRINT, ISD::FROUNDEVEN}, 985 {MVT::f32, MVT::f64, MVT::f128}, Expand); 986 987 // Default ISD::TRAP to expand (which turns it into abort). 988 setOperationAction(ISD::TRAP, MVT::Other, Expand); 989 990 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand" 991 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP. 992 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand); 993 994 setOperationAction(ISD::UBSANTRAP, MVT::Other, Expand); 995 996 setOperationAction(ISD::GET_FPENV_MEM, MVT::Other, Expand); 997 setOperationAction(ISD::SET_FPENV_MEM, MVT::Other, Expand); 998 999 for (MVT VT : {MVT::i8, MVT::i16, MVT::i32, MVT::i64}) { 1000 setOperationAction(ISD::GET_FPMODE, VT, Expand); 1001 setOperationAction(ISD::SET_FPMODE, VT, Expand); 1002 } 1003 setOperationAction(ISD::RESET_FPMODE, MVT::Other, Expand); 1004 } 1005 1006 MVT TargetLoweringBase::getScalarShiftAmountTy(const DataLayout &DL, 1007 EVT) const { 1008 return MVT::getIntegerVT(DL.getPointerSizeInBits(0)); 1009 } 1010 1011 EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy, const DataLayout &DL, 1012 bool LegalTypes) const { 1013 assert(LHSTy.isInteger() && "Shift amount is not an integer type!"); 1014 if (LHSTy.isVector()) 1015 return LHSTy; 1016 MVT ShiftVT = 1017 LegalTypes ? getScalarShiftAmountTy(DL, LHSTy) : getPointerTy(DL); 1018 // If any possible shift value won't fit in the prefered type, just use 1019 // something safe. Assume it will be legalized when the shift is expanded. 1020 if (ShiftVT.getSizeInBits() < Log2_32_Ceil(LHSTy.getSizeInBits())) 1021 ShiftVT = MVT::i32; 1022 assert(ShiftVT.getSizeInBits() >= Log2_32_Ceil(LHSTy.getSizeInBits()) && 1023 "ShiftVT is still too small!"); 1024 return ShiftVT; 1025 } 1026 1027 bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const { 1028 assert(isTypeLegal(VT)); 1029 switch (Op) { 1030 default: 1031 return false; 1032 case ISD::SDIV: 1033 case ISD::UDIV: 1034 case ISD::SREM: 1035 case ISD::UREM: 1036 return true; 1037 } 1038 } 1039 1040 bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS, 1041 unsigned DestAS) const { 1042 return TM.isNoopAddrSpaceCast(SrcAS, DestAS); 1043 } 1044 1045 void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) { 1046 // If the command-line option was specified, ignore this request. 1047 if (!JumpIsExpensiveOverride.getNumOccurrences()) 1048 JumpIsExpensive = isExpensive; 1049 } 1050 1051 TargetLoweringBase::LegalizeKind 1052 TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const { 1053 // If this is a simple type, use the ComputeRegisterProp mechanism. 1054 if (VT.isSimple()) { 1055 MVT SVT = VT.getSimpleVT(); 1056 assert((unsigned)SVT.SimpleTy < std::size(TransformToType)); 1057 MVT NVT = TransformToType[SVT.SimpleTy]; 1058 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT); 1059 1060 assert((LA == TypeLegal || LA == TypeSoftenFloat || 1061 LA == TypeSoftPromoteHalf || 1062 (NVT.isVector() || 1063 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)) && 1064 "Promote may not follow Expand or Promote"); 1065 1066 if (LA == TypeSplitVector) 1067 return LegalizeKind(LA, EVT(SVT).getHalfNumVectorElementsVT(Context)); 1068 if (LA == TypeScalarizeVector) 1069 return LegalizeKind(LA, SVT.getVectorElementType()); 1070 return LegalizeKind(LA, NVT); 1071 } 1072 1073 // Handle Extended Scalar Types. 1074 if (!VT.isVector()) { 1075 assert(VT.isInteger() && "Float types must be simple"); 1076 unsigned BitSize = VT.getSizeInBits(); 1077 // First promote to a power-of-two size, then expand if necessary. 1078 if (BitSize < 8 || !isPowerOf2_32(BitSize)) { 1079 EVT NVT = VT.getRoundIntegerType(Context); 1080 assert(NVT != VT && "Unable to round integer VT"); 1081 LegalizeKind NextStep = getTypeConversion(Context, NVT); 1082 // Avoid multi-step promotion. 1083 if (NextStep.first == TypePromoteInteger) 1084 return NextStep; 1085 // Return rounded integer type. 1086 return LegalizeKind(TypePromoteInteger, NVT); 1087 } 1088 1089 return LegalizeKind(TypeExpandInteger, 1090 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2)); 1091 } 1092 1093 // Handle vector types. 1094 ElementCount NumElts = VT.getVectorElementCount(); 1095 EVT EltVT = VT.getVectorElementType(); 1096 1097 // Vectors with only one element are always scalarized. 1098 if (NumElts.isScalar()) 1099 return LegalizeKind(TypeScalarizeVector, EltVT); 1100 1101 // Try to widen vector elements until the element type is a power of two and 1102 // promote it to a legal type later on, for example: 1103 // <3 x i8> -> <4 x i8> -> <4 x i32> 1104 if (EltVT.isInteger()) { 1105 // Vectors with a number of elements that is not a power of two are always 1106 // widened, for example <3 x i8> -> <4 x i8>. 1107 if (!VT.isPow2VectorType()) { 1108 NumElts = NumElts.coefficientNextPowerOf2(); 1109 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); 1110 return LegalizeKind(TypeWidenVector, NVT); 1111 } 1112 1113 // Examine the element type. 1114 LegalizeKind LK = getTypeConversion(Context, EltVT); 1115 1116 // If type is to be expanded, split the vector. 1117 // <4 x i140> -> <2 x i140> 1118 if (LK.first == TypeExpandInteger) { 1119 if (VT.getVectorElementCount().isScalable()) 1120 return LegalizeKind(TypeScalarizeScalableVector, EltVT); 1121 return LegalizeKind(TypeSplitVector, 1122 VT.getHalfNumVectorElementsVT(Context)); 1123 } 1124 1125 // Promote the integer element types until a legal vector type is found 1126 // or until the element integer type is too big. If a legal type was not 1127 // found, fallback to the usual mechanism of widening/splitting the 1128 // vector. 1129 EVT OldEltVT = EltVT; 1130 while (true) { 1131 // Increase the bitwidth of the element to the next pow-of-two 1132 // (which is greater than 8 bits). 1133 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()) 1134 .getRoundIntegerType(Context); 1135 1136 // Stop trying when getting a non-simple element type. 1137 // Note that vector elements may be greater than legal vector element 1138 // types. Example: X86 XMM registers hold 64bit element on 32bit 1139 // systems. 1140 if (!EltVT.isSimple()) 1141 break; 1142 1143 // Build a new vector type and check if it is legal. 1144 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1145 // Found a legal promoted vector type. 1146 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal) 1147 return LegalizeKind(TypePromoteInteger, 1148 EVT::getVectorVT(Context, EltVT, NumElts)); 1149 } 1150 1151 // Reset the type to the unexpanded type if we did not find a legal vector 1152 // type with a promoted vector element type. 1153 EltVT = OldEltVT; 1154 } 1155 1156 // Try to widen the vector until a legal type is found. 1157 // If there is no wider legal type, split the vector. 1158 while (true) { 1159 // Round up to the next power of 2. 1160 NumElts = NumElts.coefficientNextPowerOf2(); 1161 1162 // If there is no simple vector type with this many elements then there 1163 // cannot be a larger legal vector type. Note that this assumes that 1164 // there are no skipped intermediate vector types in the simple types. 1165 if (!EltVT.isSimple()) 1166 break; 1167 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); 1168 if (LargerVector == MVT()) 1169 break; 1170 1171 // If this type is legal then widen the vector. 1172 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal) 1173 return LegalizeKind(TypeWidenVector, LargerVector); 1174 } 1175 1176 // Widen odd vectors to next power of two. 1177 if (!VT.isPow2VectorType()) { 1178 EVT NVT = VT.getPow2VectorType(Context); 1179 return LegalizeKind(TypeWidenVector, NVT); 1180 } 1181 1182 if (VT.getVectorElementCount() == ElementCount::getScalable(1)) 1183 return LegalizeKind(TypeScalarizeScalableVector, EltVT); 1184 1185 // Vectors with illegal element types are expanded. 1186 EVT NVT = EVT::getVectorVT(Context, EltVT, 1187 VT.getVectorElementCount().divideCoefficientBy(2)); 1188 return LegalizeKind(TypeSplitVector, NVT); 1189 } 1190 1191 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, 1192 unsigned &NumIntermediates, 1193 MVT &RegisterVT, 1194 TargetLoweringBase *TLI) { 1195 // Figure out the right, legal destination reg to copy into. 1196 ElementCount EC = VT.getVectorElementCount(); 1197 MVT EltTy = VT.getVectorElementType(); 1198 1199 unsigned NumVectorRegs = 1; 1200 1201 // Scalable vectors cannot be scalarized, so splitting or widening is 1202 // required. 1203 if (VT.isScalableVector() && !isPowerOf2_32(EC.getKnownMinValue())) 1204 llvm_unreachable( 1205 "Splitting or widening of non-power-of-2 MVTs is not implemented."); 1206 1207 // FIXME: We don't support non-power-of-2-sized vectors for now. 1208 // Ideally we could break down into LHS/RHS like LegalizeDAG does. 1209 if (!isPowerOf2_32(EC.getKnownMinValue())) { 1210 // Split EC to unit size (scalable property is preserved). 1211 NumVectorRegs = EC.getKnownMinValue(); 1212 EC = ElementCount::getFixed(1); 1213 } 1214 1215 // Divide the input until we get to a supported size. This will 1216 // always end up with an EC that represent a scalar or a scalable 1217 // scalar. 1218 while (EC.getKnownMinValue() > 1 && 1219 !TLI->isTypeLegal(MVT::getVectorVT(EltTy, EC))) { 1220 EC = EC.divideCoefficientBy(2); 1221 NumVectorRegs <<= 1; 1222 } 1223 1224 NumIntermediates = NumVectorRegs; 1225 1226 MVT NewVT = MVT::getVectorVT(EltTy, EC); 1227 if (!TLI->isTypeLegal(NewVT)) 1228 NewVT = EltTy; 1229 IntermediateVT = NewVT; 1230 1231 unsigned LaneSizeInBits = NewVT.getScalarSizeInBits(); 1232 1233 // Convert sizes such as i33 to i64. 1234 LaneSizeInBits = llvm::bit_ceil(LaneSizeInBits); 1235 1236 MVT DestVT = TLI->getRegisterType(NewVT); 1237 RegisterVT = DestVT; 1238 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. 1239 return NumVectorRegs * (LaneSizeInBits / DestVT.getScalarSizeInBits()); 1240 1241 // Otherwise, promotion or legal types use the same number of registers as 1242 // the vector decimated to the appropriate level. 1243 return NumVectorRegs; 1244 } 1245 1246 /// isLegalRC - Return true if the value types that can be represented by the 1247 /// specified register class are all legal. 1248 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI, 1249 const TargetRegisterClass &RC) const { 1250 for (const auto *I = TRI.legalclasstypes_begin(RC); *I != MVT::Other; ++I) 1251 if (isTypeLegal(*I)) 1252 return true; 1253 return false; 1254 } 1255 1256 /// Replace/modify any TargetFrameIndex operands with a targte-dependent 1257 /// sequence of memory operands that is recognized by PrologEpilogInserter. 1258 MachineBasicBlock * 1259 TargetLoweringBase::emitPatchPoint(MachineInstr &InitialMI, 1260 MachineBasicBlock *MBB) const { 1261 MachineInstr *MI = &InitialMI; 1262 MachineFunction &MF = *MI->getMF(); 1263 MachineFrameInfo &MFI = MF.getFrameInfo(); 1264 1265 // We're handling multiple types of operands here: 1266 // PATCHPOINT MetaArgs - live-in, read only, direct 1267 // STATEPOINT Deopt Spill - live-through, read only, indirect 1268 // STATEPOINT Deopt Alloca - live-through, read only, direct 1269 // (We're currently conservative and mark the deopt slots read/write in 1270 // practice.) 1271 // STATEPOINT GC Spill - live-through, read/write, indirect 1272 // STATEPOINT GC Alloca - live-through, read/write, direct 1273 // The live-in vs live-through is handled already (the live through ones are 1274 // all stack slots), but we need to handle the different type of stackmap 1275 // operands and memory effects here. 1276 1277 if (llvm::none_of(MI->operands(), 1278 [](MachineOperand &Operand) { return Operand.isFI(); })) 1279 return MBB; 1280 1281 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc()); 1282 1283 // Inherit previous memory operands. 1284 MIB.cloneMemRefs(*MI); 1285 1286 for (unsigned i = 0; i < MI->getNumOperands(); ++i) { 1287 MachineOperand &MO = MI->getOperand(i); 1288 if (!MO.isFI()) { 1289 // Index of Def operand this Use it tied to. 1290 // Since Defs are coming before Uses, if Use is tied, then 1291 // index of Def must be smaller that index of that Use. 1292 // Also, Defs preserve their position in new MI. 1293 unsigned TiedTo = i; 1294 if (MO.isReg() && MO.isTied()) 1295 TiedTo = MI->findTiedOperandIdx(i); 1296 MIB.add(MO); 1297 if (TiedTo < i) 1298 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1); 1299 continue; 1300 } 1301 1302 // foldMemoryOperand builds a new MI after replacing a single FI operand 1303 // with the canonical set of five x86 addressing-mode operands. 1304 int FI = MO.getIndex(); 1305 1306 // Add frame index operands recognized by stackmaps.cpp 1307 if (MFI.isStatepointSpillSlotObjectIndex(FI)) { 1308 // indirect-mem-ref tag, size, #FI, offset. 1309 // Used for spills inserted by StatepointLowering. This codepath is not 1310 // used for patchpoints/stackmaps at all, for these spilling is done via 1311 // foldMemoryOperand callback only. 1312 assert(MI->getOpcode() == TargetOpcode::STATEPOINT && "sanity"); 1313 MIB.addImm(StackMaps::IndirectMemRefOp); 1314 MIB.addImm(MFI.getObjectSize(FI)); 1315 MIB.add(MO); 1316 MIB.addImm(0); 1317 } else { 1318 // direct-mem-ref tag, #FI, offset. 1319 // Used by patchpoint, and direct alloca arguments to statepoints 1320 MIB.addImm(StackMaps::DirectMemRefOp); 1321 MIB.add(MO); 1322 MIB.addImm(0); 1323 } 1324 1325 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!"); 1326 1327 // Add a new memory operand for this FI. 1328 assert(MFI.getObjectOffset(FI) != -1); 1329 1330 // Note: STATEPOINT MMOs are added during SelectionDAG. STACKMAP, and 1331 // PATCHPOINT should be updated to do the same. (TODO) 1332 if (MI->getOpcode() != TargetOpcode::STATEPOINT) { 1333 auto Flags = MachineMemOperand::MOLoad; 1334 MachineMemOperand *MMO = MF.getMachineMemOperand( 1335 MachinePointerInfo::getFixedStack(MF, FI), Flags, 1336 MF.getDataLayout().getPointerSize(), MFI.getObjectAlign(FI)); 1337 MIB->addMemOperand(MF, MMO); 1338 } 1339 } 1340 MBB->insert(MachineBasicBlock::iterator(MI), MIB); 1341 MI->eraseFromParent(); 1342 return MBB; 1343 } 1344 1345 /// findRepresentativeClass - Return the largest legal super-reg register class 1346 /// of the register class for the specified type and its associated "cost". 1347 // This function is in TargetLowering because it uses RegClassForVT which would 1348 // need to be moved to TargetRegisterInfo and would necessitate moving 1349 // isTypeLegal over as well - a massive change that would just require 1350 // TargetLowering having a TargetRegisterInfo class member that it would use. 1351 std::pair<const TargetRegisterClass *, uint8_t> 1352 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI, 1353 MVT VT) const { 1354 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy]; 1355 if (!RC) 1356 return std::make_pair(RC, 0); 1357 1358 // Compute the set of all super-register classes. 1359 BitVector SuperRegRC(TRI->getNumRegClasses()); 1360 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI) 1361 SuperRegRC.setBitsInMask(RCI.getMask()); 1362 1363 // Find the first legal register class with the largest spill size. 1364 const TargetRegisterClass *BestRC = RC; 1365 for (unsigned i : SuperRegRC.set_bits()) { 1366 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); 1367 // We want the largest possible spill size. 1368 if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC)) 1369 continue; 1370 if (!isLegalRC(*TRI, *SuperRC)) 1371 continue; 1372 BestRC = SuperRC; 1373 } 1374 return std::make_pair(BestRC, 1); 1375 } 1376 1377 /// computeRegisterProperties - Once all of the register classes are added, 1378 /// this allows us to compute derived properties we expose. 1379 void TargetLoweringBase::computeRegisterProperties( 1380 const TargetRegisterInfo *TRI) { 1381 static_assert(MVT::VALUETYPE_SIZE <= MVT::MAX_ALLOWED_VALUETYPE, 1382 "Too many value types for ValueTypeActions to hold!"); 1383 1384 // Everything defaults to needing one register. 1385 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) { 1386 NumRegistersForVT[i] = 1; 1387 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; 1388 } 1389 // ...except isVoid, which doesn't need any registers. 1390 NumRegistersForVT[MVT::isVoid] = 0; 1391 1392 // Find the largest integer register class. 1393 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; 1394 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg) 1395 assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); 1396 1397 // Every integer value type larger than this largest register takes twice as 1398 // many registers to represent as the previous ValueType. 1399 for (unsigned ExpandedReg = LargestIntReg + 1; 1400 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) { 1401 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; 1402 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; 1403 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); 1404 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg, 1405 TypeExpandInteger); 1406 } 1407 1408 // Inspect all of the ValueType's smaller than the largest integer 1409 // register to see which ones need promotion. 1410 unsigned LegalIntReg = LargestIntReg; 1411 for (unsigned IntReg = LargestIntReg - 1; 1412 IntReg >= (unsigned)MVT::i1; --IntReg) { 1413 MVT IVT = (MVT::SimpleValueType)IntReg; 1414 if (isTypeLegal(IVT)) { 1415 LegalIntReg = IntReg; 1416 } else { 1417 RegisterTypeForVT[IntReg] = TransformToType[IntReg] = 1418 (MVT::SimpleValueType)LegalIntReg; 1419 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger); 1420 } 1421 } 1422 1423 // ppcf128 type is really two f64's. 1424 if (!isTypeLegal(MVT::ppcf128)) { 1425 if (isTypeLegal(MVT::f64)) { 1426 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; 1427 RegisterTypeForVT[MVT::ppcf128] = MVT::f64; 1428 TransformToType[MVT::ppcf128] = MVT::f64; 1429 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat); 1430 } else { 1431 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128]; 1432 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128]; 1433 TransformToType[MVT::ppcf128] = MVT::i128; 1434 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat); 1435 } 1436 } 1437 1438 // Decide how to handle f128. If the target does not have native f128 support, 1439 // expand it to i128 and we will be generating soft float library calls. 1440 if (!isTypeLegal(MVT::f128)) { 1441 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128]; 1442 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128]; 1443 TransformToType[MVT::f128] = MVT::i128; 1444 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat); 1445 } 1446 1447 // Decide how to handle f80. If the target does not have native f80 support, 1448 // expand it to i96 and we will be generating soft float library calls. 1449 if (!isTypeLegal(MVT::f80)) { 1450 NumRegistersForVT[MVT::f80] = 3*NumRegistersForVT[MVT::i32]; 1451 RegisterTypeForVT[MVT::f80] = RegisterTypeForVT[MVT::i32]; 1452 TransformToType[MVT::f80] = MVT::i32; 1453 ValueTypeActions.setTypeAction(MVT::f80, TypeSoftenFloat); 1454 } 1455 1456 // Decide how to handle f64. If the target does not have native f64 support, 1457 // expand it to i64 and we will be generating soft float library calls. 1458 if (!isTypeLegal(MVT::f64)) { 1459 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; 1460 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; 1461 TransformToType[MVT::f64] = MVT::i64; 1462 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat); 1463 } 1464 1465 // Decide how to handle f32. If the target does not have native f32 support, 1466 // expand it to i32 and we will be generating soft float library calls. 1467 if (!isTypeLegal(MVT::f32)) { 1468 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; 1469 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; 1470 TransformToType[MVT::f32] = MVT::i32; 1471 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat); 1472 } 1473 1474 // Decide how to handle f16. If the target does not have native f16 support, 1475 // promote it to f32, because there are no f16 library calls (except for 1476 // conversions). 1477 if (!isTypeLegal(MVT::f16)) { 1478 // Allow targets to control how we legalize half. 1479 bool SoftPromoteHalfType = softPromoteHalfType(); 1480 bool UseFPRegsForHalfType = !SoftPromoteHalfType || useFPRegsForHalfType(); 1481 1482 if (!UseFPRegsForHalfType) { 1483 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16]; 1484 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16]; 1485 } else { 1486 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32]; 1487 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32]; 1488 } 1489 TransformToType[MVT::f16] = MVT::f32; 1490 if (SoftPromoteHalfType) { 1491 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftPromoteHalf); 1492 } else { 1493 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat); 1494 } 1495 } 1496 1497 // Decide how to handle bf16. If the target does not have native bf16 support, 1498 // promote it to f32, because there are no bf16 library calls (except for 1499 // converting from f32 to bf16). 1500 if (!isTypeLegal(MVT::bf16)) { 1501 NumRegistersForVT[MVT::bf16] = NumRegistersForVT[MVT::f32]; 1502 RegisterTypeForVT[MVT::bf16] = RegisterTypeForVT[MVT::f32]; 1503 TransformToType[MVT::bf16] = MVT::f32; 1504 ValueTypeActions.setTypeAction(MVT::bf16, TypeSoftPromoteHalf); 1505 } 1506 1507 // Loop over all of the vector value types to see which need transformations. 1508 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; 1509 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1510 MVT VT = (MVT::SimpleValueType) i; 1511 if (isTypeLegal(VT)) 1512 continue; 1513 1514 MVT EltVT = VT.getVectorElementType(); 1515 ElementCount EC = VT.getVectorElementCount(); 1516 bool IsLegalWiderType = false; 1517 bool IsScalable = VT.isScalableVector(); 1518 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT); 1519 switch (PreferredAction) { 1520 case TypePromoteInteger: { 1521 MVT::SimpleValueType EndVT = IsScalable ? 1522 MVT::LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE : 1523 MVT::LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE; 1524 // Try to promote the elements of integer vectors. If no legal 1525 // promotion was found, fall through to the widen-vector method. 1526 for (unsigned nVT = i + 1; 1527 (MVT::SimpleValueType)nVT <= EndVT; ++nVT) { 1528 MVT SVT = (MVT::SimpleValueType) nVT; 1529 // Promote vectors of integers to vectors with the same number 1530 // of elements, with a wider element type. 1531 if (SVT.getScalarSizeInBits() > EltVT.getFixedSizeInBits() && 1532 SVT.getVectorElementCount() == EC && isTypeLegal(SVT)) { 1533 TransformToType[i] = SVT; 1534 RegisterTypeForVT[i] = SVT; 1535 NumRegistersForVT[i] = 1; 1536 ValueTypeActions.setTypeAction(VT, TypePromoteInteger); 1537 IsLegalWiderType = true; 1538 break; 1539 } 1540 } 1541 if (IsLegalWiderType) 1542 break; 1543 [[fallthrough]]; 1544 } 1545 1546 case TypeWidenVector: 1547 if (isPowerOf2_32(EC.getKnownMinValue())) { 1548 // Try to widen the vector. 1549 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { 1550 MVT SVT = (MVT::SimpleValueType) nVT; 1551 if (SVT.getVectorElementType() == EltVT && 1552 SVT.isScalableVector() == IsScalable && 1553 SVT.getVectorElementCount().getKnownMinValue() > 1554 EC.getKnownMinValue() && 1555 isTypeLegal(SVT)) { 1556 TransformToType[i] = SVT; 1557 RegisterTypeForVT[i] = SVT; 1558 NumRegistersForVT[i] = 1; 1559 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1560 IsLegalWiderType = true; 1561 break; 1562 } 1563 } 1564 if (IsLegalWiderType) 1565 break; 1566 } else { 1567 // Only widen to the next power of 2 to keep consistency with EVT. 1568 MVT NVT = VT.getPow2VectorType(); 1569 if (isTypeLegal(NVT)) { 1570 TransformToType[i] = NVT; 1571 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1572 RegisterTypeForVT[i] = NVT; 1573 NumRegistersForVT[i] = 1; 1574 break; 1575 } 1576 } 1577 [[fallthrough]]; 1578 1579 case TypeSplitVector: 1580 case TypeScalarizeVector: { 1581 MVT IntermediateVT; 1582 MVT RegisterVT; 1583 unsigned NumIntermediates; 1584 unsigned NumRegisters = getVectorTypeBreakdownMVT(VT, IntermediateVT, 1585 NumIntermediates, RegisterVT, this); 1586 NumRegistersForVT[i] = NumRegisters; 1587 assert(NumRegistersForVT[i] == NumRegisters && 1588 "NumRegistersForVT size cannot represent NumRegisters!"); 1589 RegisterTypeForVT[i] = RegisterVT; 1590 1591 MVT NVT = VT.getPow2VectorType(); 1592 if (NVT == VT) { 1593 // Type is already a power of 2. The default action is to split. 1594 TransformToType[i] = MVT::Other; 1595 if (PreferredAction == TypeScalarizeVector) 1596 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector); 1597 else if (PreferredAction == TypeSplitVector) 1598 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1599 else if (EC.getKnownMinValue() > 1) 1600 ValueTypeActions.setTypeAction(VT, TypeSplitVector); 1601 else 1602 ValueTypeActions.setTypeAction(VT, EC.isScalable() 1603 ? TypeScalarizeScalableVector 1604 : TypeScalarizeVector); 1605 } else { 1606 TransformToType[i] = NVT; 1607 ValueTypeActions.setTypeAction(VT, TypeWidenVector); 1608 } 1609 break; 1610 } 1611 default: 1612 llvm_unreachable("Unknown vector legalization action!"); 1613 } 1614 } 1615 1616 // Determine the 'representative' register class for each value type. 1617 // An representative register class is the largest (meaning one which is 1618 // not a sub-register class / subreg register class) legal register class for 1619 // a group of value types. For example, on i386, i8, i16, and i32 1620 // representative would be GR32; while on x86_64 it's GR64. 1621 for (unsigned i = 0; i != MVT::VALUETYPE_SIZE; ++i) { 1622 const TargetRegisterClass* RRC; 1623 uint8_t Cost; 1624 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i); 1625 RepRegClassForVT[i] = RRC; 1626 RepRegClassCostForVT[i] = Cost; 1627 } 1628 } 1629 1630 EVT TargetLoweringBase::getSetCCResultType(const DataLayout &DL, LLVMContext &, 1631 EVT VT) const { 1632 assert(!VT.isVector() && "No default SetCC type for vectors!"); 1633 return getPointerTy(DL).SimpleTy; 1634 } 1635 1636 MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const { 1637 return MVT::i32; // return the default value 1638 } 1639 1640 /// getVectorTypeBreakdown - Vector types are broken down into some number of 1641 /// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 1642 /// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. 1643 /// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. 1644 /// 1645 /// This method returns the number of registers needed, and the VT for each 1646 /// register. It also returns the VT and quantity of the intermediate values 1647 /// before they are promoted/expanded. 1648 unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, 1649 EVT VT, EVT &IntermediateVT, 1650 unsigned &NumIntermediates, 1651 MVT &RegisterVT) const { 1652 ElementCount EltCnt = VT.getVectorElementCount(); 1653 1654 // If there is a wider vector type with the same element type as this one, 1655 // or a promoted vector type that has the same number of elements which 1656 // are wider, then we should convert to that legal vector type. 1657 // This handles things like <2 x float> -> <4 x float> and 1658 // <4 x i1> -> <4 x i32>. 1659 LegalizeTypeAction TA = getTypeAction(Context, VT); 1660 if (!EltCnt.isScalar() && 1661 (TA == TypeWidenVector || TA == TypePromoteInteger)) { 1662 EVT RegisterEVT = getTypeToTransformTo(Context, VT); 1663 if (isTypeLegal(RegisterEVT)) { 1664 IntermediateVT = RegisterEVT; 1665 RegisterVT = RegisterEVT.getSimpleVT(); 1666 NumIntermediates = 1; 1667 return 1; 1668 } 1669 } 1670 1671 // Figure out the right, legal destination reg to copy into. 1672 EVT EltTy = VT.getVectorElementType(); 1673 1674 unsigned NumVectorRegs = 1; 1675 1676 // Scalable vectors cannot be scalarized, so handle the legalisation of the 1677 // types like done elsewhere in SelectionDAG. 1678 if (EltCnt.isScalable()) { 1679 LegalizeKind LK; 1680 EVT PartVT = VT; 1681 do { 1682 // Iterate until we've found a legal (part) type to hold VT. 1683 LK = getTypeConversion(Context, PartVT); 1684 PartVT = LK.second; 1685 } while (LK.first != TypeLegal); 1686 1687 if (!PartVT.isVector()) { 1688 report_fatal_error( 1689 "Don't know how to legalize this scalable vector type"); 1690 } 1691 1692 NumIntermediates = 1693 divideCeil(VT.getVectorElementCount().getKnownMinValue(), 1694 PartVT.getVectorElementCount().getKnownMinValue()); 1695 IntermediateVT = PartVT; 1696 RegisterVT = getRegisterType(Context, IntermediateVT); 1697 return NumIntermediates; 1698 } 1699 1700 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally 1701 // we could break down into LHS/RHS like LegalizeDAG does. 1702 if (!isPowerOf2_32(EltCnt.getKnownMinValue())) { 1703 NumVectorRegs = EltCnt.getKnownMinValue(); 1704 EltCnt = ElementCount::getFixed(1); 1705 } 1706 1707 // Divide the input until we get to a supported size. This will always 1708 // end with a scalar if the target doesn't support vectors. 1709 while (EltCnt.getKnownMinValue() > 1 && 1710 !isTypeLegal(EVT::getVectorVT(Context, EltTy, EltCnt))) { 1711 EltCnt = EltCnt.divideCoefficientBy(2); 1712 NumVectorRegs <<= 1; 1713 } 1714 1715 NumIntermediates = NumVectorRegs; 1716 1717 EVT NewVT = EVT::getVectorVT(Context, EltTy, EltCnt); 1718 if (!isTypeLegal(NewVT)) 1719 NewVT = EltTy; 1720 IntermediateVT = NewVT; 1721 1722 MVT DestVT = getRegisterType(Context, NewVT); 1723 RegisterVT = DestVT; 1724 1725 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. 1726 TypeSize NewVTSize = NewVT.getSizeInBits(); 1727 // Convert sizes such as i33 to i64. 1728 if (!llvm::has_single_bit<uint32_t>(NewVTSize.getKnownMinValue())) 1729 NewVTSize = NewVTSize.coefficientNextPowerOf2(); 1730 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits()); 1731 } 1732 1733 // Otherwise, promotion or legal types use the same number of registers as 1734 // the vector decimated to the appropriate level. 1735 return NumVectorRegs; 1736 } 1737 1738 bool TargetLoweringBase::isSuitableForJumpTable(const SwitchInst *SI, 1739 uint64_t NumCases, 1740 uint64_t Range, 1741 ProfileSummaryInfo *PSI, 1742 BlockFrequencyInfo *BFI) const { 1743 // FIXME: This function check the maximum table size and density, but the 1744 // minimum size is not checked. It would be nice if the minimum size is 1745 // also combined within this function. Currently, the minimum size check is 1746 // performed in findJumpTable() in SelectionDAGBuiler and 1747 // getEstimatedNumberOfCaseClusters() in BasicTTIImpl. 1748 const bool OptForSize = 1749 SI->getParent()->getParent()->hasOptSize() || 1750 llvm::shouldOptimizeForSize(SI->getParent(), PSI, BFI); 1751 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize); 1752 const unsigned MaxJumpTableSize = getMaximumJumpTableSize(); 1753 1754 // Check whether the number of cases is small enough and 1755 // the range is dense enough for a jump table. 1756 return (OptForSize || Range <= MaxJumpTableSize) && 1757 (NumCases * 100 >= Range * MinDensity); 1758 } 1759 1760 MVT TargetLoweringBase::getPreferredSwitchConditionType(LLVMContext &Context, 1761 EVT ConditionVT) const { 1762 return getRegisterType(Context, ConditionVT); 1763 } 1764 1765 /// Get the EVTs and ArgFlags collections that represent the legalized return 1766 /// type of the given function. This does not require a DAG or a return value, 1767 /// and is suitable for use before any DAGs for the function are constructed. 1768 /// TODO: Move this out of TargetLowering.cpp. 1769 void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType, 1770 AttributeList attr, 1771 SmallVectorImpl<ISD::OutputArg> &Outs, 1772 const TargetLowering &TLI, const DataLayout &DL) { 1773 SmallVector<EVT, 4> ValueVTs; 1774 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs); 1775 unsigned NumValues = ValueVTs.size(); 1776 if (NumValues == 0) return; 1777 1778 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1779 EVT VT = ValueVTs[j]; 1780 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1781 1782 if (attr.hasRetAttr(Attribute::SExt)) 1783 ExtendKind = ISD::SIGN_EXTEND; 1784 else if (attr.hasRetAttr(Attribute::ZExt)) 1785 ExtendKind = ISD::ZERO_EXTEND; 1786 1787 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1788 VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind); 1789 1790 unsigned NumParts = 1791 TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); 1792 MVT PartVT = 1793 TLI.getRegisterTypeForCallingConv(ReturnType->getContext(), CC, VT); 1794 1795 // 'inreg' on function refers to return value 1796 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1797 if (attr.hasRetAttr(Attribute::InReg)) 1798 Flags.setInReg(); 1799 1800 // Propagate extension type if any 1801 if (attr.hasRetAttr(Attribute::SExt)) 1802 Flags.setSExt(); 1803 else if (attr.hasRetAttr(Attribute::ZExt)) 1804 Flags.setZExt(); 1805 1806 for (unsigned i = 0; i < NumParts; ++i) 1807 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isfixed=*/true, 0, 0)); 1808 } 1809 } 1810 1811 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1812 /// function arguments in the caller parameter area. This is the actual 1813 /// alignment, not its logarithm. 1814 uint64_t TargetLoweringBase::getByValTypeAlignment(Type *Ty, 1815 const DataLayout &DL) const { 1816 return DL.getABITypeAlign(Ty).value(); 1817 } 1818 1819 bool TargetLoweringBase::allowsMemoryAccessForAlignment( 1820 LLVMContext &Context, const DataLayout &DL, EVT VT, unsigned AddrSpace, 1821 Align Alignment, MachineMemOperand::Flags Flags, unsigned *Fast) const { 1822 // Check if the specified alignment is sufficient based on the data layout. 1823 // TODO: While using the data layout works in practice, a better solution 1824 // would be to implement this check directly (make this a virtual function). 1825 // For example, the ABI alignment may change based on software platform while 1826 // this function should only be affected by hardware implementation. 1827 Type *Ty = VT.getTypeForEVT(Context); 1828 if (VT.isZeroSized() || Alignment >= DL.getABITypeAlign(Ty)) { 1829 // Assume that an access that meets the ABI-specified alignment is fast. 1830 if (Fast != nullptr) 1831 *Fast = 1; 1832 return true; 1833 } 1834 1835 // This is a misaligned access. 1836 return allowsMisalignedMemoryAccesses(VT, AddrSpace, Alignment, Flags, Fast); 1837 } 1838 1839 bool TargetLoweringBase::allowsMemoryAccessForAlignment( 1840 LLVMContext &Context, const DataLayout &DL, EVT VT, 1841 const MachineMemOperand &MMO, unsigned *Fast) const { 1842 return allowsMemoryAccessForAlignment(Context, DL, VT, MMO.getAddrSpace(), 1843 MMO.getAlign(), MMO.getFlags(), Fast); 1844 } 1845 1846 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1847 const DataLayout &DL, EVT VT, 1848 unsigned AddrSpace, Align Alignment, 1849 MachineMemOperand::Flags Flags, 1850 unsigned *Fast) const { 1851 return allowsMemoryAccessForAlignment(Context, DL, VT, AddrSpace, Alignment, 1852 Flags, Fast); 1853 } 1854 1855 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1856 const DataLayout &DL, EVT VT, 1857 const MachineMemOperand &MMO, 1858 unsigned *Fast) const { 1859 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), 1860 MMO.getFlags(), Fast); 1861 } 1862 1863 bool TargetLoweringBase::allowsMemoryAccess(LLVMContext &Context, 1864 const DataLayout &DL, LLT Ty, 1865 const MachineMemOperand &MMO, 1866 unsigned *Fast) const { 1867 EVT VT = getApproximateEVTForLLT(Ty, DL, Context); 1868 return allowsMemoryAccess(Context, DL, VT, MMO.getAddrSpace(), MMO.getAlign(), 1869 MMO.getFlags(), Fast); 1870 } 1871 1872 //===----------------------------------------------------------------------===// 1873 // TargetTransformInfo Helpers 1874 //===----------------------------------------------------------------------===// 1875 1876 int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const { 1877 enum InstructionOpcodes { 1878 #define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM, 1879 #define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM 1880 #include "llvm/IR/Instruction.def" 1881 }; 1882 switch (static_cast<InstructionOpcodes>(Opcode)) { 1883 case Ret: return 0; 1884 case Br: return 0; 1885 case Switch: return 0; 1886 case IndirectBr: return 0; 1887 case Invoke: return 0; 1888 case CallBr: return 0; 1889 case Resume: return 0; 1890 case Unreachable: return 0; 1891 case CleanupRet: return 0; 1892 case CatchRet: return 0; 1893 case CatchPad: return 0; 1894 case CatchSwitch: return 0; 1895 case CleanupPad: return 0; 1896 case FNeg: return ISD::FNEG; 1897 case Add: return ISD::ADD; 1898 case FAdd: return ISD::FADD; 1899 case Sub: return ISD::SUB; 1900 case FSub: return ISD::FSUB; 1901 case Mul: return ISD::MUL; 1902 case FMul: return ISD::FMUL; 1903 case UDiv: return ISD::UDIV; 1904 case SDiv: return ISD::SDIV; 1905 case FDiv: return ISD::FDIV; 1906 case URem: return ISD::UREM; 1907 case SRem: return ISD::SREM; 1908 case FRem: return ISD::FREM; 1909 case Shl: return ISD::SHL; 1910 case LShr: return ISD::SRL; 1911 case AShr: return ISD::SRA; 1912 case And: return ISD::AND; 1913 case Or: return ISD::OR; 1914 case Xor: return ISD::XOR; 1915 case Alloca: return 0; 1916 case Load: return ISD::LOAD; 1917 case Store: return ISD::STORE; 1918 case GetElementPtr: return 0; 1919 case Fence: return 0; 1920 case AtomicCmpXchg: return 0; 1921 case AtomicRMW: return 0; 1922 case Trunc: return ISD::TRUNCATE; 1923 case ZExt: return ISD::ZERO_EXTEND; 1924 case SExt: return ISD::SIGN_EXTEND; 1925 case FPToUI: return ISD::FP_TO_UINT; 1926 case FPToSI: return ISD::FP_TO_SINT; 1927 case UIToFP: return ISD::UINT_TO_FP; 1928 case SIToFP: return ISD::SINT_TO_FP; 1929 case FPTrunc: return ISD::FP_ROUND; 1930 case FPExt: return ISD::FP_EXTEND; 1931 case PtrToInt: return ISD::BITCAST; 1932 case IntToPtr: return ISD::BITCAST; 1933 case BitCast: return ISD::BITCAST; 1934 case AddrSpaceCast: return ISD::ADDRSPACECAST; 1935 case ICmp: return ISD::SETCC; 1936 case FCmp: return ISD::SETCC; 1937 case PHI: return 0; 1938 case Call: return 0; 1939 case Select: return ISD::SELECT; 1940 case UserOp1: return 0; 1941 case UserOp2: return 0; 1942 case VAArg: return 0; 1943 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT; 1944 case InsertElement: return ISD::INSERT_VECTOR_ELT; 1945 case ShuffleVector: return ISD::VECTOR_SHUFFLE; 1946 case ExtractValue: return ISD::MERGE_VALUES; 1947 case InsertValue: return ISD::MERGE_VALUES; 1948 case LandingPad: return 0; 1949 case Freeze: return ISD::FREEZE; 1950 } 1951 1952 llvm_unreachable("Unknown instruction type encountered!"); 1953 } 1954 1955 Value * 1956 TargetLoweringBase::getDefaultSafeStackPointerLocation(IRBuilderBase &IRB, 1957 bool UseTLS) const { 1958 // compiler-rt provides a variable with a magic name. Targets that do not 1959 // link with compiler-rt may also provide such a variable. 1960 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1961 const char *UnsafeStackPtrVar = "__safestack_unsafe_stack_ptr"; 1962 auto UnsafeStackPtr = 1963 dyn_cast_or_null<GlobalVariable>(M->getNamedValue(UnsafeStackPtrVar)); 1964 1965 Type *StackPtrTy = PointerType::getUnqual(M->getContext()); 1966 1967 if (!UnsafeStackPtr) { 1968 auto TLSModel = UseTLS ? 1969 GlobalValue::InitialExecTLSModel : 1970 GlobalValue::NotThreadLocal; 1971 // The global variable is not defined yet, define it ourselves. 1972 // We use the initial-exec TLS model because we do not support the 1973 // variable living anywhere other than in the main executable. 1974 UnsafeStackPtr = new GlobalVariable( 1975 *M, StackPtrTy, false, GlobalValue::ExternalLinkage, nullptr, 1976 UnsafeStackPtrVar, nullptr, TLSModel); 1977 } else { 1978 // The variable exists, check its type and attributes. 1979 if (UnsafeStackPtr->getValueType() != StackPtrTy) 1980 report_fatal_error(Twine(UnsafeStackPtrVar) + " must have void* type"); 1981 if (UseTLS != UnsafeStackPtr->isThreadLocal()) 1982 report_fatal_error(Twine(UnsafeStackPtrVar) + " must " + 1983 (UseTLS ? "" : "not ") + "be thread-local"); 1984 } 1985 return UnsafeStackPtr; 1986 } 1987 1988 Value * 1989 TargetLoweringBase::getSafeStackPointerLocation(IRBuilderBase &IRB) const { 1990 if (!TM.getTargetTriple().isAndroid()) 1991 return getDefaultSafeStackPointerLocation(IRB, true); 1992 1993 // Android provides a libc function to retrieve the address of the current 1994 // thread's unsafe stack pointer. 1995 Module *M = IRB.GetInsertBlock()->getParent()->getParent(); 1996 auto *PtrTy = PointerType::getUnqual(M->getContext()); 1997 FunctionCallee Fn = 1998 M->getOrInsertFunction("__safestack_pointer_address", PtrTy); 1999 return IRB.CreateCall(Fn); 2000 } 2001 2002 //===----------------------------------------------------------------------===// 2003 // Loop Strength Reduction hooks 2004 //===----------------------------------------------------------------------===// 2005 2006 /// isLegalAddressingMode - Return true if the addressing mode represented 2007 /// by AM is legal for this target, for a load/store of the specified type. 2008 bool TargetLoweringBase::isLegalAddressingMode(const DataLayout &DL, 2009 const AddrMode &AM, Type *Ty, 2010 unsigned AS, Instruction *I) const { 2011 // The default implementation of this implements a conservative RISCy, r+r and 2012 // r+i addr mode. 2013 2014 // Allows a sign-extended 16-bit immediate field. 2015 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) 2016 return false; 2017 2018 // No global is ever allowed as a base. 2019 if (AM.BaseGV) 2020 return false; 2021 2022 // Only support r+r, 2023 switch (AM.Scale) { 2024 case 0: // "r+i" or just "i", depending on HasBaseReg. 2025 break; 2026 case 1: 2027 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. 2028 return false; 2029 // Otherwise we have r+r or r+i. 2030 break; 2031 case 2: 2032 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. 2033 return false; 2034 // Allow 2*r as r+r. 2035 break; 2036 default: // Don't allow n * r 2037 return false; 2038 } 2039 2040 return true; 2041 } 2042 2043 //===----------------------------------------------------------------------===// 2044 // Stack Protector 2045 //===----------------------------------------------------------------------===// 2046 2047 // For OpenBSD return its special guard variable. Otherwise return nullptr, 2048 // so that SelectionDAG handle SSP. 2049 Value *TargetLoweringBase::getIRStackGuard(IRBuilderBase &IRB) const { 2050 if (getTargetMachine().getTargetTriple().isOSOpenBSD()) { 2051 Module &M = *IRB.GetInsertBlock()->getParent()->getParent(); 2052 PointerType *PtrTy = PointerType::getUnqual(M.getContext()); 2053 Constant *C = M.getOrInsertGlobal("__guard_local", PtrTy); 2054 if (GlobalVariable *G = dyn_cast_or_null<GlobalVariable>(C)) 2055 G->setVisibility(GlobalValue::HiddenVisibility); 2056 return C; 2057 } 2058 return nullptr; 2059 } 2060 2061 // Currently only support "standard" __stack_chk_guard. 2062 // TODO: add LOAD_STACK_GUARD support. 2063 void TargetLoweringBase::insertSSPDeclarations(Module &M) const { 2064 if (!M.getNamedValue("__stack_chk_guard")) { 2065 auto *GV = new GlobalVariable(M, PointerType::getUnqual(M.getContext()), 2066 false, GlobalVariable::ExternalLinkage, 2067 nullptr, "__stack_chk_guard"); 2068 2069 // FreeBSD has "__stack_chk_guard" defined externally on libc.so 2070 if (M.getDirectAccessExternalData() && 2071 !TM.getTargetTriple().isWindowsGNUEnvironment() && 2072 !TM.getTargetTriple().isOSFreeBSD() && 2073 (!TM.getTargetTriple().isOSDarwin() || 2074 TM.getRelocationModel() == Reloc::Static)) 2075 GV->setDSOLocal(true); 2076 } 2077 } 2078 2079 // Currently only support "standard" __stack_chk_guard. 2080 // TODO: add LOAD_STACK_GUARD support. 2081 Value *TargetLoweringBase::getSDagStackGuard(const Module &M) const { 2082 return M.getNamedValue("__stack_chk_guard"); 2083 } 2084 2085 Function *TargetLoweringBase::getSSPStackGuardCheck(const Module &M) const { 2086 return nullptr; 2087 } 2088 2089 unsigned TargetLoweringBase::getMinimumJumpTableEntries() const { 2090 return MinimumJumpTableEntries; 2091 } 2092 2093 void TargetLoweringBase::setMinimumJumpTableEntries(unsigned Val) { 2094 MinimumJumpTableEntries = Val; 2095 } 2096 2097 unsigned TargetLoweringBase::getMinimumJumpTableDensity(bool OptForSize) const { 2098 return OptForSize ? OptsizeJumpTableDensity : JumpTableDensity; 2099 } 2100 2101 unsigned TargetLoweringBase::getMaximumJumpTableSize() const { 2102 return MaximumJumpTableSize; 2103 } 2104 2105 void TargetLoweringBase::setMaximumJumpTableSize(unsigned Val) { 2106 MaximumJumpTableSize = Val; 2107 } 2108 2109 bool TargetLoweringBase::isJumpTableRelative() const { 2110 return getTargetMachine().isPositionIndependent(); 2111 } 2112 2113 Align TargetLoweringBase::getPrefLoopAlignment(MachineLoop *ML) const { 2114 if (TM.Options.LoopAlignment) 2115 return Align(TM.Options.LoopAlignment); 2116 return PrefLoopAlignment; 2117 } 2118 2119 unsigned TargetLoweringBase::getMaxPermittedBytesForAlignment( 2120 MachineBasicBlock *MBB) const { 2121 return MaxBytesForAlignment; 2122 } 2123 2124 //===----------------------------------------------------------------------===// 2125 // Reciprocal Estimates 2126 //===----------------------------------------------------------------------===// 2127 2128 /// Get the reciprocal estimate attribute string for a function that will 2129 /// override the target defaults. 2130 static StringRef getRecipEstimateForFunc(MachineFunction &MF) { 2131 const Function &F = MF.getFunction(); 2132 return F.getFnAttribute("reciprocal-estimates").getValueAsString(); 2133 } 2134 2135 /// Construct a string for the given reciprocal operation of the given type. 2136 /// This string should match the corresponding option to the front-end's 2137 /// "-mrecip" flag assuming those strings have been passed through in an 2138 /// attribute string. For example, "vec-divf" for a division of a vXf32. 2139 static std::string getReciprocalOpName(bool IsSqrt, EVT VT) { 2140 std::string Name = VT.isVector() ? "vec-" : ""; 2141 2142 Name += IsSqrt ? "sqrt" : "div"; 2143 2144 // TODO: Handle other float types? 2145 if (VT.getScalarType() == MVT::f64) { 2146 Name += "d"; 2147 } else if (VT.getScalarType() == MVT::f16) { 2148 Name += "h"; 2149 } else { 2150 assert(VT.getScalarType() == MVT::f32 && 2151 "Unexpected FP type for reciprocal estimate"); 2152 Name += "f"; 2153 } 2154 2155 return Name; 2156 } 2157 2158 /// Return the character position and value (a single numeric character) of a 2159 /// customized refinement operation in the input string if it exists. Return 2160 /// false if there is no customized refinement step count. 2161 static bool parseRefinementStep(StringRef In, size_t &Position, 2162 uint8_t &Value) { 2163 const char RefStepToken = ':'; 2164 Position = In.find(RefStepToken); 2165 if (Position == StringRef::npos) 2166 return false; 2167 2168 StringRef RefStepString = In.substr(Position + 1); 2169 // Allow exactly one numeric character for the additional refinement 2170 // step parameter. 2171 if (RefStepString.size() == 1) { 2172 char RefStepChar = RefStepString[0]; 2173 if (isDigit(RefStepChar)) { 2174 Value = RefStepChar - '0'; 2175 return true; 2176 } 2177 } 2178 report_fatal_error("Invalid refinement step for -recip."); 2179 } 2180 2181 /// For the input attribute string, return one of the ReciprocalEstimate enum 2182 /// status values (enabled, disabled, or not specified) for this operation on 2183 /// the specified data type. 2184 static int getOpEnabled(bool IsSqrt, EVT VT, StringRef Override) { 2185 if (Override.empty()) 2186 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2187 2188 SmallVector<StringRef, 4> OverrideVector; 2189 Override.split(OverrideVector, ','); 2190 unsigned NumArgs = OverrideVector.size(); 2191 2192 // Check if "all", "none", or "default" was specified. 2193 if (NumArgs == 1) { 2194 // Look for an optional setting of the number of refinement steps needed 2195 // for this type of reciprocal operation. 2196 size_t RefPos; 2197 uint8_t RefSteps; 2198 if (parseRefinementStep(Override, RefPos, RefSteps)) { 2199 // Split the string for further processing. 2200 Override = Override.substr(0, RefPos); 2201 } 2202 2203 // All reciprocal types are enabled. 2204 if (Override == "all") 2205 return TargetLoweringBase::ReciprocalEstimate::Enabled; 2206 2207 // All reciprocal types are disabled. 2208 if (Override == "none") 2209 return TargetLoweringBase::ReciprocalEstimate::Disabled; 2210 2211 // Target defaults for enablement are used. 2212 if (Override == "default") 2213 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2214 } 2215 2216 // The attribute string may omit the size suffix ('f'/'d'). 2217 std::string VTName = getReciprocalOpName(IsSqrt, VT); 2218 std::string VTNameNoSize = VTName; 2219 VTNameNoSize.pop_back(); 2220 static const char DisabledPrefix = '!'; 2221 2222 for (StringRef RecipType : OverrideVector) { 2223 size_t RefPos; 2224 uint8_t RefSteps; 2225 if (parseRefinementStep(RecipType, RefPos, RefSteps)) 2226 RecipType = RecipType.substr(0, RefPos); 2227 2228 // Ignore the disablement token for string matching. 2229 bool IsDisabled = RecipType[0] == DisabledPrefix; 2230 if (IsDisabled) 2231 RecipType = RecipType.substr(1); 2232 2233 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2234 return IsDisabled ? TargetLoweringBase::ReciprocalEstimate::Disabled 2235 : TargetLoweringBase::ReciprocalEstimate::Enabled; 2236 } 2237 2238 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2239 } 2240 2241 /// For the input attribute string, return the customized refinement step count 2242 /// for this operation on the specified data type. If the step count does not 2243 /// exist, return the ReciprocalEstimate enum value for unspecified. 2244 static int getOpRefinementSteps(bool IsSqrt, EVT VT, StringRef Override) { 2245 if (Override.empty()) 2246 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2247 2248 SmallVector<StringRef, 4> OverrideVector; 2249 Override.split(OverrideVector, ','); 2250 unsigned NumArgs = OverrideVector.size(); 2251 2252 // Check if "all", "default", or "none" was specified. 2253 if (NumArgs == 1) { 2254 // Look for an optional setting of the number of refinement steps needed 2255 // for this type of reciprocal operation. 2256 size_t RefPos; 2257 uint8_t RefSteps; 2258 if (!parseRefinementStep(Override, RefPos, RefSteps)) 2259 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2260 2261 // Split the string for further processing. 2262 Override = Override.substr(0, RefPos); 2263 assert(Override != "none" && 2264 "Disabled reciprocals, but specifed refinement steps?"); 2265 2266 // If this is a general override, return the specified number of steps. 2267 if (Override == "all" || Override == "default") 2268 return RefSteps; 2269 } 2270 2271 // The attribute string may omit the size suffix ('f'/'d'). 2272 std::string VTName = getReciprocalOpName(IsSqrt, VT); 2273 std::string VTNameNoSize = VTName; 2274 VTNameNoSize.pop_back(); 2275 2276 for (StringRef RecipType : OverrideVector) { 2277 size_t RefPos; 2278 uint8_t RefSteps; 2279 if (!parseRefinementStep(RecipType, RefPos, RefSteps)) 2280 continue; 2281 2282 RecipType = RecipType.substr(0, RefPos); 2283 if (RecipType.equals(VTName) || RecipType.equals(VTNameNoSize)) 2284 return RefSteps; 2285 } 2286 2287 return TargetLoweringBase::ReciprocalEstimate::Unspecified; 2288 } 2289 2290 int TargetLoweringBase::getRecipEstimateSqrtEnabled(EVT VT, 2291 MachineFunction &MF) const { 2292 return getOpEnabled(true, VT, getRecipEstimateForFunc(MF)); 2293 } 2294 2295 int TargetLoweringBase::getRecipEstimateDivEnabled(EVT VT, 2296 MachineFunction &MF) const { 2297 return getOpEnabled(false, VT, getRecipEstimateForFunc(MF)); 2298 } 2299 2300 int TargetLoweringBase::getSqrtRefinementSteps(EVT VT, 2301 MachineFunction &MF) const { 2302 return getOpRefinementSteps(true, VT, getRecipEstimateForFunc(MF)); 2303 } 2304 2305 int TargetLoweringBase::getDivRefinementSteps(EVT VT, 2306 MachineFunction &MF) const { 2307 return getOpRefinementSteps(false, VT, getRecipEstimateForFunc(MF)); 2308 } 2309 2310 bool TargetLoweringBase::isLoadBitCastBeneficial( 2311 EVT LoadVT, EVT BitcastVT, const SelectionDAG &DAG, 2312 const MachineMemOperand &MMO) const { 2313 // Single-element vectors are scalarized, so we should generally avoid having 2314 // any memory operations on such types, as they would get scalarized too. 2315 if (LoadVT.isFixedLengthVector() && BitcastVT.isFixedLengthVector() && 2316 BitcastVT.getVectorNumElements() == 1) 2317 return false; 2318 2319 // Don't do if we could do an indexed load on the original type, but not on 2320 // the new one. 2321 if (!LoadVT.isSimple() || !BitcastVT.isSimple()) 2322 return true; 2323 2324 MVT LoadMVT = LoadVT.getSimpleVT(); 2325 2326 // Don't bother doing this if it's just going to be promoted again later, as 2327 // doing so might interfere with other combines. 2328 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote && 2329 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()) 2330 return false; 2331 2332 unsigned Fast = 0; 2333 return allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), BitcastVT, 2334 MMO, &Fast) && 2335 Fast; 2336 } 2337 2338 void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const { 2339 MF.getRegInfo().freezeReservedRegs(MF); 2340 } 2341 2342 MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags( 2343 const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC, 2344 const TargetLibraryInfo *LibInfo) const { 2345 MachineMemOperand::Flags Flags = MachineMemOperand::MOLoad; 2346 if (LI.isVolatile()) 2347 Flags |= MachineMemOperand::MOVolatile; 2348 2349 if (LI.hasMetadata(LLVMContext::MD_nontemporal)) 2350 Flags |= MachineMemOperand::MONonTemporal; 2351 2352 if (LI.hasMetadata(LLVMContext::MD_invariant_load)) 2353 Flags |= MachineMemOperand::MOInvariant; 2354 2355 if (isDereferenceableAndAlignedPointer(LI.getPointerOperand(), LI.getType(), 2356 LI.getAlign(), DL, &LI, AC, 2357 /*DT=*/nullptr, LibInfo)) 2358 Flags |= MachineMemOperand::MODereferenceable; 2359 2360 Flags |= getTargetMMOFlags(LI); 2361 return Flags; 2362 } 2363 2364 MachineMemOperand::Flags 2365 TargetLoweringBase::getStoreMemOperandFlags(const StoreInst &SI, 2366 const DataLayout &DL) const { 2367 MachineMemOperand::Flags Flags = MachineMemOperand::MOStore; 2368 2369 if (SI.isVolatile()) 2370 Flags |= MachineMemOperand::MOVolatile; 2371 2372 if (SI.hasMetadata(LLVMContext::MD_nontemporal)) 2373 Flags |= MachineMemOperand::MONonTemporal; 2374 2375 // FIXME: Not preserving dereferenceable 2376 Flags |= getTargetMMOFlags(SI); 2377 return Flags; 2378 } 2379 2380 MachineMemOperand::Flags 2381 TargetLoweringBase::getAtomicMemOperandFlags(const Instruction &AI, 2382 const DataLayout &DL) const { 2383 auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOStore; 2384 2385 if (const AtomicRMWInst *RMW = dyn_cast<AtomicRMWInst>(&AI)) { 2386 if (RMW->isVolatile()) 2387 Flags |= MachineMemOperand::MOVolatile; 2388 } else if (const AtomicCmpXchgInst *CmpX = dyn_cast<AtomicCmpXchgInst>(&AI)) { 2389 if (CmpX->isVolatile()) 2390 Flags |= MachineMemOperand::MOVolatile; 2391 } else 2392 llvm_unreachable("not an atomic instruction"); 2393 2394 // FIXME: Not preserving dereferenceable 2395 Flags |= getTargetMMOFlags(AI); 2396 return Flags; 2397 } 2398 2399 Instruction *TargetLoweringBase::emitLeadingFence(IRBuilderBase &Builder, 2400 Instruction *Inst, 2401 AtomicOrdering Ord) const { 2402 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore()) 2403 return Builder.CreateFence(Ord); 2404 else 2405 return nullptr; 2406 } 2407 2408 Instruction *TargetLoweringBase::emitTrailingFence(IRBuilderBase &Builder, 2409 Instruction *Inst, 2410 AtomicOrdering Ord) const { 2411 if (isAcquireOrStronger(Ord)) 2412 return Builder.CreateFence(Ord); 2413 else 2414 return nullptr; 2415 } 2416 2417 //===----------------------------------------------------------------------===// 2418 // GlobalISel Hooks 2419 //===----------------------------------------------------------------------===// 2420 2421 bool TargetLoweringBase::shouldLocalize(const MachineInstr &MI, 2422 const TargetTransformInfo *TTI) const { 2423 auto &MF = *MI.getMF(); 2424 auto &MRI = MF.getRegInfo(); 2425 // Assuming a spill and reload of a value has a cost of 1 instruction each, 2426 // this helper function computes the maximum number of uses we should consider 2427 // for remat. E.g. on arm64 global addresses take 2 insts to materialize. We 2428 // break even in terms of code size when the original MI has 2 users vs 2429 // choosing to potentially spill. Any more than 2 users we we have a net code 2430 // size increase. This doesn't take into account register pressure though. 2431 auto maxUses = [](unsigned RematCost) { 2432 // A cost of 1 means remats are basically free. 2433 if (RematCost == 1) 2434 return std::numeric_limits<unsigned>::max(); 2435 if (RematCost == 2) 2436 return 2U; 2437 2438 // Remat is too expensive, only sink if there's one user. 2439 if (RematCost > 2) 2440 return 1U; 2441 llvm_unreachable("Unexpected remat cost"); 2442 }; 2443 2444 switch (MI.getOpcode()) { 2445 default: 2446 return false; 2447 // Constants-like instructions should be close to their users. 2448 // We don't want long live-ranges for them. 2449 case TargetOpcode::G_CONSTANT: 2450 case TargetOpcode::G_FCONSTANT: 2451 case TargetOpcode::G_FRAME_INDEX: 2452 case TargetOpcode::G_INTTOPTR: 2453 return true; 2454 case TargetOpcode::G_GLOBAL_VALUE: { 2455 unsigned RematCost = TTI->getGISelRematGlobalCost(); 2456 Register Reg = MI.getOperand(0).getReg(); 2457 unsigned MaxUses = maxUses(RematCost); 2458 if (MaxUses == UINT_MAX) 2459 return true; // Remats are "free" so always localize. 2460 return MRI.hasAtMostUserInstrs(Reg, MaxUses); 2461 } 2462 } 2463 } 2464