1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RegisterClassInfo class which provides dynamic 10 // information about target register classes. Callee-saved vs. caller-saved and 11 // reserved registers depend on calling conventions and other dynamic 12 // information, so some things cannot be determined statically. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/CodeGen/RegisterClassInfo.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/BitVector.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/TargetRegisterInfo.h" 23 #include "llvm/CodeGen/TargetSubtargetInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/Support/CommandLine.h" 26 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <algorithm> 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "regalloc" 35 36 static cl::opt<unsigned> 37 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), 38 cl::desc("Limit all regclasses to N registers")); 39 40 RegisterClassInfo::RegisterClassInfo() = default; 41 42 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { 43 bool Update = false; 44 MF = &mf; 45 46 auto &STI = MF->getSubtarget(); 47 48 // Allocate new array the first time we see a new target. 49 if (STI.getRegisterInfo() != TRI) { 50 TRI = STI.getRegisterInfo(); 51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 52 Update = true; 53 } 54 55 // Test if CSRs have changed from the previous function. 56 const MachineRegisterInfo &MRI = MF->getRegInfo(); 57 const MCPhysReg *CSR = MRI.getCalleeSavedRegs(); 58 bool CSRChanged = true; 59 if (!Update) { 60 CSRChanged = false; 61 size_t LastSize = LastCalleeSavedRegs.size(); 62 for (unsigned I = 0;; ++I) { 63 if (CSR[I] == 0) { 64 CSRChanged = I != LastSize; 65 break; 66 } 67 if (I >= LastSize) { 68 CSRChanged = true; 69 break; 70 } 71 if (CSR[I] != LastCalleeSavedRegs[I]) { 72 CSRChanged = true; 73 break; 74 } 75 } 76 } 77 78 // Get the callee saved registers. 79 if (CSRChanged) { 80 LastCalleeSavedRegs.clear(); 81 // Build a CSRAlias map. Every CSR alias saves the last 82 // overlapping CSR. 83 CalleeSavedAliases.assign(TRI->getNumRegUnits(), 0); 84 for (const MCPhysReg *I = CSR; *I; ++I) { 85 for (MCRegUnitIterator UI(*I, TRI); UI.isValid(); ++UI) 86 CalleeSavedAliases[*UI] = *I; 87 LastCalleeSavedRegs.push_back(*I); 88 } 89 90 Update = true; 91 } 92 93 // Even if CSR list is same, we could have had a different allocation order 94 // if ignoreCSRForAllocationOrder is evaluated differently. 95 BitVector CSRHintsForAllocOrder(TRI->getNumRegs()); 96 for (MCPhysReg I = 1, E = TRI->getNumRegs(); I != E; ++I) 97 CSRHintsForAllocOrder[I] = STI.ignoreCSRForAllocationOrder(mf, I); 98 if (IgnoreCSRForAllocOrder != CSRHintsForAllocOrder) { 99 Update = true; 100 IgnoreCSRForAllocOrder = CSRHintsForAllocOrder; 101 } 102 103 RegCosts = TRI->getRegisterCosts(*MF); 104 105 // Different reserved registers? 106 const BitVector &RR = MF->getRegInfo().getReservedRegs(); 107 if (Reserved.size() != RR.size() || RR != Reserved) { 108 Update = true; 109 Reserved = RR; 110 } 111 112 // Invalidate cached information from previous function. 113 if (Update) { 114 unsigned NumPSets = TRI->getNumRegPressureSets(); 115 PSetLimits.reset(new unsigned[NumPSets]); 116 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0); 117 ++Tag; 118 } 119 } 120 121 /// compute - Compute the preferred allocation order for RC with reserved 122 /// registers filtered out. Volatile registers come first followed by CSR 123 /// aliases ordered according to the CSR order specified by the target. 124 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 125 assert(RC && "no register class given"); 126 RCInfo &RCI = RegClass[RC->getID()]; 127 auto &STI = MF->getSubtarget(); 128 129 // Raw register count, including all reserved regs. 130 unsigned NumRegs = RC->getNumRegs(); 131 132 if (!RCI.Order) 133 RCI.Order.reset(new MCPhysReg[NumRegs]); 134 135 unsigned N = 0; 136 SmallVector<MCPhysReg, 16> CSRAlias; 137 uint8_t MinCost = uint8_t(~0u); 138 uint8_t LastCost = uint8_t(~0u); 139 unsigned LastCostChange = 0; 140 141 // FIXME: Once targets reserve registers instead of removing them from the 142 // allocation order, we can simply use begin/end here. 143 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); 144 for (unsigned PhysReg : RawOrder) { 145 // Remove reserved registers from the allocation order. 146 if (Reserved.test(PhysReg)) 147 continue; 148 uint8_t Cost = RegCosts[PhysReg]; 149 MinCost = std::min(MinCost, Cost); 150 151 if (getLastCalleeSavedAlias(PhysReg) && 152 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) 153 // PhysReg aliases a CSR, save it for later. 154 CSRAlias.push_back(PhysReg); 155 else { 156 if (Cost != LastCost) 157 LastCostChange = N; 158 RCI.Order[N++] = PhysReg; 159 LastCost = Cost; 160 } 161 } 162 RCI.NumRegs = N + CSRAlias.size(); 163 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 164 165 // CSR aliases go after the volatile registers, preserve the target's order. 166 for (unsigned PhysReg : CSRAlias) { 167 uint8_t Cost = RegCosts[PhysReg]; 168 if (Cost != LastCost) 169 LastCostChange = N; 170 RCI.Order[N++] = PhysReg; 171 LastCost = Cost; 172 } 173 174 // Register allocator stress test. Clip register class to N registers. 175 if (StressRA && RCI.NumRegs > StressRA) 176 RCI.NumRegs = StressRA; 177 178 // Check if RC is a proper sub-class. 179 if (const TargetRegisterClass *Super = 180 TRI->getLargestLegalSuperClass(RC, *MF)) 181 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 182 RCI.ProperSubClass = true; 183 184 RCI.MinCost = MinCost; 185 RCI.LastCostChange = LastCostChange; 186 187 LLVM_DEBUG({ 188 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; 189 for (unsigned I = 0; I != RCI.NumRegs; ++I) 190 dbgs() << ' ' << printReg(RCI.Order[I], TRI); 191 dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n"); 192 }); 193 194 // RCI is now up-to-date. 195 RCI.Tag = Tag; 196 } 197 198 /// This is not accurate because two overlapping register sets may have some 199 /// nonoverlapping reserved registers. However, computing the allocation order 200 /// for all register classes would be too expensive. 201 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const { 202 const TargetRegisterClass *RC = nullptr; 203 unsigned NumRCUnits = 0; 204 for (const TargetRegisterClass *C : TRI->regclasses()) { 205 const int *PSetID = TRI->getRegClassPressureSets(C); 206 for (; *PSetID != -1; ++PSetID) { 207 if ((unsigned)*PSetID == Idx) 208 break; 209 } 210 if (*PSetID == -1) 211 continue; 212 213 // Found a register class that counts against this pressure set. 214 // For efficiency, only compute the set order for the largest set. 215 unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit; 216 if (!RC || NUnits > NumRCUnits) { 217 RC = C; 218 NumRCUnits = NUnits; 219 } 220 } 221 assert(RC && "Failed to find register class"); 222 compute(RC); 223 unsigned NAllocatableRegs = getNumAllocatableRegs(RC); 224 unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx); 225 // If all the regs are reserved, return raw RegPressureSetLimit. 226 // One example is VRSAVERC in PowerPC. 227 // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit 228 // return non-zero value. 229 if (NAllocatableRegs == 0) 230 return RegPressureSetLimit; 231 unsigned NReserved = RC->getNumRegs() - NAllocatableRegs; 232 return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved; 233 } 234