1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RegisterClassInfo class which provides dynamic 10 // information about target register classes. Callee-saved vs. caller-saved and 11 // reserved registers depend on calling conventions and other dynamic 12 // information, so some things cannot be determined statically. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/CodeGen/RegisterClassInfo.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/BitVector.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/TargetFrameLowering.h" 23 #include "llvm/CodeGen/TargetRegisterInfo.h" 24 #include "llvm/CodeGen/TargetSubtargetInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/Support/CommandLine.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <algorithm> 30 #include <cassert> 31 #include <cstdint> 32 33 using namespace llvm; 34 35 #define DEBUG_TYPE "regalloc" 36 37 static cl::opt<unsigned> 38 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), 39 cl::desc("Limit all regclasses to N registers")); 40 41 RegisterClassInfo::RegisterClassInfo() = default; 42 43 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { 44 bool Update = false; 45 MF = &mf; 46 47 // Allocate new array the first time we see a new target. 48 if (MF->getSubtarget().getRegisterInfo() != TRI) { 49 TRI = MF->getSubtarget().getRegisterInfo(); 50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 51 Update = true; 52 } 53 54 // Does this MF have different CSRs? 55 assert(TRI && "no register info set"); 56 57 // Get the callee saved registers. 58 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs(); 59 if (Update || CSR != CalleeSavedRegs) { 60 // Build a CSRAlias map. Every CSR alias saves the last 61 // overlapping CSR. 62 CalleeSavedAliases.assign(TRI->getNumRegs(), 0); 63 for (const MCPhysReg *I = CSR; *I; ++I) 64 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) 65 CalleeSavedAliases[*AI] = *I; 66 67 Update = true; 68 } 69 CalleeSavedRegs = CSR; 70 71 RegCosts = TRI->getRegisterCosts(*MF); 72 73 // Different reserved registers? 74 const BitVector &RR = MF->getRegInfo().getReservedRegs(); 75 if (Reserved.size() != RR.size() || RR != Reserved) { 76 Update = true; 77 Reserved = RR; 78 } 79 80 // Invalidate cached information from previous function. 81 if (Update) { 82 unsigned NumPSets = TRI->getNumRegPressureSets(); 83 PSetLimits.reset(new unsigned[NumPSets]); 84 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0); 85 ++Tag; 86 } 87 } 88 89 /// compute - Compute the preferred allocation order for RC with reserved 90 /// registers filtered out. Volatile registers come first followed by CSR 91 /// aliases ordered according to the CSR order specified by the target. 92 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 93 assert(RC && "no register class given"); 94 RCInfo &RCI = RegClass[RC->getID()]; 95 auto &STI = MF->getSubtarget(); 96 97 // Raw register count, including all reserved regs. 98 unsigned NumRegs = RC->getNumRegs(); 99 100 if (!RCI.Order) 101 RCI.Order.reset(new MCPhysReg[NumRegs]); 102 103 unsigned N = 0; 104 SmallVector<MCPhysReg, 16> CSRAlias; 105 uint8_t MinCost = uint8_t(~0u); 106 uint8_t LastCost = uint8_t(~0u); 107 unsigned LastCostChange = 0; 108 109 // FIXME: Once targets reserve registers instead of removing them from the 110 // allocation order, we can simply use begin/end here. 111 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); 112 for (unsigned PhysReg : RawOrder) { 113 // Remove reserved registers from the allocation order. 114 if (Reserved.test(PhysReg)) 115 continue; 116 uint8_t Cost = RegCosts[PhysReg]; 117 MinCost = std::min(MinCost, Cost); 118 119 if (CalleeSavedAliases[PhysReg] && 120 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) 121 // PhysReg aliases a CSR, save it for later. 122 CSRAlias.push_back(PhysReg); 123 else { 124 if (Cost != LastCost) 125 LastCostChange = N; 126 RCI.Order[N++] = PhysReg; 127 LastCost = Cost; 128 } 129 } 130 RCI.NumRegs = N + CSRAlias.size(); 131 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 132 133 // CSR aliases go after the volatile registers, preserve the target's order. 134 for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) { 135 unsigned PhysReg = CSRAlias[i]; 136 uint8_t Cost = RegCosts[PhysReg]; 137 if (Cost != LastCost) 138 LastCostChange = N; 139 RCI.Order[N++] = PhysReg; 140 LastCost = Cost; 141 } 142 143 // Register allocator stress test. Clip register class to N registers. 144 if (StressRA && RCI.NumRegs > StressRA) 145 RCI.NumRegs = StressRA; 146 147 // Check if RC is a proper sub-class. 148 if (const TargetRegisterClass *Super = 149 TRI->getLargestLegalSuperClass(RC, *MF)) 150 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 151 RCI.ProperSubClass = true; 152 153 RCI.MinCost = MinCost; 154 RCI.LastCostChange = LastCostChange; 155 156 LLVM_DEBUG({ 157 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; 158 for (unsigned I = 0; I != RCI.NumRegs; ++I) 159 dbgs() << ' ' << printReg(RCI.Order[I], TRI); 160 dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n"); 161 }); 162 163 // RCI is now up-to-date. 164 RCI.Tag = Tag; 165 } 166 167 /// This is not accurate because two overlapping register sets may have some 168 /// nonoverlapping reserved registers. However, computing the allocation order 169 /// for all register classes would be too expensive. 170 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const { 171 const TargetRegisterClass *RC = nullptr; 172 unsigned NumRCUnits = 0; 173 for (const TargetRegisterClass *C : TRI->regclasses()) { 174 const int *PSetID = TRI->getRegClassPressureSets(C); 175 for (; *PSetID != -1; ++PSetID) { 176 if ((unsigned)*PSetID == Idx) 177 break; 178 } 179 if (*PSetID == -1) 180 continue; 181 182 // Found a register class that counts against this pressure set. 183 // For efficiency, only compute the set order for the largest set. 184 unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit; 185 if (!RC || NUnits > NumRCUnits) { 186 RC = C; 187 NumRCUnits = NUnits; 188 } 189 } 190 assert(RC && "Failed to find register class"); 191 compute(RC); 192 unsigned NAllocatableRegs = getNumAllocatableRegs(RC); 193 unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx); 194 // If all the regs are reserved, return raw RegPressureSetLimit. 195 // One example is VRSAVERC in PowerPC. 196 // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit 197 // return non-zero value. 198 if (NAllocatableRegs == 0) 199 return RegPressureSetLimit; 200 unsigned NReserved = RC->getNumRegs() - NAllocatableRegs; 201 return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved; 202 } 203