1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RegisterClassInfo class which provides dynamic 10 // information about target register classes. Callee-saved vs. caller-saved and 11 // reserved registers depend on calling conventions and other dynamic 12 // information, so some things cannot be determined statically. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/CodeGen/RegisterClassInfo.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/BitVector.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/TargetRegisterInfo.h" 23 #include "llvm/CodeGen/TargetSubtargetInfo.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/Support/CommandLine.h" 26 #include "llvm/Support/Debug.h" 27 #include "llvm/Support/raw_ostream.h" 28 #include <algorithm> 29 #include <cassert> 30 #include <cstdint> 31 32 using namespace llvm; 33 34 #define DEBUG_TYPE "regalloc" 35 36 static cl::opt<unsigned> 37 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), 38 cl::desc("Limit all regclasses to N registers")); 39 40 RegisterClassInfo::RegisterClassInfo() = default; 41 42 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { 43 bool Update = false; 44 MF = &mf; 45 46 // Allocate new array the first time we see a new target. 47 if (MF->getSubtarget().getRegisterInfo() != TRI) { 48 TRI = MF->getSubtarget().getRegisterInfo(); 49 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 50 Update = true; 51 } 52 53 // Does this MF have different CSRs? 54 assert(TRI && "no register info set"); 55 56 // Get the callee saved registers. 57 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs(); 58 if (Update || CSR != CalleeSavedRegs) { 59 // Build a CSRAlias map. Every CSR alias saves the last 60 // overlapping CSR. 61 CalleeSavedAliases.assign(TRI->getNumRegs(), 0); 62 for (const MCPhysReg *I = CSR; *I; ++I) 63 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) 64 CalleeSavedAliases[*AI] = *I; 65 66 Update = true; 67 } 68 CalleeSavedRegs = CSR; 69 70 RegCosts = TRI->getRegisterCosts(*MF); 71 72 // Different reserved registers? 73 const BitVector &RR = MF->getRegInfo().getReservedRegs(); 74 if (Reserved.size() != RR.size() || RR != Reserved) { 75 Update = true; 76 Reserved = RR; 77 } 78 79 // Invalidate cached information from previous function. 80 if (Update) { 81 unsigned NumPSets = TRI->getNumRegPressureSets(); 82 PSetLimits.reset(new unsigned[NumPSets]); 83 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0); 84 ++Tag; 85 } 86 } 87 88 /// compute - Compute the preferred allocation order for RC with reserved 89 /// registers filtered out. Volatile registers come first followed by CSR 90 /// aliases ordered according to the CSR order specified by the target. 91 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 92 assert(RC && "no register class given"); 93 RCInfo &RCI = RegClass[RC->getID()]; 94 auto &STI = MF->getSubtarget(); 95 96 // Raw register count, including all reserved regs. 97 unsigned NumRegs = RC->getNumRegs(); 98 99 if (!RCI.Order) 100 RCI.Order.reset(new MCPhysReg[NumRegs]); 101 102 unsigned N = 0; 103 SmallVector<MCPhysReg, 16> CSRAlias; 104 uint8_t MinCost = uint8_t(~0u); 105 uint8_t LastCost = uint8_t(~0u); 106 unsigned LastCostChange = 0; 107 108 // FIXME: Once targets reserve registers instead of removing them from the 109 // allocation order, we can simply use begin/end here. 110 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); 111 for (unsigned PhysReg : RawOrder) { 112 // Remove reserved registers from the allocation order. 113 if (Reserved.test(PhysReg)) 114 continue; 115 uint8_t Cost = RegCosts[PhysReg]; 116 MinCost = std::min(MinCost, Cost); 117 118 if (CalleeSavedAliases[PhysReg] && 119 !STI.ignoreCSRForAllocationOrder(*MF, PhysReg)) 120 // PhysReg aliases a CSR, save it for later. 121 CSRAlias.push_back(PhysReg); 122 else { 123 if (Cost != LastCost) 124 LastCostChange = N; 125 RCI.Order[N++] = PhysReg; 126 LastCost = Cost; 127 } 128 } 129 RCI.NumRegs = N + CSRAlias.size(); 130 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 131 132 // CSR aliases go after the volatile registers, preserve the target's order. 133 for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) { 134 unsigned PhysReg = CSRAlias[i]; 135 uint8_t Cost = RegCosts[PhysReg]; 136 if (Cost != LastCost) 137 LastCostChange = N; 138 RCI.Order[N++] = PhysReg; 139 LastCost = Cost; 140 } 141 142 // Register allocator stress test. Clip register class to N registers. 143 if (StressRA && RCI.NumRegs > StressRA) 144 RCI.NumRegs = StressRA; 145 146 // Check if RC is a proper sub-class. 147 if (const TargetRegisterClass *Super = 148 TRI->getLargestLegalSuperClass(RC, *MF)) 149 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 150 RCI.ProperSubClass = true; 151 152 RCI.MinCost = MinCost; 153 RCI.LastCostChange = LastCostChange; 154 155 LLVM_DEBUG({ 156 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; 157 for (unsigned I = 0; I != RCI.NumRegs; ++I) 158 dbgs() << ' ' << printReg(RCI.Order[I], TRI); 159 dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n"); 160 }); 161 162 // RCI is now up-to-date. 163 RCI.Tag = Tag; 164 } 165 166 /// This is not accurate because two overlapping register sets may have some 167 /// nonoverlapping reserved registers. However, computing the allocation order 168 /// for all register classes would be too expensive. 169 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const { 170 const TargetRegisterClass *RC = nullptr; 171 unsigned NumRCUnits = 0; 172 for (const TargetRegisterClass *C : TRI->regclasses()) { 173 const int *PSetID = TRI->getRegClassPressureSets(C); 174 for (; *PSetID != -1; ++PSetID) { 175 if ((unsigned)*PSetID == Idx) 176 break; 177 } 178 if (*PSetID == -1) 179 continue; 180 181 // Found a register class that counts against this pressure set. 182 // For efficiency, only compute the set order for the largest set. 183 unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit; 184 if (!RC || NUnits > NumRCUnits) { 185 RC = C; 186 NumRCUnits = NUnits; 187 } 188 } 189 assert(RC && "Failed to find register class"); 190 compute(RC); 191 unsigned NAllocatableRegs = getNumAllocatableRegs(RC); 192 unsigned RegPressureSetLimit = TRI->getRegPressureSetLimit(*MF, Idx); 193 // If all the regs are reserved, return raw RegPressureSetLimit. 194 // One example is VRSAVERC in PowerPC. 195 // Avoid returning zero, getRegPressureSetLimit(Idx) assumes computePSetLimit 196 // return non-zero value. 197 if (NAllocatableRegs == 0) 198 return RegPressureSetLimit; 199 unsigned NReserved = RC->getNumRegs() - NAllocatableRegs; 200 return RegPressureSetLimit - TRI->getRegClassWeight(RC).RegWeight * NReserved; 201 } 202