1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the RegisterClassInfo class which provides dynamic 10 // information about target register classes. Callee-saved vs. caller-saved and 11 // reserved registers depend on calling conventions and other dynamic 12 // information, so some things cannot be determined statically. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "llvm/CodeGen/RegisterClassInfo.h" 17 #include "llvm/ADT/ArrayRef.h" 18 #include "llvm/ADT/BitVector.h" 19 #include "llvm/ADT/SmallVector.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/CodeGen/TargetFrameLowering.h" 23 #include "llvm/CodeGen/TargetRegisterInfo.h" 24 #include "llvm/CodeGen/TargetSubtargetInfo.h" 25 #include "llvm/MC/MCRegisterInfo.h" 26 #include "llvm/Support/CommandLine.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/raw_ostream.h" 29 #include <algorithm> 30 #include <cassert> 31 #include <cstdint> 32 33 using namespace llvm; 34 35 #define DEBUG_TYPE "regalloc" 36 37 static cl::opt<unsigned> 38 StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"), 39 cl::desc("Limit all regclasses to N registers")); 40 41 RegisterClassInfo::RegisterClassInfo() = default; 42 43 void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { 44 bool Update = false; 45 MF = &mf; 46 47 // Allocate new array the first time we see a new target. 48 if (MF->getSubtarget().getRegisterInfo() != TRI) { 49 TRI = MF->getSubtarget().getRegisterInfo(); 50 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); 51 Update = true; 52 } 53 54 // Does this MF have different CSRs? 55 assert(TRI && "no register info set"); 56 57 // Get the callee saved registers. 58 const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs(); 59 if (Update || CSR != CalleeSavedRegs) { 60 // Build a CSRAlias map. Every CSR alias saves the last 61 // overlapping CSR. 62 CalleeSavedAliases.resize(TRI->getNumRegs(), 0); 63 for (const MCPhysReg *I = CSR; *I; ++I) 64 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) 65 CalleeSavedAliases[*AI] = *I; 66 67 Update = true; 68 } 69 CalleeSavedRegs = CSR; 70 71 // Different reserved registers? 72 const BitVector &RR = MF->getRegInfo().getReservedRegs(); 73 if (Reserved.size() != RR.size() || RR != Reserved) { 74 Update = true; 75 Reserved = RR; 76 } 77 78 // Invalidate cached information from previous function. 79 if (Update) { 80 unsigned NumPSets = TRI->getNumRegPressureSets(); 81 PSetLimits.reset(new unsigned[NumPSets]); 82 std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0); 83 ++Tag; 84 } 85 } 86 87 /// compute - Compute the preferred allocation order for RC with reserved 88 /// registers filtered out. Volatile registers come first followed by CSR 89 /// aliases ordered according to the CSR order specified by the target. 90 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { 91 assert(RC && "no register class given"); 92 RCInfo &RCI = RegClass[RC->getID()]; 93 94 // Raw register count, including all reserved regs. 95 unsigned NumRegs = RC->getNumRegs(); 96 97 if (!RCI.Order) 98 RCI.Order.reset(new MCPhysReg[NumRegs]); 99 100 unsigned N = 0; 101 SmallVector<MCPhysReg, 16> CSRAlias; 102 unsigned MinCost = 0xff; 103 unsigned LastCost = ~0u; 104 unsigned LastCostChange = 0; 105 106 // FIXME: Once targets reserve registers instead of removing them from the 107 // allocation order, we can simply use begin/end here. 108 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF); 109 for (unsigned i = 0; i != RawOrder.size(); ++i) { 110 unsigned PhysReg = RawOrder[i]; 111 // Remove reserved registers from the allocation order. 112 if (Reserved.test(PhysReg)) 113 continue; 114 unsigned Cost = TRI->getCostPerUse(PhysReg); 115 MinCost = std::min(MinCost, Cost); 116 117 if (CalleeSavedAliases[PhysReg]) 118 // PhysReg aliases a CSR, save it for later. 119 CSRAlias.push_back(PhysReg); 120 else { 121 if (Cost != LastCost) 122 LastCostChange = N; 123 RCI.Order[N++] = PhysReg; 124 LastCost = Cost; 125 } 126 } 127 RCI.NumRegs = N + CSRAlias.size(); 128 assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); 129 130 // CSR aliases go after the volatile registers, preserve the target's order. 131 for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) { 132 unsigned PhysReg = CSRAlias[i]; 133 unsigned Cost = TRI->getCostPerUse(PhysReg); 134 if (Cost != LastCost) 135 LastCostChange = N; 136 RCI.Order[N++] = PhysReg; 137 LastCost = Cost; 138 } 139 140 // Register allocator stress test. Clip register class to N registers. 141 if (StressRA && RCI.NumRegs > StressRA) 142 RCI.NumRegs = StressRA; 143 144 // Check if RC is a proper sub-class. 145 if (const TargetRegisterClass *Super = 146 TRI->getLargestLegalSuperClass(RC, *MF)) 147 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs) 148 RCI.ProperSubClass = true; 149 150 RCI.MinCost = uint8_t(MinCost); 151 RCI.LastCostChange = LastCostChange; 152 153 LLVM_DEBUG({ 154 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["; 155 for (unsigned I = 0; I != RCI.NumRegs; ++I) 156 dbgs() << ' ' << printReg(RCI.Order[I], TRI); 157 dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n"); 158 }); 159 160 // RCI is now up-to-date. 161 RCI.Tag = Tag; 162 } 163 164 /// This is not accurate because two overlapping register sets may have some 165 /// nonoverlapping reserved registers. However, computing the allocation order 166 /// for all register classes would be too expensive. 167 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const { 168 const TargetRegisterClass *RC = nullptr; 169 unsigned NumRCUnits = 0; 170 for (const TargetRegisterClass *C : TRI->regclasses()) { 171 const int *PSetID = TRI->getRegClassPressureSets(C); 172 for (; *PSetID != -1; ++PSetID) { 173 if ((unsigned)*PSetID == Idx) 174 break; 175 } 176 if (*PSetID == -1) 177 continue; 178 179 // Found a register class that counts against this pressure set. 180 // For efficiency, only compute the set order for the largest set. 181 unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit; 182 if (!RC || NUnits > NumRCUnits) { 183 RC = C; 184 NumRCUnits = NUnits; 185 } 186 } 187 compute(RC); 188 unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC); 189 return TRI->getRegPressureSetLimit(*MF, Idx) - 190 TRI->getRegClassWeight(RC).RegWeight * NReserved; 191 } 192