1 //===---- ReachingDefAnalysis.cpp - Reaching Def Analysis ---*- C++ -*-----===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/ADT/SmallSet.h" 10 #include "llvm/CodeGen/LivePhysRegs.h" 11 #include "llvm/CodeGen/ReachingDefAnalysis.h" 12 #include "llvm/CodeGen/TargetRegisterInfo.h" 13 #include "llvm/CodeGen/TargetSubtargetInfo.h" 14 #include "llvm/Support/Debug.h" 15 16 using namespace llvm; 17 18 #define DEBUG_TYPE "reaching-deps-analysis" 19 20 char ReachingDefAnalysis::ID = 0; 21 INITIALIZE_PASS(ReachingDefAnalysis, DEBUG_TYPE, "ReachingDefAnalysis", false, 22 true) 23 24 bool isValidReg(const MachineOperand &MO) { 25 return MO.isReg() && MO.getReg(); 26 } 27 28 bool isValidRegUse(const MachineOperand &MO) { 29 return isValidReg(MO) && MO.isUse(); 30 } 31 32 bool isValidRegUseOf(const MachineOperand &MO, int PhysReg) { 33 return isValidRegUse(MO) && MO.getReg() == PhysReg; 34 } 35 36 bool isKilledRegUse(const MachineOperand &MO) { 37 return isValidRegUse(MO) && MO.isKill(); 38 } 39 40 bool isValidRegDef(const MachineOperand &MO) { 41 return isValidReg(MO) && MO.isDef(); 42 } 43 44 bool isValidRegDefOf(const MachineOperand &MO, int PhysReg) { 45 return isValidRegDef(MO) && MO.getReg() == PhysReg; 46 } 47 48 void ReachingDefAnalysis::enterBasicBlock( 49 const LoopTraversal::TraversedMBBInfo &TraversedMBB) { 50 51 MachineBasicBlock *MBB = TraversedMBB.MBB; 52 unsigned MBBNumber = MBB->getNumber(); 53 assert(MBBNumber < MBBReachingDefs.size() && 54 "Unexpected basic block number."); 55 MBBReachingDefs[MBBNumber].resize(NumRegUnits); 56 57 // Reset instruction counter in each basic block. 58 CurInstr = 0; 59 60 // Set up LiveRegs to represent registers entering MBB. 61 // Default values are 'nothing happened a long time ago'. 62 if (LiveRegs.empty()) 63 LiveRegs.assign(NumRegUnits, ReachingDefDefaultVal); 64 65 // This is the entry block. 66 if (MBB->pred_empty()) { 67 for (const auto &LI : MBB->liveins()) { 68 for (MCRegUnitIterator Unit(LI.PhysReg, TRI); Unit.isValid(); ++Unit) { 69 // Treat function live-ins as if they were defined just before the first 70 // instruction. Usually, function arguments are set up immediately 71 // before the call. 72 LiveRegs[*Unit] = -1; 73 MBBReachingDefs[MBBNumber][*Unit].push_back(LiveRegs[*Unit]); 74 } 75 } 76 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n"); 77 return; 78 } 79 80 // Try to coalesce live-out registers from predecessors. 81 for (MachineBasicBlock *pred : MBB->predecessors()) { 82 assert(unsigned(pred->getNumber()) < MBBOutRegsInfos.size() && 83 "Should have pre-allocated MBBInfos for all MBBs"); 84 const LiveRegsDefInfo &Incoming = MBBOutRegsInfos[pred->getNumber()]; 85 // Incoming is null if this is a backedge from a BB 86 // we haven't processed yet 87 if (Incoming.empty()) 88 continue; 89 90 for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) { 91 // Use the most recent predecessor def for each register. 92 LiveRegs[Unit] = std::max(LiveRegs[Unit], Incoming[Unit]); 93 if ((LiveRegs[Unit] != ReachingDefDefaultVal)) 94 MBBReachingDefs[MBBNumber][Unit].push_back(LiveRegs[Unit]); 95 } 96 } 97 98 LLVM_DEBUG(dbgs() << printMBBReference(*MBB) 99 << (!TraversedMBB.IsDone ? ": incomplete\n" 100 : ": all preds known\n")); 101 } 102 103 void ReachingDefAnalysis::leaveBasicBlock( 104 const LoopTraversal::TraversedMBBInfo &TraversedMBB) { 105 assert(!LiveRegs.empty() && "Must enter basic block first."); 106 unsigned MBBNumber = TraversedMBB.MBB->getNumber(); 107 assert(MBBNumber < MBBOutRegsInfos.size() && 108 "Unexpected basic block number."); 109 // Save register clearances at end of MBB - used by enterBasicBlock(). 110 MBBOutRegsInfos[MBBNumber] = LiveRegs; 111 112 // While processing the basic block, we kept `Def` relative to the start 113 // of the basic block for convenience. However, future use of this information 114 // only cares about the clearance from the end of the block, so adjust 115 // everything to be relative to the end of the basic block. 116 for (int &OutLiveReg : MBBOutRegsInfos[MBBNumber]) 117 OutLiveReg -= CurInstr; 118 LiveRegs.clear(); 119 } 120 121 void ReachingDefAnalysis::processDefs(MachineInstr *MI) { 122 assert(!MI->isDebugInstr() && "Won't process debug instructions"); 123 124 unsigned MBBNumber = MI->getParent()->getNumber(); 125 assert(MBBNumber < MBBReachingDefs.size() && 126 "Unexpected basic block number."); 127 128 for (auto &MO : MI->operands()) { 129 if (!isValidRegDef(MO)) 130 continue; 131 for (MCRegUnitIterator Unit(MO.getReg(), TRI); Unit.isValid(); ++Unit) { 132 // This instruction explicitly defines the current reg unit. 133 LLVM_DEBUG(dbgs() << printReg(MO.getReg(), TRI) << ":\t" << CurInstr 134 << '\t' << *MI); 135 136 // How many instructions since this reg unit was last written? 137 LiveRegs[*Unit] = CurInstr; 138 MBBReachingDefs[MBBNumber][*Unit].push_back(CurInstr); 139 } 140 } 141 InstIds[MI] = CurInstr; 142 ++CurInstr; 143 } 144 145 void ReachingDefAnalysis::processBasicBlock( 146 const LoopTraversal::TraversedMBBInfo &TraversedMBB) { 147 enterBasicBlock(TraversedMBB); 148 for (MachineInstr &MI : *TraversedMBB.MBB) { 149 if (!MI.isDebugInstr()) 150 processDefs(&MI); 151 } 152 leaveBasicBlock(TraversedMBB); 153 } 154 155 bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) { 156 MF = &mf; 157 TRI = MF->getSubtarget().getRegisterInfo(); 158 LLVM_DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n"); 159 init(); 160 traverse(); 161 return false; 162 } 163 164 void ReachingDefAnalysis::releaseMemory() { 165 // Clear the internal vectors. 166 MBBOutRegsInfos.clear(); 167 MBBReachingDefs.clear(); 168 InstIds.clear(); 169 LiveRegs.clear(); 170 } 171 172 void ReachingDefAnalysis::reset() { 173 releaseMemory(); 174 init(); 175 traverse(); 176 } 177 178 void ReachingDefAnalysis::init() { 179 NumRegUnits = TRI->getNumRegUnits(); 180 MBBReachingDefs.resize(MF->getNumBlockIDs()); 181 // Initialize the MBBOutRegsInfos 182 MBBOutRegsInfos.resize(MF->getNumBlockIDs()); 183 LoopTraversal Traversal; 184 TraversedMBBOrder = Traversal.traverse(*MF); 185 } 186 187 void ReachingDefAnalysis::traverse() { 188 // Traverse the basic blocks. 189 for (LoopTraversal::TraversedMBBInfo TraversedMBB : TraversedMBBOrder) 190 processBasicBlock(TraversedMBB); 191 // Sorting all reaching defs found for a ceartin reg unit in a given BB. 192 for (MBBDefsInfo &MBBDefs : MBBReachingDefs) { 193 for (MBBRegUnitDefs &RegUnitDefs : MBBDefs) 194 llvm::sort(RegUnitDefs); 195 } 196 } 197 198 int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) const { 199 assert(InstIds.count(MI) && "Unexpected machine instuction."); 200 int InstId = InstIds.lookup(MI); 201 int DefRes = ReachingDefDefaultVal; 202 unsigned MBBNumber = MI->getParent()->getNumber(); 203 assert(MBBNumber < MBBReachingDefs.size() && 204 "Unexpected basic block number."); 205 int LatestDef = ReachingDefDefaultVal; 206 for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) { 207 for (int Def : MBBReachingDefs[MBBNumber][*Unit]) { 208 if (Def >= InstId) 209 break; 210 DefRes = Def; 211 } 212 LatestDef = std::max(LatestDef, DefRes); 213 } 214 return LatestDef; 215 } 216 217 MachineInstr* ReachingDefAnalysis::getReachingLocalMIDef(MachineInstr *MI, 218 int PhysReg) const { 219 return getInstFromId(MI->getParent(), getReachingDef(MI, PhysReg)); 220 } 221 222 bool ReachingDefAnalysis::hasSameReachingDef(MachineInstr *A, MachineInstr *B, 223 int PhysReg) const { 224 MachineBasicBlock *ParentA = A->getParent(); 225 MachineBasicBlock *ParentB = B->getParent(); 226 if (ParentA != ParentB) 227 return false; 228 229 return getReachingDef(A, PhysReg) == getReachingDef(B, PhysReg); 230 } 231 232 MachineInstr *ReachingDefAnalysis::getInstFromId(MachineBasicBlock *MBB, 233 int InstId) const { 234 assert(static_cast<size_t>(MBB->getNumber()) < MBBReachingDefs.size() && 235 "Unexpected basic block number."); 236 assert(InstId < static_cast<int>(MBB->size()) && 237 "Unexpected instruction id."); 238 239 if (InstId < 0) 240 return nullptr; 241 242 for (auto &MI : *MBB) { 243 auto F = InstIds.find(&MI); 244 if (F != InstIds.end() && F->second == InstId) 245 return &MI; 246 } 247 248 return nullptr; 249 } 250 251 int 252 ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) const { 253 assert(InstIds.count(MI) && "Unexpected machine instuction."); 254 return InstIds.lookup(MI) - getReachingDef(MI, PhysReg); 255 } 256 257 bool 258 ReachingDefAnalysis::hasLocalDefBefore(MachineInstr *MI, int PhysReg) const { 259 return getReachingDef(MI, PhysReg) >= 0; 260 } 261 262 void ReachingDefAnalysis::getReachingLocalUses(MachineInstr *Def, int PhysReg, 263 InstSet &Uses) const { 264 MachineBasicBlock *MBB = Def->getParent(); 265 MachineBasicBlock::iterator MI = MachineBasicBlock::iterator(Def); 266 while (++MI != MBB->end()) { 267 if (MI->isDebugInstr()) 268 continue; 269 270 // If/when we find a new reaching def, we know that there's no more uses 271 // of 'Def'. 272 if (getReachingLocalMIDef(&*MI, PhysReg) != Def) 273 return; 274 275 for (auto &MO : MI->operands()) { 276 if (!isValidRegUseOf(MO, PhysReg)) 277 continue; 278 279 Uses.insert(&*MI); 280 if (MO.isKill()) 281 return; 282 } 283 } 284 } 285 286 bool 287 ReachingDefAnalysis::getLiveInUses(MachineBasicBlock *MBB, int PhysReg, 288 InstSet &Uses) const { 289 for (auto &MI : *MBB) { 290 if (MI.isDebugInstr()) 291 continue; 292 for (auto &MO : MI.operands()) { 293 if (!isValidRegUseOf(MO, PhysReg)) 294 continue; 295 if (getReachingDef(&MI, PhysReg) >= 0) 296 return false; 297 Uses.insert(&MI); 298 } 299 } 300 return isReachingDefLiveOut(&MBB->back(), PhysReg); 301 } 302 303 void 304 ReachingDefAnalysis::getGlobalUses(MachineInstr *MI, int PhysReg, 305 InstSet &Uses) const { 306 MachineBasicBlock *MBB = MI->getParent(); 307 308 // Collect the uses that each def touches within the block. 309 getReachingLocalUses(MI, PhysReg, Uses); 310 311 // Handle live-out values. 312 if (auto *LiveOut = getLocalLiveOutMIDef(MI->getParent(), PhysReg)) { 313 if (LiveOut != MI) 314 return; 315 316 SmallVector<MachineBasicBlock*, 4> ToVisit; 317 ToVisit.insert(ToVisit.begin(), MBB->successors().begin(), 318 MBB->successors().end()); 319 SmallPtrSet<MachineBasicBlock*, 4>Visited; 320 while (!ToVisit.empty()) { 321 MachineBasicBlock *MBB = ToVisit.back(); 322 ToVisit.pop_back(); 323 if (Visited.count(MBB) || !MBB->isLiveIn(PhysReg)) 324 continue; 325 if (getLiveInUses(MBB, PhysReg, Uses)) 326 ToVisit.insert(ToVisit.end(), MBB->successors().begin(), 327 MBB->successors().end()); 328 Visited.insert(MBB); 329 } 330 } 331 } 332 333 void 334 ReachingDefAnalysis::getLiveOuts(MachineBasicBlock *MBB, int PhysReg, 335 InstSet &Defs, BlockSet &VisitedBBs) const { 336 if (VisitedBBs.count(MBB)) 337 return; 338 339 VisitedBBs.insert(MBB); 340 LivePhysRegs LiveRegs(*TRI); 341 LiveRegs.addLiveOuts(*MBB); 342 if (!LiveRegs.contains(PhysReg)) 343 return; 344 345 if (auto *Def = getLocalLiveOutMIDef(MBB, PhysReg)) 346 Defs.insert(Def); 347 else 348 for (auto *Pred : MBB->predecessors()) 349 getLiveOuts(Pred, PhysReg, Defs, VisitedBBs); 350 } 351 352 MachineInstr *ReachingDefAnalysis::getUniqueReachingMIDef(MachineInstr *MI, 353 int PhysReg) const { 354 // If there's a local def before MI, return it. 355 MachineInstr *LocalDef = getReachingLocalMIDef(MI, PhysReg); 356 if (InstIds.lookup(LocalDef) < InstIds.lookup(MI)) 357 return LocalDef; 358 359 SmallPtrSet<MachineBasicBlock*, 4> VisitedBBs; 360 SmallPtrSet<MachineInstr*, 2> Incoming; 361 for (auto *Pred : MI->getParent()->predecessors()) 362 getLiveOuts(Pred, PhysReg, Incoming, VisitedBBs); 363 364 // If we have a local def and an incoming instruction, then there's not a 365 // unique instruction def. 366 if (!Incoming.empty() && LocalDef) 367 return nullptr; 368 else if (Incoming.size() == 1) 369 return *Incoming.begin(); 370 else 371 return LocalDef; 372 } 373 374 MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI, 375 unsigned Idx) const { 376 assert(MI->getOperand(Idx).isReg() && "Expected register operand"); 377 return getUniqueReachingMIDef(MI, MI->getOperand(Idx).getReg()); 378 } 379 380 MachineInstr *ReachingDefAnalysis::getMIOperand(MachineInstr *MI, 381 MachineOperand &MO) const { 382 assert(MO.isReg() && "Expected register operand"); 383 return getUniqueReachingMIDef(MI, MO.getReg()); 384 } 385 386 bool ReachingDefAnalysis::isRegUsedAfter(MachineInstr *MI, int PhysReg) const { 387 MachineBasicBlock *MBB = MI->getParent(); 388 LivePhysRegs LiveRegs(*TRI); 389 LiveRegs.addLiveOuts(*MBB); 390 391 // Yes if the register is live out of the basic block. 392 if (LiveRegs.contains(PhysReg)) 393 return true; 394 395 // Walk backwards through the block to see if the register is live at some 396 // point. 397 for (auto Last = MBB->rbegin(), End = MBB->rend(); Last != End; ++Last) { 398 LiveRegs.stepBackward(*Last); 399 if (LiveRegs.contains(PhysReg)) 400 return InstIds.lookup(&*Last) > InstIds.lookup(MI); 401 } 402 return false; 403 } 404 405 bool ReachingDefAnalysis::isRegDefinedAfter(MachineInstr *MI, 406 int PhysReg) const { 407 MachineBasicBlock *MBB = MI->getParent(); 408 if (getReachingDef(MI, PhysReg) != getReachingDef(&MBB->back(), PhysReg)) 409 return true; 410 411 if (auto *Def = getLocalLiveOutMIDef(MBB, PhysReg)) 412 return Def == getReachingLocalMIDef(MI, PhysReg); 413 414 return false; 415 } 416 417 bool 418 ReachingDefAnalysis::isReachingDefLiveOut(MachineInstr *MI, int PhysReg) const { 419 MachineBasicBlock *MBB = MI->getParent(); 420 LivePhysRegs LiveRegs(*TRI); 421 LiveRegs.addLiveOuts(*MBB); 422 if (!LiveRegs.contains(PhysReg)) 423 return false; 424 425 MachineInstr *Last = &MBB->back(); 426 int Def = getReachingDef(MI, PhysReg); 427 if (getReachingDef(Last, PhysReg) != Def) 428 return false; 429 430 // Finally check that the last instruction doesn't redefine the register. 431 for (auto &MO : Last->operands()) 432 if (isValidRegDefOf(MO, PhysReg)) 433 return false; 434 435 return true; 436 } 437 438 MachineInstr* ReachingDefAnalysis::getLocalLiveOutMIDef(MachineBasicBlock *MBB, 439 int PhysReg) const { 440 LivePhysRegs LiveRegs(*TRI); 441 LiveRegs.addLiveOuts(*MBB); 442 if (!LiveRegs.contains(PhysReg)) 443 return nullptr; 444 445 MachineInstr *Last = &MBB->back(); 446 int Def = getReachingDef(Last, PhysReg); 447 for (auto &MO : Last->operands()) 448 if (isValidRegDefOf(MO, PhysReg)) 449 return Last; 450 451 return Def < 0 ? nullptr : getInstFromId(MBB, Def); 452 } 453 454 static bool mayHaveSideEffects(MachineInstr &MI) { 455 return MI.mayLoadOrStore() || MI.mayRaiseFPException() || 456 MI.hasUnmodeledSideEffects() || MI.isTerminator() || 457 MI.isCall() || MI.isBarrier() || MI.isBranch() || MI.isReturn(); 458 } 459 460 // Can we safely move 'From' to just before 'To'? To satisfy this, 'From' must 461 // not define a register that is used by any instructions, after and including, 462 // 'To'. These instructions also must not redefine any of Froms operands. 463 template<typename Iterator> 464 bool ReachingDefAnalysis::isSafeToMove(MachineInstr *From, 465 MachineInstr *To) const { 466 if (From->getParent() != To->getParent()) 467 return false; 468 469 SmallSet<int, 2> Defs; 470 // First check that From would compute the same value if moved. 471 for (auto &MO : From->operands()) { 472 if (!isValidReg(MO)) 473 continue; 474 if (MO.isDef()) 475 Defs.insert(MO.getReg()); 476 else if (!hasSameReachingDef(From, To, MO.getReg())) 477 return false; 478 } 479 480 // Now walk checking that the rest of the instructions will compute the same 481 // value and that we're not overwriting anything. Don't move the instruction 482 // past any memory, control-flow or other ambigious instructions. 483 for (auto I = ++Iterator(From), E = Iterator(To); I != E; ++I) { 484 if (mayHaveSideEffects(*I)) 485 return false; 486 for (auto &MO : I->operands()) 487 if (MO.isReg() && MO.getReg() && Defs.count(MO.getReg())) 488 return false; 489 } 490 return true; 491 } 492 493 bool ReachingDefAnalysis::isSafeToMoveForwards(MachineInstr *From, 494 MachineInstr *To) const { 495 return isSafeToMove<MachineBasicBlock::reverse_iterator>(From, To); 496 } 497 498 bool ReachingDefAnalysis::isSafeToMoveBackwards(MachineInstr *From, 499 MachineInstr *To) const { 500 return isSafeToMove<MachineBasicBlock::iterator>(From, To); 501 } 502 503 bool ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI, 504 InstSet &ToRemove) const { 505 SmallPtrSet<MachineInstr*, 1> Ignore; 506 SmallPtrSet<MachineInstr*, 2> Visited; 507 return isSafeToRemove(MI, Visited, ToRemove, Ignore); 508 } 509 510 bool 511 ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI, InstSet &ToRemove, 512 InstSet &Ignore) const { 513 SmallPtrSet<MachineInstr*, 2> Visited; 514 return isSafeToRemove(MI, Visited, ToRemove, Ignore); 515 } 516 517 bool 518 ReachingDefAnalysis::isSafeToRemove(MachineInstr *MI, InstSet &Visited, 519 InstSet &ToRemove, InstSet &Ignore) const { 520 if (Visited.count(MI) || Ignore.count(MI)) 521 return true; 522 else if (mayHaveSideEffects(*MI)) { 523 // Unless told to ignore the instruction, don't remove anything which has 524 // side effects. 525 return false; 526 } 527 528 Visited.insert(MI); 529 for (auto &MO : MI->operands()) { 530 if (!isValidRegDef(MO)) 531 continue; 532 533 SmallPtrSet<MachineInstr*, 4> Uses; 534 getGlobalUses(MI, MO.getReg(), Uses); 535 536 for (auto I : Uses) { 537 if (Ignore.count(I) || ToRemove.count(I)) 538 continue; 539 if (!isSafeToRemove(I, Visited, ToRemove, Ignore)) 540 return false; 541 } 542 } 543 ToRemove.insert(MI); 544 return true; 545 } 546 547 void ReachingDefAnalysis::collectLocalKilledOperands(MachineInstr *MI, 548 InstSet &Dead) const { 549 Dead.insert(MI); 550 auto IsDead = [this, &Dead](MachineInstr *Def, int PhysReg) { 551 unsigned LiveDefs = 0; 552 for (auto &MO : Def->operands()) { 553 if (!isValidRegDef(MO)) 554 continue; 555 if (!MO.isDead()) 556 ++LiveDefs; 557 } 558 559 if (LiveDefs > 1) 560 return false; 561 562 SmallPtrSet<MachineInstr*, 4> Uses; 563 getGlobalUses(Def, PhysReg, Uses); 564 for (auto *Use : Uses) 565 if (!Dead.count(Use)) 566 return false; 567 return true; 568 }; 569 570 for (auto &MO : MI->operands()) { 571 if (!isKilledRegUse(MO)) 572 continue; 573 if (MachineInstr *Def = getReachingLocalMIDef(MI, MO.getReg())) 574 if (IsDead(Def, MO.getReg())) 575 collectLocalKilledOperands(Def, Dead); 576 } 577 } 578 579 bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI, 580 int PhysReg) const { 581 SmallPtrSet<MachineInstr*, 1> Ignore; 582 return isSafeToDefRegAt(MI, PhysReg, Ignore); 583 } 584 585 bool ReachingDefAnalysis::isSafeToDefRegAt(MachineInstr *MI, int PhysReg, 586 InstSet &Ignore) const { 587 // Check for any uses of the register after MI. 588 if (isRegUsedAfter(MI, PhysReg)) { 589 if (auto *Def = getReachingLocalMIDef(MI, PhysReg)) { 590 SmallPtrSet<MachineInstr*, 2> Uses; 591 getReachingLocalUses(Def, PhysReg, Uses); 592 for (auto *Use : Uses) 593 if (!Ignore.count(Use)) 594 return false; 595 } else 596 return false; 597 } 598 599 MachineBasicBlock *MBB = MI->getParent(); 600 // Check for any defs after MI. 601 if (isRegDefinedAfter(MI, PhysReg)) { 602 auto I = MachineBasicBlock::iterator(MI); 603 for (auto E = MBB->end(); I != E; ++I) { 604 if (Ignore.count(&*I)) 605 continue; 606 for (auto &MO : I->operands()) 607 if (isValidRegDefOf(MO, PhysReg)) 608 return false; 609 } 610 } 611 return true; 612 } 613