1 //===---------------------- ProcessImplicitDefs.cpp -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/ADT/SetVector.h" 10 #include "llvm/Analysis/AliasAnalysis.h" 11 #include "llvm/CodeGen/MachineFunctionPass.h" 12 #include "llvm/CodeGen/MachineInstr.h" 13 #include "llvm/CodeGen/MachineRegisterInfo.h" 14 #include "llvm/CodeGen/TargetInstrInfo.h" 15 #include "llvm/CodeGen/TargetSubtargetInfo.h" 16 #include "llvm/InitializePasses.h" 17 #include "llvm/Pass.h" 18 #include "llvm/PassRegistry.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Support/raw_ostream.h" 21 22 using namespace llvm; 23 24 #define DEBUG_TYPE "processimpdefs" 25 26 namespace { 27 /// Process IMPLICIT_DEF instructions and make sure there is one implicit_def 28 /// for each use. Add isUndef marker to implicit_def defs and their uses. 29 class ProcessImplicitDefs : public MachineFunctionPass { 30 const TargetInstrInfo *TII; 31 const TargetRegisterInfo *TRI; 32 MachineRegisterInfo *MRI; 33 34 SmallSetVector<MachineInstr*, 16> WorkList; 35 36 void processImplicitDef(MachineInstr *MI); 37 bool canTurnIntoImplicitDef(MachineInstr *MI); 38 39 public: 40 static char ID; 41 42 ProcessImplicitDefs() : MachineFunctionPass(ID) { 43 initializeProcessImplicitDefsPass(*PassRegistry::getPassRegistry()); 44 } 45 46 void getAnalysisUsage(AnalysisUsage &au) const override; 47 48 bool runOnMachineFunction(MachineFunction &MF) override; 49 }; 50 } // end anonymous namespace 51 52 char ProcessImplicitDefs::ID = 0; 53 char &llvm::ProcessImplicitDefsID = ProcessImplicitDefs::ID; 54 55 INITIALIZE_PASS(ProcessImplicitDefs, DEBUG_TYPE, 56 "Process Implicit Definitions", false, false) 57 58 void ProcessImplicitDefs::getAnalysisUsage(AnalysisUsage &AU) const { 59 AU.setPreservesCFG(); 60 AU.addPreserved<AAResultsWrapperPass>(); 61 MachineFunctionPass::getAnalysisUsage(AU); 62 } 63 64 bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) { 65 if (!MI->isCopyLike() && 66 !MI->isInsertSubreg() && 67 !MI->isRegSequence() && 68 !MI->isPHI()) 69 return false; 70 for (const MachineOperand &MO : MI->operands()) 71 if (MO.isReg() && MO.isUse() && MO.readsReg()) 72 return false; 73 return true; 74 } 75 76 void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) { 77 LLVM_DEBUG(dbgs() << "Processing " << *MI); 78 Register Reg = MI->getOperand(0).getReg(); 79 80 if (Register::isVirtualRegister(Reg)) { 81 // For virtual registers, mark all uses as <undef>, and convert users to 82 // implicit-def when possible. 83 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { 84 MO.setIsUndef(); 85 MachineInstr *UserMI = MO.getParent(); 86 if (!canTurnIntoImplicitDef(UserMI)) 87 continue; 88 LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI); 89 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); 90 WorkList.insert(UserMI); 91 } 92 MI->eraseFromParent(); 93 return; 94 } 95 96 // This is a physreg implicit-def. 97 // Look for the first instruction to use or define an alias. 98 MachineBasicBlock::instr_iterator UserMI = MI->getIterator(); 99 MachineBasicBlock::instr_iterator UserE = MI->getParent()->instr_end(); 100 bool Found = false; 101 for (++UserMI; UserMI != UserE; ++UserMI) { 102 for (MachineOperand &MO : UserMI->operands()) { 103 if (!MO.isReg()) 104 continue; 105 Register UserReg = MO.getReg(); 106 if (!Register::isPhysicalRegister(UserReg) || 107 !TRI->regsOverlap(Reg, UserReg)) 108 continue; 109 // UserMI uses or redefines Reg. Set <undef> flags on all uses. 110 Found = true; 111 if (MO.isUse()) 112 MO.setIsUndef(); 113 } 114 if (Found) 115 break; 116 } 117 118 // If we found the using MI, we can erase the IMPLICIT_DEF. 119 if (Found) { 120 LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI); 121 MI->eraseFromParent(); 122 return; 123 } 124 125 // Using instr wasn't found, it could be in another block. 126 // Leave the physreg IMPLICIT_DEF, but trim any extra operands. 127 for (unsigned i = MI->getNumOperands() - 1; i; --i) 128 MI->RemoveOperand(i); 129 LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI); 130 } 131 132 /// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into 133 /// <undef> operands. 134 bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) { 135 136 LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n" 137 << "********** Function: " << MF.getName() << '\n'); 138 139 bool Changed = false; 140 141 TII = MF.getSubtarget().getInstrInfo(); 142 TRI = MF.getSubtarget().getRegisterInfo(); 143 MRI = &MF.getRegInfo(); 144 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form."); 145 assert(WorkList.empty() && "Inconsistent worklist state"); 146 147 for (MachineBasicBlock &MBB : MF) { 148 // Scan the basic block for implicit defs. 149 for (MachineInstr &MI : MBB) 150 if (MI.isImplicitDef()) 151 WorkList.insert(&MI); 152 153 if (WorkList.empty()) 154 continue; 155 156 LLVM_DEBUG(dbgs() << printMBBReference(MBB) << " has " << WorkList.size() 157 << " implicit defs.\n"); 158 Changed = true; 159 160 // Drain the WorkList to recursively process any new implicit defs. 161 do processImplicitDef(WorkList.pop_back_val()); 162 while (!WorkList.empty()); 163 } 164 return Changed; 165 } 166