1 //===- MachineUniformityAnalysis.cpp --------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/CodeGen/MachineUniformityAnalysis.h" 10 #include "llvm/ADT/GenericUniformityImpl.h" 11 #include "llvm/CodeGen/MachineCycleAnalysis.h" 12 #include "llvm/CodeGen/MachineDominators.h" 13 #include "llvm/CodeGen/MachineRegisterInfo.h" 14 #include "llvm/CodeGen/MachineSSAContext.h" 15 #include "llvm/CodeGen/TargetInstrInfo.h" 16 #include "llvm/InitializePasses.h" 17 18 using namespace llvm; 19 20 template <> 21 bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::hasDivergentDefs( 22 const MachineInstr &I) const { 23 for (auto &op : I.operands()) { 24 if (!op.isReg() || !op.isDef()) 25 continue; 26 if (isDivergent(op.getReg())) 27 return true; 28 } 29 return false; 30 } 31 32 template <> 33 bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::markDefsDivergent( 34 const MachineInstr &Instr, bool AllDefsDivergent) { 35 bool insertedDivergent = false; 36 const auto &MRI = F.getRegInfo(); 37 const auto &TRI = *MRI.getTargetRegisterInfo(); 38 for (auto &op : Instr.operands()) { 39 if (!op.isReg() || !op.isDef()) 40 continue; 41 if (!op.getReg().isVirtual()) 42 continue; 43 assert(!op.getSubReg()); 44 if (!AllDefsDivergent) { 45 auto *RC = MRI.getRegClassOrNull(op.getReg()); 46 if (RC && !TRI.isDivergentRegClass(RC)) 47 continue; 48 } 49 insertedDivergent |= markDivergent(op.getReg()); 50 } 51 return insertedDivergent; 52 } 53 54 template <> 55 void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::initialize() { 56 const auto &InstrInfo = *F.getSubtarget().getInstrInfo(); 57 58 for (const MachineBasicBlock &block : F) { 59 for (const MachineInstr &instr : block) { 60 auto uniformity = InstrInfo.getInstructionUniformity(instr); 61 if (uniformity == InstructionUniformity::AlwaysUniform) { 62 addUniformOverride(instr); 63 continue; 64 } 65 66 if (uniformity == InstructionUniformity::NeverUniform) { 67 markDefsDivergent(instr, /* AllDefsDivergent = */ false); 68 } 69 } 70 } 71 } 72 73 template <> 74 void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::pushUsers( 75 Register Reg) { 76 const auto &RegInfo = F.getRegInfo(); 77 for (MachineInstr &UserInstr : RegInfo.use_instructions(Reg)) { 78 if (markDivergent(UserInstr)) 79 Worklist.push_back(&UserInstr); 80 } 81 } 82 83 template <> 84 void llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::pushUsers( 85 const MachineInstr &Instr) { 86 assert(!isAlwaysUniform(Instr)); 87 if (Instr.isTerminator()) 88 return; 89 for (const MachineOperand &op : Instr.operands()) { 90 if (op.isReg() && op.isDef() && op.getReg().isVirtual()) 91 pushUsers(op.getReg()); 92 } 93 } 94 95 template <> 96 bool llvm::GenericUniformityAnalysisImpl<MachineSSAContext>::usesValueFromCycle( 97 const MachineInstr &I, const MachineCycle &DefCycle) const { 98 assert(!isAlwaysUniform(I)); 99 for (auto &Op : I.operands()) { 100 if (!Op.isReg() || !Op.readsReg()) 101 continue; 102 auto Reg = Op.getReg(); 103 104 // FIXME: Physical registers need to be properly checked instead of always 105 // returning true 106 if (Reg.isPhysical()) 107 return true; 108 109 auto *Def = F.getRegInfo().getVRegDef(Reg); 110 if (DefCycle.contains(Def->getParent())) 111 return true; 112 } 113 return false; 114 } 115 116 // This ensures explicit instantiation of 117 // GenericUniformityAnalysisImpl::ImplDeleter::operator() 118 template class llvm::GenericUniformityInfo<MachineSSAContext>; 119 template struct llvm::GenericUniformityAnalysisImplDeleter< 120 llvm::GenericUniformityAnalysisImpl<MachineSSAContext>>; 121 122 MachineUniformityInfo 123 llvm::computeMachineUniformityInfo(MachineFunction &F, 124 const MachineCycleInfo &cycleInfo, 125 const MachineDomTree &domTree) { 126 assert(F.getRegInfo().isSSA() && "Expected to be run on SSA form!"); 127 return MachineUniformityInfo(F, domTree, cycleInfo); 128 } 129 130 namespace { 131 132 /// Legacy analysis pass which computes a \ref MachineUniformityInfo. 133 class MachineUniformityAnalysisPass : public MachineFunctionPass { 134 MachineUniformityInfo UI; 135 136 public: 137 static char ID; 138 139 MachineUniformityAnalysisPass(); 140 141 MachineUniformityInfo &getUniformityInfo() { return UI; } 142 const MachineUniformityInfo &getUniformityInfo() const { return UI; } 143 144 bool runOnMachineFunction(MachineFunction &F) override; 145 void getAnalysisUsage(AnalysisUsage &AU) const override; 146 void print(raw_ostream &OS, const Module *M = nullptr) const override; 147 148 // TODO: verify analysis 149 }; 150 151 class MachineUniformityInfoPrinterPass : public MachineFunctionPass { 152 public: 153 static char ID; 154 155 MachineUniformityInfoPrinterPass(); 156 157 bool runOnMachineFunction(MachineFunction &F) override; 158 void getAnalysisUsage(AnalysisUsage &AU) const override; 159 }; 160 161 } // namespace 162 163 char MachineUniformityAnalysisPass::ID = 0; 164 165 MachineUniformityAnalysisPass::MachineUniformityAnalysisPass() 166 : MachineFunctionPass(ID) { 167 initializeMachineUniformityAnalysisPassPass(*PassRegistry::getPassRegistry()); 168 } 169 170 INITIALIZE_PASS_BEGIN(MachineUniformityAnalysisPass, "machine-uniformity", 171 "Machine Uniformity Info Analysis", true, true) 172 INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass) 173 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 174 INITIALIZE_PASS_END(MachineUniformityAnalysisPass, "machine-uniformity", 175 "Machine Uniformity Info Analysis", true, true) 176 177 void MachineUniformityAnalysisPass::getAnalysisUsage(AnalysisUsage &AU) const { 178 AU.setPreservesAll(); 179 AU.addRequired<MachineCycleInfoWrapperPass>(); 180 AU.addRequired<MachineDominatorTree>(); 181 MachineFunctionPass::getAnalysisUsage(AU); 182 } 183 184 bool MachineUniformityAnalysisPass::runOnMachineFunction(MachineFunction &MF) { 185 auto &DomTree = getAnalysis<MachineDominatorTree>().getBase(); 186 auto &CI = getAnalysis<MachineCycleInfoWrapperPass>().getCycleInfo(); 187 UI = computeMachineUniformityInfo(MF, CI, DomTree); 188 return false; 189 } 190 191 void MachineUniformityAnalysisPass::print(raw_ostream &OS, 192 const Module *) const { 193 OS << "MachineUniformityInfo for function: " << UI.getFunction().getName() 194 << "\n"; 195 UI.print(OS); 196 } 197 198 char MachineUniformityInfoPrinterPass::ID = 0; 199 200 MachineUniformityInfoPrinterPass::MachineUniformityInfoPrinterPass() 201 : MachineFunctionPass(ID) { 202 initializeMachineUniformityInfoPrinterPassPass( 203 *PassRegistry::getPassRegistry()); 204 } 205 206 INITIALIZE_PASS_BEGIN(MachineUniformityInfoPrinterPass, 207 "print-machine-uniformity", 208 "Print Machine Uniformity Info Analysis", true, true) 209 INITIALIZE_PASS_DEPENDENCY(MachineUniformityAnalysisPass) 210 INITIALIZE_PASS_END(MachineUniformityInfoPrinterPass, 211 "print-machine-uniformity", 212 "Print Machine Uniformity Info Analysis", true, true) 213 214 void MachineUniformityInfoPrinterPass::getAnalysisUsage( 215 AnalysisUsage &AU) const { 216 AU.setPreservesAll(); 217 AU.addRequired<MachineUniformityAnalysisPass>(); 218 MachineFunctionPass::getAnalysisUsage(AU); 219 } 220 221 bool MachineUniformityInfoPrinterPass::runOnMachineFunction( 222 MachineFunction &F) { 223 auto &UI = getAnalysis<MachineUniformityAnalysisPass>(); 224 UI.print(errs()); 225 return false; 226 } 227