xref: /llvm-project/llvm/lib/CodeGen/MachineOperand.cpp (revision c01efe690f01431d8d8552d7ceff968e03af6fd6) 
1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file Methods common to all machine operands.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/MachineOperand.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
17 #include "llvm/CodeGen/MIRPrinter.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/IR/Constants.h"
24 #include "llvm/IR/IRPrintingPasses.h"
25 #include "llvm/IR/ModuleSlotTracker.h"
26 #include "llvm/Target/TargetIntrinsicInfo.h"
27 #include "llvm/Target/TargetMachine.h"
28 
29 using namespace llvm;
30 
31 static cl::opt<int>
32     PrintRegMaskNumRegs("print-regmask-num-regs",
33                         cl::desc("Number of registers to limit to when "
34                                  "printing regmask operands in IR dumps. "
35                                  "unlimited = -1"),
36                         cl::init(32), cl::Hidden);
37 
38 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
39   if (const MachineInstr *MI = MO.getParent())
40     if (const MachineBasicBlock *MBB = MI->getParent())
41       if (const MachineFunction *MF = MBB->getParent())
42         return MF;
43   return nullptr;
44 }
45 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
46   return const_cast<MachineFunction *>(
47       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
48 }
49 
50 void MachineOperand::setReg(unsigned Reg) {
51   if (getReg() == Reg)
52     return; // No change.
53 
54   // Clear the IsRenamable bit to keep it conservatively correct.
55   IsRenamable = false;
56 
57   // Otherwise, we have to change the register.  If this operand is embedded
58   // into a machine function, we need to update the old and new register's
59   // use/def lists.
60   if (MachineFunction *MF = getMFIfAvailable(*this)) {
61     MachineRegisterInfo &MRI = MF->getRegInfo();
62     MRI.removeRegOperandFromUseList(this);
63     SmallContents.RegNo = Reg;
64     MRI.addRegOperandToUseList(this);
65     return;
66   }
67 
68   // Otherwise, just change the register, no problem.  :)
69   SmallContents.RegNo = Reg;
70 }
71 
72 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
73                                   const TargetRegisterInfo &TRI) {
74   assert(TargetRegisterInfo::isVirtualRegister(Reg));
75   if (SubIdx && getSubReg())
76     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
77   setReg(Reg);
78   if (SubIdx)
79     setSubReg(SubIdx);
80 }
81 
82 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
83   assert(TargetRegisterInfo::isPhysicalRegister(Reg));
84   if (getSubReg()) {
85     Reg = TRI.getSubReg(Reg, getSubReg());
86     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
87     // That won't happen in legal code.
88     setSubReg(0);
89     if (isDef())
90       setIsUndef(false);
91   }
92   setReg(Reg);
93 }
94 
95 /// Change a def to a use, or a use to a def.
96 void MachineOperand::setIsDef(bool Val) {
97   assert(isReg() && "Wrong MachineOperand accessor");
98   assert((!Val || !isDebug()) && "Marking a debug operation as def");
99   if (IsDef == Val)
100     return;
101   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
102   // MRI may keep uses and defs in different list positions.
103   if (MachineFunction *MF = getMFIfAvailable(*this)) {
104     MachineRegisterInfo &MRI = MF->getRegInfo();
105     MRI.removeRegOperandFromUseList(this);
106     IsDef = Val;
107     MRI.addRegOperandToUseList(this);
108     return;
109   }
110   IsDef = Val;
111 }
112 
113 bool MachineOperand::isRenamable() const {
114   assert(isReg() && "Wrong MachineOperand accessor");
115   assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
116          "isRenamable should only be checked on physical registers");
117   if (!IsRenamable)
118     return false;
119 
120   const MachineInstr *MI = getParent();
121   if (!MI)
122     return true;
123 
124   if (isDef())
125     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
126 
127   assert(isUse() && "Reg is not def or use");
128   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
129 }
130 
131 void MachineOperand::setIsRenamable(bool Val) {
132   assert(isReg() && "Wrong MachineOperand accessor");
133   assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
134          "setIsRenamable should only be called on physical registers");
135   IsRenamable = Val;
136 }
137 
138 // If this operand is currently a register operand, and if this is in a
139 // function, deregister the operand from the register's use/def list.
140 void MachineOperand::removeRegFromUses() {
141   if (!isReg() || !isOnRegUseList())
142     return;
143 
144   if (MachineFunction *MF = getMFIfAvailable(*this))
145     MF->getRegInfo().removeRegOperandFromUseList(this);
146 }
147 
148 /// ChangeToImmediate - Replace this operand with a new immediate operand of
149 /// the specified value.  If an operand is known to be an immediate already,
150 /// the setImm method should be used.
151 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
152   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
153 
154   removeRegFromUses();
155 
156   OpKind = MO_Immediate;
157   Contents.ImmVal = ImmVal;
158 }
159 
160 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
161   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
162 
163   removeRegFromUses();
164 
165   OpKind = MO_FPImmediate;
166   Contents.CFP = FPImm;
167 }
168 
169 void MachineOperand::ChangeToES(const char *SymName,
170                                 unsigned char TargetFlags) {
171   assert((!isReg() || !isTied()) &&
172          "Cannot change a tied operand into an external symbol");
173 
174   removeRegFromUses();
175 
176   OpKind = MO_ExternalSymbol;
177   Contents.OffsetedInfo.Val.SymbolName = SymName;
178   setOffset(0); // Offset is always 0.
179   setTargetFlags(TargetFlags);
180 }
181 
182 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
183   assert((!isReg() || !isTied()) &&
184          "Cannot change a tied operand into an MCSymbol");
185 
186   removeRegFromUses();
187 
188   OpKind = MO_MCSymbol;
189   Contents.Sym = Sym;
190 }
191 
192 void MachineOperand::ChangeToFrameIndex(int Idx) {
193   assert((!isReg() || !isTied()) &&
194          "Cannot change a tied operand into a FrameIndex");
195 
196   removeRegFromUses();
197 
198   OpKind = MO_FrameIndex;
199   setIndex(Idx);
200 }
201 
202 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
203                                          unsigned char TargetFlags) {
204   assert((!isReg() || !isTied()) &&
205          "Cannot change a tied operand into a FrameIndex");
206 
207   removeRegFromUses();
208 
209   OpKind = MO_TargetIndex;
210   setIndex(Idx);
211   setOffset(Offset);
212   setTargetFlags(TargetFlags);
213 }
214 
215 /// ChangeToRegister - Replace this operand with a new register operand of
216 /// the specified value.  If an operand is known to be an register already,
217 /// the setReg method should be used.
218 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
219                                       bool isKill, bool isDead, bool isUndef,
220                                       bool isDebug) {
221   MachineRegisterInfo *RegInfo = nullptr;
222   if (MachineFunction *MF = getMFIfAvailable(*this))
223     RegInfo = &MF->getRegInfo();
224   // If this operand is already a register operand, remove it from the
225   // register's use/def lists.
226   bool WasReg = isReg();
227   if (RegInfo && WasReg)
228     RegInfo->removeRegOperandFromUseList(this);
229 
230   // Change this to a register and set the reg#.
231   assert(!(isDead && !isDef) && "Dead flag on non-def");
232   assert(!(isKill && isDef) && "Kill flag on def");
233   OpKind = MO_Register;
234   SmallContents.RegNo = Reg;
235   SubReg_TargetFlags = 0;
236   IsDef = isDef;
237   IsImp = isImp;
238   IsDeadOrKill = isKill | isDead;
239   IsRenamable = false;
240   IsUndef = isUndef;
241   IsInternalRead = false;
242   IsEarlyClobber = false;
243   IsDebug = isDebug;
244   // Ensure isOnRegUseList() returns false.
245   Contents.Reg.Prev = nullptr;
246   // Preserve the tie when the operand was already a register.
247   if (!WasReg)
248     TiedTo = 0;
249 
250   // If this operand is embedded in a function, add the operand to the
251   // register's use/def list.
252   if (RegInfo)
253     RegInfo->addRegOperandToUseList(this);
254 }
255 
256 /// isIdenticalTo - Return true if this operand is identical to the specified
257 /// operand. Note that this should stay in sync with the hash_value overload
258 /// below.
259 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
260   if (getType() != Other.getType() ||
261       getTargetFlags() != Other.getTargetFlags())
262     return false;
263 
264   switch (getType()) {
265   case MachineOperand::MO_Register:
266     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
267            getSubReg() == Other.getSubReg();
268   case MachineOperand::MO_Immediate:
269     return getImm() == Other.getImm();
270   case MachineOperand::MO_CImmediate:
271     return getCImm() == Other.getCImm();
272   case MachineOperand::MO_FPImmediate:
273     return getFPImm() == Other.getFPImm();
274   case MachineOperand::MO_MachineBasicBlock:
275     return getMBB() == Other.getMBB();
276   case MachineOperand::MO_FrameIndex:
277     return getIndex() == Other.getIndex();
278   case MachineOperand::MO_ConstantPoolIndex:
279   case MachineOperand::MO_TargetIndex:
280     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
281   case MachineOperand::MO_JumpTableIndex:
282     return getIndex() == Other.getIndex();
283   case MachineOperand::MO_GlobalAddress:
284     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
285   case MachineOperand::MO_ExternalSymbol:
286     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
287            getOffset() == Other.getOffset();
288   case MachineOperand::MO_BlockAddress:
289     return getBlockAddress() == Other.getBlockAddress() &&
290            getOffset() == Other.getOffset();
291   case MachineOperand::MO_RegisterMask:
292   case MachineOperand::MO_RegisterLiveOut: {
293     // Shallow compare of the two RegMasks
294     const uint32_t *RegMask = getRegMask();
295     const uint32_t *OtherRegMask = Other.getRegMask();
296     if (RegMask == OtherRegMask)
297       return true;
298 
299     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
300       // Calculate the size of the RegMask
301       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
302       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
303 
304       // Deep compare of the two RegMasks
305       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
306     }
307     // We don't know the size of the RegMask, so we can't deep compare the two
308     // reg masks.
309     return false;
310   }
311   case MachineOperand::MO_MCSymbol:
312     return getMCSymbol() == Other.getMCSymbol();
313   case MachineOperand::MO_CFIIndex:
314     return getCFIIndex() == Other.getCFIIndex();
315   case MachineOperand::MO_Metadata:
316     return getMetadata() == Other.getMetadata();
317   case MachineOperand::MO_IntrinsicID:
318     return getIntrinsicID() == Other.getIntrinsicID();
319   case MachineOperand::MO_Predicate:
320     return getPredicate() == Other.getPredicate();
321   }
322   llvm_unreachable("Invalid machine operand type");
323 }
324 
325 // Note: this must stay exactly in sync with isIdenticalTo above.
326 hash_code llvm::hash_value(const MachineOperand &MO) {
327   switch (MO.getType()) {
328   case MachineOperand::MO_Register:
329     // Register operands don't have target flags.
330     return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
331   case MachineOperand::MO_Immediate:
332     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
333   case MachineOperand::MO_CImmediate:
334     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
335   case MachineOperand::MO_FPImmediate:
336     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
337   case MachineOperand::MO_MachineBasicBlock:
338     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
339   case MachineOperand::MO_FrameIndex:
340     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
341   case MachineOperand::MO_ConstantPoolIndex:
342   case MachineOperand::MO_TargetIndex:
343     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
344                         MO.getOffset());
345   case MachineOperand::MO_JumpTableIndex:
346     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
347   case MachineOperand::MO_ExternalSymbol:
348     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
349                         MO.getSymbolName());
350   case MachineOperand::MO_GlobalAddress:
351     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
352                         MO.getOffset());
353   case MachineOperand::MO_BlockAddress:
354     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
355                         MO.getOffset());
356   case MachineOperand::MO_RegisterMask:
357   case MachineOperand::MO_RegisterLiveOut:
358     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
359   case MachineOperand::MO_Metadata:
360     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
361   case MachineOperand::MO_MCSymbol:
362     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
363   case MachineOperand::MO_CFIIndex:
364     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
365   case MachineOperand::MO_IntrinsicID:
366     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
367   case MachineOperand::MO_Predicate:
368     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
369   }
370   llvm_unreachable("Invalid machine operand type");
371 }
372 
373 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
374 // it.
375 static void tryToGetTargetInfo(const MachineOperand &MO,
376                                const TargetRegisterInfo *&TRI,
377                                const TargetIntrinsicInfo *&IntrinsicInfo) {
378   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
379     TRI = MF->getSubtarget().getRegisterInfo();
380     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
381   }
382 }
383 
384 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
385   const auto *TII = MF.getSubtarget().getInstrInfo();
386   assert(TII && "expected instruction info");
387   auto Indices = TII->getSerializableTargetIndices();
388   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
389     return I.first == Index;
390   });
391   if (Found != Indices.end())
392     return Found->second;
393   return nullptr;
394 }
395 
396 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
397   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
398   for (const auto &I : Flags) {
399     if (I.first == TF) {
400       return I.second;
401     }
402   }
403   return nullptr;
404 }
405 
406 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
407                              const TargetRegisterInfo *TRI) {
408   if (!TRI) {
409     OS << "%dwarfreg." << DwarfReg;
410     return;
411   }
412 
413   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
414   if (Reg == -1) {
415     OS << "<badreg>";
416     return;
417   }
418   OS << printReg(Reg, TRI);
419 }
420 
421 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
422                                   ModuleSlotTracker &MST) {
423   OS << "%ir-block.";
424   if (BB.hasName()) {
425     printLLVMNameWithoutPrefix(OS, BB.getName());
426     return;
427   }
428   Optional<int> Slot;
429   if (const Function *F = BB.getParent()) {
430     if (F == MST.getCurrentFunction()) {
431       Slot = MST.getLocalSlot(&BB);
432     } else if (const Module *M = F->getParent()) {
433       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
434       CustomMST.incorporateFunction(*F);
435       Slot = CustomMST.getLocalSlot(&BB);
436     }
437   }
438   if (Slot)
439     MachineOperand::printIRSlotNumber(OS, *Slot);
440   else
441     OS << "<unknown>";
442 }
443 
444 static void printIRValueReference(raw_ostream &OS, const Value &V,
445                                   ModuleSlotTracker &MST) {
446   if (isa<GlobalValue>(V)) {
447     V.printAsOperand(OS, /*PrintType=*/false, MST);
448     return;
449   }
450   if (isa<Constant>(V)) {
451     // Machine memory operands can load/store to/from constant value pointers.
452     OS << '`';
453     V.printAsOperand(OS, /*PrintType=*/true, MST);
454     OS << '`';
455     return;
456   }
457   OS << "%ir.";
458   if (V.hasName()) {
459     printLLVMNameWithoutPrefix(OS, V.getName());
460     return;
461   }
462   MachineOperand::printIRSlotNumber(OS, MST.getLocalSlot(&V));
463 }
464 
465 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
466                            SyncScope::ID SSID,
467                            SmallVectorImpl<StringRef> &SSNs) {
468   switch (SSID) {
469   case SyncScope::System:
470     break;
471   default:
472     if (SSNs.empty())
473       Context.getSyncScopeNames(SSNs);
474 
475     OS << "syncscope(\"";
476     PrintEscapedString(SSNs[SSID], OS);
477     OS << "\") ";
478     break;
479   }
480 }
481 
482 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
483                                         unsigned TMMOFlag) {
484   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
485   for (const auto &I : Flags) {
486     if (I.first == TMMOFlag) {
487       return I.second;
488     }
489   }
490   return nullptr;
491 }
492 
493 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
494                             const MachineFrameInfo *MFI) {
495   StringRef Name;
496   if (MFI) {
497     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
498     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
499       if (Alloca->hasName())
500         Name = Alloca->getName();
501     if (IsFixed)
502       FrameIndex -= MFI->getObjectIndexBegin();
503   }
504   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
505 }
506 
507 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
508                                     const TargetRegisterInfo *TRI) {
509   OS << "%subreg.";
510   if (TRI)
511     OS << TRI->getSubRegIndexName(Index);
512   else
513     OS << Index;
514 }
515 
516 void MachineOperand::printTargetFlags(raw_ostream &OS,
517                                       const MachineOperand &Op) {
518   if (!Op.getTargetFlags())
519     return;
520   const MachineFunction *MF = getMFIfAvailable(Op);
521   if (!MF)
522     return;
523 
524   const auto *TII = MF->getSubtarget().getInstrInfo();
525   assert(TII && "expected instruction info");
526   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
527   OS << "target-flags(";
528   const bool HasDirectFlags = Flags.first;
529   const bool HasBitmaskFlags = Flags.second;
530   if (!HasDirectFlags && !HasBitmaskFlags) {
531     OS << "<unknown>) ";
532     return;
533   }
534   if (HasDirectFlags) {
535     if (const auto *Name = getTargetFlagName(TII, Flags.first))
536       OS << Name;
537     else
538       OS << "<unknown target flag>";
539   }
540   if (!HasBitmaskFlags) {
541     OS << ") ";
542     return;
543   }
544   bool IsCommaNeeded = HasDirectFlags;
545   unsigned BitMask = Flags.second;
546   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
547   for (const auto &Mask : BitMasks) {
548     // Check if the flag's bitmask has the bits of the current mask set.
549     if ((BitMask & Mask.first) == Mask.first) {
550       if (IsCommaNeeded)
551         OS << ", ";
552       IsCommaNeeded = true;
553       OS << Mask.second;
554       // Clear the bits which were serialized from the flag's bitmask.
555       BitMask &= ~(Mask.first);
556     }
557   }
558   if (BitMask) {
559     // When the resulting flag's bitmask isn't zero, we know that we didn't
560     // serialize all of the bit flags.
561     if (IsCommaNeeded)
562       OS << ", ";
563     OS << "<unknown bitmask target flag>";
564   }
565   OS << ") ";
566 }
567 
568 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
569   OS << "<mcsymbol " << Sym << ">";
570 }
571 
572 void MachineOperand::printStackObjectReference(raw_ostream &OS,
573                                                unsigned FrameIndex,
574                                                bool IsFixed, StringRef Name) {
575   if (IsFixed) {
576     OS << "%fixed-stack." << FrameIndex;
577     return;
578   }
579 
580   OS << "%stack." << FrameIndex;
581   if (!Name.empty())
582     OS << '.' << Name;
583 }
584 
585 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
586   if (Offset == 0)
587     return;
588   if (Offset < 0) {
589     OS << " - " << -Offset;
590     return;
591   }
592   OS << " + " << Offset;
593 }
594 
595 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
596   if (Slot == -1)
597     OS << "<badref>";
598   else
599     OS << Slot;
600 }
601 
602 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
603                      const TargetRegisterInfo *TRI) {
604   switch (CFI.getOperation()) {
605   case MCCFIInstruction::OpSameValue:
606     OS << "same_value ";
607     if (MCSymbol *Label = CFI.getLabel())
608       MachineOperand::printSymbol(OS, *Label);
609     printCFIRegister(CFI.getRegister(), OS, TRI);
610     break;
611   case MCCFIInstruction::OpRememberState:
612     OS << "remember_state ";
613     if (MCSymbol *Label = CFI.getLabel())
614       MachineOperand::printSymbol(OS, *Label);
615     break;
616   case MCCFIInstruction::OpRestoreState:
617     OS << "restore_state ";
618     if (MCSymbol *Label = CFI.getLabel())
619       MachineOperand::printSymbol(OS, *Label);
620     break;
621   case MCCFIInstruction::OpOffset:
622     OS << "offset ";
623     if (MCSymbol *Label = CFI.getLabel())
624       MachineOperand::printSymbol(OS, *Label);
625     printCFIRegister(CFI.getRegister(), OS, TRI);
626     OS << ", " << CFI.getOffset();
627     break;
628   case MCCFIInstruction::OpDefCfaRegister:
629     OS << "def_cfa_register ";
630     if (MCSymbol *Label = CFI.getLabel())
631       MachineOperand::printSymbol(OS, *Label);
632     printCFIRegister(CFI.getRegister(), OS, TRI);
633     break;
634   case MCCFIInstruction::OpDefCfaOffset:
635     OS << "def_cfa_offset ";
636     if (MCSymbol *Label = CFI.getLabel())
637       MachineOperand::printSymbol(OS, *Label);
638     OS << CFI.getOffset();
639     break;
640   case MCCFIInstruction::OpDefCfa:
641     OS << "def_cfa ";
642     if (MCSymbol *Label = CFI.getLabel())
643       MachineOperand::printSymbol(OS, *Label);
644     printCFIRegister(CFI.getRegister(), OS, TRI);
645     OS << ", " << CFI.getOffset();
646     break;
647   case MCCFIInstruction::OpRelOffset:
648     OS << "rel_offset ";
649     if (MCSymbol *Label = CFI.getLabel())
650       MachineOperand::printSymbol(OS, *Label);
651     printCFIRegister(CFI.getRegister(), OS, TRI);
652     OS << ", " << CFI.getOffset();
653     break;
654   case MCCFIInstruction::OpAdjustCfaOffset:
655     OS << "adjust_cfa_offset ";
656     if (MCSymbol *Label = CFI.getLabel())
657       MachineOperand::printSymbol(OS, *Label);
658     OS << CFI.getOffset();
659     break;
660   case MCCFIInstruction::OpRestore:
661     OS << "restore ";
662     if (MCSymbol *Label = CFI.getLabel())
663       MachineOperand::printSymbol(OS, *Label);
664     printCFIRegister(CFI.getRegister(), OS, TRI);
665     break;
666   case MCCFIInstruction::OpEscape: {
667     OS << "escape ";
668     if (MCSymbol *Label = CFI.getLabel())
669       MachineOperand::printSymbol(OS, *Label);
670     if (!CFI.getValues().empty()) {
671       size_t e = CFI.getValues().size() - 1;
672       for (size_t i = 0; i < e; ++i)
673         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
674       OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
675     }
676     break;
677   }
678   case MCCFIInstruction::OpUndefined:
679     OS << "undefined ";
680     if (MCSymbol *Label = CFI.getLabel())
681       MachineOperand::printSymbol(OS, *Label);
682     printCFIRegister(CFI.getRegister(), OS, TRI);
683     break;
684   case MCCFIInstruction::OpRegister:
685     OS << "register ";
686     if (MCSymbol *Label = CFI.getLabel())
687       MachineOperand::printSymbol(OS, *Label);
688     printCFIRegister(CFI.getRegister(), OS, TRI);
689     OS << ", ";
690     printCFIRegister(CFI.getRegister2(), OS, TRI);
691     break;
692   case MCCFIInstruction::OpWindowSave:
693     OS << "window_save ";
694     if (MCSymbol *Label = CFI.getLabel())
695       MachineOperand::printSymbol(OS, *Label);
696     break;
697   default:
698     // TODO: Print the other CFI Operations.
699     OS << "<unserializable cfi directive>";
700     break;
701   }
702 }
703 
704 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
705                            const TargetIntrinsicInfo *IntrinsicInfo) const {
706   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
707   ModuleSlotTracker DummyMST(nullptr);
708   print(OS, DummyMST, LLT{}, /*PrintDef=*/false, /*IsStandalone=*/true,
709         /*ShouldPrintRegisterTies=*/true,
710         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
711 }
712 
713 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
714                            LLT TypeToPrint, bool PrintDef, bool IsStandalone,
715                            bool ShouldPrintRegisterTies,
716                            unsigned TiedOperandIdx,
717                            const TargetRegisterInfo *TRI,
718                            const TargetIntrinsicInfo *IntrinsicInfo) const {
719   printTargetFlags(OS, *this);
720   switch (getType()) {
721   case MachineOperand::MO_Register: {
722     unsigned Reg = getReg();
723     if (isImplicit())
724       OS << (isDef() ? "implicit-def " : "implicit ");
725     else if (PrintDef && isDef())
726       // Print the 'def' flag only when the operand is defined after '='.
727       OS << "def ";
728     if (isInternalRead())
729       OS << "internal ";
730     if (isDead())
731       OS << "dead ";
732     if (isKill())
733       OS << "killed ";
734     if (isUndef())
735       OS << "undef ";
736     if (isEarlyClobber())
737       OS << "early-clobber ";
738     if (isDebug())
739       OS << "debug-use ";
740     if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
741       OS << "renamable ";
742 
743     const MachineRegisterInfo *MRI = nullptr;
744     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
745       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
746         MRI = &MF->getRegInfo();
747       }
748     }
749 
750     OS << printReg(Reg, TRI, 0, MRI);
751     // Print the sub register.
752     if (unsigned SubReg = getSubReg()) {
753       if (TRI)
754         OS << '.' << TRI->getSubRegIndexName(SubReg);
755       else
756         OS << ".subreg" << SubReg;
757     }
758     // Print the register class / bank.
759     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
760       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
761         const MachineRegisterInfo &MRI = MF->getRegInfo();
762         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
763           OS << ':';
764           OS << printRegClassOrBank(Reg, MRI, TRI);
765         }
766       }
767     }
768     // Print ties.
769     if (ShouldPrintRegisterTies && isTied() && !isDef())
770       OS << "(tied-def " << TiedOperandIdx << ")";
771     // Print types.
772     if (TypeToPrint.isValid())
773       OS << '(' << TypeToPrint << ')';
774     break;
775   }
776   case MachineOperand::MO_Immediate:
777     OS << getImm();
778     break;
779   case MachineOperand::MO_CImmediate:
780     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
781     break;
782   case MachineOperand::MO_FPImmediate:
783     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
784     break;
785   case MachineOperand::MO_MachineBasicBlock:
786     OS << printMBBReference(*getMBB());
787     break;
788   case MachineOperand::MO_FrameIndex: {
789     int FrameIndex = getIndex();
790     bool IsFixed = false;
791     const MachineFrameInfo *MFI = nullptr;
792     if (const MachineFunction *MF = getMFIfAvailable(*this))
793       MFI = &MF->getFrameInfo();
794     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
795     break;
796   }
797   case MachineOperand::MO_ConstantPoolIndex:
798     OS << "%const." << getIndex();
799     printOperandOffset(OS, getOffset());
800     break;
801   case MachineOperand::MO_TargetIndex: {
802     OS << "target-index(";
803     const char *Name = "<unknown>";
804     if (const MachineFunction *MF = getMFIfAvailable(*this))
805       if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
806         Name = TargetIndexName;
807     OS << Name << ')';
808     printOperandOffset(OS, getOffset());
809     break;
810   }
811   case MachineOperand::MO_JumpTableIndex:
812     OS << printJumpTableEntryReference(getIndex());
813     break;
814   case MachineOperand::MO_GlobalAddress:
815     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
816     printOperandOffset(OS, getOffset());
817     break;
818   case MachineOperand::MO_ExternalSymbol: {
819     StringRef Name = getSymbolName();
820     OS << '&';
821     if (Name.empty()) {
822       OS << "\"\"";
823     } else {
824       printLLVMNameWithoutPrefix(OS, Name);
825     }
826     printOperandOffset(OS, getOffset());
827     break;
828   }
829   case MachineOperand::MO_BlockAddress: {
830     OS << "blockaddress(";
831     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
832                                                      MST);
833     OS << ", ";
834     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
835     OS << ')';
836     MachineOperand::printOperandOffset(OS, getOffset());
837     break;
838   }
839   case MachineOperand::MO_RegisterMask: {
840     OS << "<regmask";
841     if (TRI) {
842       unsigned NumRegsInMask = 0;
843       unsigned NumRegsEmitted = 0;
844       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
845         unsigned MaskWord = i / 32;
846         unsigned MaskBit = i % 32;
847         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
848           if (PrintRegMaskNumRegs < 0 ||
849               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
850             OS << " " << printReg(i, TRI);
851             NumRegsEmitted++;
852           }
853           NumRegsInMask++;
854         }
855       }
856       if (NumRegsEmitted != NumRegsInMask)
857         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
858     } else {
859       OS << " ...";
860     }
861     OS << ">";
862     break;
863   }
864   case MachineOperand::MO_RegisterLiveOut: {
865     const uint32_t *RegMask = getRegLiveOut();
866     OS << "liveout(";
867     if (!TRI) {
868       OS << "<unknown>";
869     } else {
870       bool IsCommaNeeded = false;
871       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
872         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
873           if (IsCommaNeeded)
874             OS << ", ";
875           OS << printReg(Reg, TRI);
876           IsCommaNeeded = true;
877         }
878       }
879     }
880     OS << ")";
881     break;
882   }
883   case MachineOperand::MO_Metadata:
884     getMetadata()->printAsOperand(OS, MST);
885     break;
886   case MachineOperand::MO_MCSymbol:
887     printSymbol(OS, *getMCSymbol());
888     break;
889   case MachineOperand::MO_CFIIndex: {
890     if (const MachineFunction *MF = getMFIfAvailable(*this))
891       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
892     else
893       OS << "<cfi directive>";
894     break;
895   }
896   case MachineOperand::MO_IntrinsicID: {
897     Intrinsic::ID ID = getIntrinsicID();
898     if (ID < Intrinsic::num_intrinsics)
899       OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
900     else if (IntrinsicInfo)
901       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
902     else
903       OS << "intrinsic(" << ID << ')';
904     break;
905   }
906   case MachineOperand::MO_Predicate: {
907     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
908     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
909        << CmpInst::getPredicateName(Pred) << ')';
910     break;
911   }
912   }
913 }
914 
915 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
916 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
917 #endif
918 
919 //===----------------------------------------------------------------------===//
920 // MachineMemOperand Implementation
921 //===----------------------------------------------------------------------===//
922 
923 /// getAddrSpace - Return the LLVM IR address space number that this pointer
924 /// points into.
925 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
926 
927 /// isDereferenceable - Return true if V is always dereferenceable for
928 /// Offset + Size byte.
929 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
930                                            const DataLayout &DL) const {
931   if (!V.is<const Value *>())
932     return false;
933 
934   const Value *BasePtr = V.get<const Value *>();
935   if (BasePtr == nullptr)
936     return false;
937 
938   return isDereferenceableAndAlignedPointer(
939       BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
940 }
941 
942 /// getConstantPool - Return a MachinePointerInfo record that refers to the
943 /// constant pool.
944 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
945   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
946 }
947 
948 /// getFixedStack - Return a MachinePointerInfo record that refers to the
949 /// the specified FrameIndex.
950 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
951                                                      int FI, int64_t Offset) {
952   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
953 }
954 
955 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
956   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
957 }
958 
959 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
960   return MachinePointerInfo(MF.getPSVManager().getGOT());
961 }
962 
963 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
964                                                 int64_t Offset, uint8_t ID) {
965   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
966 }
967 
968 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
969   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
970 }
971 
972 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
973                                      uint64_t s, uint64_t a,
974                                      const AAMDNodes &AAInfo,
975                                      const MDNode *Ranges, SyncScope::ID SSID,
976                                      AtomicOrdering Ordering,
977                                      AtomicOrdering FailureOrdering)
978     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
979       AAInfo(AAInfo), Ranges(Ranges) {
980   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
981           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
982          "invalid pointer value");
983   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
984   assert((isLoad() || isStore()) && "Not a load/store!");
985 
986   AtomicInfo.SSID = static_cast<unsigned>(SSID);
987   assert(getSyncScopeID() == SSID && "Value truncated");
988   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
989   assert(getOrdering() == Ordering && "Value truncated");
990   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
991   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
992 }
993 
994 /// Profile - Gather unique data for the object.
995 ///
996 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
997   ID.AddInteger(getOffset());
998   ID.AddInteger(Size);
999   ID.AddPointer(getOpaqueValue());
1000   ID.AddInteger(getFlags());
1001   ID.AddInteger(getBaseAlignment());
1002 }
1003 
1004 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1005   // The Value and Offset may differ due to CSE. But the flags and size
1006   // should be the same.
1007   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1008   assert(MMO->getSize() == getSize() && "Size mismatch!");
1009 
1010   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1011     // Update the alignment value.
1012     BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1013     // Also update the base and offset, because the new alignment may
1014     // not be applicable with the old ones.
1015     PtrInfo = MMO->PtrInfo;
1016   }
1017 }
1018 
1019 /// getAlignment - Return the minimum known alignment in bytes of the
1020 /// actual memory reference.
1021 uint64_t MachineMemOperand::getAlignment() const {
1022   return MinAlign(getBaseAlignment(), getOffset());
1023 }
1024 
1025 void MachineMemOperand::print(raw_ostream &OS) const {
1026   ModuleSlotTracker DummyMST(nullptr);
1027   print(OS, DummyMST);
1028 }
1029 
1030 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1031   SmallVector<StringRef, 0> SSNs;
1032   LLVMContext Ctx;
1033   print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1034 }
1035 
1036 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1037                               SmallVectorImpl<StringRef> &SSNs,
1038                               const LLVMContext &Context,
1039                               const MachineFrameInfo *MFI,
1040                               const TargetInstrInfo *TII) const {
1041   OS << '(';
1042   if (isVolatile())
1043     OS << "volatile ";
1044   if (isNonTemporal())
1045     OS << "non-temporal ";
1046   if (isDereferenceable())
1047     OS << "dereferenceable ";
1048   if (isInvariant())
1049     OS << "invariant ";
1050   if (getFlags() & MachineMemOperand::MOTargetFlag1)
1051     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1052        << "\" ";
1053   if (getFlags() & MachineMemOperand::MOTargetFlag2)
1054     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1055        << "\" ";
1056   if (getFlags() & MachineMemOperand::MOTargetFlag3)
1057     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1058        << "\" ";
1059 
1060   assert((isLoad() || isStore()) &&
1061          "machine memory operand must be a load or store (or both)");
1062   if (isLoad())
1063     OS << "load ";
1064   if (isStore())
1065     OS << "store ";
1066 
1067   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1068 
1069   if (getOrdering() != AtomicOrdering::NotAtomic)
1070     OS << toIRString(getOrdering()) << ' ';
1071   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1072     OS << toIRString(getFailureOrdering()) << ' ';
1073 
1074   OS << getSize();
1075   if (const Value *Val = getValue()) {
1076     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1077     printIRValueReference(OS, *Val, MST);
1078   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1079     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1080     assert(PVal && "Expected a pseudo source value");
1081     switch (PVal->kind()) {
1082     case PseudoSourceValue::Stack:
1083       OS << "stack";
1084       break;
1085     case PseudoSourceValue::GOT:
1086       OS << "got";
1087       break;
1088     case PseudoSourceValue::JumpTable:
1089       OS << "jump-table";
1090       break;
1091     case PseudoSourceValue::ConstantPool:
1092       OS << "constant-pool";
1093       break;
1094     case PseudoSourceValue::FixedStack: {
1095       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1096       bool IsFixed = true;
1097       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1098       break;
1099     }
1100     case PseudoSourceValue::GlobalValueCallEntry:
1101       OS << "call-entry ";
1102       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1103           OS, /*PrintType=*/false, MST);
1104       break;
1105     case PseudoSourceValue::ExternalSymbolCallEntry:
1106       OS << "call-entry &";
1107       printLLVMNameWithoutPrefix(
1108           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1109       break;
1110     case PseudoSourceValue::TargetCustom:
1111       // FIXME: This is not necessarily the correct MIR serialization format for
1112       // a custom pseudo source value, but at least it allows
1113       // -print-machineinstrs to work on a target with custom pseudo source
1114       // values.
1115       OS << "custom ";
1116       PVal->printCustom(OS);
1117       break;
1118     }
1119   }
1120   MachineOperand::printOperandOffset(OS, getOffset());
1121   if (getBaseAlignment() != getSize())
1122     OS << ", align " << getBaseAlignment();
1123   auto AAInfo = getAAInfo();
1124   if (AAInfo.TBAA) {
1125     OS << ", !tbaa ";
1126     AAInfo.TBAA->printAsOperand(OS, MST);
1127   }
1128   if (AAInfo.Scope) {
1129     OS << ", !alias.scope ";
1130     AAInfo.Scope->printAsOperand(OS, MST);
1131   }
1132   if (AAInfo.NoAlias) {
1133     OS << ", !noalias ";
1134     AAInfo.NoAlias->printAsOperand(OS, MST);
1135   }
1136   if (getRanges()) {
1137     OS << ", !range ";
1138     getRanges()->printAsOperand(OS, MST);
1139   }
1140   // FIXME: Implement addrspace printing/parsing in MIR.
1141   // For now, print this even though parsing it is not available in MIR.
1142   if (unsigned AS = getAddrSpace())
1143     OS << ", addrspace " << AS;
1144 
1145   OS << ')';
1146 }
1147