xref: /llvm-project/llvm/lib/CodeGen/MachineOperand.cpp (revision 8a45032e5c3ad8581fd925b1ec670c82df38f8fe) 
1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/MachineOperand.h"
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
17 #include "llvm/CodeGen/MIRFormatter.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/StableHashing.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/Instructions.h"
28 #include "llvm/IR/ModuleSlotTracker.h"
29 #include "llvm/MC/MCDwarf.h"
30 #include "llvm/Target/TargetIntrinsicInfo.h"
31 #include "llvm/Target/TargetMachine.h"
32 #include <optional>
33 
34 using namespace llvm;
35 
36 static cl::opt<int>
37     PrintRegMaskNumRegs("print-regmask-num-regs",
38                         cl::desc("Number of registers to limit to when "
39                                  "printing regmask operands in IR dumps. "
40                                  "unlimited = -1"),
41                         cl::init(32), cl::Hidden);
42 
43 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
44   if (const MachineInstr *MI = MO.getParent())
45     if (const MachineBasicBlock *MBB = MI->getParent())
46       if (const MachineFunction *MF = MBB->getParent())
47         return MF;
48   return nullptr;
49 }
50 
51 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
52   return const_cast<MachineFunction *>(
53       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
54 }
55 
56 void MachineOperand::setReg(Register Reg) {
57   if (getReg() == Reg)
58     return; // No change.
59 
60   // Clear the IsRenamable bit to keep it conservatively correct.
61   IsRenamable = false;
62 
63   // Otherwise, we have to change the register.  If this operand is embedded
64   // into a machine function, we need to update the old and new register's
65   // use/def lists.
66   if (MachineFunction *MF = getMFIfAvailable(*this)) {
67     MachineRegisterInfo &MRI = MF->getRegInfo();
68     MRI.removeRegOperandFromUseList(this);
69     SmallContents.RegNo = Reg;
70     MRI.addRegOperandToUseList(this);
71     return;
72   }
73 
74   // Otherwise, just change the register, no problem.  :)
75   SmallContents.RegNo = Reg;
76 }
77 
78 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
79                                   const TargetRegisterInfo &TRI) {
80   assert(Reg.isVirtual());
81   if (SubIdx && getSubReg())
82     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
83   setReg(Reg);
84   if (SubIdx)
85     setSubReg(SubIdx);
86 }
87 
88 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
89   assert(Register::isPhysicalRegister(Reg));
90   if (getSubReg()) {
91     Reg = TRI.getSubReg(Reg, getSubReg());
92     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
93     // That won't happen in legal code.
94     setSubReg(0);
95     if (isDef())
96       setIsUndef(false);
97   }
98   setReg(Reg);
99 }
100 
101 /// Change a def to a use, or a use to a def.
102 void MachineOperand::setIsDef(bool Val) {
103   assert(isReg() && "Wrong MachineOperand accessor");
104   assert((!Val || !isDebug()) && "Marking a debug operation as def");
105   if (IsDef == Val)
106     return;
107   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
108   // MRI may keep uses and defs in different list positions.
109   if (MachineFunction *MF = getMFIfAvailable(*this)) {
110     MachineRegisterInfo &MRI = MF->getRegInfo();
111     MRI.removeRegOperandFromUseList(this);
112     IsDef = Val;
113     MRI.addRegOperandToUseList(this);
114     return;
115   }
116   IsDef = Val;
117 }
118 
119 bool MachineOperand::isRenamable() const {
120   assert(isReg() && "Wrong MachineOperand accessor");
121   assert(Register::isPhysicalRegister(getReg()) &&
122          "isRenamable should only be checked on physical registers");
123   if (!IsRenamable)
124     return false;
125 
126   const MachineInstr *MI = getParent();
127   if (!MI)
128     return true;
129 
130   if (isDef())
131     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
132 
133   assert(isUse() && "Reg is not def or use");
134   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
135 }
136 
137 void MachineOperand::setIsRenamable(bool Val) {
138   assert(isReg() && "Wrong MachineOperand accessor");
139   assert(Register::isPhysicalRegister(getReg()) &&
140          "setIsRenamable should only be called on physical registers");
141   IsRenamable = Val;
142 }
143 
144 // If this operand is currently a register operand, and if this is in a
145 // function, deregister the operand from the register's use/def list.
146 void MachineOperand::removeRegFromUses() {
147   if (!isReg() || !isOnRegUseList())
148     return;
149 
150   if (MachineFunction *MF = getMFIfAvailable(*this))
151     MF->getRegInfo().removeRegOperandFromUseList(this);
152 }
153 
154 /// ChangeToImmediate - Replace this operand with a new immediate operand of
155 /// the specified value.  If an operand is known to be an immediate already,
156 /// the setImm method should be used.
157 void MachineOperand::ChangeToImmediate(int64_t ImmVal, unsigned TargetFlags) {
158   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
159 
160   removeRegFromUses();
161 
162   OpKind = MO_Immediate;
163   Contents.ImmVal = ImmVal;
164   setTargetFlags(TargetFlags);
165 }
166 
167 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm,
168                                          unsigned TargetFlags) {
169   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
170 
171   removeRegFromUses();
172 
173   OpKind = MO_FPImmediate;
174   Contents.CFP = FPImm;
175   setTargetFlags(TargetFlags);
176 }
177 
178 void MachineOperand::ChangeToES(const char *SymName,
179                                 unsigned TargetFlags) {
180   assert((!isReg() || !isTied()) &&
181          "Cannot change a tied operand into an external symbol");
182 
183   removeRegFromUses();
184 
185   OpKind = MO_ExternalSymbol;
186   Contents.OffsetedInfo.Val.SymbolName = SymName;
187   setOffset(0); // Offset is always 0.
188   setTargetFlags(TargetFlags);
189 }
190 
191 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
192                                 unsigned TargetFlags) {
193   assert((!isReg() || !isTied()) &&
194          "Cannot change a tied operand into a global address");
195 
196   removeRegFromUses();
197 
198   OpKind = MO_GlobalAddress;
199   Contents.OffsetedInfo.Val.GV = GV;
200   setOffset(Offset);
201   setTargetFlags(TargetFlags);
202 }
203 
204 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym, unsigned TargetFlags) {
205   assert((!isReg() || !isTied()) &&
206          "Cannot change a tied operand into an MCSymbol");
207 
208   removeRegFromUses();
209 
210   OpKind = MO_MCSymbol;
211   Contents.Sym = Sym;
212   setTargetFlags(TargetFlags);
213 }
214 
215 void MachineOperand::ChangeToFrameIndex(int Idx, unsigned TargetFlags) {
216   assert((!isReg() || !isTied()) &&
217          "Cannot change a tied operand into a FrameIndex");
218 
219   removeRegFromUses();
220 
221   OpKind = MO_FrameIndex;
222   setIndex(Idx);
223   setTargetFlags(TargetFlags);
224 }
225 
226 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
227                                          unsigned TargetFlags) {
228   assert((!isReg() || !isTied()) &&
229          "Cannot change a tied operand into a FrameIndex");
230 
231   removeRegFromUses();
232 
233   OpKind = MO_TargetIndex;
234   setIndex(Idx);
235   setOffset(Offset);
236   setTargetFlags(TargetFlags);
237 }
238 
239 /// ChangeToRegister - Replace this operand with a new register operand of
240 /// the specified value.  If an operand is known to be an register already,
241 /// the setReg method should be used.
242 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
243                                       bool isKill, bool isDead, bool isUndef,
244                                       bool isDebug) {
245   MachineRegisterInfo *RegInfo = nullptr;
246   if (MachineFunction *MF = getMFIfAvailable(*this))
247     RegInfo = &MF->getRegInfo();
248   // If this operand is already a register operand, remove it from the
249   // register's use/def lists.
250   bool WasReg = isReg();
251   if (RegInfo && WasReg)
252     RegInfo->removeRegOperandFromUseList(this);
253 
254   // Ensure debug instructions set debug flag on register uses.
255   const MachineInstr *MI = getParent();
256   if (!isDef && MI && MI->isDebugInstr())
257     isDebug = true;
258 
259   // Change this to a register and set the reg#.
260   assert(!(isDead && !isDef) && "Dead flag on non-def");
261   assert(!(isKill && isDef) && "Kill flag on def");
262   OpKind = MO_Register;
263   SmallContents.RegNo = Reg;
264   SubReg_TargetFlags = 0;
265   IsDef = isDef;
266   IsImp = isImp;
267   IsDeadOrKill = isKill | isDead;
268   IsRenamable = false;
269   IsUndef = isUndef;
270   IsInternalRead = false;
271   IsEarlyClobber = false;
272   IsDebug = isDebug;
273   // Ensure isOnRegUseList() returns false.
274   Contents.Reg.Prev = nullptr;
275   // Preserve the tie when the operand was already a register.
276   if (!WasReg)
277     TiedTo = 0;
278 
279   // If this operand is embedded in a function, add the operand to the
280   // register's use/def list.
281   if (RegInfo)
282     RegInfo->addRegOperandToUseList(this);
283 }
284 
285 /// isIdenticalTo - Return true if this operand is identical to the specified
286 /// operand. Note that this should stay in sync with the hash_value overload
287 /// below.
288 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
289   if (getType() != Other.getType() ||
290       getTargetFlags() != Other.getTargetFlags())
291     return false;
292 
293   switch (getType()) {
294   case MachineOperand::MO_Register:
295     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
296            getSubReg() == Other.getSubReg();
297   case MachineOperand::MO_Immediate:
298     return getImm() == Other.getImm();
299   case MachineOperand::MO_CImmediate:
300     return getCImm() == Other.getCImm();
301   case MachineOperand::MO_FPImmediate:
302     return getFPImm() == Other.getFPImm();
303   case MachineOperand::MO_MachineBasicBlock:
304     return getMBB() == Other.getMBB();
305   case MachineOperand::MO_FrameIndex:
306     return getIndex() == Other.getIndex();
307   case MachineOperand::MO_ConstantPoolIndex:
308   case MachineOperand::MO_TargetIndex:
309     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
310   case MachineOperand::MO_JumpTableIndex:
311     return getIndex() == Other.getIndex();
312   case MachineOperand::MO_GlobalAddress:
313     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
314   case MachineOperand::MO_ExternalSymbol:
315     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
316            getOffset() == Other.getOffset();
317   case MachineOperand::MO_BlockAddress:
318     return getBlockAddress() == Other.getBlockAddress() &&
319            getOffset() == Other.getOffset();
320   case MachineOperand::MO_RegisterMask:
321   case MachineOperand::MO_RegisterLiveOut: {
322     // Shallow compare of the two RegMasks
323     const uint32_t *RegMask = getRegMask();
324     const uint32_t *OtherRegMask = Other.getRegMask();
325     if (RegMask == OtherRegMask)
326       return true;
327 
328     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
329       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
330       unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
331       // Deep compare of the two RegMasks
332       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
333     }
334     // We don't know the size of the RegMask, so we can't deep compare the two
335     // reg masks.
336     return false;
337   }
338   case MachineOperand::MO_MCSymbol:
339     return getMCSymbol() == Other.getMCSymbol();
340   case MachineOperand::MO_CFIIndex:
341     return getCFIIndex() == Other.getCFIIndex();
342   case MachineOperand::MO_Metadata:
343     return getMetadata() == Other.getMetadata();
344   case MachineOperand::MO_IntrinsicID:
345     return getIntrinsicID() == Other.getIntrinsicID();
346   case MachineOperand::MO_Predicate:
347     return getPredicate() == Other.getPredicate();
348   case MachineOperand::MO_ShuffleMask:
349     return getShuffleMask() == Other.getShuffleMask();
350   }
351   llvm_unreachable("Invalid machine operand type");
352 }
353 
354 // Note: this must stay exactly in sync with isIdenticalTo above.
355 hash_code llvm::hash_value(const MachineOperand &MO) {
356   switch (MO.getType()) {
357   case MachineOperand::MO_Register:
358     // Register operands don't have target flags.
359     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
360   case MachineOperand::MO_Immediate:
361     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
362   case MachineOperand::MO_CImmediate:
363     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
364   case MachineOperand::MO_FPImmediate:
365     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
366   case MachineOperand::MO_MachineBasicBlock:
367     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
368   case MachineOperand::MO_FrameIndex:
369     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
370   case MachineOperand::MO_ConstantPoolIndex:
371   case MachineOperand::MO_TargetIndex:
372     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
373                         MO.getOffset());
374   case MachineOperand::MO_JumpTableIndex:
375     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
376   case MachineOperand::MO_ExternalSymbol:
377     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
378                         StringRef(MO.getSymbolName()));
379   case MachineOperand::MO_GlobalAddress:
380     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
381                         MO.getOffset());
382   case MachineOperand::MO_BlockAddress:
383     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
384                         MO.getOffset());
385   case MachineOperand::MO_RegisterMask:
386   case MachineOperand::MO_RegisterLiveOut: {
387     if (const MachineFunction *MF = getMFIfAvailable(MO)) {
388       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
389       unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
390       const uint32_t *RegMask = MO.getRegMask();
391       std::vector<stable_hash> RegMaskHashes(RegMask, RegMask + RegMaskSize);
392       return hash_combine(MO.getType(), MO.getTargetFlags(),
393                           stable_hash_combine_array(RegMaskHashes.data(),
394                                                     RegMaskHashes.size()));
395     }
396 
397     assert(0 && "MachineOperand not associated with any MachineFunction");
398     return hash_combine(MO.getType(), MO.getTargetFlags());
399   }
400   case MachineOperand::MO_Metadata:
401     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
402   case MachineOperand::MO_MCSymbol:
403     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
404   case MachineOperand::MO_CFIIndex:
405     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
406   case MachineOperand::MO_IntrinsicID:
407     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
408   case MachineOperand::MO_Predicate:
409     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
410   case MachineOperand::MO_ShuffleMask:
411     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
412   }
413   llvm_unreachable("Invalid machine operand type");
414 }
415 
416 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
417 // it.
418 static void tryToGetTargetInfo(const MachineOperand &MO,
419                                const TargetRegisterInfo *&TRI,
420                                const TargetIntrinsicInfo *&IntrinsicInfo) {
421   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
422     TRI = MF->getSubtarget().getRegisterInfo();
423     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
424   }
425 }
426 
427 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
428   const auto *TII = MF.getSubtarget().getInstrInfo();
429   assert(TII && "expected instruction info");
430   auto Indices = TII->getSerializableTargetIndices();
431   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
432     return I.first == Index;
433   });
434   if (Found != Indices.end())
435     return Found->second;
436   return nullptr;
437 }
438 
439 const char *MachineOperand::getTargetIndexName() const {
440   const MachineFunction *MF = getMFIfAvailable(*this);
441   return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
442 }
443 
444 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
445   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
446   for (const auto &I : Flags) {
447     if (I.first == TF) {
448       return I.second;
449     }
450   }
451   return nullptr;
452 }
453 
454 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
455                              const TargetRegisterInfo *TRI) {
456   if (!TRI) {
457     OS << "%dwarfreg." << DwarfReg;
458     return;
459   }
460 
461   if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
462     OS << printReg(*Reg, TRI);
463   else
464     OS << "<badreg>";
465 }
466 
467 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
468                                   ModuleSlotTracker &MST) {
469   OS << "%ir-block.";
470   if (BB.hasName()) {
471     printLLVMNameWithoutPrefix(OS, BB.getName());
472     return;
473   }
474   std::optional<int> Slot;
475   if (const Function *F = BB.getParent()) {
476     if (F == MST.getCurrentFunction()) {
477       Slot = MST.getLocalSlot(&BB);
478     } else if (const Module *M = F->getParent()) {
479       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
480       CustomMST.incorporateFunction(*F);
481       Slot = CustomMST.getLocalSlot(&BB);
482     }
483   }
484   if (Slot)
485     MachineOperand::printIRSlotNumber(OS, *Slot);
486   else
487     OS << "<unknown>";
488 }
489 
490 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
491                            SyncScope::ID SSID,
492                            SmallVectorImpl<StringRef> &SSNs) {
493   switch (SSID) {
494   case SyncScope::System:
495     break;
496   default:
497     if (SSNs.empty())
498       Context.getSyncScopeNames(SSNs);
499 
500     OS << "syncscope(\"";
501     printEscapedString(SSNs[SSID], OS);
502     OS << "\") ";
503     break;
504   }
505 }
506 
507 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
508                                         unsigned TMMOFlag) {
509   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
510   for (const auto &I : Flags) {
511     if (I.first == TMMOFlag) {
512       return I.second;
513     }
514   }
515   return nullptr;
516 }
517 
518 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
519                             const MachineFrameInfo *MFI) {
520   StringRef Name;
521   if (MFI) {
522     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
523     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
524       if (Alloca->hasName())
525         Name = Alloca->getName();
526     if (IsFixed)
527       FrameIndex -= MFI->getObjectIndexBegin();
528   }
529   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
530 }
531 
532 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
533                                     const TargetRegisterInfo *TRI) {
534   OS << "%subreg.";
535   if (TRI && Index != 0 && Index < TRI->getNumSubRegIndices())
536     OS << TRI->getSubRegIndexName(Index);
537   else
538     OS << Index;
539 }
540 
541 void MachineOperand::printTargetFlags(raw_ostream &OS,
542                                       const MachineOperand &Op) {
543   if (!Op.getTargetFlags())
544     return;
545   const MachineFunction *MF = getMFIfAvailable(Op);
546   if (!MF)
547     return;
548 
549   const auto *TII = MF->getSubtarget().getInstrInfo();
550   assert(TII && "expected instruction info");
551   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
552   OS << "target-flags(";
553   const bool HasDirectFlags = Flags.first;
554   const bool HasBitmaskFlags = Flags.second;
555   if (!HasDirectFlags && !HasBitmaskFlags) {
556     OS << "<unknown>) ";
557     return;
558   }
559   if (HasDirectFlags) {
560     if (const auto *Name = getTargetFlagName(TII, Flags.first))
561       OS << Name;
562     else
563       OS << "<unknown target flag>";
564   }
565   if (!HasBitmaskFlags) {
566     OS << ") ";
567     return;
568   }
569   bool IsCommaNeeded = HasDirectFlags;
570   unsigned BitMask = Flags.second;
571   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
572   for (const auto &Mask : BitMasks) {
573     // Check if the flag's bitmask has the bits of the current mask set.
574     if ((BitMask & Mask.first) == Mask.first) {
575       if (IsCommaNeeded)
576         OS << ", ";
577       IsCommaNeeded = true;
578       OS << Mask.second;
579       // Clear the bits which were serialized from the flag's bitmask.
580       BitMask &= ~(Mask.first);
581     }
582   }
583   if (BitMask) {
584     // When the resulting flag's bitmask isn't zero, we know that we didn't
585     // serialize all of the bit flags.
586     if (IsCommaNeeded)
587       OS << ", ";
588     OS << "<unknown bitmask target flag>";
589   }
590   OS << ") ";
591 }
592 
593 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
594   OS << "<mcsymbol " << Sym << ">";
595 }
596 
597 void MachineOperand::printStackObjectReference(raw_ostream &OS,
598                                                unsigned FrameIndex,
599                                                bool IsFixed, StringRef Name) {
600   if (IsFixed) {
601     OS << "%fixed-stack." << FrameIndex;
602     return;
603   }
604 
605   OS << "%stack." << FrameIndex;
606   if (!Name.empty())
607     OS << '.' << Name;
608 }
609 
610 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
611   if (Offset == 0)
612     return;
613   if (Offset < 0) {
614     OS << " - " << -Offset;
615     return;
616   }
617   OS << " + " << Offset;
618 }
619 
620 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
621   if (Slot == -1)
622     OS << "<badref>";
623   else
624     OS << Slot;
625 }
626 
627 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
628                      const TargetRegisterInfo *TRI) {
629   switch (CFI.getOperation()) {
630   case MCCFIInstruction::OpSameValue:
631     OS << "same_value ";
632     if (MCSymbol *Label = CFI.getLabel())
633       MachineOperand::printSymbol(OS, *Label);
634     printCFIRegister(CFI.getRegister(), OS, TRI);
635     break;
636   case MCCFIInstruction::OpRememberState:
637     OS << "remember_state ";
638     if (MCSymbol *Label = CFI.getLabel())
639       MachineOperand::printSymbol(OS, *Label);
640     break;
641   case MCCFIInstruction::OpRestoreState:
642     OS << "restore_state ";
643     if (MCSymbol *Label = CFI.getLabel())
644       MachineOperand::printSymbol(OS, *Label);
645     break;
646   case MCCFIInstruction::OpOffset:
647     OS << "offset ";
648     if (MCSymbol *Label = CFI.getLabel())
649       MachineOperand::printSymbol(OS, *Label);
650     printCFIRegister(CFI.getRegister(), OS, TRI);
651     OS << ", " << CFI.getOffset();
652     break;
653   case MCCFIInstruction::OpDefCfaRegister:
654     OS << "def_cfa_register ";
655     if (MCSymbol *Label = CFI.getLabel())
656       MachineOperand::printSymbol(OS, *Label);
657     printCFIRegister(CFI.getRegister(), OS, TRI);
658     break;
659   case MCCFIInstruction::OpDefCfaOffset:
660     OS << "def_cfa_offset ";
661     if (MCSymbol *Label = CFI.getLabel())
662       MachineOperand::printSymbol(OS, *Label);
663     OS << CFI.getOffset();
664     break;
665   case MCCFIInstruction::OpDefCfa:
666     OS << "def_cfa ";
667     if (MCSymbol *Label = CFI.getLabel())
668       MachineOperand::printSymbol(OS, *Label);
669     printCFIRegister(CFI.getRegister(), OS, TRI);
670     OS << ", " << CFI.getOffset();
671     break;
672   case MCCFIInstruction::OpLLVMDefAspaceCfa:
673     OS << "llvm_def_aspace_cfa ";
674     if (MCSymbol *Label = CFI.getLabel())
675       MachineOperand::printSymbol(OS, *Label);
676     printCFIRegister(CFI.getRegister(), OS, TRI);
677     OS << ", " << CFI.getOffset();
678     OS << ", " << CFI.getAddressSpace();
679     break;
680   case MCCFIInstruction::OpRelOffset:
681     OS << "rel_offset ";
682     if (MCSymbol *Label = CFI.getLabel())
683       MachineOperand::printSymbol(OS, *Label);
684     printCFIRegister(CFI.getRegister(), OS, TRI);
685     OS << ", " << CFI.getOffset();
686     break;
687   case MCCFIInstruction::OpAdjustCfaOffset:
688     OS << "adjust_cfa_offset ";
689     if (MCSymbol *Label = CFI.getLabel())
690       MachineOperand::printSymbol(OS, *Label);
691     OS << CFI.getOffset();
692     break;
693   case MCCFIInstruction::OpRestore:
694     OS << "restore ";
695     if (MCSymbol *Label = CFI.getLabel())
696       MachineOperand::printSymbol(OS, *Label);
697     printCFIRegister(CFI.getRegister(), OS, TRI);
698     break;
699   case MCCFIInstruction::OpEscape: {
700     OS << "escape ";
701     if (MCSymbol *Label = CFI.getLabel())
702       MachineOperand::printSymbol(OS, *Label);
703     if (!CFI.getValues().empty()) {
704       size_t e = CFI.getValues().size() - 1;
705       for (size_t i = 0; i < e; ++i)
706         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
707       OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
708     }
709     break;
710   }
711   case MCCFIInstruction::OpUndefined:
712     OS << "undefined ";
713     if (MCSymbol *Label = CFI.getLabel())
714       MachineOperand::printSymbol(OS, *Label);
715     printCFIRegister(CFI.getRegister(), OS, TRI);
716     break;
717   case MCCFIInstruction::OpRegister:
718     OS << "register ";
719     if (MCSymbol *Label = CFI.getLabel())
720       MachineOperand::printSymbol(OS, *Label);
721     printCFIRegister(CFI.getRegister(), OS, TRI);
722     OS << ", ";
723     printCFIRegister(CFI.getRegister2(), OS, TRI);
724     break;
725   case MCCFIInstruction::OpWindowSave:
726     OS << "window_save ";
727     if (MCSymbol *Label = CFI.getLabel())
728       MachineOperand::printSymbol(OS, *Label);
729     break;
730   case MCCFIInstruction::OpNegateRAState:
731     OS << "negate_ra_sign_state ";
732     if (MCSymbol *Label = CFI.getLabel())
733       MachineOperand::printSymbol(OS, *Label);
734     break;
735   default:
736     // TODO: Print the other CFI Operations.
737     OS << "<unserializable cfi directive>";
738     break;
739   }
740 }
741 
742 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
743                            const TargetIntrinsicInfo *IntrinsicInfo) const {
744   print(OS, LLT{}, TRI, IntrinsicInfo);
745 }
746 
747 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
748                            const TargetRegisterInfo *TRI,
749                            const TargetIntrinsicInfo *IntrinsicInfo) const {
750   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
751   ModuleSlotTracker DummyMST(nullptr);
752   print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
753         /*IsStandalone=*/true,
754         /*ShouldPrintRegisterTies=*/true,
755         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
756 }
757 
758 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
759                            LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
760                            bool IsStandalone, bool ShouldPrintRegisterTies,
761                            unsigned TiedOperandIdx,
762                            const TargetRegisterInfo *TRI,
763                            const TargetIntrinsicInfo *IntrinsicInfo) const {
764   printTargetFlags(OS, *this);
765   switch (getType()) {
766   case MachineOperand::MO_Register: {
767     Register Reg = getReg();
768     if (isImplicit())
769       OS << (isDef() ? "implicit-def " : "implicit ");
770     else if (PrintDef && isDef())
771       // Print the 'def' flag only when the operand is defined after '='.
772       OS << "def ";
773     if (isInternalRead())
774       OS << "internal ";
775     if (isDead())
776       OS << "dead ";
777     if (isKill())
778       OS << "killed ";
779     if (isUndef())
780       OS << "undef ";
781     if (isEarlyClobber())
782       OS << "early-clobber ";
783     if (Register::isPhysicalRegister(getReg()) && isRenamable())
784       OS << "renamable ";
785     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
786     // simply infer it when parsing and do not need to print it.
787 
788     const MachineRegisterInfo *MRI = nullptr;
789     if (Register::isVirtualRegister(Reg)) {
790       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
791         MRI = &MF->getRegInfo();
792       }
793     }
794 
795     OS << printReg(Reg, TRI, 0, MRI);
796     // Print the sub register.
797     if (unsigned SubReg = getSubReg()) {
798       if (TRI)
799         OS << '.' << TRI->getSubRegIndexName(SubReg);
800       else
801         OS << ".subreg" << SubReg;
802     }
803     // Print the register class / bank.
804     if (Register::isVirtualRegister(Reg)) {
805       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
806         const MachineRegisterInfo &MRI = MF->getRegInfo();
807         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
808           OS << ':';
809           OS << printRegClassOrBank(Reg, MRI, TRI);
810         }
811       }
812     }
813     // Print ties.
814     if (ShouldPrintRegisterTies && isTied() && !isDef())
815       OS << "(tied-def " << TiedOperandIdx << ")";
816     // Print types.
817     if (TypeToPrint.isValid())
818       OS << '(' << TypeToPrint << ')';
819     break;
820   }
821   case MachineOperand::MO_Immediate: {
822     const MIRFormatter *Formatter = nullptr;
823     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
824       const auto *TII = MF->getSubtarget().getInstrInfo();
825       assert(TII && "expected instruction info");
826       Formatter = TII->getMIRFormatter();
827     }
828     if (Formatter)
829       Formatter->printImm(OS, *getParent(), OpIdx, getImm());
830     else
831       OS << getImm();
832     break;
833   }
834   case MachineOperand::MO_CImmediate:
835     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
836     break;
837   case MachineOperand::MO_FPImmediate:
838     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
839     break;
840   case MachineOperand::MO_MachineBasicBlock:
841     OS << printMBBReference(*getMBB());
842     break;
843   case MachineOperand::MO_FrameIndex: {
844     int FrameIndex = getIndex();
845     bool IsFixed = false;
846     const MachineFrameInfo *MFI = nullptr;
847     if (const MachineFunction *MF = getMFIfAvailable(*this))
848       MFI = &MF->getFrameInfo();
849     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
850     break;
851   }
852   case MachineOperand::MO_ConstantPoolIndex:
853     OS << "%const." << getIndex();
854     printOperandOffset(OS, getOffset());
855     break;
856   case MachineOperand::MO_TargetIndex: {
857     OS << "target-index(";
858     const char *Name = "<unknown>";
859     if (const MachineFunction *MF = getMFIfAvailable(*this))
860       if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
861         Name = TargetIndexName;
862     OS << Name << ')';
863     printOperandOffset(OS, getOffset());
864     break;
865   }
866   case MachineOperand::MO_JumpTableIndex:
867     OS << printJumpTableEntryReference(getIndex());
868     break;
869   case MachineOperand::MO_GlobalAddress:
870     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
871     printOperandOffset(OS, getOffset());
872     break;
873   case MachineOperand::MO_ExternalSymbol: {
874     StringRef Name = getSymbolName();
875     OS << '&';
876     if (Name.empty()) {
877       OS << "\"\"";
878     } else {
879       printLLVMNameWithoutPrefix(OS, Name);
880     }
881     printOperandOffset(OS, getOffset());
882     break;
883   }
884   case MachineOperand::MO_BlockAddress: {
885     OS << "blockaddress(";
886     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
887                                                      MST);
888     OS << ", ";
889     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
890     OS << ')';
891     MachineOperand::printOperandOffset(OS, getOffset());
892     break;
893   }
894   case MachineOperand::MO_RegisterMask: {
895     OS << "<regmask";
896     if (TRI) {
897       unsigned NumRegsInMask = 0;
898       unsigned NumRegsEmitted = 0;
899       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
900         unsigned MaskWord = i / 32;
901         unsigned MaskBit = i % 32;
902         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
903           if (PrintRegMaskNumRegs < 0 ||
904               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
905             OS << " " << printReg(i, TRI);
906             NumRegsEmitted++;
907           }
908           NumRegsInMask++;
909         }
910       }
911       if (NumRegsEmitted != NumRegsInMask)
912         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
913     } else {
914       OS << " ...";
915     }
916     OS << ">";
917     break;
918   }
919   case MachineOperand::MO_RegisterLiveOut: {
920     const uint32_t *RegMask = getRegLiveOut();
921     OS << "liveout(";
922     if (!TRI) {
923       OS << "<unknown>";
924     } else {
925       bool IsCommaNeeded = false;
926       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
927         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
928           if (IsCommaNeeded)
929             OS << ", ";
930           OS << printReg(Reg, TRI);
931           IsCommaNeeded = true;
932         }
933       }
934     }
935     OS << ")";
936     break;
937   }
938   case MachineOperand::MO_Metadata:
939     getMetadata()->printAsOperand(OS, MST);
940     break;
941   case MachineOperand::MO_MCSymbol:
942     printSymbol(OS, *getMCSymbol());
943     break;
944   case MachineOperand::MO_CFIIndex: {
945     if (const MachineFunction *MF = getMFIfAvailable(*this))
946       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
947     else
948       OS << "<cfi directive>";
949     break;
950   }
951   case MachineOperand::MO_IntrinsicID: {
952     Intrinsic::ID ID = getIntrinsicID();
953     if (ID < Intrinsic::num_intrinsics)
954       OS << "intrinsic(@" << Intrinsic::getBaseName(ID) << ')';
955     else if (IntrinsicInfo)
956       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
957     else
958       OS << "intrinsic(" << ID << ')';
959     break;
960   }
961   case MachineOperand::MO_Predicate: {
962     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
963     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
964        << CmpInst::getPredicateName(Pred) << ')';
965     break;
966   }
967   case MachineOperand::MO_ShuffleMask:
968     OS << "shufflemask(";
969     ArrayRef<int> Mask = getShuffleMask();
970     StringRef Separator;
971     for (int Elt : Mask) {
972       if (Elt == -1)
973         OS << Separator << "undef";
974       else
975         OS << Separator << Elt;
976       Separator = ", ";
977     }
978 
979     OS << ')';
980     break;
981   }
982 }
983 
984 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
985 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
986 #endif
987 
988 //===----------------------------------------------------------------------===//
989 // MachineMemOperand Implementation
990 //===----------------------------------------------------------------------===//
991 
992 /// getAddrSpace - Return the LLVM IR address space number that this pointer
993 /// points into.
994 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
995 
996 /// isDereferenceable - Return true if V is always dereferenceable for
997 /// Offset + Size byte.
998 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
999                                            const DataLayout &DL) const {
1000   if (!V.is<const Value *>())
1001     return false;
1002 
1003   const Value *BasePtr = V.get<const Value *>();
1004   if (BasePtr == nullptr)
1005     return false;
1006 
1007   return isDereferenceableAndAlignedPointer(
1008       BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
1009 }
1010 
1011 /// getConstantPool - Return a MachinePointerInfo record that refers to the
1012 /// constant pool.
1013 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
1014   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
1015 }
1016 
1017 /// getFixedStack - Return a MachinePointerInfo record that refers to the
1018 /// the specified FrameIndex.
1019 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
1020                                                      int FI, int64_t Offset) {
1021   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
1022 }
1023 
1024 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
1025   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1026 }
1027 
1028 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1029   return MachinePointerInfo(MF.getPSVManager().getGOT());
1030 }
1031 
1032 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1033                                                 int64_t Offset, uint8_t ID) {
1034   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1035 }
1036 
1037 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1038   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1039 }
1040 
1041 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1042                                      LLT type, Align a, const AAMDNodes &AAInfo,
1043                                      const MDNode *Ranges, SyncScope::ID SSID,
1044                                      AtomicOrdering Ordering,
1045                                      AtomicOrdering FailureOrdering)
1046     : PtrInfo(ptrinfo), MemoryType(type), FlagVals(f), BaseAlign(a),
1047       AAInfo(AAInfo), Ranges(Ranges) {
1048   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1049           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1050          "invalid pointer value");
1051   assert((isLoad() || isStore()) && "Not a load/store!");
1052 
1053   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1054   assert(getSyncScopeID() == SSID && "Value truncated");
1055   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1056   assert(getSuccessOrdering() == Ordering && "Value truncated");
1057   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1058   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1059 }
1060 
1061 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1062                                      uint64_t s, Align a,
1063                                      const AAMDNodes &AAInfo,
1064                                      const MDNode *Ranges, SyncScope::ID SSID,
1065                                      AtomicOrdering Ordering,
1066                                      AtomicOrdering FailureOrdering)
1067     : MachineMemOperand(ptrinfo, f,
1068                         s == ~UINT64_C(0) ? LLT() : LLT::scalar(8 * s), a,
1069                         AAInfo, Ranges, SSID, Ordering, FailureOrdering) {}
1070 
1071 /// Profile - Gather unique data for the object.
1072 ///
1073 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1074   ID.AddInteger(getOffset());
1075   ID.AddInteger(getMemoryType().getUniqueRAWLLTData());
1076   ID.AddPointer(getOpaqueValue());
1077   ID.AddInteger(getFlags());
1078   ID.AddInteger(getBaseAlign().value());
1079 }
1080 
1081 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1082   // The Value and Offset may differ due to CSE. But the flags and size
1083   // should be the same.
1084   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1085   assert((MMO->getSize() == ~UINT64_C(0) || getSize() == ~UINT64_C(0) ||
1086           MMO->getSize() == getSize()) &&
1087          "Size mismatch!");
1088 
1089   if (MMO->getBaseAlign() >= getBaseAlign()) {
1090     // Update the alignment value.
1091     BaseAlign = MMO->getBaseAlign();
1092     // Also update the base and offset, because the new alignment may
1093     // not be applicable with the old ones.
1094     PtrInfo = MMO->PtrInfo;
1095   }
1096 }
1097 
1098 /// getAlign - Return the minimum known alignment in bytes of the
1099 /// actual memory reference.
1100 Align MachineMemOperand::getAlign() const {
1101   return commonAlignment(getBaseAlign(), getOffset());
1102 }
1103 
1104 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1105                               SmallVectorImpl<StringRef> &SSNs,
1106                               const LLVMContext &Context,
1107                               const MachineFrameInfo *MFI,
1108                               const TargetInstrInfo *TII) const {
1109   OS << '(';
1110   if (isVolatile())
1111     OS << "volatile ";
1112   if (isNonTemporal())
1113     OS << "non-temporal ";
1114   if (isDereferenceable())
1115     OS << "dereferenceable ";
1116   if (isInvariant())
1117     OS << "invariant ";
1118   if (TII) {
1119     if (getFlags() & MachineMemOperand::MOTargetFlag1)
1120       OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1121          << "\" ";
1122     if (getFlags() & MachineMemOperand::MOTargetFlag2)
1123       OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1124          << "\" ";
1125     if (getFlags() & MachineMemOperand::MOTargetFlag3)
1126       OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1127          << "\" ";
1128   } else {
1129     if (getFlags() & MachineMemOperand::MOTargetFlag1)
1130       OS << "\"MOTargetFlag1\" ";
1131     if (getFlags() & MachineMemOperand::MOTargetFlag2)
1132       OS << "\"MOTargetFlag2\" ";
1133     if (getFlags() & MachineMemOperand::MOTargetFlag3)
1134       OS << "\"MOTargetFlag3\" ";
1135   }
1136 
1137   assert((isLoad() || isStore()) &&
1138          "machine memory operand must be a load or store (or both)");
1139   if (isLoad())
1140     OS << "load ";
1141   if (isStore())
1142     OS << "store ";
1143 
1144   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1145 
1146   if (getSuccessOrdering() != AtomicOrdering::NotAtomic)
1147     OS << toIRString(getSuccessOrdering()) << ' ';
1148   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1149     OS << toIRString(getFailureOrdering()) << ' ';
1150 
1151   if (getMemoryType().isValid())
1152     OS << '(' << getMemoryType() << ')';
1153   else
1154     OS << "unknown-size";
1155 
1156   if (const Value *Val = getValue()) {
1157     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1158     MIRFormatter::printIRValue(OS, *Val, MST);
1159   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1160     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1161     assert(PVal && "Expected a pseudo source value");
1162     switch (PVal->kind()) {
1163     case PseudoSourceValue::Stack:
1164       OS << "stack";
1165       break;
1166     case PseudoSourceValue::GOT:
1167       OS << "got";
1168       break;
1169     case PseudoSourceValue::JumpTable:
1170       OS << "jump-table";
1171       break;
1172     case PseudoSourceValue::ConstantPool:
1173       OS << "constant-pool";
1174       break;
1175     case PseudoSourceValue::FixedStack: {
1176       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1177       bool IsFixed = true;
1178       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1179       break;
1180     }
1181     case PseudoSourceValue::GlobalValueCallEntry:
1182       OS << "call-entry ";
1183       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1184           OS, /*PrintType=*/false, MST);
1185       break;
1186     case PseudoSourceValue::ExternalSymbolCallEntry:
1187       OS << "call-entry &";
1188       printLLVMNameWithoutPrefix(
1189           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1190       break;
1191     default: {
1192       const MIRFormatter *Formatter = TII->getMIRFormatter();
1193       // FIXME: This is not necessarily the correct MIR serialization format for
1194       // a custom pseudo source value, but at least it allows
1195       // MIR printing to work on a target with custom pseudo source
1196       // values.
1197       OS << "custom \"";
1198       Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1199       OS << '\"';
1200       break;
1201     }
1202     }
1203   } else if (getOpaqueValue() == nullptr && getOffset() != 0) {
1204     OS << ((isLoad() && isStore()) ? " on "
1205            : isLoad()              ? " from "
1206                                    : " into ")
1207        << "unknown-address";
1208   }
1209   MachineOperand::printOperandOffset(OS, getOffset());
1210   if (getSize() > 0 && getAlign() != getSize())
1211     OS << ", align " << getAlign().value();
1212   if (getAlign() != getBaseAlign())
1213     OS << ", basealign " << getBaseAlign().value();
1214   auto AAInfo = getAAInfo();
1215   if (AAInfo.TBAA) {
1216     OS << ", !tbaa ";
1217     AAInfo.TBAA->printAsOperand(OS, MST);
1218   }
1219   if (AAInfo.Scope) {
1220     OS << ", !alias.scope ";
1221     AAInfo.Scope->printAsOperand(OS, MST);
1222   }
1223   if (AAInfo.NoAlias) {
1224     OS << ", !noalias ";
1225     AAInfo.NoAlias->printAsOperand(OS, MST);
1226   }
1227   if (getRanges()) {
1228     OS << ", !range ";
1229     getRanges()->printAsOperand(OS, MST);
1230   }
1231   // FIXME: Implement addrspace printing/parsing in MIR.
1232   // For now, print this even though parsing it is not available in MIR.
1233   if (unsigned AS = getAddrSpace())
1234     OS << ", addrspace " << AS;
1235 
1236   OS << ')';
1237 }
1238