xref: /llvm-project/llvm/lib/CodeGen/MachineOperand.cpp (revision 7fff1fbd3ce1c069aff0f475e896d50a39deb1ac) 
1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/MachineOperand.h"
14 #include "llvm/ADT/FoldingSet.h"
15 #include "llvm/ADT/StringExtras.h"
16 #include "llvm/Analysis/Loads.h"
17 #include "llvm/Analysis/MemoryLocation.h"
18 #include "llvm/CodeGen/MIRFormatter.h"
19 #include "llvm/CodeGen/MIRPrinter.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineJumpTableInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/CodeGen/TargetRegisterInfo.h"
25 #include "llvm/Config/llvm-config.h"
26 #include "llvm/IR/Constants.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/ModuleSlotTracker.h"
30 #include "llvm/MC/MCDwarf.h"
31 #include "llvm/Target/TargetIntrinsicInfo.h"
32 #include "llvm/Target/TargetMachine.h"
33 
34 using namespace llvm;
35 
36 static cl::opt<int>
37     PrintRegMaskNumRegs("print-regmask-num-regs",
38                         cl::desc("Number of registers to limit to when "
39                                  "printing regmask operands in IR dumps. "
40                                  "unlimited = -1"),
41                         cl::init(32), cl::Hidden);
42 
43 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
44   if (const MachineInstr *MI = MO.getParent())
45     if (const MachineBasicBlock *MBB = MI->getParent())
46       if (const MachineFunction *MF = MBB->getParent())
47         return MF;
48   return nullptr;
49 }
50 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
51   return const_cast<MachineFunction *>(
52       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
53 }
54 
55 void MachineOperand::setReg(Register Reg) {
56   if (getReg() == Reg)
57     return; // No change.
58 
59   // Clear the IsRenamable bit to keep it conservatively correct.
60   IsRenamable = false;
61 
62   // Otherwise, we have to change the register.  If this operand is embedded
63   // into a machine function, we need to update the old and new register's
64   // use/def lists.
65   if (MachineFunction *MF = getMFIfAvailable(*this)) {
66     MachineRegisterInfo &MRI = MF->getRegInfo();
67     MRI.removeRegOperandFromUseList(this);
68     SmallContents.RegNo = Reg;
69     MRI.addRegOperandToUseList(this);
70     return;
71   }
72 
73   // Otherwise, just change the register, no problem.  :)
74   SmallContents.RegNo = Reg;
75 }
76 
77 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
78                                   const TargetRegisterInfo &TRI) {
79   assert(Reg.isVirtual());
80   if (SubIdx && getSubReg())
81     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
82   setReg(Reg);
83   if (SubIdx)
84     setSubReg(SubIdx);
85 }
86 
87 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
88   assert(Reg.isPhysical());
89   if (getSubReg()) {
90     Reg = TRI.getSubReg(Reg, getSubReg());
91     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
92     // That won't happen in legal code.
93     setSubReg(0);
94     if (isDef())
95       setIsUndef(false);
96   }
97   setReg(Reg);
98 }
99 
100 /// Change a def to a use, or a use to a def.
101 void MachineOperand::setIsDef(bool Val) {
102   assert(isReg() && "Wrong MachineOperand accessor");
103   assert((!Val || !isDebug()) && "Marking a debug operation as def");
104   if (IsDef == Val)
105     return;
106   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
107   // MRI may keep uses and defs in different list positions.
108   if (MachineFunction *MF = getMFIfAvailable(*this)) {
109     MachineRegisterInfo &MRI = MF->getRegInfo();
110     MRI.removeRegOperandFromUseList(this);
111     IsDef = Val;
112     MRI.addRegOperandToUseList(this);
113     return;
114   }
115   IsDef = Val;
116 }
117 
118 bool MachineOperand::isRenamable() const {
119   assert(isReg() && "Wrong MachineOperand accessor");
120   assert(Register::isPhysicalRegister(getReg()) &&
121          "isRenamable should only be checked on physical registers");
122   if (!IsRenamable)
123     return false;
124 
125   const MachineInstr *MI = getParent();
126   if (!MI)
127     return true;
128 
129   if (isDef())
130     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
131 
132   assert(isUse() && "Reg is not def or use");
133   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
134 }
135 
136 void MachineOperand::setIsRenamable(bool Val) {
137   assert(isReg() && "Wrong MachineOperand accessor");
138   assert(Register::isPhysicalRegister(getReg()) &&
139          "setIsRenamable should only be called on physical registers");
140   IsRenamable = Val;
141 }
142 
143 // If this operand is currently a register operand, and if this is in a
144 // function, deregister the operand from the register's use/def list.
145 void MachineOperand::removeRegFromUses() {
146   if (!isReg() || !isOnRegUseList())
147     return;
148 
149   if (MachineFunction *MF = getMFIfAvailable(*this))
150     MF->getRegInfo().removeRegOperandFromUseList(this);
151 }
152 
153 /// ChangeToImmediate - Replace this operand with a new immediate operand of
154 /// the specified value.  If an operand is known to be an immediate already,
155 /// the setImm method should be used.
156 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
157   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
158 
159   removeRegFromUses();
160 
161   OpKind = MO_Immediate;
162   Contents.ImmVal = ImmVal;
163 }
164 
165 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
166   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
167 
168   removeRegFromUses();
169 
170   OpKind = MO_FPImmediate;
171   Contents.CFP = FPImm;
172 }
173 
174 void MachineOperand::ChangeToES(const char *SymName,
175                                 unsigned TargetFlags) {
176   assert((!isReg() || !isTied()) &&
177          "Cannot change a tied operand into an external symbol");
178 
179   removeRegFromUses();
180 
181   OpKind = MO_ExternalSymbol;
182   Contents.OffsetedInfo.Val.SymbolName = SymName;
183   setOffset(0); // Offset is always 0.
184   setTargetFlags(TargetFlags);
185 }
186 
187 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
188                                 unsigned TargetFlags) {
189   assert((!isReg() || !isTied()) &&
190          "Cannot change a tied operand into a global address");
191 
192   removeRegFromUses();
193 
194   OpKind = MO_GlobalAddress;
195   Contents.OffsetedInfo.Val.GV = GV;
196   setOffset(Offset);
197   setTargetFlags(TargetFlags);
198 }
199 
200 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
201   assert((!isReg() || !isTied()) &&
202          "Cannot change a tied operand into an MCSymbol");
203 
204   removeRegFromUses();
205 
206   OpKind = MO_MCSymbol;
207   Contents.Sym = Sym;
208 }
209 
210 void MachineOperand::ChangeToFrameIndex(int Idx) {
211   assert((!isReg() || !isTied()) &&
212          "Cannot change a tied operand into a FrameIndex");
213 
214   removeRegFromUses();
215 
216   OpKind = MO_FrameIndex;
217   setIndex(Idx);
218 }
219 
220 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
221                                          unsigned TargetFlags) {
222   assert((!isReg() || !isTied()) &&
223          "Cannot change a tied operand into a FrameIndex");
224 
225   removeRegFromUses();
226 
227   OpKind = MO_TargetIndex;
228   setIndex(Idx);
229   setOffset(Offset);
230   setTargetFlags(TargetFlags);
231 }
232 
233 /// ChangeToRegister - Replace this operand with a new register operand of
234 /// the specified value.  If an operand is known to be an register already,
235 /// the setReg method should be used.
236 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
237                                       bool isKill, bool isDead, bool isUndef,
238                                       bool isDebug) {
239   MachineRegisterInfo *RegInfo = nullptr;
240   if (MachineFunction *MF = getMFIfAvailable(*this))
241     RegInfo = &MF->getRegInfo();
242   // If this operand is already a register operand, remove it from the
243   // register's use/def lists.
244   bool WasReg = isReg();
245   if (RegInfo && WasReg)
246     RegInfo->removeRegOperandFromUseList(this);
247 
248   // Change this to a register and set the reg#.
249   assert(!(isDead && !isDef) && "Dead flag on non-def");
250   assert(!(isKill && isDef) && "Kill flag on def");
251   OpKind = MO_Register;
252   SmallContents.RegNo = Reg;
253   SubReg_TargetFlags = 0;
254   IsDef = isDef;
255   IsImp = isImp;
256   IsDeadOrKill = isKill | isDead;
257   IsRenamable = false;
258   IsUndef = isUndef;
259   IsInternalRead = false;
260   IsEarlyClobber = false;
261   IsDebug = isDebug;
262   // Ensure isOnRegUseList() returns false.
263   Contents.Reg.Prev = nullptr;
264   // Preserve the tie when the operand was already a register.
265   if (!WasReg)
266     TiedTo = 0;
267 
268   // If this operand is embedded in a function, add the operand to the
269   // register's use/def list.
270   if (RegInfo)
271     RegInfo->addRegOperandToUseList(this);
272 }
273 
274 /// isIdenticalTo - Return true if this operand is identical to the specified
275 /// operand. Note that this should stay in sync with the hash_value overload
276 /// below.
277 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
278   if (getType() != Other.getType() ||
279       getTargetFlags() != Other.getTargetFlags())
280     return false;
281 
282   switch (getType()) {
283   case MachineOperand::MO_Register:
284     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
285            getSubReg() == Other.getSubReg();
286   case MachineOperand::MO_Immediate:
287     return getImm() == Other.getImm();
288   case MachineOperand::MO_CImmediate:
289     return getCImm() == Other.getCImm();
290   case MachineOperand::MO_FPImmediate:
291     return getFPImm() == Other.getFPImm();
292   case MachineOperand::MO_MachineBasicBlock:
293     return getMBB() == Other.getMBB();
294   case MachineOperand::MO_FrameIndex:
295     return getIndex() == Other.getIndex();
296   case MachineOperand::MO_ConstantPoolIndex:
297   case MachineOperand::MO_TargetIndex:
298     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
299   case MachineOperand::MO_JumpTableIndex:
300     return getIndex() == Other.getIndex();
301   case MachineOperand::MO_GlobalAddress:
302     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
303   case MachineOperand::MO_ExternalSymbol:
304     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
305            getOffset() == Other.getOffset();
306   case MachineOperand::MO_BlockAddress:
307     return getBlockAddress() == Other.getBlockAddress() &&
308            getOffset() == Other.getOffset();
309   case MachineOperand::MO_RegisterMask:
310   case MachineOperand::MO_RegisterLiveOut: {
311     // Shallow compare of the two RegMasks
312     const uint32_t *RegMask = getRegMask();
313     const uint32_t *OtherRegMask = Other.getRegMask();
314     if (RegMask == OtherRegMask)
315       return true;
316 
317     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
318       // Calculate the size of the RegMask
319       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
320       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
321 
322       // Deep compare of the two RegMasks
323       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
324     }
325     // We don't know the size of the RegMask, so we can't deep compare the two
326     // reg masks.
327     return false;
328   }
329   case MachineOperand::MO_MCSymbol:
330     return getMCSymbol() == Other.getMCSymbol();
331   case MachineOperand::MO_CFIIndex:
332     return getCFIIndex() == Other.getCFIIndex();
333   case MachineOperand::MO_Metadata:
334     return getMetadata() == Other.getMetadata();
335   case MachineOperand::MO_IntrinsicID:
336     return getIntrinsicID() == Other.getIntrinsicID();
337   case MachineOperand::MO_Predicate:
338     return getPredicate() == Other.getPredicate();
339   case MachineOperand::MO_ShuffleMask:
340     return getShuffleMask() == Other.getShuffleMask();
341   }
342   llvm_unreachable("Invalid machine operand type");
343 }
344 
345 // Note: this must stay exactly in sync with isIdenticalTo above.
346 hash_code llvm::hash_value(const MachineOperand &MO) {
347   switch (MO.getType()) {
348   case MachineOperand::MO_Register:
349     // Register operands don't have target flags.
350     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
351   case MachineOperand::MO_Immediate:
352     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
353   case MachineOperand::MO_CImmediate:
354     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
355   case MachineOperand::MO_FPImmediate:
356     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
357   case MachineOperand::MO_MachineBasicBlock:
358     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
359   case MachineOperand::MO_FrameIndex:
360     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
361   case MachineOperand::MO_ConstantPoolIndex:
362   case MachineOperand::MO_TargetIndex:
363     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
364                         MO.getOffset());
365   case MachineOperand::MO_JumpTableIndex:
366     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
367   case MachineOperand::MO_ExternalSymbol:
368     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
369                         StringRef(MO.getSymbolName()));
370   case MachineOperand::MO_GlobalAddress:
371     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
372                         MO.getOffset());
373   case MachineOperand::MO_BlockAddress:
374     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
375                         MO.getOffset());
376   case MachineOperand::MO_RegisterMask:
377   case MachineOperand::MO_RegisterLiveOut:
378     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
379   case MachineOperand::MO_Metadata:
380     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
381   case MachineOperand::MO_MCSymbol:
382     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
383   case MachineOperand::MO_CFIIndex:
384     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
385   case MachineOperand::MO_IntrinsicID:
386     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
387   case MachineOperand::MO_Predicate:
388     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
389   case MachineOperand::MO_ShuffleMask:
390     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
391   }
392   llvm_unreachable("Invalid machine operand type");
393 }
394 
395 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
396 // it.
397 static void tryToGetTargetInfo(const MachineOperand &MO,
398                                const TargetRegisterInfo *&TRI,
399                                const TargetIntrinsicInfo *&IntrinsicInfo) {
400   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
401     TRI = MF->getSubtarget().getRegisterInfo();
402     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
403   }
404 }
405 
406 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
407   const auto *TII = MF.getSubtarget().getInstrInfo();
408   assert(TII && "expected instruction info");
409   auto Indices = TII->getSerializableTargetIndices();
410   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
411     return I.first == Index;
412   });
413   if (Found != Indices.end())
414     return Found->second;
415   return nullptr;
416 }
417 
418 const char *MachineOperand::getTargetIndexName() const {
419   const MachineFunction *MF = getMFIfAvailable(*this);
420   return MF ? ::getTargetIndexName(*MF, this->getIndex()) : nullptr;
421 }
422 
423 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
424   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
425   for (const auto &I : Flags) {
426     if (I.first == TF) {
427       return I.second;
428     }
429   }
430   return nullptr;
431 }
432 
433 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
434                              const TargetRegisterInfo *TRI) {
435   if (!TRI) {
436     OS << "%dwarfreg." << DwarfReg;
437     return;
438   }
439 
440   if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
441     OS << printReg(*Reg, TRI);
442   else
443     OS << "<badreg>";
444 }
445 
446 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
447                                   ModuleSlotTracker &MST) {
448   OS << "%ir-block.";
449   if (BB.hasName()) {
450     printLLVMNameWithoutPrefix(OS, BB.getName());
451     return;
452   }
453   Optional<int> Slot;
454   if (const Function *F = BB.getParent()) {
455     if (F == MST.getCurrentFunction()) {
456       Slot = MST.getLocalSlot(&BB);
457     } else if (const Module *M = F->getParent()) {
458       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
459       CustomMST.incorporateFunction(*F);
460       Slot = CustomMST.getLocalSlot(&BB);
461     }
462   }
463   if (Slot)
464     MachineOperand::printIRSlotNumber(OS, *Slot);
465   else
466     OS << "<unknown>";
467 }
468 
469 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
470                            SyncScope::ID SSID,
471                            SmallVectorImpl<StringRef> &SSNs) {
472   switch (SSID) {
473   case SyncScope::System:
474     break;
475   default:
476     if (SSNs.empty())
477       Context.getSyncScopeNames(SSNs);
478 
479     OS << "syncscope(\"";
480     printEscapedString(SSNs[SSID], OS);
481     OS << "\") ";
482     break;
483   }
484 }
485 
486 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
487                                         unsigned TMMOFlag) {
488   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
489   for (const auto &I : Flags) {
490     if (I.first == TMMOFlag) {
491       return I.second;
492     }
493   }
494   return nullptr;
495 }
496 
497 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
498                             const MachineFrameInfo *MFI) {
499   StringRef Name;
500   if (MFI) {
501     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
502     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
503       if (Alloca->hasName())
504         Name = Alloca->getName();
505     if (IsFixed)
506       FrameIndex -= MFI->getObjectIndexBegin();
507   }
508   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
509 }
510 
511 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
512                                     const TargetRegisterInfo *TRI) {
513   OS << "%subreg.";
514   if (TRI)
515     OS << TRI->getSubRegIndexName(Index);
516   else
517     OS << Index;
518 }
519 
520 void MachineOperand::printTargetFlags(raw_ostream &OS,
521                                       const MachineOperand &Op) {
522   if (!Op.getTargetFlags())
523     return;
524   const MachineFunction *MF = getMFIfAvailable(Op);
525   if (!MF)
526     return;
527 
528   const auto *TII = MF->getSubtarget().getInstrInfo();
529   assert(TII && "expected instruction info");
530   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
531   OS << "target-flags(";
532   const bool HasDirectFlags = Flags.first;
533   const bool HasBitmaskFlags = Flags.second;
534   if (!HasDirectFlags && !HasBitmaskFlags) {
535     OS << "<unknown>) ";
536     return;
537   }
538   if (HasDirectFlags) {
539     if (const auto *Name = getTargetFlagName(TII, Flags.first))
540       OS << Name;
541     else
542       OS << "<unknown target flag>";
543   }
544   if (!HasBitmaskFlags) {
545     OS << ") ";
546     return;
547   }
548   bool IsCommaNeeded = HasDirectFlags;
549   unsigned BitMask = Flags.second;
550   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
551   for (const auto &Mask : BitMasks) {
552     // Check if the flag's bitmask has the bits of the current mask set.
553     if ((BitMask & Mask.first) == Mask.first) {
554       if (IsCommaNeeded)
555         OS << ", ";
556       IsCommaNeeded = true;
557       OS << Mask.second;
558       // Clear the bits which were serialized from the flag's bitmask.
559       BitMask &= ~(Mask.first);
560     }
561   }
562   if (BitMask) {
563     // When the resulting flag's bitmask isn't zero, we know that we didn't
564     // serialize all of the bit flags.
565     if (IsCommaNeeded)
566       OS << ", ";
567     OS << "<unknown bitmask target flag>";
568   }
569   OS << ") ";
570 }
571 
572 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
573   OS << "<mcsymbol " << Sym << ">";
574 }
575 
576 void MachineOperand::printStackObjectReference(raw_ostream &OS,
577                                                unsigned FrameIndex,
578                                                bool IsFixed, StringRef Name) {
579   if (IsFixed) {
580     OS << "%fixed-stack." << FrameIndex;
581     return;
582   }
583 
584   OS << "%stack." << FrameIndex;
585   if (!Name.empty())
586     OS << '.' << Name;
587 }
588 
589 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
590   if (Offset == 0)
591     return;
592   if (Offset < 0) {
593     OS << " - " << -Offset;
594     return;
595   }
596   OS << " + " << Offset;
597 }
598 
599 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
600   if (Slot == -1)
601     OS << "<badref>";
602   else
603     OS << Slot;
604 }
605 
606 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
607                      const TargetRegisterInfo *TRI) {
608   switch (CFI.getOperation()) {
609   case MCCFIInstruction::OpSameValue:
610     OS << "same_value ";
611     if (MCSymbol *Label = CFI.getLabel())
612       MachineOperand::printSymbol(OS, *Label);
613     printCFIRegister(CFI.getRegister(), OS, TRI);
614     break;
615   case MCCFIInstruction::OpRememberState:
616     OS << "remember_state ";
617     if (MCSymbol *Label = CFI.getLabel())
618       MachineOperand::printSymbol(OS, *Label);
619     break;
620   case MCCFIInstruction::OpRestoreState:
621     OS << "restore_state ";
622     if (MCSymbol *Label = CFI.getLabel())
623       MachineOperand::printSymbol(OS, *Label);
624     break;
625   case MCCFIInstruction::OpOffset:
626     OS << "offset ";
627     if (MCSymbol *Label = CFI.getLabel())
628       MachineOperand::printSymbol(OS, *Label);
629     printCFIRegister(CFI.getRegister(), OS, TRI);
630     OS << ", " << CFI.getOffset();
631     break;
632   case MCCFIInstruction::OpDefCfaRegister:
633     OS << "def_cfa_register ";
634     if (MCSymbol *Label = CFI.getLabel())
635       MachineOperand::printSymbol(OS, *Label);
636     printCFIRegister(CFI.getRegister(), OS, TRI);
637     break;
638   case MCCFIInstruction::OpDefCfaOffset:
639     OS << "def_cfa_offset ";
640     if (MCSymbol *Label = CFI.getLabel())
641       MachineOperand::printSymbol(OS, *Label);
642     OS << CFI.getOffset();
643     break;
644   case MCCFIInstruction::OpDefCfa:
645     OS << "def_cfa ";
646     if (MCSymbol *Label = CFI.getLabel())
647       MachineOperand::printSymbol(OS, *Label);
648     printCFIRegister(CFI.getRegister(), OS, TRI);
649     OS << ", " << CFI.getOffset();
650     break;
651   case MCCFIInstruction::OpRelOffset:
652     OS << "rel_offset ";
653     if (MCSymbol *Label = CFI.getLabel())
654       MachineOperand::printSymbol(OS, *Label);
655     printCFIRegister(CFI.getRegister(), OS, TRI);
656     OS << ", " << CFI.getOffset();
657     break;
658   case MCCFIInstruction::OpAdjustCfaOffset:
659     OS << "adjust_cfa_offset ";
660     if (MCSymbol *Label = CFI.getLabel())
661       MachineOperand::printSymbol(OS, *Label);
662     OS << CFI.getOffset();
663     break;
664   case MCCFIInstruction::OpRestore:
665     OS << "restore ";
666     if (MCSymbol *Label = CFI.getLabel())
667       MachineOperand::printSymbol(OS, *Label);
668     printCFIRegister(CFI.getRegister(), OS, TRI);
669     break;
670   case MCCFIInstruction::OpEscape: {
671     OS << "escape ";
672     if (MCSymbol *Label = CFI.getLabel())
673       MachineOperand::printSymbol(OS, *Label);
674     if (!CFI.getValues().empty()) {
675       size_t e = CFI.getValues().size() - 1;
676       for (size_t i = 0; i < e; ++i)
677         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
678       OS << format("0x%02x", uint8_t(CFI.getValues()[e]));
679     }
680     break;
681   }
682   case MCCFIInstruction::OpUndefined:
683     OS << "undefined ";
684     if (MCSymbol *Label = CFI.getLabel())
685       MachineOperand::printSymbol(OS, *Label);
686     printCFIRegister(CFI.getRegister(), OS, TRI);
687     break;
688   case MCCFIInstruction::OpRegister:
689     OS << "register ";
690     if (MCSymbol *Label = CFI.getLabel())
691       MachineOperand::printSymbol(OS, *Label);
692     printCFIRegister(CFI.getRegister(), OS, TRI);
693     OS << ", ";
694     printCFIRegister(CFI.getRegister2(), OS, TRI);
695     break;
696   case MCCFIInstruction::OpWindowSave:
697     OS << "window_save ";
698     if (MCSymbol *Label = CFI.getLabel())
699       MachineOperand::printSymbol(OS, *Label);
700     break;
701   case MCCFIInstruction::OpNegateRAState:
702     OS << "negate_ra_sign_state ";
703     if (MCSymbol *Label = CFI.getLabel())
704       MachineOperand::printSymbol(OS, *Label);
705     break;
706   default:
707     // TODO: Print the other CFI Operations.
708     OS << "<unserializable cfi directive>";
709     break;
710   }
711 }
712 
713 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
714                            const TargetIntrinsicInfo *IntrinsicInfo) const {
715   print(OS, LLT{}, TRI, IntrinsicInfo);
716 }
717 
718 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
719                            const TargetRegisterInfo *TRI,
720                            const TargetIntrinsicInfo *IntrinsicInfo) const {
721   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
722   ModuleSlotTracker DummyMST(nullptr);
723   print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
724         /*IsStandalone=*/true,
725         /*ShouldPrintRegisterTies=*/true,
726         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
727 }
728 
729 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
730                            LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
731                            bool IsStandalone, bool ShouldPrintRegisterTies,
732                            unsigned TiedOperandIdx,
733                            const TargetRegisterInfo *TRI,
734                            const TargetIntrinsicInfo *IntrinsicInfo) const {
735   printTargetFlags(OS, *this);
736   switch (getType()) {
737   case MachineOperand::MO_Register: {
738     Register Reg = getReg();
739     if (isImplicit())
740       OS << (isDef() ? "implicit-def " : "implicit ");
741     else if (PrintDef && isDef())
742       // Print the 'def' flag only when the operand is defined after '='.
743       OS << "def ";
744     if (isInternalRead())
745       OS << "internal ";
746     if (isDead())
747       OS << "dead ";
748     if (isKill())
749       OS << "killed ";
750     if (isUndef())
751       OS << "undef ";
752     if (isEarlyClobber())
753       OS << "early-clobber ";
754     if (Register::isPhysicalRegister(getReg()) && isRenamable())
755       OS << "renamable ";
756     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
757     // simply infer it when parsing and do not need to print it.
758 
759     const MachineRegisterInfo *MRI = nullptr;
760     if (Register::isVirtualRegister(Reg)) {
761       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
762         MRI = &MF->getRegInfo();
763       }
764     }
765 
766     OS << printReg(Reg, TRI, 0, MRI);
767     // Print the sub register.
768     if (unsigned SubReg = getSubReg()) {
769       if (TRI)
770         OS << '.' << TRI->getSubRegIndexName(SubReg);
771       else
772         OS << ".subreg" << SubReg;
773     }
774     // Print the register class / bank.
775     if (Register::isVirtualRegister(Reg)) {
776       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
777         const MachineRegisterInfo &MRI = MF->getRegInfo();
778         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
779           OS << ':';
780           OS << printRegClassOrBank(Reg, MRI, TRI);
781         }
782       }
783     }
784     // Print ties.
785     if (ShouldPrintRegisterTies && isTied() && !isDef())
786       OS << "(tied-def " << TiedOperandIdx << ")";
787     // Print types.
788     if (TypeToPrint.isValid())
789       OS << '(' << TypeToPrint << ')';
790     break;
791   }
792   case MachineOperand::MO_Immediate: {
793     const MIRFormatter *Formatter = nullptr;
794     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
795       const auto *TII = MF->getSubtarget().getInstrInfo();
796       assert(TII && "expected instruction info");
797       Formatter = TII->getMIRFormatter();
798     }
799     if (Formatter)
800       Formatter->printImm(OS, *getParent(), OpIdx, getImm());
801     else
802       OS << getImm();
803     break;
804   }
805   case MachineOperand::MO_CImmediate:
806     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
807     break;
808   case MachineOperand::MO_FPImmediate:
809     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
810     break;
811   case MachineOperand::MO_MachineBasicBlock:
812     OS << printMBBReference(*getMBB());
813     break;
814   case MachineOperand::MO_FrameIndex: {
815     int FrameIndex = getIndex();
816     bool IsFixed = false;
817     const MachineFrameInfo *MFI = nullptr;
818     if (const MachineFunction *MF = getMFIfAvailable(*this))
819       MFI = &MF->getFrameInfo();
820     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
821     break;
822   }
823   case MachineOperand::MO_ConstantPoolIndex:
824     OS << "%const." << getIndex();
825     printOperandOffset(OS, getOffset());
826     break;
827   case MachineOperand::MO_TargetIndex: {
828     OS << "target-index(";
829     const char *Name = "<unknown>";
830     if (const MachineFunction *MF = getMFIfAvailable(*this))
831       if (const auto *TargetIndexName = ::getTargetIndexName(*MF, getIndex()))
832         Name = TargetIndexName;
833     OS << Name << ')';
834     printOperandOffset(OS, getOffset());
835     break;
836   }
837   case MachineOperand::MO_JumpTableIndex:
838     OS << printJumpTableEntryReference(getIndex());
839     break;
840   case MachineOperand::MO_GlobalAddress:
841     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
842     printOperandOffset(OS, getOffset());
843     break;
844   case MachineOperand::MO_ExternalSymbol: {
845     StringRef Name = getSymbolName();
846     OS << '&';
847     if (Name.empty()) {
848       OS << "\"\"";
849     } else {
850       printLLVMNameWithoutPrefix(OS, Name);
851     }
852     printOperandOffset(OS, getOffset());
853     break;
854   }
855   case MachineOperand::MO_BlockAddress: {
856     OS << "blockaddress(";
857     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
858                                                      MST);
859     OS << ", ";
860     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
861     OS << ')';
862     MachineOperand::printOperandOffset(OS, getOffset());
863     break;
864   }
865   case MachineOperand::MO_RegisterMask: {
866     OS << "<regmask";
867     if (TRI) {
868       unsigned NumRegsInMask = 0;
869       unsigned NumRegsEmitted = 0;
870       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
871         unsigned MaskWord = i / 32;
872         unsigned MaskBit = i % 32;
873         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
874           if (PrintRegMaskNumRegs < 0 ||
875               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
876             OS << " " << printReg(i, TRI);
877             NumRegsEmitted++;
878           }
879           NumRegsInMask++;
880         }
881       }
882       if (NumRegsEmitted != NumRegsInMask)
883         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
884     } else {
885       OS << " ...";
886     }
887     OS << ">";
888     break;
889   }
890   case MachineOperand::MO_RegisterLiveOut: {
891     const uint32_t *RegMask = getRegLiveOut();
892     OS << "liveout(";
893     if (!TRI) {
894       OS << "<unknown>";
895     } else {
896       bool IsCommaNeeded = false;
897       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
898         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
899           if (IsCommaNeeded)
900             OS << ", ";
901           OS << printReg(Reg, TRI);
902           IsCommaNeeded = true;
903         }
904       }
905     }
906     OS << ")";
907     break;
908   }
909   case MachineOperand::MO_Metadata:
910     getMetadata()->printAsOperand(OS, MST);
911     break;
912   case MachineOperand::MO_MCSymbol:
913     printSymbol(OS, *getMCSymbol());
914     break;
915   case MachineOperand::MO_CFIIndex: {
916     if (const MachineFunction *MF = getMFIfAvailable(*this))
917       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
918     else
919       OS << "<cfi directive>";
920     break;
921   }
922   case MachineOperand::MO_IntrinsicID: {
923     Intrinsic::ID ID = getIntrinsicID();
924     if (ID < Intrinsic::num_intrinsics)
925       OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
926     else if (IntrinsicInfo)
927       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
928     else
929       OS << "intrinsic(" << ID << ')';
930     break;
931   }
932   case MachineOperand::MO_Predicate: {
933     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
934     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
935        << CmpInst::getPredicateName(Pred) << ')';
936     break;
937   }
938   case MachineOperand::MO_ShuffleMask:
939     OS << "shufflemask(";
940     ArrayRef<int> Mask = getShuffleMask();
941     StringRef Separator;
942     for (int Elt : Mask) {
943       if (Elt == -1)
944         OS << Separator << "undef";
945       else
946         OS << Separator << Elt;
947       Separator = ", ";
948     }
949 
950     OS << ')';
951     break;
952   }
953 }
954 
955 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
956 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
957 #endif
958 
959 //===----------------------------------------------------------------------===//
960 // MachineMemOperand Implementation
961 //===----------------------------------------------------------------------===//
962 
963 /// getAddrSpace - Return the LLVM IR address space number that this pointer
964 /// points into.
965 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
966 
967 /// isDereferenceable - Return true if V is always dereferenceable for
968 /// Offset + Size byte.
969 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
970                                            const DataLayout &DL) const {
971   if (!V.is<const Value *>())
972     return false;
973 
974   const Value *BasePtr = V.get<const Value *>();
975   if (BasePtr == nullptr)
976     return false;
977 
978   return isDereferenceableAndAlignedPointer(
979       BasePtr, Align(1), APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
980 }
981 
982 /// getConstantPool - Return a MachinePointerInfo record that refers to the
983 /// constant pool.
984 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
985   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
986 }
987 
988 /// getFixedStack - Return a MachinePointerInfo record that refers to the
989 /// the specified FrameIndex.
990 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
991                                                      int FI, int64_t Offset) {
992   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
993 }
994 
995 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
996   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
997 }
998 
999 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1000   return MachinePointerInfo(MF.getPSVManager().getGOT());
1001 }
1002 
1003 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1004                                                 int64_t Offset, uint8_t ID) {
1005   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1006 }
1007 
1008 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1009   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1010 }
1011 
1012 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1013                                      uint64_t s, Align a,
1014                                      const AAMDNodes &AAInfo,
1015                                      const MDNode *Ranges, SyncScope::ID SSID,
1016                                      AtomicOrdering Ordering,
1017                                      AtomicOrdering FailureOrdering)
1018     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlign(a), AAInfo(AAInfo),
1019       Ranges(Ranges) {
1020   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1021           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1022          "invalid pointer value");
1023   assert((isLoad() || isStore()) && "Not a load/store!");
1024 
1025   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1026   assert(getSyncScopeID() == SSID && "Value truncated");
1027   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1028   assert(getOrdering() == Ordering && "Value truncated");
1029   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1030   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1031 }
1032 
1033 /// Profile - Gather unique data for the object.
1034 ///
1035 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1036   ID.AddInteger(getOffset());
1037   ID.AddInteger(Size);
1038   ID.AddPointer(getOpaqueValue());
1039   ID.AddInteger(getFlags());
1040   ID.AddInteger(getBaseAlign().value());
1041 }
1042 
1043 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1044   // The Value and Offset may differ due to CSE. But the flags and size
1045   // should be the same.
1046   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1047   assert(MMO->getSize() == getSize() && "Size mismatch!");
1048 
1049   if (MMO->getBaseAlign() >= getBaseAlign()) {
1050     // Update the alignment value.
1051     BaseAlign = MMO->getBaseAlign();
1052     // Also update the base and offset, because the new alignment may
1053     // not be applicable with the old ones.
1054     PtrInfo = MMO->PtrInfo;
1055   }
1056 }
1057 
1058 /// getAlignment - Return the minimum known alignment in bytes of the
1059 /// actual memory reference.
1060 uint64_t MachineMemOperand::getAlignment() const { return getAlign().value(); }
1061 
1062 /// getAlign - Return the minimum known alignment in bytes of the
1063 /// actual memory reference.
1064 Align MachineMemOperand::getAlign() const {
1065   return commonAlignment(getBaseAlign(), getOffset());
1066 }
1067 
1068 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1069                               SmallVectorImpl<StringRef> &SSNs,
1070                               const LLVMContext &Context,
1071                               const MachineFrameInfo *MFI,
1072                               const TargetInstrInfo *TII) const {
1073   OS << '(';
1074   if (isVolatile())
1075     OS << "volatile ";
1076   if (isNonTemporal())
1077     OS << "non-temporal ";
1078   if (isDereferenceable())
1079     OS << "dereferenceable ";
1080   if (isInvariant())
1081     OS << "invariant ";
1082   if (getFlags() & MachineMemOperand::MOTargetFlag1)
1083     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1084        << "\" ";
1085   if (getFlags() & MachineMemOperand::MOTargetFlag2)
1086     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1087        << "\" ";
1088   if (getFlags() & MachineMemOperand::MOTargetFlag3)
1089     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1090        << "\" ";
1091 
1092   assert((isLoad() || isStore()) &&
1093          "machine memory operand must be a load or store (or both)");
1094   if (isLoad())
1095     OS << "load ";
1096   if (isStore())
1097     OS << "store ";
1098 
1099   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1100 
1101   if (getOrdering() != AtomicOrdering::NotAtomic)
1102     OS << toIRString(getOrdering()) << ' ';
1103   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1104     OS << toIRString(getFailureOrdering()) << ' ';
1105 
1106   if (getSize() == MemoryLocation::UnknownSize)
1107     OS << "unknown-size";
1108   else
1109     OS << getSize();
1110 
1111   if (const Value *Val = getValue()) {
1112     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1113     MIRFormatter::printIRValue(OS, *Val, MST);
1114   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1115     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1116     assert(PVal && "Expected a pseudo source value");
1117     switch (PVal->kind()) {
1118     case PseudoSourceValue::Stack:
1119       OS << "stack";
1120       break;
1121     case PseudoSourceValue::GOT:
1122       OS << "got";
1123       break;
1124     case PseudoSourceValue::JumpTable:
1125       OS << "jump-table";
1126       break;
1127     case PseudoSourceValue::ConstantPool:
1128       OS << "constant-pool";
1129       break;
1130     case PseudoSourceValue::FixedStack: {
1131       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1132       bool IsFixed = true;
1133       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1134       break;
1135     }
1136     case PseudoSourceValue::GlobalValueCallEntry:
1137       OS << "call-entry ";
1138       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1139           OS, /*PrintType=*/false, MST);
1140       break;
1141     case PseudoSourceValue::ExternalSymbolCallEntry:
1142       OS << "call-entry &";
1143       printLLVMNameWithoutPrefix(
1144           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1145       break;
1146     default: {
1147       const MIRFormatter *Formatter = TII->getMIRFormatter();
1148       // FIXME: This is not necessarily the correct MIR serialization format for
1149       // a custom pseudo source value, but at least it allows
1150       // MIR printing to work on a target with custom pseudo source
1151       // values.
1152       OS << "custom \"";
1153       Formatter->printCustomPseudoSourceValue(OS, MST, *PVal);
1154       OS << '\"';
1155       break;
1156     }
1157     }
1158   }
1159   MachineOperand::printOperandOffset(OS, getOffset());
1160   if (getBaseAlign() != getSize())
1161     OS << ", align " << getBaseAlign().value();
1162   auto AAInfo = getAAInfo();
1163   if (AAInfo.TBAA) {
1164     OS << ", !tbaa ";
1165     AAInfo.TBAA->printAsOperand(OS, MST);
1166   }
1167   if (AAInfo.Scope) {
1168     OS << ", !alias.scope ";
1169     AAInfo.Scope->printAsOperand(OS, MST);
1170   }
1171   if (AAInfo.NoAlias) {
1172     OS << ", !noalias ";
1173     AAInfo.NoAlias->printAsOperand(OS, MST);
1174   }
1175   if (getRanges()) {
1176     OS << ", !range ";
1177     getRanges()->printAsOperand(OS, MST);
1178   }
1179   // FIXME: Implement addrspace printing/parsing in MIR.
1180   // For now, print this even though parsing it is not available in MIR.
1181   if (unsigned AS = getAddrSpace())
1182     OS << ", addrspace " << AS;
1183 
1184   OS << ')';
1185 }
1186