xref: /llvm-project/llvm/lib/CodeGen/MachineOperand.cpp (revision 5af9cf042f21d6b044f8925b581a8f089d739bc5) 
1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/MachineOperand.h"
14 #include "llvm/ADT/StringExtras.h"
15 #include "llvm/Analysis/Loads.h"
16 #include "llvm/Analysis/MemoryLocation.h"
17 #include "llvm/CodeGen/MIRPrinter.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/IRPrintingPasses.h"
26 #include "llvm/IR/ModuleSlotTracker.h"
27 #include "llvm/MC/MCDwarf.h"
28 #include "llvm/Target/TargetIntrinsicInfo.h"
29 #include "llvm/Target/TargetMachine.h"
30 
31 using namespace llvm;
32 
33 static cl::opt<int>
34     PrintRegMaskNumRegs("print-regmask-num-regs",
35                         cl::desc("Number of registers to limit to when "
36                                  "printing regmask operands in IR dumps. "
37                                  "unlimited = -1"),
38                         cl::init(32), cl::Hidden);
39 
40 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
41   if (const MachineInstr *MI = MO.getParent())
42     if (const MachineBasicBlock *MBB = MI->getParent())
43       if (const MachineFunction *MF = MBB->getParent())
44         return MF;
45   return nullptr;
46 }
47 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
48   return const_cast<MachineFunction *>(
49       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
50 }
51 
52 void MachineOperand::setReg(Register Reg) {
53   if (getReg() == Reg)
54     return; // No change.
55 
56   // Clear the IsRenamable bit to keep it conservatively correct.
57   IsRenamable = false;
58 
59   // Otherwise, we have to change the register.  If this operand is embedded
60   // into a machine function, we need to update the old and new register's
61   // use/def lists.
62   if (MachineFunction *MF = getMFIfAvailable(*this)) {
63     MachineRegisterInfo &MRI = MF->getRegInfo();
64     MRI.removeRegOperandFromUseList(this);
65     SmallContents.RegNo = Reg;
66     MRI.addRegOperandToUseList(this);
67     return;
68   }
69 
70   // Otherwise, just change the register, no problem.  :)
71   SmallContents.RegNo = Reg;
72 }
73 
74 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
75                                   const TargetRegisterInfo &TRI) {
76   assert(Reg.isVirtual());
77   if (SubIdx && getSubReg())
78     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
79   setReg(Reg);
80   if (SubIdx)
81     setSubReg(SubIdx);
82 }
83 
84 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
85   assert(Reg.isPhysical());
86   if (getSubReg()) {
87     Reg = TRI.getSubReg(Reg, getSubReg());
88     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
89     // That won't happen in legal code.
90     setSubReg(0);
91     if (isDef())
92       setIsUndef(false);
93   }
94   setReg(Reg);
95 }
96 
97 /// Change a def to a use, or a use to a def.
98 void MachineOperand::setIsDef(bool Val) {
99   assert(isReg() && "Wrong MachineOperand accessor");
100   assert((!Val || !isDebug()) && "Marking a debug operation as def");
101   if (IsDef == Val)
102     return;
103   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
104   // MRI may keep uses and defs in different list positions.
105   if (MachineFunction *MF = getMFIfAvailable(*this)) {
106     MachineRegisterInfo &MRI = MF->getRegInfo();
107     MRI.removeRegOperandFromUseList(this);
108     IsDef = Val;
109     MRI.addRegOperandToUseList(this);
110     return;
111   }
112   IsDef = Val;
113 }
114 
115 bool MachineOperand::isRenamable() const {
116   assert(isReg() && "Wrong MachineOperand accessor");
117   assert(Register::isPhysicalRegister(getReg()) &&
118          "isRenamable should only be checked on physical registers");
119   if (!IsRenamable)
120     return false;
121 
122   const MachineInstr *MI = getParent();
123   if (!MI)
124     return true;
125 
126   if (isDef())
127     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
128 
129   assert(isUse() && "Reg is not def or use");
130   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
131 }
132 
133 void MachineOperand::setIsRenamable(bool Val) {
134   assert(isReg() && "Wrong MachineOperand accessor");
135   assert(Register::isPhysicalRegister(getReg()) &&
136          "setIsRenamable should only be called on physical registers");
137   IsRenamable = Val;
138 }
139 
140 // If this operand is currently a register operand, and if this is in a
141 // function, deregister the operand from the register's use/def list.
142 void MachineOperand::removeRegFromUses() {
143   if (!isReg() || !isOnRegUseList())
144     return;
145 
146   if (MachineFunction *MF = getMFIfAvailable(*this))
147     MF->getRegInfo().removeRegOperandFromUseList(this);
148 }
149 
150 /// ChangeToImmediate - Replace this operand with a new immediate operand of
151 /// the specified value.  If an operand is known to be an immediate already,
152 /// the setImm method should be used.
153 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
154   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
155 
156   removeRegFromUses();
157 
158   OpKind = MO_Immediate;
159   Contents.ImmVal = ImmVal;
160 }
161 
162 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
163   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
164 
165   removeRegFromUses();
166 
167   OpKind = MO_FPImmediate;
168   Contents.CFP = FPImm;
169 }
170 
171 void MachineOperand::ChangeToES(const char *SymName,
172                                 unsigned TargetFlags) {
173   assert((!isReg() || !isTied()) &&
174          "Cannot change a tied operand into an external symbol");
175 
176   removeRegFromUses();
177 
178   OpKind = MO_ExternalSymbol;
179   Contents.OffsetedInfo.Val.SymbolName = SymName;
180   setOffset(0); // Offset is always 0.
181   setTargetFlags(TargetFlags);
182 }
183 
184 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
185                                 unsigned TargetFlags) {
186   assert((!isReg() || !isTied()) &&
187          "Cannot change a tied operand into a global address");
188 
189   removeRegFromUses();
190 
191   OpKind = MO_GlobalAddress;
192   Contents.OffsetedInfo.Val.GV = GV;
193   setOffset(Offset);
194   setTargetFlags(TargetFlags);
195 }
196 
197 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
198   assert((!isReg() || !isTied()) &&
199          "Cannot change a tied operand into an MCSymbol");
200 
201   removeRegFromUses();
202 
203   OpKind = MO_MCSymbol;
204   Contents.Sym = Sym;
205 }
206 
207 void MachineOperand::ChangeToFrameIndex(int Idx) {
208   assert((!isReg() || !isTied()) &&
209          "Cannot change a tied operand into a FrameIndex");
210 
211   removeRegFromUses();
212 
213   OpKind = MO_FrameIndex;
214   setIndex(Idx);
215 }
216 
217 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
218                                          unsigned TargetFlags) {
219   assert((!isReg() || !isTied()) &&
220          "Cannot change a tied operand into a FrameIndex");
221 
222   removeRegFromUses();
223 
224   OpKind = MO_TargetIndex;
225   setIndex(Idx);
226   setOffset(Offset);
227   setTargetFlags(TargetFlags);
228 }
229 
230 /// ChangeToRegister - Replace this operand with a new register operand of
231 /// the specified value.  If an operand is known to be an register already,
232 /// the setReg method should be used.
233 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
234                                       bool isKill, bool isDead, bool isUndef,
235                                       bool isDebug) {
236   MachineRegisterInfo *RegInfo = nullptr;
237   if (MachineFunction *MF = getMFIfAvailable(*this))
238     RegInfo = &MF->getRegInfo();
239   // If this operand is already a register operand, remove it from the
240   // register's use/def lists.
241   bool WasReg = isReg();
242   if (RegInfo && WasReg)
243     RegInfo->removeRegOperandFromUseList(this);
244 
245   // Change this to a register and set the reg#.
246   assert(!(isDead && !isDef) && "Dead flag on non-def");
247   assert(!(isKill && isDef) && "Kill flag on def");
248   OpKind = MO_Register;
249   SmallContents.RegNo = Reg;
250   SubReg_TargetFlags = 0;
251   IsDef = isDef;
252   IsImp = isImp;
253   IsDeadOrKill = isKill | isDead;
254   IsRenamable = false;
255   IsUndef = isUndef;
256   IsInternalRead = false;
257   IsEarlyClobber = false;
258   IsDebug = isDebug;
259   // Ensure isOnRegUseList() returns false.
260   Contents.Reg.Prev = nullptr;
261   // Preserve the tie when the operand was already a register.
262   if (!WasReg)
263     TiedTo = 0;
264 
265   // If this operand is embedded in a function, add the operand to the
266   // register's use/def list.
267   if (RegInfo)
268     RegInfo->addRegOperandToUseList(this);
269 }
270 
271 /// isIdenticalTo - Return true if this operand is identical to the specified
272 /// operand. Note that this should stay in sync with the hash_value overload
273 /// below.
274 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
275   if (getType() != Other.getType() ||
276       getTargetFlags() != Other.getTargetFlags())
277     return false;
278 
279   switch (getType()) {
280   case MachineOperand::MO_Register:
281     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
282            getSubReg() == Other.getSubReg();
283   case MachineOperand::MO_Immediate:
284     return getImm() == Other.getImm();
285   case MachineOperand::MO_CImmediate:
286     return getCImm() == Other.getCImm();
287   case MachineOperand::MO_FPImmediate:
288     return getFPImm() == Other.getFPImm();
289   case MachineOperand::MO_MachineBasicBlock:
290     return getMBB() == Other.getMBB();
291   case MachineOperand::MO_FrameIndex:
292     return getIndex() == Other.getIndex();
293   case MachineOperand::MO_ConstantPoolIndex:
294   case MachineOperand::MO_TargetIndex:
295     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
296   case MachineOperand::MO_JumpTableIndex:
297     return getIndex() == Other.getIndex();
298   case MachineOperand::MO_GlobalAddress:
299     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
300   case MachineOperand::MO_ExternalSymbol:
301     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
302            getOffset() == Other.getOffset();
303   case MachineOperand::MO_BlockAddress:
304     return getBlockAddress() == Other.getBlockAddress() &&
305            getOffset() == Other.getOffset();
306   case MachineOperand::MO_RegisterMask:
307   case MachineOperand::MO_RegisterLiveOut: {
308     // Shallow compare of the two RegMasks
309     const uint32_t *RegMask = getRegMask();
310     const uint32_t *OtherRegMask = Other.getRegMask();
311     if (RegMask == OtherRegMask)
312       return true;
313 
314     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
315       // Calculate the size of the RegMask
316       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
317       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
318 
319       // Deep compare of the two RegMasks
320       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
321     }
322     // We don't know the size of the RegMask, so we can't deep compare the two
323     // reg masks.
324     return false;
325   }
326   case MachineOperand::MO_MCSymbol:
327     return getMCSymbol() == Other.getMCSymbol();
328   case MachineOperand::MO_CFIIndex:
329     return getCFIIndex() == Other.getCFIIndex();
330   case MachineOperand::MO_Metadata:
331     return getMetadata() == Other.getMetadata();
332   case MachineOperand::MO_IntrinsicID:
333     return getIntrinsicID() == Other.getIntrinsicID();
334   case MachineOperand::MO_Predicate:
335     return getPredicate() == Other.getPredicate();
336   case MachineOperand::MO_ShuffleMask:
337     return getShuffleMask() == Other.getShuffleMask();
338   }
339   llvm_unreachable("Invalid machine operand type");
340 }
341 
342 // Note: this must stay exactly in sync with isIdenticalTo above.
343 hash_code llvm::hash_value(const MachineOperand &MO) {
344   switch (MO.getType()) {
345   case MachineOperand::MO_Register:
346     // Register operands don't have target flags.
347     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
348   case MachineOperand::MO_Immediate:
349     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
350   case MachineOperand::MO_CImmediate:
351     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
352   case MachineOperand::MO_FPImmediate:
353     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
354   case MachineOperand::MO_MachineBasicBlock:
355     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
356   case MachineOperand::MO_FrameIndex:
357     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
358   case MachineOperand::MO_ConstantPoolIndex:
359   case MachineOperand::MO_TargetIndex:
360     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
361                         MO.getOffset());
362   case MachineOperand::MO_JumpTableIndex:
363     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
364   case MachineOperand::MO_ExternalSymbol:
365     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
366                         StringRef(MO.getSymbolName()));
367   case MachineOperand::MO_GlobalAddress:
368     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
369                         MO.getOffset());
370   case MachineOperand::MO_BlockAddress:
371     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
372                         MO.getOffset());
373   case MachineOperand::MO_RegisterMask:
374   case MachineOperand::MO_RegisterLiveOut:
375     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
376   case MachineOperand::MO_Metadata:
377     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
378   case MachineOperand::MO_MCSymbol:
379     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
380   case MachineOperand::MO_CFIIndex:
381     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
382   case MachineOperand::MO_IntrinsicID:
383     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
384   case MachineOperand::MO_Predicate:
385     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
386   case MachineOperand::MO_ShuffleMask:
387     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
388   }
389   llvm_unreachable("Invalid machine operand type");
390 }
391 
392 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
393 // it.
394 static void tryToGetTargetInfo(const MachineOperand &MO,
395                                const TargetRegisterInfo *&TRI,
396                                const TargetIntrinsicInfo *&IntrinsicInfo) {
397   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
398     TRI = MF->getSubtarget().getRegisterInfo();
399     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
400   }
401 }
402 
403 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
404   const auto *TII = MF.getSubtarget().getInstrInfo();
405   assert(TII && "expected instruction info");
406   auto Indices = TII->getSerializableTargetIndices();
407   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
408     return I.first == Index;
409   });
410   if (Found != Indices.end())
411     return Found->second;
412   return nullptr;
413 }
414 
415 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
416   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
417   for (const auto &I : Flags) {
418     if (I.first == TF) {
419       return I.second;
420     }
421   }
422   return nullptr;
423 }
424 
425 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
426                              const TargetRegisterInfo *TRI) {
427   if (!TRI) {
428     OS << "%dwarfreg." << DwarfReg;
429     return;
430   }
431 
432   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
433   if (Reg == -1) {
434     OS << "<badreg>";
435     return;
436   }
437   OS << printReg(Reg, TRI);
438 }
439 
440 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
441                                   ModuleSlotTracker &MST) {
442   OS << "%ir-block.";
443   if (BB.hasName()) {
444     printLLVMNameWithoutPrefix(OS, BB.getName());
445     return;
446   }
447   Optional<int> Slot;
448   if (const Function *F = BB.getParent()) {
449     if (F == MST.getCurrentFunction()) {
450       Slot = MST.getLocalSlot(&BB);
451     } else if (const Module *M = F->getParent()) {
452       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
453       CustomMST.incorporateFunction(*F);
454       Slot = CustomMST.getLocalSlot(&BB);
455     }
456   }
457   if (Slot)
458     MachineOperand::printIRSlotNumber(OS, *Slot);
459   else
460     OS << "<unknown>";
461 }
462 
463 static void printIRValueReference(raw_ostream &OS, const Value &V,
464                                   ModuleSlotTracker &MST) {
465   if (isa<GlobalValue>(V)) {
466     V.printAsOperand(OS, /*PrintType=*/false, MST);
467     return;
468   }
469   if (isa<Constant>(V)) {
470     // Machine memory operands can load/store to/from constant value pointers.
471     OS << '`';
472     V.printAsOperand(OS, /*PrintType=*/true, MST);
473     OS << '`';
474     return;
475   }
476   OS << "%ir.";
477   if (V.hasName()) {
478     printLLVMNameWithoutPrefix(OS, V.getName());
479     return;
480   }
481   int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
482   MachineOperand::printIRSlotNumber(OS, Slot);
483 }
484 
485 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
486                            SyncScope::ID SSID,
487                            SmallVectorImpl<StringRef> &SSNs) {
488   switch (SSID) {
489   case SyncScope::System:
490     break;
491   default:
492     if (SSNs.empty())
493       Context.getSyncScopeNames(SSNs);
494 
495     OS << "syncscope(\"";
496     printEscapedString(SSNs[SSID], OS);
497     OS << "\") ";
498     break;
499   }
500 }
501 
502 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
503                                         unsigned TMMOFlag) {
504   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
505   for (const auto &I : Flags) {
506     if (I.first == TMMOFlag) {
507       return I.second;
508     }
509   }
510   return nullptr;
511 }
512 
513 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
514                             const MachineFrameInfo *MFI) {
515   StringRef Name;
516   if (MFI) {
517     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
518     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
519       if (Alloca->hasName())
520         Name = Alloca->getName();
521     if (IsFixed)
522       FrameIndex -= MFI->getObjectIndexBegin();
523   }
524   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
525 }
526 
527 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
528                                     const TargetRegisterInfo *TRI) {
529   OS << "%subreg.";
530   if (TRI)
531     OS << TRI->getSubRegIndexName(Index);
532   else
533     OS << Index;
534 }
535 
536 void MachineOperand::printTargetFlags(raw_ostream &OS,
537                                       const MachineOperand &Op) {
538   if (!Op.getTargetFlags())
539     return;
540   const MachineFunction *MF = getMFIfAvailable(Op);
541   if (!MF)
542     return;
543 
544   const auto *TII = MF->getSubtarget().getInstrInfo();
545   assert(TII && "expected instruction info");
546   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
547   OS << "target-flags(";
548   const bool HasDirectFlags = Flags.first;
549   const bool HasBitmaskFlags = Flags.second;
550   if (!HasDirectFlags && !HasBitmaskFlags) {
551     OS << "<unknown>) ";
552     return;
553   }
554   if (HasDirectFlags) {
555     if (const auto *Name = getTargetFlagName(TII, Flags.first))
556       OS << Name;
557     else
558       OS << "<unknown target flag>";
559   }
560   if (!HasBitmaskFlags) {
561     OS << ") ";
562     return;
563   }
564   bool IsCommaNeeded = HasDirectFlags;
565   unsigned BitMask = Flags.second;
566   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
567   for (const auto &Mask : BitMasks) {
568     // Check if the flag's bitmask has the bits of the current mask set.
569     if ((BitMask & Mask.first) == Mask.first) {
570       if (IsCommaNeeded)
571         OS << ", ";
572       IsCommaNeeded = true;
573       OS << Mask.second;
574       // Clear the bits which were serialized from the flag's bitmask.
575       BitMask &= ~(Mask.first);
576     }
577   }
578   if (BitMask) {
579     // When the resulting flag's bitmask isn't zero, we know that we didn't
580     // serialize all of the bit flags.
581     if (IsCommaNeeded)
582       OS << ", ";
583     OS << "<unknown bitmask target flag>";
584   }
585   OS << ") ";
586 }
587 
588 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
589   OS << "<mcsymbol " << Sym << ">";
590 }
591 
592 void MachineOperand::printStackObjectReference(raw_ostream &OS,
593                                                unsigned FrameIndex,
594                                                bool IsFixed, StringRef Name) {
595   if (IsFixed) {
596     OS << "%fixed-stack." << FrameIndex;
597     return;
598   }
599 
600   OS << "%stack." << FrameIndex;
601   if (!Name.empty())
602     OS << '.' << Name;
603 }
604 
605 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
606   if (Offset == 0)
607     return;
608   if (Offset < 0) {
609     OS << " - " << -Offset;
610     return;
611   }
612   OS << " + " << Offset;
613 }
614 
615 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
616   if (Slot == -1)
617     OS << "<badref>";
618   else
619     OS << Slot;
620 }
621 
622 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
623                      const TargetRegisterInfo *TRI) {
624   switch (CFI.getOperation()) {
625   case MCCFIInstruction::OpSameValue:
626     OS << "same_value ";
627     if (MCSymbol *Label = CFI.getLabel())
628       MachineOperand::printSymbol(OS, *Label);
629     printCFIRegister(CFI.getRegister(), OS, TRI);
630     break;
631   case MCCFIInstruction::OpRememberState:
632     OS << "remember_state ";
633     if (MCSymbol *Label = CFI.getLabel())
634       MachineOperand::printSymbol(OS, *Label);
635     break;
636   case MCCFIInstruction::OpRestoreState:
637     OS << "restore_state ";
638     if (MCSymbol *Label = CFI.getLabel())
639       MachineOperand::printSymbol(OS, *Label);
640     break;
641   case MCCFIInstruction::OpOffset:
642     OS << "offset ";
643     if (MCSymbol *Label = CFI.getLabel())
644       MachineOperand::printSymbol(OS, *Label);
645     printCFIRegister(CFI.getRegister(), OS, TRI);
646     OS << ", " << CFI.getOffset();
647     break;
648   case MCCFIInstruction::OpDefCfaRegister:
649     OS << "def_cfa_register ";
650     if (MCSymbol *Label = CFI.getLabel())
651       MachineOperand::printSymbol(OS, *Label);
652     printCFIRegister(CFI.getRegister(), OS, TRI);
653     break;
654   case MCCFIInstruction::OpDefCfaOffset:
655     OS << "def_cfa_offset ";
656     if (MCSymbol *Label = CFI.getLabel())
657       MachineOperand::printSymbol(OS, *Label);
658     OS << CFI.getOffset();
659     break;
660   case MCCFIInstruction::OpDefCfa:
661     OS << "def_cfa ";
662     if (MCSymbol *Label = CFI.getLabel())
663       MachineOperand::printSymbol(OS, *Label);
664     printCFIRegister(CFI.getRegister(), OS, TRI);
665     OS << ", " << CFI.getOffset();
666     break;
667   case MCCFIInstruction::OpRelOffset:
668     OS << "rel_offset ";
669     if (MCSymbol *Label = CFI.getLabel())
670       MachineOperand::printSymbol(OS, *Label);
671     printCFIRegister(CFI.getRegister(), OS, TRI);
672     OS << ", " << CFI.getOffset();
673     break;
674   case MCCFIInstruction::OpAdjustCfaOffset:
675     OS << "adjust_cfa_offset ";
676     if (MCSymbol *Label = CFI.getLabel())
677       MachineOperand::printSymbol(OS, *Label);
678     OS << CFI.getOffset();
679     break;
680   case MCCFIInstruction::OpRestore:
681     OS << "restore ";
682     if (MCSymbol *Label = CFI.getLabel())
683       MachineOperand::printSymbol(OS, *Label);
684     printCFIRegister(CFI.getRegister(), OS, TRI);
685     break;
686   case MCCFIInstruction::OpEscape: {
687     OS << "escape ";
688     if (MCSymbol *Label = CFI.getLabel())
689       MachineOperand::printSymbol(OS, *Label);
690     if (!CFI.getValues().empty()) {
691       size_t e = CFI.getValues().size() - 1;
692       for (size_t i = 0; i < e; ++i)
693         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
694       OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
695     }
696     break;
697   }
698   case MCCFIInstruction::OpUndefined:
699     OS << "undefined ";
700     if (MCSymbol *Label = CFI.getLabel())
701       MachineOperand::printSymbol(OS, *Label);
702     printCFIRegister(CFI.getRegister(), OS, TRI);
703     break;
704   case MCCFIInstruction::OpRegister:
705     OS << "register ";
706     if (MCSymbol *Label = CFI.getLabel())
707       MachineOperand::printSymbol(OS, *Label);
708     printCFIRegister(CFI.getRegister(), OS, TRI);
709     OS << ", ";
710     printCFIRegister(CFI.getRegister2(), OS, TRI);
711     break;
712   case MCCFIInstruction::OpWindowSave:
713     OS << "window_save ";
714     if (MCSymbol *Label = CFI.getLabel())
715       MachineOperand::printSymbol(OS, *Label);
716     break;
717   case MCCFIInstruction::OpNegateRAState:
718     OS << "negate_ra_sign_state ";
719     if (MCSymbol *Label = CFI.getLabel())
720       MachineOperand::printSymbol(OS, *Label);
721     break;
722   default:
723     // TODO: Print the other CFI Operations.
724     OS << "<unserializable cfi directive>";
725     break;
726   }
727 }
728 
729 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
730                            const TargetIntrinsicInfo *IntrinsicInfo) const {
731   print(OS, LLT{}, TRI, IntrinsicInfo);
732 }
733 
734 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
735                            const TargetRegisterInfo *TRI,
736                            const TargetIntrinsicInfo *IntrinsicInfo) const {
737   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
738   ModuleSlotTracker DummyMST(nullptr);
739   print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
740         /*ShouldPrintRegisterTies=*/true,
741         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
742 }
743 
744 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
745                            LLT TypeToPrint, bool PrintDef, bool IsStandalone,
746                            bool ShouldPrintRegisterTies,
747                            unsigned TiedOperandIdx,
748                            const TargetRegisterInfo *TRI,
749                            const TargetIntrinsicInfo *IntrinsicInfo) const {
750   printTargetFlags(OS, *this);
751   switch (getType()) {
752   case MachineOperand::MO_Register: {
753     unsigned Reg = getReg();
754     if (isImplicit())
755       OS << (isDef() ? "implicit-def " : "implicit ");
756     else if (PrintDef && isDef())
757       // Print the 'def' flag only when the operand is defined after '='.
758       OS << "def ";
759     if (isInternalRead())
760       OS << "internal ";
761     if (isDead())
762       OS << "dead ";
763     if (isKill())
764       OS << "killed ";
765     if (isUndef())
766       OS << "undef ";
767     if (isEarlyClobber())
768       OS << "early-clobber ";
769     if (Register::isPhysicalRegister(getReg()) && isRenamable())
770       OS << "renamable ";
771     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
772     // simply infer it when parsing and do not need to print it.
773 
774     const MachineRegisterInfo *MRI = nullptr;
775     if (Register::isVirtualRegister(Reg)) {
776       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
777         MRI = &MF->getRegInfo();
778       }
779     }
780 
781     OS << printReg(Reg, TRI, 0, MRI);
782     // Print the sub register.
783     if (unsigned SubReg = getSubReg()) {
784       if (TRI)
785         OS << '.' << TRI->getSubRegIndexName(SubReg);
786       else
787         OS << ".subreg" << SubReg;
788     }
789     // Print the register class / bank.
790     if (Register::isVirtualRegister(Reg)) {
791       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
792         const MachineRegisterInfo &MRI = MF->getRegInfo();
793         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
794           OS << ':';
795           OS << printRegClassOrBank(Reg, MRI, TRI);
796         }
797       }
798     }
799     // Print ties.
800     if (ShouldPrintRegisterTies && isTied() && !isDef())
801       OS << "(tied-def " << TiedOperandIdx << ")";
802     // Print types.
803     if (TypeToPrint.isValid())
804       OS << '(' << TypeToPrint << ')';
805     break;
806   }
807   case MachineOperand::MO_Immediate:
808     OS << getImm();
809     break;
810   case MachineOperand::MO_CImmediate:
811     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
812     break;
813   case MachineOperand::MO_FPImmediate:
814     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
815     break;
816   case MachineOperand::MO_MachineBasicBlock:
817     OS << printMBBReference(*getMBB());
818     break;
819   case MachineOperand::MO_FrameIndex: {
820     int FrameIndex = getIndex();
821     bool IsFixed = false;
822     const MachineFrameInfo *MFI = nullptr;
823     if (const MachineFunction *MF = getMFIfAvailable(*this))
824       MFI = &MF->getFrameInfo();
825     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
826     break;
827   }
828   case MachineOperand::MO_ConstantPoolIndex:
829     OS << "%const." << getIndex();
830     printOperandOffset(OS, getOffset());
831     break;
832   case MachineOperand::MO_TargetIndex: {
833     OS << "target-index(";
834     const char *Name = "<unknown>";
835     if (const MachineFunction *MF = getMFIfAvailable(*this))
836       if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
837         Name = TargetIndexName;
838     OS << Name << ')';
839     printOperandOffset(OS, getOffset());
840     break;
841   }
842   case MachineOperand::MO_JumpTableIndex:
843     OS << printJumpTableEntryReference(getIndex());
844     break;
845   case MachineOperand::MO_GlobalAddress:
846     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
847     printOperandOffset(OS, getOffset());
848     break;
849   case MachineOperand::MO_ExternalSymbol: {
850     StringRef Name = getSymbolName();
851     OS << '&';
852     if (Name.empty()) {
853       OS << "\"\"";
854     } else {
855       printLLVMNameWithoutPrefix(OS, Name);
856     }
857     printOperandOffset(OS, getOffset());
858     break;
859   }
860   case MachineOperand::MO_BlockAddress: {
861     OS << "blockaddress(";
862     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
863                                                      MST);
864     OS << ", ";
865     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
866     OS << ')';
867     MachineOperand::printOperandOffset(OS, getOffset());
868     break;
869   }
870   case MachineOperand::MO_RegisterMask: {
871     OS << "<regmask";
872     if (TRI) {
873       unsigned NumRegsInMask = 0;
874       unsigned NumRegsEmitted = 0;
875       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
876         unsigned MaskWord = i / 32;
877         unsigned MaskBit = i % 32;
878         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
879           if (PrintRegMaskNumRegs < 0 ||
880               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
881             OS << " " << printReg(i, TRI);
882             NumRegsEmitted++;
883           }
884           NumRegsInMask++;
885         }
886       }
887       if (NumRegsEmitted != NumRegsInMask)
888         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
889     } else {
890       OS << " ...";
891     }
892     OS << ">";
893     break;
894   }
895   case MachineOperand::MO_RegisterLiveOut: {
896     const uint32_t *RegMask = getRegLiveOut();
897     OS << "liveout(";
898     if (!TRI) {
899       OS << "<unknown>";
900     } else {
901       bool IsCommaNeeded = false;
902       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
903         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
904           if (IsCommaNeeded)
905             OS << ", ";
906           OS << printReg(Reg, TRI);
907           IsCommaNeeded = true;
908         }
909       }
910     }
911     OS << ")";
912     break;
913   }
914   case MachineOperand::MO_Metadata:
915     getMetadata()->printAsOperand(OS, MST);
916     break;
917   case MachineOperand::MO_MCSymbol:
918     printSymbol(OS, *getMCSymbol());
919     break;
920   case MachineOperand::MO_CFIIndex: {
921     if (const MachineFunction *MF = getMFIfAvailable(*this))
922       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
923     else
924       OS << "<cfi directive>";
925     break;
926   }
927   case MachineOperand::MO_IntrinsicID: {
928     Intrinsic::ID ID = getIntrinsicID();
929     if (ID < Intrinsic::num_intrinsics)
930       OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
931     else if (IntrinsicInfo)
932       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
933     else
934       OS << "intrinsic(" << ID << ')';
935     break;
936   }
937   case MachineOperand::MO_Predicate: {
938     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
939     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
940        << CmpInst::getPredicateName(Pred) << ')';
941     break;
942   }
943   case MachineOperand::MO_ShuffleMask:
944     OS << "shufflemask(";
945     const Constant* C = getShuffleMask();
946     const int NumElts = C->getType()->getVectorNumElements();
947 
948     StringRef Separator;
949     for (int I = 0; I != NumElts; ++I) {
950       OS << Separator;
951       C->getAggregateElement(I)->printAsOperand(OS, false, MST);
952       Separator = ", ";
953     }
954 
955     OS << ')';
956     break;
957   }
958 }
959 
960 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
961 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
962 #endif
963 
964 //===----------------------------------------------------------------------===//
965 // MachineMemOperand Implementation
966 //===----------------------------------------------------------------------===//
967 
968 /// getAddrSpace - Return the LLVM IR address space number that this pointer
969 /// points into.
970 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
971 
972 /// isDereferenceable - Return true if V is always dereferenceable for
973 /// Offset + Size byte.
974 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
975                                            const DataLayout &DL) const {
976   if (!V.is<const Value *>())
977     return false;
978 
979   const Value *BasePtr = V.get<const Value *>();
980   if (BasePtr == nullptr)
981     return false;
982 
983   return isDereferenceableAndAlignedPointer(
984       BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
985 }
986 
987 /// getConstantPool - Return a MachinePointerInfo record that refers to the
988 /// constant pool.
989 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
990   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
991 }
992 
993 /// getFixedStack - Return a MachinePointerInfo record that refers to the
994 /// the specified FrameIndex.
995 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
996                                                      int FI, int64_t Offset) {
997   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
998 }
999 
1000 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
1001   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
1002 }
1003 
1004 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
1005   return MachinePointerInfo(MF.getPSVManager().getGOT());
1006 }
1007 
1008 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
1009                                                 int64_t Offset, uint8_t ID) {
1010   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
1011 }
1012 
1013 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1014   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1015 }
1016 
1017 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1018                                      uint64_t s, uint64_t a,
1019                                      const AAMDNodes &AAInfo,
1020                                      const MDNode *Ranges, SyncScope::ID SSID,
1021                                      AtomicOrdering Ordering,
1022                                      AtomicOrdering FailureOrdering)
1023     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
1024       AAInfo(AAInfo), Ranges(Ranges) {
1025   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1026           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1027          "invalid pointer value");
1028   assert(getBaseAlignment() == a && a != 0 && "Alignment is not a power of 2!");
1029   assert((isLoad() || isStore()) && "Not a load/store!");
1030 
1031   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1032   assert(getSyncScopeID() == SSID && "Value truncated");
1033   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1034   assert(getOrdering() == Ordering && "Value truncated");
1035   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1036   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1037 }
1038 
1039 /// Profile - Gather unique data for the object.
1040 ///
1041 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1042   ID.AddInteger(getOffset());
1043   ID.AddInteger(Size);
1044   ID.AddPointer(getOpaqueValue());
1045   ID.AddInteger(getFlags());
1046   ID.AddInteger(getBaseAlignment());
1047 }
1048 
1049 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1050   // The Value and Offset may differ due to CSE. But the flags and size
1051   // should be the same.
1052   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1053   assert(MMO->getSize() == getSize() && "Size mismatch!");
1054 
1055   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1056     // Update the alignment value.
1057     BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1058     // Also update the base and offset, because the new alignment may
1059     // not be applicable with the old ones.
1060     PtrInfo = MMO->PtrInfo;
1061   }
1062 }
1063 
1064 /// getAlignment - Return the minimum known alignment in bytes of the
1065 /// actual memory reference.
1066 uint64_t MachineMemOperand::getAlignment() const {
1067   return MinAlign(getBaseAlignment(), getOffset());
1068 }
1069 
1070 void MachineMemOperand::print(raw_ostream &OS) const {
1071   ModuleSlotTracker DummyMST(nullptr);
1072   print(OS, DummyMST);
1073 }
1074 
1075 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1076   SmallVector<StringRef, 0> SSNs;
1077   LLVMContext Ctx;
1078   print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1079 }
1080 
1081 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1082                               SmallVectorImpl<StringRef> &SSNs,
1083                               const LLVMContext &Context,
1084                               const MachineFrameInfo *MFI,
1085                               const TargetInstrInfo *TII) const {
1086   OS << '(';
1087   if (isVolatile())
1088     OS << "volatile ";
1089   if (isNonTemporal())
1090     OS << "non-temporal ";
1091   if (isDereferenceable())
1092     OS << "dereferenceable ";
1093   if (isInvariant())
1094     OS << "invariant ";
1095   if (getFlags() & MachineMemOperand::MOTargetFlag1)
1096     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1097        << "\" ";
1098   if (getFlags() & MachineMemOperand::MOTargetFlag2)
1099     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1100        << "\" ";
1101   if (getFlags() & MachineMemOperand::MOTargetFlag3)
1102     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1103        << "\" ";
1104 
1105   assert((isLoad() || isStore()) &&
1106          "machine memory operand must be a load or store (or both)");
1107   if (isLoad())
1108     OS << "load ";
1109   if (isStore())
1110     OS << "store ";
1111 
1112   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1113 
1114   if (getOrdering() != AtomicOrdering::NotAtomic)
1115     OS << toIRString(getOrdering()) << ' ';
1116   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1117     OS << toIRString(getFailureOrdering()) << ' ';
1118 
1119   if (getSize() == MemoryLocation::UnknownSize)
1120     OS << "unknown-size";
1121   else
1122     OS << getSize();
1123 
1124   if (const Value *Val = getValue()) {
1125     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1126     printIRValueReference(OS, *Val, MST);
1127   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1128     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1129     assert(PVal && "Expected a pseudo source value");
1130     switch (PVal->kind()) {
1131     case PseudoSourceValue::Stack:
1132       OS << "stack";
1133       break;
1134     case PseudoSourceValue::GOT:
1135       OS << "got";
1136       break;
1137     case PseudoSourceValue::JumpTable:
1138       OS << "jump-table";
1139       break;
1140     case PseudoSourceValue::ConstantPool:
1141       OS << "constant-pool";
1142       break;
1143     case PseudoSourceValue::FixedStack: {
1144       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1145       bool IsFixed = true;
1146       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1147       break;
1148     }
1149     case PseudoSourceValue::GlobalValueCallEntry:
1150       OS << "call-entry ";
1151       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1152           OS, /*PrintType=*/false, MST);
1153       break;
1154     case PseudoSourceValue::ExternalSymbolCallEntry:
1155       OS << "call-entry &";
1156       printLLVMNameWithoutPrefix(
1157           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1158       break;
1159     default:
1160       // FIXME: This is not necessarily the correct MIR serialization format for
1161       // a custom pseudo source value, but at least it allows
1162       // -print-machineinstrs to work on a target with custom pseudo source
1163       // values.
1164       OS << "custom ";
1165       PVal->printCustom(OS);
1166       break;
1167     }
1168   }
1169   MachineOperand::printOperandOffset(OS, getOffset());
1170   if (getBaseAlignment() != getSize())
1171     OS << ", align " << getBaseAlignment();
1172   auto AAInfo = getAAInfo();
1173   if (AAInfo.TBAA) {
1174     OS << ", !tbaa ";
1175     AAInfo.TBAA->printAsOperand(OS, MST);
1176   }
1177   if (AAInfo.Scope) {
1178     OS << ", !alias.scope ";
1179     AAInfo.Scope->printAsOperand(OS, MST);
1180   }
1181   if (AAInfo.NoAlias) {
1182     OS << ", !noalias ";
1183     AAInfo.NoAlias->printAsOperand(OS, MST);
1184   }
1185   if (getRanges()) {
1186     OS << ", !range ";
1187     getRanges()->printAsOperand(OS, MST);
1188   }
1189   // FIXME: Implement addrspace printing/parsing in MIR.
1190   // For now, print this even though parsing it is not available in MIR.
1191   if (unsigned AS = getAddrSpace())
1192     OS << ", addrspace " << AS;
1193 
1194   OS << ')';
1195 }
1196