xref: /llvm-project/llvm/lib/CodeGen/MachineOperand.cpp (revision 3ef05d85be8c3666ebfa3ad986eb334da5195a47) 
1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/MachineOperand.h"
14 #include "llvm/ADT/StringExtras.h"
15 #include "llvm/Analysis/Loads.h"
16 #include "llvm/Analysis/MemoryLocation.h"
17 #include "llvm/CodeGen/MIRFormatter.h"
18 #include "llvm/CodeGen/MIRPrinter.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineJumpTableInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
24 #include "llvm/Config/llvm-config.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/IRPrintingPasses.h"
27 #include "llvm/IR/ModuleSlotTracker.h"
28 #include "llvm/MC/MCDwarf.h"
29 #include "llvm/Target/TargetIntrinsicInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 
32 using namespace llvm;
33 
34 static cl::opt<int>
35     PrintRegMaskNumRegs("print-regmask-num-regs",
36                         cl::desc("Number of registers to limit to when "
37                                  "printing regmask operands in IR dumps. "
38                                  "unlimited = -1"),
39                         cl::init(32), cl::Hidden);
40 
41 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
42   if (const MachineInstr *MI = MO.getParent())
43     if (const MachineBasicBlock *MBB = MI->getParent())
44       if (const MachineFunction *MF = MBB->getParent())
45         return MF;
46   return nullptr;
47 }
48 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
49   return const_cast<MachineFunction *>(
50       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
51 }
52 
53 void MachineOperand::setReg(Register Reg) {
54   if (getReg() == Reg)
55     return; // No change.
56 
57   // Clear the IsRenamable bit to keep it conservatively correct.
58   IsRenamable = false;
59 
60   // Otherwise, we have to change the register.  If this operand is embedded
61   // into a machine function, we need to update the old and new register's
62   // use/def lists.
63   if (MachineFunction *MF = getMFIfAvailable(*this)) {
64     MachineRegisterInfo &MRI = MF->getRegInfo();
65     MRI.removeRegOperandFromUseList(this);
66     SmallContents.RegNo = Reg;
67     MRI.addRegOperandToUseList(this);
68     return;
69   }
70 
71   // Otherwise, just change the register, no problem.  :)
72   SmallContents.RegNo = Reg;
73 }
74 
75 void MachineOperand::substVirtReg(Register Reg, unsigned SubIdx,
76                                   const TargetRegisterInfo &TRI) {
77   assert(Reg.isVirtual());
78   if (SubIdx && getSubReg())
79     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80   setReg(Reg);
81   if (SubIdx)
82     setSubReg(SubIdx);
83 }
84 
85 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
86   assert(Reg.isPhysical());
87   if (getSubReg()) {
88     Reg = TRI.getSubReg(Reg, getSubReg());
89     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
90     // That won't happen in legal code.
91     setSubReg(0);
92     if (isDef())
93       setIsUndef(false);
94   }
95   setReg(Reg);
96 }
97 
98 /// Change a def to a use, or a use to a def.
99 void MachineOperand::setIsDef(bool Val) {
100   assert(isReg() && "Wrong MachineOperand accessor");
101   assert((!Val || !isDebug()) && "Marking a debug operation as def");
102   if (IsDef == Val)
103     return;
104   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
105   // MRI may keep uses and defs in different list positions.
106   if (MachineFunction *MF = getMFIfAvailable(*this)) {
107     MachineRegisterInfo &MRI = MF->getRegInfo();
108     MRI.removeRegOperandFromUseList(this);
109     IsDef = Val;
110     MRI.addRegOperandToUseList(this);
111     return;
112   }
113   IsDef = Val;
114 }
115 
116 bool MachineOperand::isRenamable() const {
117   assert(isReg() && "Wrong MachineOperand accessor");
118   assert(Register::isPhysicalRegister(getReg()) &&
119          "isRenamable should only be checked on physical registers");
120   if (!IsRenamable)
121     return false;
122 
123   const MachineInstr *MI = getParent();
124   if (!MI)
125     return true;
126 
127   if (isDef())
128     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
129 
130   assert(isUse() && "Reg is not def or use");
131   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
132 }
133 
134 void MachineOperand::setIsRenamable(bool Val) {
135   assert(isReg() && "Wrong MachineOperand accessor");
136   assert(Register::isPhysicalRegister(getReg()) &&
137          "setIsRenamable should only be called on physical registers");
138   IsRenamable = Val;
139 }
140 
141 // If this operand is currently a register operand, and if this is in a
142 // function, deregister the operand from the register's use/def list.
143 void MachineOperand::removeRegFromUses() {
144   if (!isReg() || !isOnRegUseList())
145     return;
146 
147   if (MachineFunction *MF = getMFIfAvailable(*this))
148     MF->getRegInfo().removeRegOperandFromUseList(this);
149 }
150 
151 /// ChangeToImmediate - Replace this operand with a new immediate operand of
152 /// the specified value.  If an operand is known to be an immediate already,
153 /// the setImm method should be used.
154 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
155   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
156 
157   removeRegFromUses();
158 
159   OpKind = MO_Immediate;
160   Contents.ImmVal = ImmVal;
161 }
162 
163 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
164   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
165 
166   removeRegFromUses();
167 
168   OpKind = MO_FPImmediate;
169   Contents.CFP = FPImm;
170 }
171 
172 void MachineOperand::ChangeToES(const char *SymName,
173                                 unsigned TargetFlags) {
174   assert((!isReg() || !isTied()) &&
175          "Cannot change a tied operand into an external symbol");
176 
177   removeRegFromUses();
178 
179   OpKind = MO_ExternalSymbol;
180   Contents.OffsetedInfo.Val.SymbolName = SymName;
181   setOffset(0); // Offset is always 0.
182   setTargetFlags(TargetFlags);
183 }
184 
185 void MachineOperand::ChangeToGA(const GlobalValue *GV, int64_t Offset,
186                                 unsigned TargetFlags) {
187   assert((!isReg() || !isTied()) &&
188          "Cannot change a tied operand into a global address");
189 
190   removeRegFromUses();
191 
192   OpKind = MO_GlobalAddress;
193   Contents.OffsetedInfo.Val.GV = GV;
194   setOffset(Offset);
195   setTargetFlags(TargetFlags);
196 }
197 
198 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
199   assert((!isReg() || !isTied()) &&
200          "Cannot change a tied operand into an MCSymbol");
201 
202   removeRegFromUses();
203 
204   OpKind = MO_MCSymbol;
205   Contents.Sym = Sym;
206 }
207 
208 void MachineOperand::ChangeToFrameIndex(int Idx) {
209   assert((!isReg() || !isTied()) &&
210          "Cannot change a tied operand into a FrameIndex");
211 
212   removeRegFromUses();
213 
214   OpKind = MO_FrameIndex;
215   setIndex(Idx);
216 }
217 
218 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
219                                          unsigned TargetFlags) {
220   assert((!isReg() || !isTied()) &&
221          "Cannot change a tied operand into a FrameIndex");
222 
223   removeRegFromUses();
224 
225   OpKind = MO_TargetIndex;
226   setIndex(Idx);
227   setOffset(Offset);
228   setTargetFlags(TargetFlags);
229 }
230 
231 /// ChangeToRegister - Replace this operand with a new register operand of
232 /// the specified value.  If an operand is known to be an register already,
233 /// the setReg method should be used.
234 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp,
235                                       bool isKill, bool isDead, bool isUndef,
236                                       bool isDebug) {
237   MachineRegisterInfo *RegInfo = nullptr;
238   if (MachineFunction *MF = getMFIfAvailable(*this))
239     RegInfo = &MF->getRegInfo();
240   // If this operand is already a register operand, remove it from the
241   // register's use/def lists.
242   bool WasReg = isReg();
243   if (RegInfo && WasReg)
244     RegInfo->removeRegOperandFromUseList(this);
245 
246   // Change this to a register and set the reg#.
247   assert(!(isDead && !isDef) && "Dead flag on non-def");
248   assert(!(isKill && isDef) && "Kill flag on def");
249   OpKind = MO_Register;
250   SmallContents.RegNo = Reg;
251   SubReg_TargetFlags = 0;
252   IsDef = isDef;
253   IsImp = isImp;
254   IsDeadOrKill = isKill | isDead;
255   IsRenamable = false;
256   IsUndef = isUndef;
257   IsInternalRead = false;
258   IsEarlyClobber = false;
259   IsDebug = isDebug;
260   // Ensure isOnRegUseList() returns false.
261   Contents.Reg.Prev = nullptr;
262   // Preserve the tie when the operand was already a register.
263   if (!WasReg)
264     TiedTo = 0;
265 
266   // If this operand is embedded in a function, add the operand to the
267   // register's use/def list.
268   if (RegInfo)
269     RegInfo->addRegOperandToUseList(this);
270 }
271 
272 /// isIdenticalTo - Return true if this operand is identical to the specified
273 /// operand. Note that this should stay in sync with the hash_value overload
274 /// below.
275 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
276   if (getType() != Other.getType() ||
277       getTargetFlags() != Other.getTargetFlags())
278     return false;
279 
280   switch (getType()) {
281   case MachineOperand::MO_Register:
282     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
283            getSubReg() == Other.getSubReg();
284   case MachineOperand::MO_Immediate:
285     return getImm() == Other.getImm();
286   case MachineOperand::MO_CImmediate:
287     return getCImm() == Other.getCImm();
288   case MachineOperand::MO_FPImmediate:
289     return getFPImm() == Other.getFPImm();
290   case MachineOperand::MO_MachineBasicBlock:
291     return getMBB() == Other.getMBB();
292   case MachineOperand::MO_FrameIndex:
293     return getIndex() == Other.getIndex();
294   case MachineOperand::MO_ConstantPoolIndex:
295   case MachineOperand::MO_TargetIndex:
296     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
297   case MachineOperand::MO_JumpTableIndex:
298     return getIndex() == Other.getIndex();
299   case MachineOperand::MO_GlobalAddress:
300     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
301   case MachineOperand::MO_ExternalSymbol:
302     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
303            getOffset() == Other.getOffset();
304   case MachineOperand::MO_BlockAddress:
305     return getBlockAddress() == Other.getBlockAddress() &&
306            getOffset() == Other.getOffset();
307   case MachineOperand::MO_RegisterMask:
308   case MachineOperand::MO_RegisterLiveOut: {
309     // Shallow compare of the two RegMasks
310     const uint32_t *RegMask = getRegMask();
311     const uint32_t *OtherRegMask = Other.getRegMask();
312     if (RegMask == OtherRegMask)
313       return true;
314 
315     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
316       // Calculate the size of the RegMask
317       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
318       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
319 
320       // Deep compare of the two RegMasks
321       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
322     }
323     // We don't know the size of the RegMask, so we can't deep compare the two
324     // reg masks.
325     return false;
326   }
327   case MachineOperand::MO_MCSymbol:
328     return getMCSymbol() == Other.getMCSymbol();
329   case MachineOperand::MO_CFIIndex:
330     return getCFIIndex() == Other.getCFIIndex();
331   case MachineOperand::MO_Metadata:
332     return getMetadata() == Other.getMetadata();
333   case MachineOperand::MO_IntrinsicID:
334     return getIntrinsicID() == Other.getIntrinsicID();
335   case MachineOperand::MO_Predicate:
336     return getPredicate() == Other.getPredicate();
337   case MachineOperand::MO_ShuffleMask:
338     return getShuffleMask() == Other.getShuffleMask();
339   }
340   llvm_unreachable("Invalid machine operand type");
341 }
342 
343 // Note: this must stay exactly in sync with isIdenticalTo above.
344 hash_code llvm::hash_value(const MachineOperand &MO) {
345   switch (MO.getType()) {
346   case MachineOperand::MO_Register:
347     // Register operands don't have target flags.
348     return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
349   case MachineOperand::MO_Immediate:
350     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
351   case MachineOperand::MO_CImmediate:
352     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
353   case MachineOperand::MO_FPImmediate:
354     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
355   case MachineOperand::MO_MachineBasicBlock:
356     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
357   case MachineOperand::MO_FrameIndex:
358     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
359   case MachineOperand::MO_ConstantPoolIndex:
360   case MachineOperand::MO_TargetIndex:
361     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
362                         MO.getOffset());
363   case MachineOperand::MO_JumpTableIndex:
364     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
365   case MachineOperand::MO_ExternalSymbol:
366     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
367                         StringRef(MO.getSymbolName()));
368   case MachineOperand::MO_GlobalAddress:
369     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
370                         MO.getOffset());
371   case MachineOperand::MO_BlockAddress:
372     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
373                         MO.getOffset());
374   case MachineOperand::MO_RegisterMask:
375   case MachineOperand::MO_RegisterLiveOut:
376     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
377   case MachineOperand::MO_Metadata:
378     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
379   case MachineOperand::MO_MCSymbol:
380     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
381   case MachineOperand::MO_CFIIndex:
382     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
383   case MachineOperand::MO_IntrinsicID:
384     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
385   case MachineOperand::MO_Predicate:
386     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
387   case MachineOperand::MO_ShuffleMask:
388     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getShuffleMask());
389   }
390   llvm_unreachable("Invalid machine operand type");
391 }
392 
393 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
394 // it.
395 static void tryToGetTargetInfo(const MachineOperand &MO,
396                                const TargetRegisterInfo *&TRI,
397                                const TargetIntrinsicInfo *&IntrinsicInfo) {
398   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
399     TRI = MF->getSubtarget().getRegisterInfo();
400     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
401   }
402 }
403 
404 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
405   const auto *TII = MF.getSubtarget().getInstrInfo();
406   assert(TII && "expected instruction info");
407   auto Indices = TII->getSerializableTargetIndices();
408   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
409     return I.first == Index;
410   });
411   if (Found != Indices.end())
412     return Found->second;
413   return nullptr;
414 }
415 
416 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
417   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
418   for (const auto &I : Flags) {
419     if (I.first == TF) {
420       return I.second;
421     }
422   }
423   return nullptr;
424 }
425 
426 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
427                              const TargetRegisterInfo *TRI) {
428   if (!TRI) {
429     OS << "%dwarfreg." << DwarfReg;
430     return;
431   }
432 
433   if (Optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
434     OS << printReg(*Reg, TRI);
435   else
436     OS << "<badreg>";
437 }
438 
439 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
440                                   ModuleSlotTracker &MST) {
441   OS << "%ir-block.";
442   if (BB.hasName()) {
443     printLLVMNameWithoutPrefix(OS, BB.getName());
444     return;
445   }
446   Optional<int> Slot;
447   if (const Function *F = BB.getParent()) {
448     if (F == MST.getCurrentFunction()) {
449       Slot = MST.getLocalSlot(&BB);
450     } else if (const Module *M = F->getParent()) {
451       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
452       CustomMST.incorporateFunction(*F);
453       Slot = CustomMST.getLocalSlot(&BB);
454     }
455   }
456   if (Slot)
457     MachineOperand::printIRSlotNumber(OS, *Slot);
458   else
459     OS << "<unknown>";
460 }
461 
462 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
463                            SyncScope::ID SSID,
464                            SmallVectorImpl<StringRef> &SSNs) {
465   switch (SSID) {
466   case SyncScope::System:
467     break;
468   default:
469     if (SSNs.empty())
470       Context.getSyncScopeNames(SSNs);
471 
472     OS << "syncscope(\"";
473     printEscapedString(SSNs[SSID], OS);
474     OS << "\") ";
475     break;
476   }
477 }
478 
479 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
480                                         unsigned TMMOFlag) {
481   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
482   for (const auto &I : Flags) {
483     if (I.first == TMMOFlag) {
484       return I.second;
485     }
486   }
487   return nullptr;
488 }
489 
490 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
491                             const MachineFrameInfo *MFI) {
492   StringRef Name;
493   if (MFI) {
494     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
495     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
496       if (Alloca->hasName())
497         Name = Alloca->getName();
498     if (IsFixed)
499       FrameIndex -= MFI->getObjectIndexBegin();
500   }
501   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
502 }
503 
504 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
505                                     const TargetRegisterInfo *TRI) {
506   OS << "%subreg.";
507   if (TRI)
508     OS << TRI->getSubRegIndexName(Index);
509   else
510     OS << Index;
511 }
512 
513 void MachineOperand::printTargetFlags(raw_ostream &OS,
514                                       const MachineOperand &Op) {
515   if (!Op.getTargetFlags())
516     return;
517   const MachineFunction *MF = getMFIfAvailable(Op);
518   if (!MF)
519     return;
520 
521   const auto *TII = MF->getSubtarget().getInstrInfo();
522   assert(TII && "expected instruction info");
523   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
524   OS << "target-flags(";
525   const bool HasDirectFlags = Flags.first;
526   const bool HasBitmaskFlags = Flags.second;
527   if (!HasDirectFlags && !HasBitmaskFlags) {
528     OS << "<unknown>) ";
529     return;
530   }
531   if (HasDirectFlags) {
532     if (const auto *Name = getTargetFlagName(TII, Flags.first))
533       OS << Name;
534     else
535       OS << "<unknown target flag>";
536   }
537   if (!HasBitmaskFlags) {
538     OS << ") ";
539     return;
540   }
541   bool IsCommaNeeded = HasDirectFlags;
542   unsigned BitMask = Flags.second;
543   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
544   for (const auto &Mask : BitMasks) {
545     // Check if the flag's bitmask has the bits of the current mask set.
546     if ((BitMask & Mask.first) == Mask.first) {
547       if (IsCommaNeeded)
548         OS << ", ";
549       IsCommaNeeded = true;
550       OS << Mask.second;
551       // Clear the bits which were serialized from the flag's bitmask.
552       BitMask &= ~(Mask.first);
553     }
554   }
555   if (BitMask) {
556     // When the resulting flag's bitmask isn't zero, we know that we didn't
557     // serialize all of the bit flags.
558     if (IsCommaNeeded)
559       OS << ", ";
560     OS << "<unknown bitmask target flag>";
561   }
562   OS << ") ";
563 }
564 
565 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
566   OS << "<mcsymbol " << Sym << ">";
567 }
568 
569 void MachineOperand::printStackObjectReference(raw_ostream &OS,
570                                                unsigned FrameIndex,
571                                                bool IsFixed, StringRef Name) {
572   if (IsFixed) {
573     OS << "%fixed-stack." << FrameIndex;
574     return;
575   }
576 
577   OS << "%stack." << FrameIndex;
578   if (!Name.empty())
579     OS << '.' << Name;
580 }
581 
582 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
583   if (Offset == 0)
584     return;
585   if (Offset < 0) {
586     OS << " - " << -Offset;
587     return;
588   }
589   OS << " + " << Offset;
590 }
591 
592 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
593   if (Slot == -1)
594     OS << "<badref>";
595   else
596     OS << Slot;
597 }
598 
599 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
600                      const TargetRegisterInfo *TRI) {
601   switch (CFI.getOperation()) {
602   case MCCFIInstruction::OpSameValue:
603     OS << "same_value ";
604     if (MCSymbol *Label = CFI.getLabel())
605       MachineOperand::printSymbol(OS, *Label);
606     printCFIRegister(CFI.getRegister(), OS, TRI);
607     break;
608   case MCCFIInstruction::OpRememberState:
609     OS << "remember_state ";
610     if (MCSymbol *Label = CFI.getLabel())
611       MachineOperand::printSymbol(OS, *Label);
612     break;
613   case MCCFIInstruction::OpRestoreState:
614     OS << "restore_state ";
615     if (MCSymbol *Label = CFI.getLabel())
616       MachineOperand::printSymbol(OS, *Label);
617     break;
618   case MCCFIInstruction::OpOffset:
619     OS << "offset ";
620     if (MCSymbol *Label = CFI.getLabel())
621       MachineOperand::printSymbol(OS, *Label);
622     printCFIRegister(CFI.getRegister(), OS, TRI);
623     OS << ", " << CFI.getOffset();
624     break;
625   case MCCFIInstruction::OpDefCfaRegister:
626     OS << "def_cfa_register ";
627     if (MCSymbol *Label = CFI.getLabel())
628       MachineOperand::printSymbol(OS, *Label);
629     printCFIRegister(CFI.getRegister(), OS, TRI);
630     break;
631   case MCCFIInstruction::OpDefCfaOffset:
632     OS << "def_cfa_offset ";
633     if (MCSymbol *Label = CFI.getLabel())
634       MachineOperand::printSymbol(OS, *Label);
635     OS << CFI.getOffset();
636     break;
637   case MCCFIInstruction::OpDefCfa:
638     OS << "def_cfa ";
639     if (MCSymbol *Label = CFI.getLabel())
640       MachineOperand::printSymbol(OS, *Label);
641     printCFIRegister(CFI.getRegister(), OS, TRI);
642     OS << ", " << CFI.getOffset();
643     break;
644   case MCCFIInstruction::OpRelOffset:
645     OS << "rel_offset ";
646     if (MCSymbol *Label = CFI.getLabel())
647       MachineOperand::printSymbol(OS, *Label);
648     printCFIRegister(CFI.getRegister(), OS, TRI);
649     OS << ", " << CFI.getOffset();
650     break;
651   case MCCFIInstruction::OpAdjustCfaOffset:
652     OS << "adjust_cfa_offset ";
653     if (MCSymbol *Label = CFI.getLabel())
654       MachineOperand::printSymbol(OS, *Label);
655     OS << CFI.getOffset();
656     break;
657   case MCCFIInstruction::OpRestore:
658     OS << "restore ";
659     if (MCSymbol *Label = CFI.getLabel())
660       MachineOperand::printSymbol(OS, *Label);
661     printCFIRegister(CFI.getRegister(), OS, TRI);
662     break;
663   case MCCFIInstruction::OpEscape: {
664     OS << "escape ";
665     if (MCSymbol *Label = CFI.getLabel())
666       MachineOperand::printSymbol(OS, *Label);
667     if (!CFI.getValues().empty()) {
668       size_t e = CFI.getValues().size() - 1;
669       for (size_t i = 0; i < e; ++i)
670         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
671       OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
672     }
673     break;
674   }
675   case MCCFIInstruction::OpUndefined:
676     OS << "undefined ";
677     if (MCSymbol *Label = CFI.getLabel())
678       MachineOperand::printSymbol(OS, *Label);
679     printCFIRegister(CFI.getRegister(), OS, TRI);
680     break;
681   case MCCFIInstruction::OpRegister:
682     OS << "register ";
683     if (MCSymbol *Label = CFI.getLabel())
684       MachineOperand::printSymbol(OS, *Label);
685     printCFIRegister(CFI.getRegister(), OS, TRI);
686     OS << ", ";
687     printCFIRegister(CFI.getRegister2(), OS, TRI);
688     break;
689   case MCCFIInstruction::OpWindowSave:
690     OS << "window_save ";
691     if (MCSymbol *Label = CFI.getLabel())
692       MachineOperand::printSymbol(OS, *Label);
693     break;
694   case MCCFIInstruction::OpNegateRAState:
695     OS << "negate_ra_sign_state ";
696     if (MCSymbol *Label = CFI.getLabel())
697       MachineOperand::printSymbol(OS, *Label);
698     break;
699   default:
700     // TODO: Print the other CFI Operations.
701     OS << "<unserializable cfi directive>";
702     break;
703   }
704 }
705 
706 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
707                            const TargetIntrinsicInfo *IntrinsicInfo) const {
708   print(OS, LLT{}, TRI, IntrinsicInfo);
709 }
710 
711 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
712                            const TargetRegisterInfo *TRI,
713                            const TargetIntrinsicInfo *IntrinsicInfo) const {
714   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
715   ModuleSlotTracker DummyMST(nullptr);
716   print(OS, DummyMST, TypeToPrint, None, /*PrintDef=*/false,
717         /*IsStandalone=*/true,
718         /*ShouldPrintRegisterTies=*/true,
719         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
720 }
721 
722 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
723                            LLT TypeToPrint, Optional<unsigned> OpIdx, bool PrintDef,
724                            bool IsStandalone, bool ShouldPrintRegisterTies,
725                            unsigned TiedOperandIdx,
726                            const TargetRegisterInfo *TRI,
727                            const TargetIntrinsicInfo *IntrinsicInfo) const {
728   printTargetFlags(OS, *this);
729   switch (getType()) {
730   case MachineOperand::MO_Register: {
731     Register Reg = getReg();
732     if (isImplicit())
733       OS << (isDef() ? "implicit-def " : "implicit ");
734     else if (PrintDef && isDef())
735       // Print the 'def' flag only when the operand is defined after '='.
736       OS << "def ";
737     if (isInternalRead())
738       OS << "internal ";
739     if (isDead())
740       OS << "dead ";
741     if (isKill())
742       OS << "killed ";
743     if (isUndef())
744       OS << "undef ";
745     if (isEarlyClobber())
746       OS << "early-clobber ";
747     if (Register::isPhysicalRegister(getReg()) && isRenamable())
748       OS << "renamable ";
749     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
750     // simply infer it when parsing and do not need to print it.
751 
752     const MachineRegisterInfo *MRI = nullptr;
753     if (Register::isVirtualRegister(Reg)) {
754       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
755         MRI = &MF->getRegInfo();
756       }
757     }
758 
759     OS << printReg(Reg, TRI, 0, MRI);
760     // Print the sub register.
761     if (unsigned SubReg = getSubReg()) {
762       if (TRI)
763         OS << '.' << TRI->getSubRegIndexName(SubReg);
764       else
765         OS << ".subreg" << SubReg;
766     }
767     // Print the register class / bank.
768     if (Register::isVirtualRegister(Reg)) {
769       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
770         const MachineRegisterInfo &MRI = MF->getRegInfo();
771         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
772           OS << ':';
773           OS << printRegClassOrBank(Reg, MRI, TRI);
774         }
775       }
776     }
777     // Print ties.
778     if (ShouldPrintRegisterTies && isTied() && !isDef())
779       OS << "(tied-def " << TiedOperandIdx << ")";
780     // Print types.
781     if (TypeToPrint.isValid())
782       OS << '(' << TypeToPrint << ')';
783     break;
784   }
785   case MachineOperand::MO_Immediate: {
786     const MIRFormatter *Formatter = nullptr;
787     if (const MachineFunction *MF = getMFIfAvailable(*this))
788       Formatter = MF->getTarget().getMIRFormatter();
789     if (Formatter)
790       Formatter->printImm(OS, *getParent(), OpIdx, getImm());
791     else
792       OS << getImm();
793     break;
794   }
795   case MachineOperand::MO_CImmediate:
796     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
797     break;
798   case MachineOperand::MO_FPImmediate:
799     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
800     break;
801   case MachineOperand::MO_MachineBasicBlock:
802     OS << printMBBReference(*getMBB());
803     break;
804   case MachineOperand::MO_FrameIndex: {
805     int FrameIndex = getIndex();
806     bool IsFixed = false;
807     const MachineFrameInfo *MFI = nullptr;
808     if (const MachineFunction *MF = getMFIfAvailable(*this))
809       MFI = &MF->getFrameInfo();
810     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
811     break;
812   }
813   case MachineOperand::MO_ConstantPoolIndex:
814     OS << "%const." << getIndex();
815     printOperandOffset(OS, getOffset());
816     break;
817   case MachineOperand::MO_TargetIndex: {
818     OS << "target-index(";
819     const char *Name = "<unknown>";
820     if (const MachineFunction *MF = getMFIfAvailable(*this))
821       if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
822         Name = TargetIndexName;
823     OS << Name << ')';
824     printOperandOffset(OS, getOffset());
825     break;
826   }
827   case MachineOperand::MO_JumpTableIndex:
828     OS << printJumpTableEntryReference(getIndex());
829     break;
830   case MachineOperand::MO_GlobalAddress:
831     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
832     printOperandOffset(OS, getOffset());
833     break;
834   case MachineOperand::MO_ExternalSymbol: {
835     StringRef Name = getSymbolName();
836     OS << '&';
837     if (Name.empty()) {
838       OS << "\"\"";
839     } else {
840       printLLVMNameWithoutPrefix(OS, Name);
841     }
842     printOperandOffset(OS, getOffset());
843     break;
844   }
845   case MachineOperand::MO_BlockAddress: {
846     OS << "blockaddress(";
847     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
848                                                      MST);
849     OS << ", ";
850     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
851     OS << ')';
852     MachineOperand::printOperandOffset(OS, getOffset());
853     break;
854   }
855   case MachineOperand::MO_RegisterMask: {
856     OS << "<regmask";
857     if (TRI) {
858       unsigned NumRegsInMask = 0;
859       unsigned NumRegsEmitted = 0;
860       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
861         unsigned MaskWord = i / 32;
862         unsigned MaskBit = i % 32;
863         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
864           if (PrintRegMaskNumRegs < 0 ||
865               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
866             OS << " " << printReg(i, TRI);
867             NumRegsEmitted++;
868           }
869           NumRegsInMask++;
870         }
871       }
872       if (NumRegsEmitted != NumRegsInMask)
873         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
874     } else {
875       OS << " ...";
876     }
877     OS << ">";
878     break;
879   }
880   case MachineOperand::MO_RegisterLiveOut: {
881     const uint32_t *RegMask = getRegLiveOut();
882     OS << "liveout(";
883     if (!TRI) {
884       OS << "<unknown>";
885     } else {
886       bool IsCommaNeeded = false;
887       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
888         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
889           if (IsCommaNeeded)
890             OS << ", ";
891           OS << printReg(Reg, TRI);
892           IsCommaNeeded = true;
893         }
894       }
895     }
896     OS << ")";
897     break;
898   }
899   case MachineOperand::MO_Metadata:
900     getMetadata()->printAsOperand(OS, MST);
901     break;
902   case MachineOperand::MO_MCSymbol:
903     printSymbol(OS, *getMCSymbol());
904     break;
905   case MachineOperand::MO_CFIIndex: {
906     if (const MachineFunction *MF = getMFIfAvailable(*this))
907       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
908     else
909       OS << "<cfi directive>";
910     break;
911   }
912   case MachineOperand::MO_IntrinsicID: {
913     Intrinsic::ID ID = getIntrinsicID();
914     if (ID < Intrinsic::num_intrinsics)
915       OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
916     else if (IntrinsicInfo)
917       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
918     else
919       OS << "intrinsic(" << ID << ')';
920     break;
921   }
922   case MachineOperand::MO_Predicate: {
923     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
924     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
925        << CmpInst::getPredicateName(Pred) << ')';
926     break;
927   }
928   case MachineOperand::MO_ShuffleMask:
929     OS << "shufflemask(";
930     const Constant* C = getShuffleMask();
931     const int NumElts = C->getType()->getVectorNumElements();
932 
933     StringRef Separator;
934     for (int I = 0; I != NumElts; ++I) {
935       OS << Separator;
936       C->getAggregateElement(I)->printAsOperand(OS, false, MST);
937       Separator = ", ";
938     }
939 
940     OS << ')';
941     break;
942   }
943 }
944 
945 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
946 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
947 #endif
948 
949 //===----------------------------------------------------------------------===//
950 // MachineMemOperand Implementation
951 //===----------------------------------------------------------------------===//
952 
953 /// getAddrSpace - Return the LLVM IR address space number that this pointer
954 /// points into.
955 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
956 
957 /// isDereferenceable - Return true if V is always dereferenceable for
958 /// Offset + Size byte.
959 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
960                                            const DataLayout &DL) const {
961   if (!V.is<const Value *>())
962     return false;
963 
964   const Value *BasePtr = V.get<const Value *>();
965   if (BasePtr == nullptr)
966     return false;
967 
968   return isDereferenceableAndAlignedPointer(
969       BasePtr, Align::None(), APInt(DL.getPointerSizeInBits(), Offset + Size),
970       DL);
971 }
972 
973 /// getConstantPool - Return a MachinePointerInfo record that refers to the
974 /// constant pool.
975 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
976   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
977 }
978 
979 /// getFixedStack - Return a MachinePointerInfo record that refers to the
980 /// the specified FrameIndex.
981 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
982                                                      int FI, int64_t Offset) {
983   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
984 }
985 
986 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
987   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
988 }
989 
990 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
991   return MachinePointerInfo(MF.getPSVManager().getGOT());
992 }
993 
994 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
995                                                 int64_t Offset, uint8_t ID) {
996   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
997 }
998 
999 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
1000   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
1001 }
1002 
1003 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
1004                                      uint64_t s, uint64_t a,
1005                                      const AAMDNodes &AAInfo,
1006                                      const MDNode *Ranges, SyncScope::ID SSID,
1007                                      AtomicOrdering Ordering,
1008                                      AtomicOrdering FailureOrdering)
1009     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
1010       AAInfo(AAInfo), Ranges(Ranges) {
1011   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
1012           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
1013          "invalid pointer value");
1014   assert(getBaseAlignment() == a && a != 0 && "Alignment is not a power of 2!");
1015   assert((isLoad() || isStore()) && "Not a load/store!");
1016 
1017   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1018   assert(getSyncScopeID() == SSID && "Value truncated");
1019   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1020   assert(getOrdering() == Ordering && "Value truncated");
1021   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1022   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1023 }
1024 
1025 /// Profile - Gather unique data for the object.
1026 ///
1027 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1028   ID.AddInteger(getOffset());
1029   ID.AddInteger(Size);
1030   ID.AddPointer(getOpaqueValue());
1031   ID.AddInteger(getFlags());
1032   ID.AddInteger(getBaseAlignment());
1033 }
1034 
1035 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1036   // The Value and Offset may differ due to CSE. But the flags and size
1037   // should be the same.
1038   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1039   assert(MMO->getSize() == getSize() && "Size mismatch!");
1040 
1041   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1042     // Update the alignment value.
1043     BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1044     // Also update the base and offset, because the new alignment may
1045     // not be applicable with the old ones.
1046     PtrInfo = MMO->PtrInfo;
1047   }
1048 }
1049 
1050 /// getAlignment - Return the minimum known alignment in bytes of the
1051 /// actual memory reference.
1052 uint64_t MachineMemOperand::getAlignment() const {
1053   return MinAlign(getBaseAlignment(), getOffset());
1054 }
1055 
1056 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1057                               SmallVectorImpl<StringRef> &SSNs,
1058                               const LLVMContext &Context,
1059                               const MachineFrameInfo *MFI,
1060                               const TargetInstrInfo *TII,
1061                               const MIRFormatter* MIRF) const {
1062   OS << '(';
1063   if (isVolatile())
1064     OS << "volatile ";
1065   if (isNonTemporal())
1066     OS << "non-temporal ";
1067   if (isDereferenceable())
1068     OS << "dereferenceable ";
1069   if (isInvariant())
1070     OS << "invariant ";
1071   if (getFlags() & MachineMemOperand::MOTargetFlag1)
1072     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1073        << "\" ";
1074   if (getFlags() & MachineMemOperand::MOTargetFlag2)
1075     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1076        << "\" ";
1077   if (getFlags() & MachineMemOperand::MOTargetFlag3)
1078     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1079        << "\" ";
1080 
1081   assert((isLoad() || isStore()) &&
1082          "machine memory operand must be a load or store (or both)");
1083   if (isLoad())
1084     OS << "load ";
1085   if (isStore())
1086     OS << "store ";
1087 
1088   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1089 
1090   if (getOrdering() != AtomicOrdering::NotAtomic)
1091     OS << toIRString(getOrdering()) << ' ';
1092   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1093     OS << toIRString(getFailureOrdering()) << ' ';
1094 
1095   if (getSize() == MemoryLocation::UnknownSize)
1096     OS << "unknown-size";
1097   else
1098     OS << getSize();
1099 
1100   if (const Value *Val = getValue()) {
1101     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1102     MIRFormatter::printIRValue(OS, *Val, MST);
1103   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1104     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1105     assert(PVal && "Expected a pseudo source value");
1106     switch (PVal->kind()) {
1107     case PseudoSourceValue::Stack:
1108       OS << "stack";
1109       break;
1110     case PseudoSourceValue::GOT:
1111       OS << "got";
1112       break;
1113     case PseudoSourceValue::JumpTable:
1114       OS << "jump-table";
1115       break;
1116     case PseudoSourceValue::ConstantPool:
1117       OS << "constant-pool";
1118       break;
1119     case PseudoSourceValue::FixedStack: {
1120       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1121       bool IsFixed = true;
1122       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1123       break;
1124     }
1125     case PseudoSourceValue::GlobalValueCallEntry:
1126       OS << "call-entry ";
1127       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1128           OS, /*PrintType=*/false, MST);
1129       break;
1130     case PseudoSourceValue::ExternalSymbolCallEntry:
1131       OS << "call-entry &";
1132       printLLVMNameWithoutPrefix(
1133           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1134       break;
1135     default: {
1136       // FIXME: This is not necessarily the correct MIR serialization format for
1137       // a custom pseudo source value, but at least it allows
1138       // -print-machineinstrs to work on a target with custom pseudo source
1139       // values.
1140       OS << "custom \"";
1141       if (MIRF)
1142         MIRF->printCustomPseudoSourceValue(OS, MST, *PVal);
1143       else
1144         PVal->printCustom(OS);
1145       OS << '\"';
1146       break;
1147     }
1148     }
1149   }
1150   MachineOperand::printOperandOffset(OS, getOffset());
1151   if (getBaseAlignment() != getSize())
1152     OS << ", align " << getBaseAlignment();
1153   auto AAInfo = getAAInfo();
1154   if (AAInfo.TBAA) {
1155     OS << ", !tbaa ";
1156     AAInfo.TBAA->printAsOperand(OS, MST);
1157   }
1158   if (AAInfo.Scope) {
1159     OS << ", !alias.scope ";
1160     AAInfo.Scope->printAsOperand(OS, MST);
1161   }
1162   if (AAInfo.NoAlias) {
1163     OS << ", !noalias ";
1164     AAInfo.NoAlias->printAsOperand(OS, MST);
1165   }
1166   if (getRanges()) {
1167     OS << ", !range ";
1168     getRanges()->printAsOperand(OS, MST);
1169   }
1170   // FIXME: Implement addrspace printing/parsing in MIR.
1171   // For now, print this even though parsing it is not available in MIR.
1172   if (unsigned AS = getAddrSpace())
1173     OS << ", addrspace " << AS;
1174 
1175   OS << ')';
1176 }
1177