xref: /llvm-project/llvm/lib/CodeGen/MachineOperand.cpp (revision 2946cd701067404b99c39fb29dc9c74bd7193eb3) 
1 //===- lib/CodeGen/MachineOperand.cpp -------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file Methods common to all machine operands.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/MachineOperand.h"
14 #include "llvm/ADT/StringExtras.h"
15 #include "llvm/Analysis/Loads.h"
16 #include "llvm/Analysis/MemoryLocation.h"
17 #include "llvm/CodeGen/MIRPrinter.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineJumpTableInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
23 #include "llvm/Config/llvm-config.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/IRPrintingPasses.h"
26 #include "llvm/IR/ModuleSlotTracker.h"
27 #include "llvm/Target/TargetIntrinsicInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 
30 using namespace llvm;
31 
32 static cl::opt<int>
33     PrintRegMaskNumRegs("print-regmask-num-regs",
34                         cl::desc("Number of registers to limit to when "
35                                  "printing regmask operands in IR dumps. "
36                                  "unlimited = -1"),
37                         cl::init(32), cl::Hidden);
38 
39 static const MachineFunction *getMFIfAvailable(const MachineOperand &MO) {
40   if (const MachineInstr *MI = MO.getParent())
41     if (const MachineBasicBlock *MBB = MI->getParent())
42       if (const MachineFunction *MF = MBB->getParent())
43         return MF;
44   return nullptr;
45 }
46 static MachineFunction *getMFIfAvailable(MachineOperand &MO) {
47   return const_cast<MachineFunction *>(
48       getMFIfAvailable(const_cast<const MachineOperand &>(MO)));
49 }
50 
51 void MachineOperand::setReg(unsigned Reg) {
52   if (getReg() == Reg)
53     return; // No change.
54 
55   // Clear the IsRenamable bit to keep it conservatively correct.
56   IsRenamable = false;
57 
58   // Otherwise, we have to change the register.  If this operand is embedded
59   // into a machine function, we need to update the old and new register's
60   // use/def lists.
61   if (MachineFunction *MF = getMFIfAvailable(*this)) {
62     MachineRegisterInfo &MRI = MF->getRegInfo();
63     MRI.removeRegOperandFromUseList(this);
64     SmallContents.RegNo = Reg;
65     MRI.addRegOperandToUseList(this);
66     return;
67   }
68 
69   // Otherwise, just change the register, no problem.  :)
70   SmallContents.RegNo = Reg;
71 }
72 
73 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
74                                   const TargetRegisterInfo &TRI) {
75   assert(TargetRegisterInfo::isVirtualRegister(Reg));
76   if (SubIdx && getSubReg())
77     SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
78   setReg(Reg);
79   if (SubIdx)
80     setSubReg(SubIdx);
81 }
82 
83 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
84   assert(TargetRegisterInfo::isPhysicalRegister(Reg));
85   if (getSubReg()) {
86     Reg = TRI.getSubReg(Reg, getSubReg());
87     // Note that getSubReg() may return 0 if the sub-register doesn't exist.
88     // That won't happen in legal code.
89     setSubReg(0);
90     if (isDef())
91       setIsUndef(false);
92   }
93   setReg(Reg);
94 }
95 
96 /// Change a def to a use, or a use to a def.
97 void MachineOperand::setIsDef(bool Val) {
98   assert(isReg() && "Wrong MachineOperand accessor");
99   assert((!Val || !isDebug()) && "Marking a debug operation as def");
100   if (IsDef == Val)
101     return;
102   assert(!IsDeadOrKill && "Changing def/use with dead/kill set not supported");
103   // MRI may keep uses and defs in different list positions.
104   if (MachineFunction *MF = getMFIfAvailable(*this)) {
105     MachineRegisterInfo &MRI = MF->getRegInfo();
106     MRI.removeRegOperandFromUseList(this);
107     IsDef = Val;
108     MRI.addRegOperandToUseList(this);
109     return;
110   }
111   IsDef = Val;
112 }
113 
114 bool MachineOperand::isRenamable() const {
115   assert(isReg() && "Wrong MachineOperand accessor");
116   assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
117          "isRenamable should only be checked on physical registers");
118   if (!IsRenamable)
119     return false;
120 
121   const MachineInstr *MI = getParent();
122   if (!MI)
123     return true;
124 
125   if (isDef())
126     return !MI->hasExtraDefRegAllocReq(MachineInstr::IgnoreBundle);
127 
128   assert(isUse() && "Reg is not def or use");
129   return !MI->hasExtraSrcRegAllocReq(MachineInstr::IgnoreBundle);
130 }
131 
132 void MachineOperand::setIsRenamable(bool Val) {
133   assert(isReg() && "Wrong MachineOperand accessor");
134   assert(TargetRegisterInfo::isPhysicalRegister(getReg()) &&
135          "setIsRenamable should only be called on physical registers");
136   IsRenamable = Val;
137 }
138 
139 // If this operand is currently a register operand, and if this is in a
140 // function, deregister the operand from the register's use/def list.
141 void MachineOperand::removeRegFromUses() {
142   if (!isReg() || !isOnRegUseList())
143     return;
144 
145   if (MachineFunction *MF = getMFIfAvailable(*this))
146     MF->getRegInfo().removeRegOperandFromUseList(this);
147 }
148 
149 /// ChangeToImmediate - Replace this operand with a new immediate operand of
150 /// the specified value.  If an operand is known to be an immediate already,
151 /// the setImm method should be used.
152 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
153   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
154 
155   removeRegFromUses();
156 
157   OpKind = MO_Immediate;
158   Contents.ImmVal = ImmVal;
159 }
160 
161 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
162   assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
163 
164   removeRegFromUses();
165 
166   OpKind = MO_FPImmediate;
167   Contents.CFP = FPImm;
168 }
169 
170 void MachineOperand::ChangeToES(const char *SymName,
171                                 unsigned char TargetFlags) {
172   assert((!isReg() || !isTied()) &&
173          "Cannot change a tied operand into an external symbol");
174 
175   removeRegFromUses();
176 
177   OpKind = MO_ExternalSymbol;
178   Contents.OffsetedInfo.Val.SymbolName = SymName;
179   setOffset(0); // Offset is always 0.
180   setTargetFlags(TargetFlags);
181 }
182 
183 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
184   assert((!isReg() || !isTied()) &&
185          "Cannot change a tied operand into an MCSymbol");
186 
187   removeRegFromUses();
188 
189   OpKind = MO_MCSymbol;
190   Contents.Sym = Sym;
191 }
192 
193 void MachineOperand::ChangeToFrameIndex(int Idx) {
194   assert((!isReg() || !isTied()) &&
195          "Cannot change a tied operand into a FrameIndex");
196 
197   removeRegFromUses();
198 
199   OpKind = MO_FrameIndex;
200   setIndex(Idx);
201 }
202 
203 void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
204                                          unsigned char TargetFlags) {
205   assert((!isReg() || !isTied()) &&
206          "Cannot change a tied operand into a FrameIndex");
207 
208   removeRegFromUses();
209 
210   OpKind = MO_TargetIndex;
211   setIndex(Idx);
212   setOffset(Offset);
213   setTargetFlags(TargetFlags);
214 }
215 
216 /// ChangeToRegister - Replace this operand with a new register operand of
217 /// the specified value.  If an operand is known to be an register already,
218 /// the setReg method should be used.
219 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
220                                       bool isKill, bool isDead, bool isUndef,
221                                       bool isDebug) {
222   MachineRegisterInfo *RegInfo = nullptr;
223   if (MachineFunction *MF = getMFIfAvailable(*this))
224     RegInfo = &MF->getRegInfo();
225   // If this operand is already a register operand, remove it from the
226   // register's use/def lists.
227   bool WasReg = isReg();
228   if (RegInfo && WasReg)
229     RegInfo->removeRegOperandFromUseList(this);
230 
231   // Change this to a register and set the reg#.
232   assert(!(isDead && !isDef) && "Dead flag on non-def");
233   assert(!(isKill && isDef) && "Kill flag on def");
234   OpKind = MO_Register;
235   SmallContents.RegNo = Reg;
236   SubReg_TargetFlags = 0;
237   IsDef = isDef;
238   IsImp = isImp;
239   IsDeadOrKill = isKill | isDead;
240   IsRenamable = false;
241   IsUndef = isUndef;
242   IsInternalRead = false;
243   IsEarlyClobber = false;
244   IsDebug = isDebug;
245   // Ensure isOnRegUseList() returns false.
246   Contents.Reg.Prev = nullptr;
247   // Preserve the tie when the operand was already a register.
248   if (!WasReg)
249     TiedTo = 0;
250 
251   // If this operand is embedded in a function, add the operand to the
252   // register's use/def list.
253   if (RegInfo)
254     RegInfo->addRegOperandToUseList(this);
255 }
256 
257 /// isIdenticalTo - Return true if this operand is identical to the specified
258 /// operand. Note that this should stay in sync with the hash_value overload
259 /// below.
260 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
261   if (getType() != Other.getType() ||
262       getTargetFlags() != Other.getTargetFlags())
263     return false;
264 
265   switch (getType()) {
266   case MachineOperand::MO_Register:
267     return getReg() == Other.getReg() && isDef() == Other.isDef() &&
268            getSubReg() == Other.getSubReg();
269   case MachineOperand::MO_Immediate:
270     return getImm() == Other.getImm();
271   case MachineOperand::MO_CImmediate:
272     return getCImm() == Other.getCImm();
273   case MachineOperand::MO_FPImmediate:
274     return getFPImm() == Other.getFPImm();
275   case MachineOperand::MO_MachineBasicBlock:
276     return getMBB() == Other.getMBB();
277   case MachineOperand::MO_FrameIndex:
278     return getIndex() == Other.getIndex();
279   case MachineOperand::MO_ConstantPoolIndex:
280   case MachineOperand::MO_TargetIndex:
281     return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
282   case MachineOperand::MO_JumpTableIndex:
283     return getIndex() == Other.getIndex();
284   case MachineOperand::MO_GlobalAddress:
285     return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
286   case MachineOperand::MO_ExternalSymbol:
287     return strcmp(getSymbolName(), Other.getSymbolName()) == 0 &&
288            getOffset() == Other.getOffset();
289   case MachineOperand::MO_BlockAddress:
290     return getBlockAddress() == Other.getBlockAddress() &&
291            getOffset() == Other.getOffset();
292   case MachineOperand::MO_RegisterMask:
293   case MachineOperand::MO_RegisterLiveOut: {
294     // Shallow compare of the two RegMasks
295     const uint32_t *RegMask = getRegMask();
296     const uint32_t *OtherRegMask = Other.getRegMask();
297     if (RegMask == OtherRegMask)
298       return true;
299 
300     if (const MachineFunction *MF = getMFIfAvailable(*this)) {
301       // Calculate the size of the RegMask
302       const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
303       unsigned RegMaskSize = (TRI->getNumRegs() + 31) / 32;
304 
305       // Deep compare of the two RegMasks
306       return std::equal(RegMask, RegMask + RegMaskSize, OtherRegMask);
307     }
308     // We don't know the size of the RegMask, so we can't deep compare the two
309     // reg masks.
310     return false;
311   }
312   case MachineOperand::MO_MCSymbol:
313     return getMCSymbol() == Other.getMCSymbol();
314   case MachineOperand::MO_CFIIndex:
315     return getCFIIndex() == Other.getCFIIndex();
316   case MachineOperand::MO_Metadata:
317     return getMetadata() == Other.getMetadata();
318   case MachineOperand::MO_IntrinsicID:
319     return getIntrinsicID() == Other.getIntrinsicID();
320   case MachineOperand::MO_Predicate:
321     return getPredicate() == Other.getPredicate();
322   }
323   llvm_unreachable("Invalid machine operand type");
324 }
325 
326 // Note: this must stay exactly in sync with isIdenticalTo above.
327 hash_code llvm::hash_value(const MachineOperand &MO) {
328   switch (MO.getType()) {
329   case MachineOperand::MO_Register:
330     // Register operands don't have target flags.
331     return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
332   case MachineOperand::MO_Immediate:
333     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
334   case MachineOperand::MO_CImmediate:
335     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
336   case MachineOperand::MO_FPImmediate:
337     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
338   case MachineOperand::MO_MachineBasicBlock:
339     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
340   case MachineOperand::MO_FrameIndex:
341     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
342   case MachineOperand::MO_ConstantPoolIndex:
343   case MachineOperand::MO_TargetIndex:
344     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
345                         MO.getOffset());
346   case MachineOperand::MO_JumpTableIndex:
347     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
348   case MachineOperand::MO_ExternalSymbol:
349     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
350                         MO.getSymbolName());
351   case MachineOperand::MO_GlobalAddress:
352     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
353                         MO.getOffset());
354   case MachineOperand::MO_BlockAddress:
355     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getBlockAddress(),
356                         MO.getOffset());
357   case MachineOperand::MO_RegisterMask:
358   case MachineOperand::MO_RegisterLiveOut:
359     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
360   case MachineOperand::MO_Metadata:
361     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
362   case MachineOperand::MO_MCSymbol:
363     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
364   case MachineOperand::MO_CFIIndex:
365     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
366   case MachineOperand::MO_IntrinsicID:
367     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIntrinsicID());
368   case MachineOperand::MO_Predicate:
369     return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getPredicate());
370   }
371   llvm_unreachable("Invalid machine operand type");
372 }
373 
374 // Try to crawl up to the machine function and get TRI and IntrinsicInfo from
375 // it.
376 static void tryToGetTargetInfo(const MachineOperand &MO,
377                                const TargetRegisterInfo *&TRI,
378                                const TargetIntrinsicInfo *&IntrinsicInfo) {
379   if (const MachineFunction *MF = getMFIfAvailable(MO)) {
380     TRI = MF->getSubtarget().getRegisterInfo();
381     IntrinsicInfo = MF->getTarget().getIntrinsicInfo();
382   }
383 }
384 
385 static const char *getTargetIndexName(const MachineFunction &MF, int Index) {
386   const auto *TII = MF.getSubtarget().getInstrInfo();
387   assert(TII && "expected instruction info");
388   auto Indices = TII->getSerializableTargetIndices();
389   auto Found = find_if(Indices, [&](const std::pair<int, const char *> &I) {
390     return I.first == Index;
391   });
392   if (Found != Indices.end())
393     return Found->second;
394   return nullptr;
395 }
396 
397 static const char *getTargetFlagName(const TargetInstrInfo *TII, unsigned TF) {
398   auto Flags = TII->getSerializableDirectMachineOperandTargetFlags();
399   for (const auto &I : Flags) {
400     if (I.first == TF) {
401       return I.second;
402     }
403   }
404   return nullptr;
405 }
406 
407 static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
408                              const TargetRegisterInfo *TRI) {
409   if (!TRI) {
410     OS << "%dwarfreg." << DwarfReg;
411     return;
412   }
413 
414   int Reg = TRI->getLLVMRegNum(DwarfReg, true);
415   if (Reg == -1) {
416     OS << "<badreg>";
417     return;
418   }
419   OS << printReg(Reg, TRI);
420 }
421 
422 static void printIRBlockReference(raw_ostream &OS, const BasicBlock &BB,
423                                   ModuleSlotTracker &MST) {
424   OS << "%ir-block.";
425   if (BB.hasName()) {
426     printLLVMNameWithoutPrefix(OS, BB.getName());
427     return;
428   }
429   Optional<int> Slot;
430   if (const Function *F = BB.getParent()) {
431     if (F == MST.getCurrentFunction()) {
432       Slot = MST.getLocalSlot(&BB);
433     } else if (const Module *M = F->getParent()) {
434       ModuleSlotTracker CustomMST(M, /*ShouldInitializeAllMetadata=*/false);
435       CustomMST.incorporateFunction(*F);
436       Slot = CustomMST.getLocalSlot(&BB);
437     }
438   }
439   if (Slot)
440     MachineOperand::printIRSlotNumber(OS, *Slot);
441   else
442     OS << "<unknown>";
443 }
444 
445 static void printIRValueReference(raw_ostream &OS, const Value &V,
446                                   ModuleSlotTracker &MST) {
447   if (isa<GlobalValue>(V)) {
448     V.printAsOperand(OS, /*PrintType=*/false, MST);
449     return;
450   }
451   if (isa<Constant>(V)) {
452     // Machine memory operands can load/store to/from constant value pointers.
453     OS << '`';
454     V.printAsOperand(OS, /*PrintType=*/true, MST);
455     OS << '`';
456     return;
457   }
458   OS << "%ir.";
459   if (V.hasName()) {
460     printLLVMNameWithoutPrefix(OS, V.getName());
461     return;
462   }
463   int Slot = MST.getCurrentFunction() ? MST.getLocalSlot(&V) : -1;
464   MachineOperand::printIRSlotNumber(OS, Slot);
465 }
466 
467 static void printSyncScope(raw_ostream &OS, const LLVMContext &Context,
468                            SyncScope::ID SSID,
469                            SmallVectorImpl<StringRef> &SSNs) {
470   switch (SSID) {
471   case SyncScope::System:
472     break;
473   default:
474     if (SSNs.empty())
475       Context.getSyncScopeNames(SSNs);
476 
477     OS << "syncscope(\"";
478     printEscapedString(SSNs[SSID], OS);
479     OS << "\") ";
480     break;
481   }
482 }
483 
484 static const char *getTargetMMOFlagName(const TargetInstrInfo &TII,
485                                         unsigned TMMOFlag) {
486   auto Flags = TII.getSerializableMachineMemOperandTargetFlags();
487   for (const auto &I : Flags) {
488     if (I.first == TMMOFlag) {
489       return I.second;
490     }
491   }
492   return nullptr;
493 }
494 
495 static void printFrameIndex(raw_ostream& OS, int FrameIndex, bool IsFixed,
496                             const MachineFrameInfo *MFI) {
497   StringRef Name;
498   if (MFI) {
499     IsFixed = MFI->isFixedObjectIndex(FrameIndex);
500     if (const AllocaInst *Alloca = MFI->getObjectAllocation(FrameIndex))
501       if (Alloca->hasName())
502         Name = Alloca->getName();
503     if (IsFixed)
504       FrameIndex -= MFI->getObjectIndexBegin();
505   }
506   MachineOperand::printStackObjectReference(OS, FrameIndex, IsFixed, Name);
507 }
508 
509 void MachineOperand::printSubRegIdx(raw_ostream &OS, uint64_t Index,
510                                     const TargetRegisterInfo *TRI) {
511   OS << "%subreg.";
512   if (TRI)
513     OS << TRI->getSubRegIndexName(Index);
514   else
515     OS << Index;
516 }
517 
518 void MachineOperand::printTargetFlags(raw_ostream &OS,
519                                       const MachineOperand &Op) {
520   if (!Op.getTargetFlags())
521     return;
522   const MachineFunction *MF = getMFIfAvailable(Op);
523   if (!MF)
524     return;
525 
526   const auto *TII = MF->getSubtarget().getInstrInfo();
527   assert(TII && "expected instruction info");
528   auto Flags = TII->decomposeMachineOperandsTargetFlags(Op.getTargetFlags());
529   OS << "target-flags(";
530   const bool HasDirectFlags = Flags.first;
531   const bool HasBitmaskFlags = Flags.second;
532   if (!HasDirectFlags && !HasBitmaskFlags) {
533     OS << "<unknown>) ";
534     return;
535   }
536   if (HasDirectFlags) {
537     if (const auto *Name = getTargetFlagName(TII, Flags.first))
538       OS << Name;
539     else
540       OS << "<unknown target flag>";
541   }
542   if (!HasBitmaskFlags) {
543     OS << ") ";
544     return;
545   }
546   bool IsCommaNeeded = HasDirectFlags;
547   unsigned BitMask = Flags.second;
548   auto BitMasks = TII->getSerializableBitmaskMachineOperandTargetFlags();
549   for (const auto &Mask : BitMasks) {
550     // Check if the flag's bitmask has the bits of the current mask set.
551     if ((BitMask & Mask.first) == Mask.first) {
552       if (IsCommaNeeded)
553         OS << ", ";
554       IsCommaNeeded = true;
555       OS << Mask.second;
556       // Clear the bits which were serialized from the flag's bitmask.
557       BitMask &= ~(Mask.first);
558     }
559   }
560   if (BitMask) {
561     // When the resulting flag's bitmask isn't zero, we know that we didn't
562     // serialize all of the bit flags.
563     if (IsCommaNeeded)
564       OS << ", ";
565     OS << "<unknown bitmask target flag>";
566   }
567   OS << ") ";
568 }
569 
570 void MachineOperand::printSymbol(raw_ostream &OS, MCSymbol &Sym) {
571   OS << "<mcsymbol " << Sym << ">";
572 }
573 
574 void MachineOperand::printStackObjectReference(raw_ostream &OS,
575                                                unsigned FrameIndex,
576                                                bool IsFixed, StringRef Name) {
577   if (IsFixed) {
578     OS << "%fixed-stack." << FrameIndex;
579     return;
580   }
581 
582   OS << "%stack." << FrameIndex;
583   if (!Name.empty())
584     OS << '.' << Name;
585 }
586 
587 void MachineOperand::printOperandOffset(raw_ostream &OS, int64_t Offset) {
588   if (Offset == 0)
589     return;
590   if (Offset < 0) {
591     OS << " - " << -Offset;
592     return;
593   }
594   OS << " + " << Offset;
595 }
596 
597 void MachineOperand::printIRSlotNumber(raw_ostream &OS, int Slot) {
598   if (Slot == -1)
599     OS << "<badref>";
600   else
601     OS << Slot;
602 }
603 
604 static void printCFI(raw_ostream &OS, const MCCFIInstruction &CFI,
605                      const TargetRegisterInfo *TRI) {
606   switch (CFI.getOperation()) {
607   case MCCFIInstruction::OpSameValue:
608     OS << "same_value ";
609     if (MCSymbol *Label = CFI.getLabel())
610       MachineOperand::printSymbol(OS, *Label);
611     printCFIRegister(CFI.getRegister(), OS, TRI);
612     break;
613   case MCCFIInstruction::OpRememberState:
614     OS << "remember_state ";
615     if (MCSymbol *Label = CFI.getLabel())
616       MachineOperand::printSymbol(OS, *Label);
617     break;
618   case MCCFIInstruction::OpRestoreState:
619     OS << "restore_state ";
620     if (MCSymbol *Label = CFI.getLabel())
621       MachineOperand::printSymbol(OS, *Label);
622     break;
623   case MCCFIInstruction::OpOffset:
624     OS << "offset ";
625     if (MCSymbol *Label = CFI.getLabel())
626       MachineOperand::printSymbol(OS, *Label);
627     printCFIRegister(CFI.getRegister(), OS, TRI);
628     OS << ", " << CFI.getOffset();
629     break;
630   case MCCFIInstruction::OpDefCfaRegister:
631     OS << "def_cfa_register ";
632     if (MCSymbol *Label = CFI.getLabel())
633       MachineOperand::printSymbol(OS, *Label);
634     printCFIRegister(CFI.getRegister(), OS, TRI);
635     break;
636   case MCCFIInstruction::OpDefCfaOffset:
637     OS << "def_cfa_offset ";
638     if (MCSymbol *Label = CFI.getLabel())
639       MachineOperand::printSymbol(OS, *Label);
640     OS << CFI.getOffset();
641     break;
642   case MCCFIInstruction::OpDefCfa:
643     OS << "def_cfa ";
644     if (MCSymbol *Label = CFI.getLabel())
645       MachineOperand::printSymbol(OS, *Label);
646     printCFIRegister(CFI.getRegister(), OS, TRI);
647     OS << ", " << CFI.getOffset();
648     break;
649   case MCCFIInstruction::OpRelOffset:
650     OS << "rel_offset ";
651     if (MCSymbol *Label = CFI.getLabel())
652       MachineOperand::printSymbol(OS, *Label);
653     printCFIRegister(CFI.getRegister(), OS, TRI);
654     OS << ", " << CFI.getOffset();
655     break;
656   case MCCFIInstruction::OpAdjustCfaOffset:
657     OS << "adjust_cfa_offset ";
658     if (MCSymbol *Label = CFI.getLabel())
659       MachineOperand::printSymbol(OS, *Label);
660     OS << CFI.getOffset();
661     break;
662   case MCCFIInstruction::OpRestore:
663     OS << "restore ";
664     if (MCSymbol *Label = CFI.getLabel())
665       MachineOperand::printSymbol(OS, *Label);
666     printCFIRegister(CFI.getRegister(), OS, TRI);
667     break;
668   case MCCFIInstruction::OpEscape: {
669     OS << "escape ";
670     if (MCSymbol *Label = CFI.getLabel())
671       MachineOperand::printSymbol(OS, *Label);
672     if (!CFI.getValues().empty()) {
673       size_t e = CFI.getValues().size() - 1;
674       for (size_t i = 0; i < e; ++i)
675         OS << format("0x%02x", uint8_t(CFI.getValues()[i])) << ", ";
676       OS << format("0x%02x", uint8_t(CFI.getValues()[e])) << ", ";
677     }
678     break;
679   }
680   case MCCFIInstruction::OpUndefined:
681     OS << "undefined ";
682     if (MCSymbol *Label = CFI.getLabel())
683       MachineOperand::printSymbol(OS, *Label);
684     printCFIRegister(CFI.getRegister(), OS, TRI);
685     break;
686   case MCCFIInstruction::OpRegister:
687     OS << "register ";
688     if (MCSymbol *Label = CFI.getLabel())
689       MachineOperand::printSymbol(OS, *Label);
690     printCFIRegister(CFI.getRegister(), OS, TRI);
691     OS << ", ";
692     printCFIRegister(CFI.getRegister2(), OS, TRI);
693     break;
694   case MCCFIInstruction::OpWindowSave:
695     OS << "window_save ";
696     if (MCSymbol *Label = CFI.getLabel())
697       MachineOperand::printSymbol(OS, *Label);
698     break;
699   case MCCFIInstruction::OpNegateRAState:
700     OS << "negate_ra_sign_state ";
701     if (MCSymbol *Label = CFI.getLabel())
702       MachineOperand::printSymbol(OS, *Label);
703     break;
704   default:
705     // TODO: Print the other CFI Operations.
706     OS << "<unserializable cfi directive>";
707     break;
708   }
709 }
710 
711 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
712                            const TargetIntrinsicInfo *IntrinsicInfo) const {
713   print(OS, LLT{}, TRI, IntrinsicInfo);
714 }
715 
716 void MachineOperand::print(raw_ostream &OS, LLT TypeToPrint,
717                            const TargetRegisterInfo *TRI,
718                            const TargetIntrinsicInfo *IntrinsicInfo) const {
719   tryToGetTargetInfo(*this, TRI, IntrinsicInfo);
720   ModuleSlotTracker DummyMST(nullptr);
721   print(OS, DummyMST, TypeToPrint, /*PrintDef=*/false, /*IsStandalone=*/true,
722         /*ShouldPrintRegisterTies=*/true,
723         /*TiedOperandIdx=*/0, TRI, IntrinsicInfo);
724 }
725 
726 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
727                            LLT TypeToPrint, bool PrintDef, bool IsStandalone,
728                            bool ShouldPrintRegisterTies,
729                            unsigned TiedOperandIdx,
730                            const TargetRegisterInfo *TRI,
731                            const TargetIntrinsicInfo *IntrinsicInfo) const {
732   printTargetFlags(OS, *this);
733   switch (getType()) {
734   case MachineOperand::MO_Register: {
735     unsigned Reg = getReg();
736     if (isImplicit())
737       OS << (isDef() ? "implicit-def " : "implicit ");
738     else if (PrintDef && isDef())
739       // Print the 'def' flag only when the operand is defined after '='.
740       OS << "def ";
741     if (isInternalRead())
742       OS << "internal ";
743     if (isDead())
744       OS << "dead ";
745     if (isKill())
746       OS << "killed ";
747     if (isUndef())
748       OS << "undef ";
749     if (isEarlyClobber())
750       OS << "early-clobber ";
751     if (TargetRegisterInfo::isPhysicalRegister(getReg()) && isRenamable())
752       OS << "renamable ";
753     // isDebug() is exactly true for register operands of a DBG_VALUE. So we
754     // simply infer it when parsing and do not need to print it.
755 
756     const MachineRegisterInfo *MRI = nullptr;
757     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
758       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
759         MRI = &MF->getRegInfo();
760       }
761     }
762 
763     OS << printReg(Reg, TRI, 0, MRI);
764     // Print the sub register.
765     if (unsigned SubReg = getSubReg()) {
766       if (TRI)
767         OS << '.' << TRI->getSubRegIndexName(SubReg);
768       else
769         OS << ".subreg" << SubReg;
770     }
771     // Print the register class / bank.
772     if (TargetRegisterInfo::isVirtualRegister(Reg)) {
773       if (const MachineFunction *MF = getMFIfAvailable(*this)) {
774         const MachineRegisterInfo &MRI = MF->getRegInfo();
775         if (IsStandalone || !PrintDef || MRI.def_empty(Reg)) {
776           OS << ':';
777           OS << printRegClassOrBank(Reg, MRI, TRI);
778         }
779       }
780     }
781     // Print ties.
782     if (ShouldPrintRegisterTies && isTied() && !isDef())
783       OS << "(tied-def " << TiedOperandIdx << ")";
784     // Print types.
785     if (TypeToPrint.isValid())
786       OS << '(' << TypeToPrint << ')';
787     break;
788   }
789   case MachineOperand::MO_Immediate:
790     OS << getImm();
791     break;
792   case MachineOperand::MO_CImmediate:
793     getCImm()->printAsOperand(OS, /*PrintType=*/true, MST);
794     break;
795   case MachineOperand::MO_FPImmediate:
796     getFPImm()->printAsOperand(OS, /*PrintType=*/true, MST);
797     break;
798   case MachineOperand::MO_MachineBasicBlock:
799     OS << printMBBReference(*getMBB());
800     break;
801   case MachineOperand::MO_FrameIndex: {
802     int FrameIndex = getIndex();
803     bool IsFixed = false;
804     const MachineFrameInfo *MFI = nullptr;
805     if (const MachineFunction *MF = getMFIfAvailable(*this))
806       MFI = &MF->getFrameInfo();
807     printFrameIndex(OS, FrameIndex, IsFixed, MFI);
808     break;
809   }
810   case MachineOperand::MO_ConstantPoolIndex:
811     OS << "%const." << getIndex();
812     printOperandOffset(OS, getOffset());
813     break;
814   case MachineOperand::MO_TargetIndex: {
815     OS << "target-index(";
816     const char *Name = "<unknown>";
817     if (const MachineFunction *MF = getMFIfAvailable(*this))
818       if (const auto *TargetIndexName = getTargetIndexName(*MF, getIndex()))
819         Name = TargetIndexName;
820     OS << Name << ')';
821     printOperandOffset(OS, getOffset());
822     break;
823   }
824   case MachineOperand::MO_JumpTableIndex:
825     OS << printJumpTableEntryReference(getIndex());
826     break;
827   case MachineOperand::MO_GlobalAddress:
828     getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
829     printOperandOffset(OS, getOffset());
830     break;
831   case MachineOperand::MO_ExternalSymbol: {
832     StringRef Name = getSymbolName();
833     OS << '&';
834     if (Name.empty()) {
835       OS << "\"\"";
836     } else {
837       printLLVMNameWithoutPrefix(OS, Name);
838     }
839     printOperandOffset(OS, getOffset());
840     break;
841   }
842   case MachineOperand::MO_BlockAddress: {
843     OS << "blockaddress(";
844     getBlockAddress()->getFunction()->printAsOperand(OS, /*PrintType=*/false,
845                                                      MST);
846     OS << ", ";
847     printIRBlockReference(OS, *getBlockAddress()->getBasicBlock(), MST);
848     OS << ')';
849     MachineOperand::printOperandOffset(OS, getOffset());
850     break;
851   }
852   case MachineOperand::MO_RegisterMask: {
853     OS << "<regmask";
854     if (TRI) {
855       unsigned NumRegsInMask = 0;
856       unsigned NumRegsEmitted = 0;
857       for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
858         unsigned MaskWord = i / 32;
859         unsigned MaskBit = i % 32;
860         if (getRegMask()[MaskWord] & (1 << MaskBit)) {
861           if (PrintRegMaskNumRegs < 0 ||
862               NumRegsEmitted <= static_cast<unsigned>(PrintRegMaskNumRegs)) {
863             OS << " " << printReg(i, TRI);
864             NumRegsEmitted++;
865           }
866           NumRegsInMask++;
867         }
868       }
869       if (NumRegsEmitted != NumRegsInMask)
870         OS << " and " << (NumRegsInMask - NumRegsEmitted) << " more...";
871     } else {
872       OS << " ...";
873     }
874     OS << ">";
875     break;
876   }
877   case MachineOperand::MO_RegisterLiveOut: {
878     const uint32_t *RegMask = getRegLiveOut();
879     OS << "liveout(";
880     if (!TRI) {
881       OS << "<unknown>";
882     } else {
883       bool IsCommaNeeded = false;
884       for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
885         if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
886           if (IsCommaNeeded)
887             OS << ", ";
888           OS << printReg(Reg, TRI);
889           IsCommaNeeded = true;
890         }
891       }
892     }
893     OS << ")";
894     break;
895   }
896   case MachineOperand::MO_Metadata:
897     getMetadata()->printAsOperand(OS, MST);
898     break;
899   case MachineOperand::MO_MCSymbol:
900     printSymbol(OS, *getMCSymbol());
901     break;
902   case MachineOperand::MO_CFIIndex: {
903     if (const MachineFunction *MF = getMFIfAvailable(*this))
904       printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
905     else
906       OS << "<cfi directive>";
907     break;
908   }
909   case MachineOperand::MO_IntrinsicID: {
910     Intrinsic::ID ID = getIntrinsicID();
911     if (ID < Intrinsic::num_intrinsics)
912       OS << "intrinsic(@" << Intrinsic::getName(ID, None) << ')';
913     else if (IntrinsicInfo)
914       OS << "intrinsic(@" << IntrinsicInfo->getName(ID) << ')';
915     else
916       OS << "intrinsic(" << ID << ')';
917     break;
918   }
919   case MachineOperand::MO_Predicate: {
920     auto Pred = static_cast<CmpInst::Predicate>(getPredicate());
921     OS << (CmpInst::isIntPredicate(Pred) ? "int" : "float") << "pred("
922        << CmpInst::getPredicateName(Pred) << ')';
923     break;
924   }
925   }
926 }
927 
928 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
929 LLVM_DUMP_METHOD void MachineOperand::dump() const { dbgs() << *this << '\n'; }
930 #endif
931 
932 //===----------------------------------------------------------------------===//
933 // MachineMemOperand Implementation
934 //===----------------------------------------------------------------------===//
935 
936 /// getAddrSpace - Return the LLVM IR address space number that this pointer
937 /// points into.
938 unsigned MachinePointerInfo::getAddrSpace() const { return AddrSpace; }
939 
940 /// isDereferenceable - Return true if V is always dereferenceable for
941 /// Offset + Size byte.
942 bool MachinePointerInfo::isDereferenceable(unsigned Size, LLVMContext &C,
943                                            const DataLayout &DL) const {
944   if (!V.is<const Value *>())
945     return false;
946 
947   const Value *BasePtr = V.get<const Value *>();
948   if (BasePtr == nullptr)
949     return false;
950 
951   return isDereferenceableAndAlignedPointer(
952       BasePtr, 1, APInt(DL.getPointerSizeInBits(), Offset + Size), DL);
953 }
954 
955 /// getConstantPool - Return a MachinePointerInfo record that refers to the
956 /// constant pool.
957 MachinePointerInfo MachinePointerInfo::getConstantPool(MachineFunction &MF) {
958   return MachinePointerInfo(MF.getPSVManager().getConstantPool());
959 }
960 
961 /// getFixedStack - Return a MachinePointerInfo record that refers to the
962 /// the specified FrameIndex.
963 MachinePointerInfo MachinePointerInfo::getFixedStack(MachineFunction &MF,
964                                                      int FI, int64_t Offset) {
965   return MachinePointerInfo(MF.getPSVManager().getFixedStack(FI), Offset);
966 }
967 
968 MachinePointerInfo MachinePointerInfo::getJumpTable(MachineFunction &MF) {
969   return MachinePointerInfo(MF.getPSVManager().getJumpTable());
970 }
971 
972 MachinePointerInfo MachinePointerInfo::getGOT(MachineFunction &MF) {
973   return MachinePointerInfo(MF.getPSVManager().getGOT());
974 }
975 
976 MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF,
977                                                 int64_t Offset, uint8_t ID) {
978   return MachinePointerInfo(MF.getPSVManager().getStack(), Offset, ID);
979 }
980 
981 MachinePointerInfo MachinePointerInfo::getUnknownStack(MachineFunction &MF) {
982   return MachinePointerInfo(MF.getDataLayout().getAllocaAddrSpace());
983 }
984 
985 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f,
986                                      uint64_t s, uint64_t a,
987                                      const AAMDNodes &AAInfo,
988                                      const MDNode *Ranges, SyncScope::ID SSID,
989                                      AtomicOrdering Ordering,
990                                      AtomicOrdering FailureOrdering)
991     : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1),
992       AAInfo(AAInfo), Ranges(Ranges) {
993   assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue *>() ||
994           isa<PointerType>(PtrInfo.V.get<const Value *>()->getType())) &&
995          "invalid pointer value");
996   assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
997   assert((isLoad() || isStore()) && "Not a load/store!");
998 
999   AtomicInfo.SSID = static_cast<unsigned>(SSID);
1000   assert(getSyncScopeID() == SSID && "Value truncated");
1001   AtomicInfo.Ordering = static_cast<unsigned>(Ordering);
1002   assert(getOrdering() == Ordering && "Value truncated");
1003   AtomicInfo.FailureOrdering = static_cast<unsigned>(FailureOrdering);
1004   assert(getFailureOrdering() == FailureOrdering && "Value truncated");
1005 }
1006 
1007 /// Profile - Gather unique data for the object.
1008 ///
1009 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
1010   ID.AddInteger(getOffset());
1011   ID.AddInteger(Size);
1012   ID.AddPointer(getOpaqueValue());
1013   ID.AddInteger(getFlags());
1014   ID.AddInteger(getBaseAlignment());
1015 }
1016 
1017 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
1018   // The Value and Offset may differ due to CSE. But the flags and size
1019   // should be the same.
1020   assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
1021   assert(MMO->getSize() == getSize() && "Size mismatch!");
1022 
1023   if (MMO->getBaseAlignment() >= getBaseAlignment()) {
1024     // Update the alignment value.
1025     BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1;
1026     // Also update the base and offset, because the new alignment may
1027     // not be applicable with the old ones.
1028     PtrInfo = MMO->PtrInfo;
1029   }
1030 }
1031 
1032 /// getAlignment - Return the minimum known alignment in bytes of the
1033 /// actual memory reference.
1034 uint64_t MachineMemOperand::getAlignment() const {
1035   return MinAlign(getBaseAlignment(), getOffset());
1036 }
1037 
1038 void MachineMemOperand::print(raw_ostream &OS) const {
1039   ModuleSlotTracker DummyMST(nullptr);
1040   print(OS, DummyMST);
1041 }
1042 
1043 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
1044   SmallVector<StringRef, 0> SSNs;
1045   LLVMContext Ctx;
1046   print(OS, MST, SSNs, Ctx, nullptr, nullptr);
1047 }
1048 
1049 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
1050                               SmallVectorImpl<StringRef> &SSNs,
1051                               const LLVMContext &Context,
1052                               const MachineFrameInfo *MFI,
1053                               const TargetInstrInfo *TII) const {
1054   OS << '(';
1055   if (isVolatile())
1056     OS << "volatile ";
1057   if (isNonTemporal())
1058     OS << "non-temporal ";
1059   if (isDereferenceable())
1060     OS << "dereferenceable ";
1061   if (isInvariant())
1062     OS << "invariant ";
1063   if (getFlags() & MachineMemOperand::MOTargetFlag1)
1064     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag1)
1065        << "\" ";
1066   if (getFlags() & MachineMemOperand::MOTargetFlag2)
1067     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag2)
1068        << "\" ";
1069   if (getFlags() & MachineMemOperand::MOTargetFlag3)
1070     OS << '"' << getTargetMMOFlagName(*TII, MachineMemOperand::MOTargetFlag3)
1071        << "\" ";
1072 
1073   assert((isLoad() || isStore()) &&
1074          "machine memory operand must be a load or store (or both)");
1075   if (isLoad())
1076     OS << "load ";
1077   if (isStore())
1078     OS << "store ";
1079 
1080   printSyncScope(OS, Context, getSyncScopeID(), SSNs);
1081 
1082   if (getOrdering() != AtomicOrdering::NotAtomic)
1083     OS << toIRString(getOrdering()) << ' ';
1084   if (getFailureOrdering() != AtomicOrdering::NotAtomic)
1085     OS << toIRString(getFailureOrdering()) << ' ';
1086 
1087   if (getSize() == MemoryLocation::UnknownSize)
1088     OS << "unknown-size";
1089   else
1090     OS << getSize();
1091 
1092   if (const Value *Val = getValue()) {
1093     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1094     printIRValueReference(OS, *Val, MST);
1095   } else if (const PseudoSourceValue *PVal = getPseudoValue()) {
1096     OS << ((isLoad() && isStore()) ? " on " : isLoad() ? " from " : " into ");
1097     assert(PVal && "Expected a pseudo source value");
1098     switch (PVal->kind()) {
1099     case PseudoSourceValue::Stack:
1100       OS << "stack";
1101       break;
1102     case PseudoSourceValue::GOT:
1103       OS << "got";
1104       break;
1105     case PseudoSourceValue::JumpTable:
1106       OS << "jump-table";
1107       break;
1108     case PseudoSourceValue::ConstantPool:
1109       OS << "constant-pool";
1110       break;
1111     case PseudoSourceValue::FixedStack: {
1112       int FrameIndex = cast<FixedStackPseudoSourceValue>(PVal)->getFrameIndex();
1113       bool IsFixed = true;
1114       printFrameIndex(OS, FrameIndex, IsFixed, MFI);
1115       break;
1116     }
1117     case PseudoSourceValue::GlobalValueCallEntry:
1118       OS << "call-entry ";
1119       cast<GlobalValuePseudoSourceValue>(PVal)->getValue()->printAsOperand(
1120           OS, /*PrintType=*/false, MST);
1121       break;
1122     case PseudoSourceValue::ExternalSymbolCallEntry:
1123       OS << "call-entry &";
1124       printLLVMNameWithoutPrefix(
1125           OS, cast<ExternalSymbolPseudoSourceValue>(PVal)->getSymbol());
1126       break;
1127     case PseudoSourceValue::TargetCustom:
1128       // FIXME: This is not necessarily the correct MIR serialization format for
1129       // a custom pseudo source value, but at least it allows
1130       // -print-machineinstrs to work on a target with custom pseudo source
1131       // values.
1132       OS << "custom ";
1133       PVal->printCustom(OS);
1134       break;
1135     }
1136   }
1137   MachineOperand::printOperandOffset(OS, getOffset());
1138   if (getBaseAlignment() != getSize())
1139     OS << ", align " << getBaseAlignment();
1140   auto AAInfo = getAAInfo();
1141   if (AAInfo.TBAA) {
1142     OS << ", !tbaa ";
1143     AAInfo.TBAA->printAsOperand(OS, MST);
1144   }
1145   if (AAInfo.Scope) {
1146     OS << ", !alias.scope ";
1147     AAInfo.Scope->printAsOperand(OS, MST);
1148   }
1149   if (AAInfo.NoAlias) {
1150     OS << ", !noalias ";
1151     AAInfo.NoAlias->printAsOperand(OS, MST);
1152   }
1153   if (getRanges()) {
1154     OS << ", !range ";
1155     getRanges()->printAsOperand(OS, MST);
1156   }
1157   // FIXME: Implement addrspace printing/parsing in MIR.
1158   // For now, print this even though parsing it is not available in MIR.
1159   if (unsigned AS = getAddrSpace())
1160     OS << ", addrspace " << AS;
1161 
1162   OS << ')';
1163 }
1164