1 //===-- MachineInstr.cpp --------------------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Methods common to all machine instructions. 11 // 12 // FIXME: Now that MachineInstrs have parent pointers, they should always 13 // print themselves using their MachineFunction's TargetMachine. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "llvm/CodeGen/MachineInstr.h" 18 #include "llvm/CodeGen/MachineBasicBlock.h" 19 #include "llvm/Value.h" 20 #include "llvm/Target/TargetMachine.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 #include "llvm/Target/MRegisterInfo.h" 23 24 namespace llvm { 25 26 // Global variable holding an array of descriptors for machine instructions. 27 // The actual object needs to be created separately for each target machine. 28 // This variable is initialized and reset by class TargetInstrInfo. 29 // 30 // FIXME: This should be a property of the target so that more than one target 31 // at a time can be active... 32 // 33 extern const TargetInstrDescriptor *TargetInstrDescriptors; 34 35 // Constructor for instructions with variable #operands 36 MachineInstr::MachineInstr(short opcode, unsigned numOperands) 37 : Opcode(opcode), 38 numImplicitRefs(0), 39 operands(numOperands, MachineOperand()), 40 parent(0) { 41 } 42 43 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 44 /// not a resize for them. It is expected that if you use this that you call 45 /// add* methods below to fill up the operands, instead of the Set methods. 46 /// Eventually, the "resizing" ctors will be phased out. 47 /// 48 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) 49 : Opcode(opcode), numImplicitRefs(0), parent(0) { 50 operands.reserve(numOperands); 51 } 52 53 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 54 /// MachineInstr is created and added to the end of the specified basic block. 55 /// 56 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode, 57 unsigned numOperands) 58 : Opcode(opcode), numImplicitRefs(0), parent(0) { 59 assert(MBB && "Cannot use inserting ctor with null basic block!"); 60 operands.reserve(numOperands); 61 MBB->push_back(this); // Add instruction to end of basic block! 62 } 63 64 /// OperandComplete - Return true if it's illegal to add a new operand 65 /// 66 bool MachineInstr::OperandsComplete() const { 67 int NumOperands = TargetInstrDescriptors[Opcode].numOperands; 68 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 69 return true; // Broken: we have all the operands of this instruction! 70 return false; 71 } 72 73 /// replace - Support for replacing opcode and operands of a MachineInstr in 74 /// place. This only resets the size of the operand vector and initializes it. 75 /// The new operands must be set explicitly later. 76 /// 77 void MachineInstr::replace(short opcode, unsigned numOperands) { 78 assert(getNumImplicitRefs() == 0 && 79 "This is probably broken because implicit refs are going to be lost."); 80 Opcode = opcode; 81 operands.clear(); 82 operands.resize(numOperands, MachineOperand()); 83 } 84 85 void MachineInstr::SetMachineOperandVal(unsigned i, 86 MachineOperand::MachineOperandType opTy, 87 Value* V) { 88 assert(i < operands.size()); // may be explicit or implicit op 89 operands[i].opType = opTy; 90 operands[i].value = V; 91 operands[i].regNum = -1; 92 } 93 94 void 95 MachineInstr::SetMachineOperandConst(unsigned i, 96 MachineOperand::MachineOperandType opTy, 97 int64_t intValue) { 98 assert(i < getNumOperands()); // must be explicit op 99 assert(TargetInstrDescriptors[Opcode].resultPos != (int) i && 100 "immed. constant cannot be defined"); 101 102 operands[i].opType = opTy; 103 operands[i].value = NULL; 104 operands[i].immedVal = intValue; 105 operands[i].regNum = -1; 106 operands[i].flags = 0; 107 } 108 109 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { 110 assert(i < getNumOperands()); // must be explicit op 111 112 operands[i].opType = MachineOperand::MO_MachineRegister; 113 operands[i].value = NULL; 114 operands[i].regNum = regNum; 115 } 116 117 // Used only by the SPARC back-end. 118 void MachineInstr::SetRegForOperand(unsigned i, int regNum) { 119 assert(i < getNumOperands()); // must be explicit op 120 operands[i].setRegForValue(regNum); 121 } 122 123 // Used only by the SPARC back-end. 124 void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) { 125 getImplicitOp(i).setRegForValue(regNum); 126 } 127 128 /// substituteValue - Substitute all occurrences of Value* oldVal with newVal 129 /// in all operands and all implicit refs. If defsOnly == true, substitute defs 130 /// only. 131 /// 132 /// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865, 133 /// or make it a static function in that file. 134 /// 135 unsigned 136 MachineInstr::substituteValue(const Value* oldVal, Value* newVal, 137 bool defsOnly, bool notDefsAndUses, 138 bool& someArgsWereIgnored) 139 { 140 assert((!defsOnly || !notDefsAndUses) && 141 "notDefsAndUses is irrelevant if defsOnly == true."); 142 143 unsigned numSubst = 0; 144 145 // Substitute operands 146 for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O) 147 if (*O == oldVal) 148 if (!defsOnly || 149 notDefsAndUses && (O.isDef() && !O.isUse()) || 150 !notDefsAndUses && O.isDef()) 151 { 152 O.getMachineOperand().value = newVal; 153 ++numSubst; 154 } 155 else 156 someArgsWereIgnored = true; 157 158 // Substitute implicit refs 159 for (unsigned i=0, N=getNumImplicitRefs(); i < N; ++i) 160 if (getImplicitRef(i) == oldVal) 161 if (!defsOnly || 162 notDefsAndUses && (getImplicitOp(i).isDef() && !getImplicitOp(i).isUse()) || 163 !notDefsAndUses && getImplicitOp(i).isDef()) 164 { 165 getImplicitOp(i).value = newVal; 166 ++numSubst; 167 } 168 else 169 someArgsWereIgnored = true; 170 171 return numSubst; 172 } 173 174 void MachineInstr::dump() const { 175 std::cerr << " " << *this; 176 } 177 178 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { 179 os << "(val "; 180 os << (void*) val; // print address always 181 if (val && val->hasName()) 182 os << " " << val->getName(); // print name also, if available 183 os << ")"; 184 return os; 185 } 186 187 static inline void OutputReg(std::ostream &os, unsigned RegNo, 188 const MRegisterInfo *MRI = 0) { 189 if (MRI) { 190 if (RegNo < MRegisterInfo::FirstVirtualRegister) 191 os << "%" << MRI->get(RegNo).Name; 192 else 193 os << "%reg" << RegNo; 194 } else 195 os << "%mreg(" << RegNo << ")"; 196 } 197 198 static void print(const MachineOperand &MO, std::ostream &OS, 199 const TargetMachine &TM) { 200 const MRegisterInfo *MRI = TM.getRegisterInfo(); 201 bool CloseParen = true; 202 if (MO.isHiBits32()) 203 OS << "%lm("; 204 else if (MO.isLoBits32()) 205 OS << "%lo("; 206 else if (MO.isHiBits64()) 207 OS << "%hh("; 208 else if (MO.isLoBits64()) 209 OS << "%hm("; 210 else 211 CloseParen = false; 212 213 switch (MO.getType()) { 214 case MachineOperand::MO_VirtualRegister: 215 if (MO.getVRegValue()) { 216 OS << "%reg"; 217 OutputValue(OS, MO.getVRegValue()); 218 if (MO.hasAllocatedReg()) 219 OS << "=="; 220 } 221 if (MO.hasAllocatedReg()) 222 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 223 break; 224 case MachineOperand::MO_CCRegister: 225 OS << "%ccreg"; 226 OutputValue(OS, MO.getVRegValue()); 227 if (MO.hasAllocatedReg()) { 228 OS << "=="; 229 OutputReg(OS, MO.getAllocatedRegNum(), MRI); 230 } 231 break; 232 case MachineOperand::MO_MachineRegister: 233 OutputReg(OS, MO.getMachineRegNum(), MRI); 234 break; 235 case MachineOperand::MO_SignExtendedImmed: 236 OS << (long)MO.getImmedValue(); 237 break; 238 case MachineOperand::MO_UnextendedImmed: 239 OS << (long)MO.getImmedValue(); 240 break; 241 case MachineOperand::MO_PCRelativeDisp: { 242 const Value* opVal = MO.getVRegValue(); 243 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 244 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 245 if (opVal->hasName()) 246 OS << opVal->getName(); 247 else 248 OS << (const void*) opVal; 249 OS << ")"; 250 break; 251 } 252 case MachineOperand::MO_MachineBasicBlock: 253 OS << "bb<" 254 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 255 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 256 break; 257 case MachineOperand::MO_FrameIndex: 258 OS << "<fi#" << MO.getFrameIndex() << ">"; 259 break; 260 case MachineOperand::MO_ConstantPoolIndex: 261 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 262 break; 263 case MachineOperand::MO_GlobalAddress: 264 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 265 break; 266 case MachineOperand::MO_ExternalSymbol: 267 OS << "<es:" << MO.getSymbolName() << ">"; 268 break; 269 default: 270 assert(0 && "Unrecognized operand type"); 271 } 272 273 if (CloseParen) 274 OS << ")"; 275 } 276 277 void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { 278 unsigned StartOp = 0; 279 280 // Specialize printing if op#0 is definition 281 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) { 282 llvm::print(getOperand(0), OS, TM); 283 OS << " = "; 284 ++StartOp; // Don't print this operand again! 285 } 286 OS << TM.getInstrInfo().getName(getOpcode()); 287 288 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 289 const MachineOperand& mop = getOperand(i); 290 if (i != StartOp) 291 OS << ","; 292 OS << " "; 293 llvm::print(mop, OS, TM); 294 295 if (mop.isDef()) 296 if (mop.isUse()) 297 OS << "<def&use>"; 298 else 299 OS << "<def>"; 300 } 301 302 // code for printing implicit references 303 if (getNumImplicitRefs()) { 304 OS << "\tImplicitRefs: "; 305 for(unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) { 306 OS << "\t"; 307 OutputValue(OS, getImplicitRef(i)); 308 if (getImplicitOp(i).isDef()) 309 if (getImplicitOp(i).isUse()) 310 OS << "<def&use>"; 311 else 312 OS << "<def>"; 313 } 314 } 315 316 OS << "\n"; 317 } 318 319 std::ostream &operator<<(std::ostream& os, const MachineInstr& MI) { 320 os << TargetInstrDescriptors[MI.getOpcode()].Name; 321 322 for (unsigned i=0, N=MI.getNumOperands(); i < N; i++) { 323 os << "\t" << MI.getOperand(i); 324 if (MI.getOperand(i).isDef()) 325 if (MI.getOperand(i).isUse()) 326 os << "<d&u>"; 327 else 328 os << "<d>"; 329 } 330 331 // code for printing implicit references 332 unsigned NumOfImpRefs = MI.getNumImplicitRefs(); 333 if (NumOfImpRefs > 0) { 334 os << "\tImplicit: "; 335 for (unsigned z=0; z < NumOfImpRefs; z++) { 336 OutputValue(os, MI.getImplicitRef(z)); 337 if (MI.getImplicitOp(z).isDef()) 338 if (MI.getImplicitOp(z).isUse()) 339 os << "<d&u>"; 340 else 341 os << "<d>"; 342 os << "\t"; 343 } 344 } 345 346 return os << "\n"; 347 } 348 349 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { 350 if (MO.isHiBits32()) 351 OS << "%lm("; 352 else if (MO.isLoBits32()) 353 OS << "%lo("; 354 else if (MO.isHiBits64()) 355 OS << "%hh("; 356 else if (MO.isLoBits64()) 357 OS << "%hm("; 358 359 switch (MO.getType()) 360 { 361 case MachineOperand::MO_VirtualRegister: 362 if (MO.hasAllocatedReg()) 363 OutputReg(OS, MO.getAllocatedRegNum()); 364 365 if (MO.getVRegValue()) { 366 if (MO.hasAllocatedReg()) OS << "=="; 367 OS << "%vreg"; 368 OutputValue(OS, MO.getVRegValue()); 369 } 370 break; 371 case MachineOperand::MO_CCRegister: 372 OS << "%ccreg"; 373 OutputValue(OS, MO.getVRegValue()); 374 if (MO.hasAllocatedReg()) { 375 OS << "=="; 376 OutputReg(OS, MO.getAllocatedRegNum()); 377 } 378 break; 379 case MachineOperand::MO_MachineRegister: 380 OutputReg(OS, MO.getMachineRegNum()); 381 break; 382 case MachineOperand::MO_SignExtendedImmed: 383 OS << (long)MO.getImmedValue(); 384 break; 385 case MachineOperand::MO_UnextendedImmed: 386 OS << (long)MO.getImmedValue(); 387 break; 388 case MachineOperand::MO_PCRelativeDisp: 389 { 390 const Value* opVal = MO.getVRegValue(); 391 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 392 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 393 if (opVal->hasName()) 394 OS << opVal->getName(); 395 else 396 OS << (const void*) opVal; 397 OS << ")"; 398 break; 399 } 400 case MachineOperand::MO_MachineBasicBlock: 401 OS << "bb<" 402 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 403 << "," << (void*)MO.getMachineBasicBlock()->getBasicBlock() << ">"; 404 break; 405 case MachineOperand::MO_FrameIndex: 406 OS << "<fi#" << MO.getFrameIndex() << ">"; 407 break; 408 case MachineOperand::MO_ConstantPoolIndex: 409 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 410 break; 411 case MachineOperand::MO_GlobalAddress: 412 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 413 break; 414 case MachineOperand::MO_ExternalSymbol: 415 OS << "<es:" << MO.getSymbolName() << ">"; 416 break; 417 default: 418 assert(0 && "Unrecognized operand type"); 419 break; 420 } 421 422 if (MO.flags & 423 (MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 | 424 MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64)) 425 OS << ")"; 426 427 return OS; 428 } 429 430 } // End llvm namespace 431