1 //===-- MachineInstr.cpp --------------------------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file was developed by the LLVM research group and is distributed under 6 // the University of Illinois Open Source License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Methods common to all machine instructions. 11 // 12 // FIXME: Now that MachineInstrs have parent pointers, they should always 13 // print themselves using their MachineFunction's TargetMachine. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #include "llvm/CodeGen/MachineInstr.h" 18 #include "llvm/CodeGen/MachineFunction.h" 19 #include "llvm/Value.h" 20 #include "llvm/Target/TargetMachine.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 #include "llvm/Target/MRegisterInfo.h" 23 #include "llvm/Support/LeakDetector.h" 24 #include <iostream> 25 26 using namespace llvm; 27 28 // Global variable holding an array of descriptors for machine instructions. 29 // The actual object needs to be created separately for each target machine. 30 // This variable is initialized and reset by class TargetInstrInfo. 31 // 32 // FIXME: This should be a property of the target so that more than one target 33 // at a time can be active... 34 // 35 namespace llvm { 36 extern const TargetInstrDescriptor *TargetInstrDescriptors; 37 } 38 39 // Constructor for instructions with variable #operands 40 MachineInstr::MachineInstr(short opcode, unsigned numOperands) 41 : Opcode(opcode), 42 operands(numOperands, MachineOperand()), 43 parent(0) { 44 // Make sure that we get added to a machine basicblock 45 LeakDetector::addGarbageObject(this); 46 } 47 48 /// MachineInstr ctor - This constructor only does a _reserve_ of the operands, 49 /// not a resize for them. It is expected that if you use this that you call 50 /// add* methods below to fill up the operands, instead of the Set methods. 51 /// Eventually, the "resizing" ctors will be phased out. 52 /// 53 MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY) 54 : Opcode(opcode), parent(0) { 55 operands.reserve(numOperands); 56 // Make sure that we get added to a machine basicblock 57 LeakDetector::addGarbageObject(this); 58 } 59 60 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the 61 /// MachineInstr is created and added to the end of the specified basic block. 62 /// 63 MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode, 64 unsigned numOperands) 65 : Opcode(opcode), parent(0) { 66 assert(MBB && "Cannot use inserting ctor with null basic block!"); 67 operands.reserve(numOperands); 68 // Make sure that we get added to a machine basicblock 69 LeakDetector::addGarbageObject(this); 70 MBB->push_back(this); // Add instruction to end of basic block! 71 } 72 73 /// MachineInstr ctor - Copies MachineInstr arg exactly 74 /// 75 MachineInstr::MachineInstr(const MachineInstr &MI) { 76 Opcode = MI.getOpcode(); 77 operands.reserve(MI.getNumOperands()); 78 79 // Add operands 80 for (unsigned i = 0; i < MI.getNumOperands(); ++i) 81 operands.push_back(MachineOperand(MI.getOperand(i))); 82 83 // Set parent, next, and prev to null 84 parent = 0; 85 prev = 0; 86 next = 0; 87 } 88 89 90 MachineInstr::~MachineInstr() { 91 LeakDetector::removeGarbageObject(this); 92 } 93 94 /// clone - Create a copy of 'this' instruction that is identical in all ways 95 /// except the following: the new instruction has no parent and it has no name 96 /// 97 MachineInstr* MachineInstr::clone() const { 98 return new MachineInstr(*this); 99 } 100 101 /// removeFromParent - This method unlinks 'this' from the containing basic 102 /// block, and returns it, but does not delete it. 103 MachineInstr *MachineInstr::removeFromParent() { 104 assert(getParent() && "Not embedded in a basic block!"); 105 getParent()->remove(this); 106 return this; 107 } 108 109 110 /// OperandComplete - Return true if it's illegal to add a new operand 111 /// 112 bool MachineInstr::OperandsComplete() const { 113 int NumOperands = TargetInstrDescriptors[Opcode].numOperands; 114 if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands) 115 return true; // Broken: we have all the operands of this instruction! 116 return false; 117 } 118 119 void MachineInstr::SetMachineOperandVal(unsigned i, 120 MachineOperand::MachineOperandType opTy, 121 Value* V) { 122 assert(i < operands.size()); // may be explicit or implicit op 123 operands[i].opType = opTy; 124 operands[i].contents.value = V; 125 operands[i].extra.regNum = -1; 126 } 127 128 void 129 MachineInstr::SetMachineOperandConst(unsigned i, 130 MachineOperand::MachineOperandType opTy, 131 int intValue) { 132 assert(i < getNumOperands()); // must be explicit op 133 134 operands[i].opType = opTy; 135 operands[i].contents.value = NULL; 136 operands[i].contents.immedVal = intValue; 137 operands[i].extra.regNum = -1; 138 operands[i].flags = 0; 139 } 140 141 void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) { 142 assert(i < getNumOperands()); // must be explicit op 143 144 operands[i].opType = MachineOperand::MO_MachineRegister; 145 operands[i].contents.value = NULL; 146 operands[i].extra.regNum = regNum; 147 } 148 149 void MachineInstr::dump() const { 150 std::cerr << " " << *this; 151 } 152 153 static inline std::ostream& OutputValue(std::ostream &os, const Value* val) { 154 os << "(val "; 155 os << (void*) val; // print address always 156 if (val && val->hasName()) 157 os << " " << val->getName(); // print name also, if available 158 os << ")"; 159 return os; 160 } 161 162 static inline void OutputReg(std::ostream &os, unsigned RegNo, 163 const MRegisterInfo *MRI = 0) { 164 if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) { 165 if (MRI) 166 os << "%" << MRI->get(RegNo).Name; 167 else 168 os << "%mreg(" << RegNo << ")"; 169 } else 170 os << "%reg" << RegNo; 171 } 172 173 static void print(const MachineOperand &MO, std::ostream &OS, 174 const TargetMachine *TM) { 175 const MRegisterInfo *MRI = 0; 176 177 if (TM) MRI = TM->getRegisterInfo(); 178 179 bool CloseParen = true; 180 if (MO.isHiBits32()) 181 OS << "%lm("; 182 else if (MO.isLoBits32()) 183 OS << "%lo("; 184 else if (MO.isHiBits64()) 185 OS << "%hh("; 186 else if (MO.isLoBits64()) 187 OS << "%hm("; 188 else 189 CloseParen = false; 190 191 switch (MO.getType()) { 192 case MachineOperand::MO_VirtualRegister: 193 if (MO.getVRegValue()) { 194 OS << "%reg"; 195 OutputValue(OS, MO.getVRegValue()); 196 if (MO.hasAllocatedReg()) 197 OS << "=="; 198 } 199 if (MO.hasAllocatedReg()) 200 OutputReg(OS, MO.getReg(), MRI); 201 break; 202 case MachineOperand::MO_CCRegister: 203 OS << "%ccreg"; 204 OutputValue(OS, MO.getVRegValue()); 205 if (MO.hasAllocatedReg()) { 206 OS << "=="; 207 OutputReg(OS, MO.getReg(), MRI); 208 } 209 break; 210 case MachineOperand::MO_MachineRegister: 211 OutputReg(OS, MO.getMachineRegNum(), MRI); 212 break; 213 case MachineOperand::MO_SignExtendedImmed: 214 OS << (long)MO.getImmedValue(); 215 break; 216 case MachineOperand::MO_UnextendedImmed: 217 OS << (long)MO.getImmedValue(); 218 break; 219 case MachineOperand::MO_PCRelativeDisp: { 220 const Value* opVal = MO.getVRegValue(); 221 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 222 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 223 if (opVal->hasName()) 224 OS << opVal->getName(); 225 else 226 OS << (const void*) opVal; 227 OS << ")"; 228 break; 229 } 230 case MachineOperand::MO_MachineBasicBlock: 231 OS << "mbb<" 232 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 233 << "," << (void*)MO.getMachineBasicBlock() << ">"; 234 break; 235 case MachineOperand::MO_FrameIndex: 236 OS << "<fi#" << MO.getFrameIndex() << ">"; 237 break; 238 case MachineOperand::MO_ConstantPoolIndex: 239 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 240 break; 241 case MachineOperand::MO_GlobalAddress: 242 OS << "<ga:" << ((Value*)MO.getGlobal())->getName(); 243 if (MO.getOffset()) OS << "+" << MO.getOffset(); 244 OS << ">"; 245 break; 246 case MachineOperand::MO_ExternalSymbol: 247 OS << "<es:" << MO.getSymbolName(); 248 if (MO.getOffset()) OS << "+" << MO.getOffset(); 249 OS << ">"; 250 break; 251 default: 252 assert(0 && "Unrecognized operand type"); 253 } 254 255 if (CloseParen) 256 OS << ")"; 257 } 258 259 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const { 260 unsigned StartOp = 0; 261 262 // Specialize printing if op#0 is definition 263 if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) { 264 ::print(getOperand(0), OS, TM); 265 OS << " = "; 266 ++StartOp; // Don't print this operand again! 267 } 268 269 // Must check if Target machine is not null because machine BB could not 270 // be attached to a Machine function yet 271 if (TM) 272 OS << TM->getInstrInfo()->getName(getOpcode()); 273 274 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { 275 const MachineOperand& mop = getOperand(i); 276 if (i != StartOp) 277 OS << ","; 278 OS << " "; 279 ::print(mop, OS, TM); 280 281 if (mop.isDef()) 282 if (mop.isUse()) 283 OS << "<def&use>"; 284 else 285 OS << "<def>"; 286 } 287 288 OS << "\n"; 289 } 290 291 namespace llvm { 292 std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) { 293 // If the instruction is embedded into a basic block, we can find the target 294 // info for the instruction. 295 if (const MachineBasicBlock *MBB = MI.getParent()) { 296 const MachineFunction *MF = MBB->getParent(); 297 if (MF) 298 MI.print(os, &MF->getTarget()); 299 else 300 MI.print(os, 0); 301 return os; 302 } 303 304 // Otherwise, print it out in the "raw" format without symbolic register names 305 // and such. 306 os << TargetInstrDescriptors[MI.getOpcode()].Name; 307 308 for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) { 309 os << "\t" << MI.getOperand(i); 310 if (MI.getOperand(i).isDef()) 311 if (MI.getOperand(i).isUse()) 312 os << "<d&u>"; 313 else 314 os << "<d>"; 315 } 316 317 return os << "\n"; 318 } 319 320 std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) { 321 if (MO.isHiBits32()) 322 OS << "%lm("; 323 else if (MO.isLoBits32()) 324 OS << "%lo("; 325 else if (MO.isHiBits64()) 326 OS << "%hh("; 327 else if (MO.isLoBits64()) 328 OS << "%hm("; 329 330 switch (MO.getType()) { 331 case MachineOperand::MO_VirtualRegister: 332 if (MO.hasAllocatedReg()) 333 OutputReg(OS, MO.getReg()); 334 335 if (MO.getVRegValue()) { 336 if (MO.hasAllocatedReg()) OS << "=="; 337 OS << "%vreg"; 338 OutputValue(OS, MO.getVRegValue()); 339 } 340 break; 341 case MachineOperand::MO_CCRegister: 342 OS << "%ccreg"; 343 OutputValue(OS, MO.getVRegValue()); 344 if (MO.hasAllocatedReg()) { 345 OS << "=="; 346 OutputReg(OS, MO.getReg()); 347 } 348 break; 349 case MachineOperand::MO_MachineRegister: 350 OutputReg(OS, MO.getMachineRegNum()); 351 break; 352 case MachineOperand::MO_SignExtendedImmed: 353 OS << (long)MO.getImmedValue(); 354 break; 355 case MachineOperand::MO_UnextendedImmed: 356 OS << (long)MO.getImmedValue(); 357 break; 358 case MachineOperand::MO_PCRelativeDisp: { 359 const Value* opVal = MO.getVRegValue(); 360 bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal); 361 OS << "%disp(" << (isLabel? "label " : "addr-of-val "); 362 if (opVal->hasName()) 363 OS << opVal->getName(); 364 else 365 OS << (const void*) opVal; 366 OS << ")"; 367 break; 368 } 369 case MachineOperand::MO_MachineBasicBlock: 370 OS << "<mbb:" 371 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName() 372 << "@" << (void*)MO.getMachineBasicBlock() << ">"; 373 break; 374 case MachineOperand::MO_FrameIndex: 375 OS << "<fi#" << MO.getFrameIndex() << ">"; 376 break; 377 case MachineOperand::MO_ConstantPoolIndex: 378 OS << "<cp#" << MO.getConstantPoolIndex() << ">"; 379 break; 380 case MachineOperand::MO_GlobalAddress: 381 OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">"; 382 break; 383 case MachineOperand::MO_ExternalSymbol: 384 OS << "<es:" << MO.getSymbolName() << ">"; 385 break; 386 default: 387 assert(0 && "Unrecognized operand type"); 388 break; 389 } 390 391 if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64()) 392 OS << ")"; 393 394 return OS; 395 } 396 397 } 398